An adaptive charge measurement circuit for data converters.

Abstract

A data conversion circuit and a method of operating the data conversion circuit are disclosed. In some embodiments, the data conversion circuit includes a charge measurement circuit. In some embodiments, the charge measurement circuit is a capacitive transimpedance amplifier (CTIA). In some embodiments, the data conversion circuit includes a CTIA, a quantizer, a digital-to-analog converter, a summer, and a digital filter. In some embodiments, the data conversion circuit includes an analog-to-digital converter electrically coupled to the CTIA and the digital filter. In some embodiments, the method includes integrating an input signal with the CTIA, determining whether the CTIA output signal is greater than a threshold, and reducing or refraining from reducing the CTIA output signal based on a determination of whether the CTIA output signal is greater than a threshold. TIFF2024502327000011.tif207146

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 132,309, filed December 30, 2020, the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] Field The present disclosure relates generally to data converters and, more particularly, to data converters including charge measurement circuits such as capacitive transimpedance amplifiers (CTIAs). [Background technology]

[0003] background Columns of a sensor array (e.g., an X-ray panel) may contain large parasitic capacitances and / or large parasitic resistances. Depending on the distance from the pixel to the readout circuit input and / or the pixel resistance, the parasitic resistance can range from a few ohms to 5 kilohms. Variations in pixel and column parameters (e.g., for different sensor arrays) can affect the charge transfer dynamics (e.g., differences in the transient waveforms associated with the same total charge).

[0004] The CTIA may be a charge measurement circuit used to convert the charge from the sensor into a voltage value. The advantage of using a CTIA for this purpose is that the DC level of the CTIA output voltage is a function of the total input charge during the integration period. The DC level is not affected by noise from the circuit components, other than the offset noise of the CTIA, although noise from the circuit components will add noise to the CTIA output voltage. The column may be connected to a CTIA configured to transfer the charge of a selected sensor pixel from the column to a feedback capacitor of the CTIA.

[0005] In some cases, the capacitance of the feedback capacitor may need to be large enough to store the charge transferred from the pixel. This capacitance may be large (e.g., in the pF range), requiring the feedback capacitor(s) to occupy a large area of ​​the chip. If a CTIA is required for each column, the number of feedback capacitors is the number of columns in the sensor array (e.g., a 500-column array requires a capacitor with an area of ​​500 pF). Furthermore, since the capacitance value may be large, the corresponding output voltage may be low (due to the Q=CV relationship), requiring the subsequent circuitry (e.g., an analog-to-digital converter (ADC)) to have a higher resolution or sensitivity. In some instances, the CTIA may be configured to obtain variable gain by including feedback capacitors of different values, which further increases the area of ​​the chip.

[0006] In some examples, a particular feedback capacitor may be suitable for one sensor array size, one type of pixel, and / or one dynamic range, so different CTIA designs may be required for different sensor array sizes, different types of pixels, and / or different dynamic ranges, increasing the cost of designing specific readout circuitry for different systems.

[0007] In addition, the charge integration time and the signal digitization time may not overlap. To reduce the time spent reading out each row of the sensor, a sample-and-hold circuit may be included to allow simultaneous integration of the charge from the first row and digitization of the charge from the second row, requiring one or two more capacitors (in addition to the feedback capacitor). The additional capacitor may be the same size as the feedback capacitor to reduce noise (e.g., Johnson noise). The additional capacitor further increases the area of ​​the chip, limiting the ability of the chip to be used for different array sizes, different types of sensors, or different dynamic ranges. Summary of the Invention

[0008] overview A data conversion circuit and a method of operating the data conversion circuit are disclosed. In some embodiments, the data conversion circuit includes a charge measurement circuit. In some embodiments, the charge measurement circuit is a capacitive transimpedance amplifier (CTIA). In some embodiments, the data conversion circuit includes a CTIA, a quantizer, a digital-to-analog converter, a summer, and a digital filter. In some embodiments, the data conversion circuit includes an analog-to-digital converter electrically coupled to the CTIA and the digital filter. In some embodiments, the method includes integrating an input signal with the CTIA, determining whether the CTIA output signal is greater than a threshold, and reducing or refraining from reducing the CTIA output signal based on a determination of whether the CTIA output signal is greater than a threshold.

[0009] In some embodiments, the circuit includes an analog input, a charge transimpedance amplifier (CTIA) electrically coupled to the analog input, a quantizer electrically coupled to an output of the CTIA, a digital-to-analog converter (DAC) electrically coupled to an output of the quantizer, and a summer electrically coupled to an output of the DAC. The CTIA is electrically coupled to an output of the summer, a digital filter electrically coupled to the output of the quantizer, and a digital output electrically coupled to the digital filter. In some embodiments, the circuit allows the CTIA to be adaptively and advantageously integrated. As a result, a larger capacitor configured to store the entirety of the sensor charge may no longer be needed and the circuit may be used to read sensors from different array sizes, read different types of sensors, or with different dynamic ranges.

[0010] In some embodiments, the method includes integrating an input signal with a CTIA of the circuit, determining whether a CTIA output signal at an output of the CTIA is greater than a threshold, reducing the CTIA output signal in accordance with a determination that the CTIA output signal is greater than the threshold, and ceasing to reduce the CTIA output signal in accordance with a determination that the CTIA output signal is equal to or less than the threshold. In some embodiments, a non-transitory computer-readable storage medium stores one or more programs, the one or more programs including instructions that, when executed by an electronic device having one or more processors and a memory, cause the device to perform the method.

[0011] In some embodiments, the method advantageously allows the CTIA to be adaptively integrated, such that a larger capacitor configured to store the entirety of the sensor charge may no longer be required in the circuit, and the circuit may be used to read out sensors from different array sizes, different types of sensors, or with different dynamic ranges. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 illustrates an exemplary circuit according to an aspect of the present disclosure. [Diagram 2] FIG. 13 illustrates example waveforms of a circuit in accordance with aspects of the present disclosure. [Diagram 3] FIG. 2 illustrates an exemplary timing diagram according to an aspect of the present disclosure. [Figure 4] FIG. 2 illustrates an exemplary circuit according to an aspect of the present disclosure. [Diagram 5] FIG. 2 illustrates an exemplary circuit according to an aspect of the present disclosure. [Figure 6] FIG. 2 illustrates an exemplary circuit according to an aspect of the present disclosure. [Figure 7] FIG. 1 illustrates an exemplary method according to an aspect of the present disclosure. [Figure 8] 1 illustrates a method for manufacturing a MEMS system, according to one embodiment. [Figure 9] FIG. 1 illustrates an exemplary sensor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS In the following description of the aspects, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific aspects which may be practiced. It is to be understood that other aspects may be utilized and structural changes may be made without departing from the scope of the disclosed aspects.

[0014] 1 illustrates an exemplary circuit 100 according to an embodiment of the disclosure. In some embodiments, the circuit 100 is a data converter and includes a CTIA 102, a quantizer 104 electrically coupled to an output of the CTIA, a digital-to-analog converter (DAC) 106 electrically coupled to an output of the quantizer, and a summer 108 electrically coupled to the DAC and an output of the CTIA. In some embodiments, the circuit 100 is configured to generate a digital output signal 112 (e.g., provided at a digital output 128) that corresponds to an input signal 110 at an input 114 of the circuit. For example, the input 114 is an analog input and the digital output signal 112 is a converted digital value of the analog input.

[0015] Although examples of the present disclosure are described with respect to a CTIA, it is understood that the disclosed circuits are not limited to processing inputs using a CTIA. For example, the disclosed circuits and methods may process inputs using different types of integrating amplifiers or current-to-voltage converters. As another example, more generally, the disclosed circuits and methods may process inputs using different charge measurement circuits. In some aspects, the circuit 100 includes a charge measurement circuit (not shown) in place of the CTIA 102. For example, the charge measurement circuit receives charge at its input (e.g., electrically coupled to the input 114) and generates a signal at its output (e.g., electrically coupled to the quantizer 104) that reflects the amount of charge.

[0016] For example, the input signal 110 is an analog signal and the digital output signal 112 is a digital representation of the input signal 110. In some embodiments, the digital output signal 112 represents an analog sensor readout (e.g., sensor charge, sensor voltage, sensor current), and the digital output signal 112 is provided to another portion of the sensor system for further processing.

[0017] In some embodiments, the digital output signal 112 is a digital value of a charge at the input 114 of the circuit (e.g., the circuit 100 is configured for charge detection). In some embodiments, the digital output signal 112 is a digital value of a current at the input 114 of the circuit (e.g., the circuit 100 is configured for current detection by measuring an input charge over a period of time or integrating an input charge). In some embodiments, the digital output signal 112 is a digital value of a voltage at the input 114 of the circuit (e.g., the circuit 100 is configured for voltage detection). For example, to configure the circuit 100 for voltage detection, a voltage-to-current converter is electrically coupled to the CTIA 102. It will be appreciated that the digital output signal 112 may correspond to other electrical quantities at the input 114 of the circuit 100.

[0018] In some embodiments, when the circuit 100 is configured for current or voltage sensing (e.g., to detect a steady current or voltage), the circuit 100 is operating as a multi-stage noise shaping (MASH) modulator. For example, the circuit 100 may operate as a MASH to measure a steady current (e.g., a noise current, as opposed to a shorter duration transient or signal current from a sensor, which may include larger signal transitions). In some embodiments, while the circuit is operating as a MASH, the quantizer is turned off when the input signal is low enough that it no longer saturates the feedback capacitor to prevent the accumulation of switching noise (e.g., while the circuit is operating as a MASH, the integration of the input signal does not saturate the feedback capacitor). Meanwhile, the pixel remains connected, so that the thermal noise can be reduced by the ADC (e.g., the average noise is reduced).

[0019] In some embodiments, the CTIA 102 includes a feedback capacitor 116, and the input 114 of the circuit is configured to be electrically coupled to a sensor (e.g., a bolometer pixel, an X-ray sensor pixel, a visible image sensor pixel, an infrared image sensor pixel, a MEMS sensor pixel, a sensor pixel that converts information about the environment into an electrical signal), and the capacitance of the feedback capacitor is smaller than the capacitance of the sensor. As an example, the capacitance of the sensor pixel is 2.6 pF, and the capacitance of the feedback capacitor 116 is 0.5 pF. In some embodiments, the capacitance of the feedback capacitor 116 is determined so that the feedback capacitor 116 does not saturate during integration, as described in more detail herein. Exemplary methods of sensor readout can be found in International Publications WO2019204515 and WO2020033930, the disclosures of which are incorporated herein by reference in their entirety for all purposes.

[0020] In some embodiments, the input signal 110 is integrated using the circuit 100. That is, the CTIA 102 integrates portions of the signal 110 (e.g., the charge of a sensor electrically coupled to the CTIA) during different integration times using elements of the circuit 100 and / or methods of operating the disclosed circuit, as described in more detail herein. In some embodiments, if the output of the CTIA is greater than a threshold after a portion of the signal is integrated, the charge on the CTIA is reduced by a value (e.g., by subtracting a fixed value 214 from the CTIA output signal). By integrating portions of the input signal at different times and reducing the CTIA output by a value after integrating the portion, the CTIA can advantageously integrate adaptively. As a result, a larger capacitor configured to store the entire sensor charge is no longer needed. Additionally, as described in more detail below, the CTIA can adaptively integrate such that the timing of integration (e.g., timing of quantizer decision times, timing of feedback times, number of quantizer decision times, number of feedback times) may be adjusted (e.g., for different input signal levels, for different sensitivity or resolution, for different CTIA gains), advantageously allowing circuit 100 to be used for a wider input range (e.g., different types of sensors, different sensor array configurations, different dynamic ranges).

[0021] As an exemplary advantage, the disclosed circuits and methods of operating the circuits may allow for smaller feedback capacitance values ​​compared to the feedback capacitors of conventional CTIAs. For example, integrating the output waveform 204 does not involve integrating portions of the input signal at different times and reducing the CTIA output by a value after integrating the portions. A CTIA described herein (e.g., CTIA 102, CTIA 402, circuit 500, circuit 600) with a smaller feedback capacitor may integrate the same input as a conventional CTIA but without the larger feedback capacitor. Thus, the corresponding output voltage of the CTIA disclosed herein may be higher (e.g., due to the Q=CV relationship), relaxing the resolution or sensitivity requirements of the subsequent circuitry (e.g., ADC). As another exemplary advantage, because the CTIA can adaptively integrate, the disclosed circuits and methods of operating the circuits may accommodate readout of different array sizes, different types of pixels, and / or different dynamic ranges. This may reduce the need for different CTIA designs and reduce the cost of designing specific readout circuits.

[0022] For example, the circuit may have a maximum allowable analog voltage of 3V and a sensor pixel (e.g., an X-ray sensor pixel) with a maximum charge of 8 pC and a capacitance of 2.6 pF. A conventional CTIA may further require a correlated double sampler, which requires two additional capacitors with the same value as the capacitance of the sensor pixel. In this exemplary system, a data conversion circuit using a conventional CTIA requires a capacitance of about 8 pF per channel (e.g., three times 2.6 pF for the feedback capacitor and the two capacitors for correlated double sampling).

[0023] In contrast, if this exemplary system instead uses a data conversion circuit that uses the disclosed CTIA (e.g., CTIA 102, CTIA 402, circuit 500, circuit 600), a 0.5 pF feedback capacitor may be used for the CTIA and a second 0.5 pF capacitor (e.g., offset cancellation capacitor 506, offset cancellation capacitor 610) may be used for offset cancellation, meaning that 1 pF of capacitance is required per channel. In this exemplary system, using a data conversion circuit that includes the disclosed CTIA, the capacitor area can be reduced by a factor of 8.

[0024] Furthermore, because the feedback capacitor of the CTIA described herein may not saturate while being integrated, a smaller feedback capacitor of 0.5 pF may be used to integrate charge beyond the capacity of the conventional CTIA feedback capacitor of 2.6 pF. In some embodiments, the effective capacitance of the CTIA feedback capacitor (e.g., feedback capacitor 116, feedback capacitor 416, feedback capacitor 516, feedback capacitor 616) (e.g., corresponding to the total number of charges that the CTIA feedback capacitor can integrate during an integration described herein) may be determined based on a clock that controls a quantizer (e.g., quantizer 104, quantizer 404). For example, if N1 cycles are available for use by the CTIA (e.g., there are N1 quantizer decision times 210 during integration and there are N1 feedback times 212 during integration), then the effective capacitance of the CTIA feedback capacitor is N1 x (the capacitance of the CTIA feedback capacitor). In some aspects, the number N1 is determined based on the total number N of oversampling ratio (OSR) clock cycles and how the N clock cycles are allocated between the integration time (e.g., integrate 308) and the remainder transform (e.g., remainder transform and remainder transform portion of FIR output 310). As an example, N1=16, and the effective capacitance of the CTIA feedback capacitor is 16×0.5pF=8pF, which means that a CTIA including a 0.5pF feedback capacitor can have three times the charge capacity compared to a conventional CTIA including a 2.6pF feedback capacitor.

[0025] Further, because the CTIA can adaptively integrate, the CTIA (e.g., CTIA102, CTIA402, circuit 500, circuit 600) may be configured to obtain variable gain by varying the integration time, reducing the need for additional feedback capacitors for different gains. In addition, by integrating as described, portions of the input may be converted simultaneously (e.g., a first portion of the input is integrated and then converted while a second portion of the input is integrated), reducing the need for sample-and-hold circuits and additional capacitors without slowing down the conversion speed.

[0026] The area efficiency and flexibility of the disclosed circuits may be advantageously suited for array-type sensors, such as x-ray sensors, bolometers, visible image sensors, infrared image sensors, MEMS sensors, etc., where a set of signals can be read out and converted to digital form. Without hardware modifications, the disclosed circuits can be advantageously configured to convert data of different array sizes, different types of sensors, or different dynamic ranges (e.g., by adjusting the integration time) while at least maintaining the accuracy of a corresponding data conversion circuit that integrates in a conventional manner.

[0027] As yet another exemplary advantage, the impact of thermal noise (e.g., from the parasitic capacitance of the sensor array) on the disclosed circuitry may be lower due to the sigma-delta oversampling (e.g., by integrating, i.e., by using a sigma-delta converter in ADC 118, as described herein) performed by the disclosed circuitry as compared to the higher bandwidth sample-and-hold circuits used to capture the output of conventional CTIAs.

[0028] In some embodiments, the CTIA 102 includes a reset switch 126 electrically coupled in parallel with the feedback capacitor 116. In some embodiments, before the sensor pixel begins transferring charge to the CTIA (e.g., during feedback capacitor reset 302), the feedback capacitor 116 is reset by the reset switch 126, which is closed (e.g., during feedback capacitor reset 302) to remove any residual charge on the feedback capacitor (e.g., resetting the value of the output of the CTIA (e.g., leaving the output at an offset value)).

[0029] In some aspects, the quantizer 104 is configured to determine whether the CTIA output signal at the output of the CTIA is greater than a threshold. In response to a determination that the CTIA output signal is greater than the threshold, the quantizer 104 outputs a first digital value (e.g., to the DAC 106, to the finite impulse response (FIR) decimator 122). In response to a determination that the CTIA output signal is equal to or less than the threshold, the quantizer 104 outputs a second digital value (e.g., to the DAC 106, to the FIR decimator 122). In some aspects, during integration, the output of the quantizer 104 outputs a binary sequence (e.g., the quantizer output waveform 208) based on the quantizer comparison result.

[0030] In some aspects, the threshold is set to provide a margin or headroom for the integrator output voltage, for example, the threshold prevents the CTIA 102 from saturating while still effectively utilizing the dynamic range of the amplifier (e.g., the threshold does not cause premature reduction of the input signal).

[0031] In some embodiments, the threshold is set based on the capacitance of the feedback capacitor 116. For example, the threshold is less than a level corresponding to the charge storage capacity of the feedback capacitor 116. In some embodiments, the threshold of the quantizer 104 is adjustable based on an input electrically coupled to the circuit 100, allowing the circuit 100 to be used for different sensor array sizes, different types of sensors, and / or different dynamic ranges.

[0032] In some aspects, the quantizer 104 is a comparator. In some aspects, the quantizer 104 performs a comparison of the output of the CTIA to a threshold during a quantizer decision time of the integral, as described in more detail herein.

[0033] As an example, during a quantizer decision time, the quantizer 104 compares the output of the CTIA 102 to a threshold value. If the output level of the CTIA 102 is greater than the threshold value, the quantizer 104 outputs a "high" signal to the DAC 106, and if the output level is equal to or less than the threshold value, the quantizer 104 outputs a "low" signal to the DAC 106.

[0034] In some aspects, the DAC 106 is configured to output a high DAC output signal (e.g., a signal that reduces the CTIA output signal by a value (e.g., a fixed value 214) during integration) to the summer 108 in response to receiving a first digital value from the quantizer 104. In some aspects, the high DAC output signal is this value (e.g., the high DAC output signal is a charge corresponding to a value (e.g., a charge corresponding to a reduced voltage) that reduces the charge from the feedback capacitor and reduces the CTIA output level by this value). In response to receiving a second digital value, the DAC 106 ceases to output the high DAC output signal to the summer 108. For example, if the quantizer 104 outputs a "high" signal to the DAC 106, the DAC 106 outputs the high DAC output signal to the summer 108. If the quantizer 104 outputs a "low" signal to the DAC 106, the DAC 106 ceases to output the high DAC output signal to the summer 108.

[0035] As an example, the CTIA output voltage ranges from 0V to 3.3V (e.g., the analog voltage rail is 3.3V). The quantizer threshold can be set to 2.8V, which is 2.3V. That is, in response to a determination that the CTIA output voltage is greater than the threshold, the DAC outputs a high DAC output signal, and in response to the high DAC output signal being output, the circuit reduces the output voltage by 2.3V. It will be understood that these values ​​are merely exemplary and that different output voltage values, quantizer thresholds, and DAC output values ​​may be set.

[0036] In some aspects, the DAC 106 ceases providing an output when the quantizer 104 outputs a “low” signal to the DAC 106. As an exemplary advantage, by ceasing to provide an output when the quantizer 104 outputs a “low” signal to the DAC 106, noise charge (e.g., from charge injection) may be minimized when the quantizer 104 outputs a “low” signal to the DAC 106.

[0037] In some embodiments, the CTIA 102 includes a feedback capacitor 116, which is configured to store a total charge. The CTIA output signal is reduced by a value (e.g., the fixed value 214) that corresponds to a charge that is less than the total charge that the feedback capacitor 116 is configured to store. For example, the value (e.g., the fixed value 214) by which the CTIA output signal is reduced is an amount that is less than the difference between a voltage level corresponding to the charge storage capacity of the feedback capacitor 116 and a threshold level of the quantizer 104.

[0038] In some aspects, the quantizer 104 and the DAC 106 are combined into one component. For example, the combined quantizer and DAC is configured to output the result of the comparison of the output of the CTIA with a threshold and a high DAC output signal.

[0039] In some aspects, the summer 108 is configured to reduce the output signal of the CTIA 102 by a value (e.g., fixed value 214) corresponding to the high DAC output signal in response to receiving the high DAC output signal from the DAC 106. For example, (e.g., as shown by the CTIA waveform 206), a portion of the input signal is integrated and then an amount corresponding to this value (e.g., fixed value 214) is reduced from the CTIA output. The portions of the input signal are integrated at different times. The amount corresponding to this value is reduced each time the integrated portion (e.g., the CTIA output) exceeds the threshold of the quantizer 104 to prevent the feedback capacitor 116 from saturating. As described in more detail below, portions of the input signal are integrated and the output of the CTIA is reduced in this manner until a final portion of the input signal remains below the threshold level of the quantizer 104, which final portion is the remainder (e.g., residual charge, residual voltage, remainder 216) of the CTIA 102.

[0040] In some aspects, the summer 108 is electrically coupled to terminals of the feedback capacitor 116 (e.g., at the input of the CTIA, at the output of the CTIA) and reduces the CTIA output signal by reducing the voltage at the terminals. In some aspects, the summer 108 is electrically coupled to additional circuit components and, in response to receiving a signal from the summer 108 to reduce the CTIA output signal, these additional circuit components reduce the CTIA output signal.

[0041] Although adder 108 is illustrated as shown in Figure 1, it will be understood that the illustration is merely exemplary. Adder 108 may be electrically coupled in a manner different than that shown. For example, adder 108 may be electrically coupled to the output of the CTIA to subtract a value from the output of the CTIA.

[0042] In some aspects, the circuit 100 includes an ADC 118 electrically coupled to the output of the CTIA 102. The ADC 118 is configured to receive a voltage corresponding to the residual voltage or charge at the output of the CTIA 102 and generate a digital value corresponding to the residual voltage or charge. In some aspects, the digital output signal 112 includes a digital value corresponding to the remainder (e.g., a binary sequence generated from the digital value of the residual voltage or charge and the quantizer output is processed (e.g., by the FIR decimator 122) to generate the digital output signal 112). In some aspects, the ADC 118 is a sigma-delta ADC.

[0043] In some aspects, the voltage corresponding to the residual charge (e.g., the voltage of the CTIA output 206 near the end of integration, the residual voltage, remainder 216) is below a threshold (e.g., threshold 218) of the quantizer 104. For example, the portion of the input signal is integrated and reduced in the described manner until a portion of the input signal remains below the threshold level of the quantizer 104 near the end of integration, which is the residual voltage or residual charge of the CTIA 102. The ADC 118 receives the voltage corresponding to the residual charge and converts the residual voltage or residual charge to a digital signal that is provided to an input of the FIR decimator 122, which is described in more detail herein.

[0044] In some aspects, the circuit 100 includes an offset removal circuit 120 configured to remove an offset from the output of the CTIA 102. For example, the offset removal circuit 120 captures an offset value that is subtracted from a voltage corresponding to a residual charge or voltage before being provided to the ADC 118 to remove the offset from the digital output signal 112 and improve the accuracy of the data conversion of the circuit 100.

[0045] In some embodiments, the offset removal circuit 120 is configured for correlated double sampling. After the reset switch 126 resets the feedback capacitor 116 (e.g., after feedback capacitor reset 302), random noise may be sampled. In some embodiments, the capacitance of the sensor string may be large, and the noise may be thermal noise in the parasitic string elements, which may cause random charge values. The standard deviation of this random charge is May be approximately equal to TIFF2024502327000002.tif6128.

[0046] In some embodiments, to remove this random noise, the output of the CTIA is measured (e.g., measured multiple times and averaged) by the offset removal circuit 120 measuring the noise charge once at or before the start of integration and measuring the integrated signal or residual plus noise charge once at the end or after integration is completed. The difference between these two measurements (e.g., the difference between these two measurements excludes the offset) is converted to a digital value using the ADC 118 (e.g., a sigma-delta converter). For example, without using the disclosed offset removal circuit and method, the offset is 4 mV. When the disclosed offset removal circuit and method (e.g., offset removal circuit 120, circuit 400, circuit 500, circuit 600) is used, the offset is reduced to 1.5 mV.

[0047] In some aspects, the CTIA can adaptively integrate such that the sensitivity (e.g., resolution) of the circuit 100 is based on the operating frequency of the circuit, which in turn is based on the integration time of the CTIA 102. By having sensitivity adjustability based on the operating frequency, the circuit can be advantageously used in a wider range of applications (e.g., the circuit is suitable for both low and high resolution systems).

[0048] For example, by increasing the frequency of integration (e.g., shortening the time between integration of the first and second portions of the input signal, shortening the timing between the quantizer decision time 210 and the feedback time 212), the sensitivity (e.g., resolution) of the circuit 100 is improved. Conversely, by decreasing the frequency of integration (e.g., extending the time between integration of the first and second portions of the input signal, extending the timing between the quantizer decision time 210 and the feedback time 212), the sensitivity (e.g., resolution) of the circuit 100 is decreased. The relationship between integration time, frequency, and sensitivity of the disclosed circuits is described in more detail with respect to FIGS. 2 and 3.

[0049] In some embodiments, the circuit 100 includes a variable resistor (not shown) (e.g., a MOS transistor) electrically coupled to the input of the circuit, the variable resistor configured to provide a reduced current level to the input of the circuit to prevent the feedback capacitor from saturating.

[0050] For example, a sensor that accumulates a charge corresponding to the data being sensed that is being read out begins to discharge. During this time (e.g., t=0), the resistance of the variable resistor is at an initial resistance (e.g., R0) and the sensor is electrically coupled to the variable resistor. As time passes during this discharge time, the resistance of the variable resistor decreases from R0. By the end of the discharge time (e.g., t=T, when the sensor has completed discharging), the resistance decreases linearly from R0 to 0. In some embodiments, T is the duration of the integration 308. In some embodiments, T is the duration of the sensor readout 306. In some embodiments, T is a fraction of the duration of the sensor readout 306. In some embodiments, the discharge time window is several times longer than the rise time of a signal that turns on a comparable MOS transistor. Thus, reducing the resistance of the variable resistor over the discharge time window may be different from simply turning on a transistor. For example, the discharge time window is in the microsecond range and the rise time of the signal that turns on the MOS transistor is in the nanosecond range. The resistance of the variable resistor can be calculated as follows: TIFF2024502327000003.tif9128

[0051] In some embodiments, a control voltage is electrically coupled to the gate of the MOS variable resistor to control the resistance, and increases the drain-source transconductance from low to high (i.e., the resistance decreases from high to low) every row time during readout (e.g., by increasing the gate voltage). As explained in the above formula, the resistance of the variable resistor decreases linearly from t=0 to t=T, where the resistance (e.g., R(0)) at t=0 is R0, the initial resistance, and after t=0, the resistance decreases linearly as explained with respect to the formula, where the resistance (e.g., R(T)) approaches substantially 0 at t=T.

[0052] Although equation (1) indicates that in the ideal case, R(t) reaches 0 at t=T, it is understood that the components used to implement the variable resistor may not reach a resistance of 0 exactly at the end of the discharge time window. In some embodiments, this resistance is the minimum resistance of the variable resistor. For example, if the variable resistor is a MOS transistor, the minimum resistance is determined by the conductance of the transistor (e.g., the "on" resistance of the transistor).

[0053] The capacitance of the sensor can be expressed as C. The current into the variable resistor can be calculated as follows: TIFF2024502327000004.tif10128

[0054] By solving for V(t), the voltage across the variable resistor as a function of time can be calculated. TIFF2024502327000005.tif12128

[0055] The current I(t) flowing through the variable resistor can be expressed as follows: TIFF2024502327000006.tif19128

[0056] As shown in equation (4), if the discharge time window T is set to be equal to the initial time constant (e.g., T=C×R0), the current output can be made substantially constant (e.g., I=V(0) / R0). Thus, in some embodiments, R0 of the variable resistor is determined by the effective capacitance of the sensor (e.g., 1-5 pF) and the discharge time window (e.g., the time to read out one row of the sensor). By converting the discharge current to a constant current, the peak currents associated with the transient sensor readout signal can be reduced and prevents the feedback capacitor 116 from being saturated by high currents.

[0057] In some embodiments, instead of linearly changing the resistance of the variable resistor over the sensor discharge time as described above, the resistor (e.g., a MOS transistor) is driven by a two-state voltage. When driven by a first voltage of the two states, the resistor has a low impedance, and when driven by a second voltage of the two states, the resistor has a high impedance. In some embodiments, when the signal associated with the input is at a high level (e.g., due to the transient nature of the input signal), the variable resistor is set to have a high impedance by driving the variable resistor with a second voltage. The waveform of the signal can be advantageously reduced, slowing the signal propagation speed (e.g., the rate at which the feedback capacitor is charged) and preventing the feedback capacitor from saturating (e.g., reducing the need for a larger feedback capacitor). After the signal amplitude decreases to a lower level (e.g., due to the transient nature of the sensor discharge), the variable resistor is set to have a low impedance by driving the variable resistor with a first voltage to increase the signal propagation speed (e.g., the rate at which the feedback capacitor is charged).

[0058] In some embodiments, the circuit 100 includes a digital filter. In some embodiments, the digital filter is electrically coupled to the output of the quantizer 104. It is understood that the digital filter may perform operations other than digital filtering. For example, the digital filter is configured to decode a pulse code modulation (PCM) sequence from the quantizer output 104 and / or the ADC 118. As another example, the digital filter is configured to combine signals from the quantizer output 104 and the ADC 118 to generate the digital output signal 112 at the digital output 128.

[0059] In some aspects, the digital filter includes an FIR decimator 122 (e.g., the FIR decimator 122 is electrically coupled to the output of the quantizer 104), where the FIR decimator 122 is configured to receive a signal from the output of the quantizer 104. In some aspects, the FIR decimator 122 is further configured to receive a digital value corresponding to the residual charge or residual voltage at the output of the CTIA 102 (e.g., from the ADC 118). For example, the FIR decimator receives a signal from the output of the quantizer 104 (e.g., a binary sequence representing the input signal 110, from integrating the CTIA 102, the quantizer output waveform 208) or a signal from the output of the quantizer 104 (e.g., a binary sequence representing the input signal 110 without the remainder, from integrating the CTIA 102, the quantizer output waveform 208) and a digital value corresponding to the CTIA residual charge or residual voltage from the ADC 118, filters these inputs, and provides a digital output signal 112 (e.g., at the digital output 128) that more accurately represents the input signal 110.

[0060] In some aspects, the FIR decimator combines the output from the CTIA 102 (e.g., representing the integration result) with the output from the ADC 118 (e.g., representing the CTIA remainder). For example, a set of PCM sequences is created from the CTIA 102 (e.g., the PCM sequences are generated at the output of the quantizer 104 based on the quantizer result (e.g., the quantizer output waveform 208)) and the ADC 118 outputs for the possible input signal 110 levels. A vector determinant (e.g., Equation (5) and Equation (6)) may be set. This equation relates the PCM sequence processed by the FIR tap coefficients to be equal to the corresponding analog input signal value. In some aspects, the input signal is obtained from the output of the CTIA 102 and the ADC 118 using the following equation: TIFF2024502327000007.tif5128 where A1 is the PCM sequence for CTIA102, A2 is the PCM sequence of ADC118, C1 is the CTIA102 FIR filter coefficients, normalized to a sum of 1. C2 is the FIR filter coefficients for the SD modulator, normalized to a sum of 1; g2 is the weight applied to the ADC PCM sequence (to be added to the CTIA PCM sequence), g1 is the gain of the digital output signal 112 with respect to the input signal 110; μ 0 is the offset of the digital output signal 112 relative to the input signal 110 .

[0061] In some embodiments, μ is a quantity such as charge, current, voltage, etc. It is understood that the disclosed coefficient determination methods are not limited to quantities that can be read by circuit 100. In some embodiments, μ is temperature, pressure, or x-ray dose, depending on the particular application, and the degrees of freedom built into coefficients C1 and C2 can help linearize other aspects of the system beyond the disclosed circuits.

[0062] In some aspects, the coefficients associated with the FIR decimator 122 (e.g., the coefficients of an FIR filter) are determined using at least one of analytical determination, numerical determination based on simulation, and numerical determination based on measurement.

[0063] For example, C1 and C2 are linear optimal FIR coefficients determined using at least one of analytical determination, numerical determination based on simulation, and numerical determination based on measurement. In some embodiments, the number of coefficients of C1 is the number of cycles of the CTIA (e.g., cycles of the quantizer decision time and the feedback time), and the number of coefficients of C2 is the number of oversampling (OSR) cycles of the SD modulator. Using analytical determination (e.g., theoretical analysis), constants of C1 and accumulation filters of C2 may be used. These filter coefficients may be used as default values. More optimal filter coefficients may use numerical determination based on simulation and numerical determination based on measurement for more specific circuit implementation.

[0064] Using a numerical determination based on simulation (e.g., numerical simulation), the coefficients will more closely reflect the structure of the circuit. Using a numerical determination based on measurement (e.g., based on experimentation), the coefficients can also be found to be optimal for a particular chip incorporating noise and systematic errors (e.g., op-amp non-idealities, device mismatches). In some embodiments, these coefficients are determined before operating the circuit 100 (e.g., during manufacturing of the circuit 100, before operating a system including the circuit 100). In some embodiments, these coefficients are determined or updated while operating the circuit 100 (e.g., calibration may be performed to determine more suitable coefficients). In some embodiments, the circuit 100 is calibrated in wafer form, as a packaged chip, or using a probe card embedded in a detection system to provide an optimal decimation filter. In some embodiments, the variables (e.g., coefficient weights) of equation (5) are calibrated by operating the circuit 100 without an input signal (e.g., integrating with a CTIA without an input signal).

[0065] In some embodiments, in the simulation-based numerical determination and the measurement-based numerical determination, the input analog values ​​(μ1, μ2, ..., μ N ) is output (A11, A12, …, A1 N ), (A21, A22, …, A2 N ). The number N is equal to or greater than the number of parameters to be determined, which is the number of components in C1 + the number of components in C2 + 3 (e.g., for g1, g2, μ0). A numerical method such as a least-squares fit is used to determine C1, C2, g1, g2, μ0 and the linear transformation from output to input. TIFF2024502327000008.tif18128

[0066] In some aspects, depending on the parameters (e.g., fewer parameters) of the chip fabrication, the simulation-based numerical determination is advantageously a simpler way to determine the coefficients. In some aspects, the simulation-based numerical determination sets the default coefficients for the system, and the measurement-based numerical determination is used for more accurate values.

[0067] In some embodiments, depending on the parameters (e.g., more parameters) of the chip manufacturing, the measurement-based numerical determination is performed during wafer probe characterization of ASICs having on-chip test circuits, such as stable reference voltage levels. When the chip manufacturing parameters are more complex, the coefficients can be determined more accurately by using the measurement-based numerical determination.

[0068] In some embodiments, the C1 and C2 FIR coefficients are treated as independent variables, and in some examples, the number of independent variables is reduced. For example, in charge measurements, C1 is a constant and C2 is non-zero while the ADC 118 is operating (e.g., while the residual value is being converted). In some examples, further constraints, such as continuity, are applied to further reduce the number of independent variables and reduce the complexity of determining the optimal FIR coefficients.

[0069] In some aspects, the circuit 100 includes a timing and control circuit 124 that provides timing and control signals for operating elements of the circuit 100. For example, the timing and control circuit 124 is electrically coupled to the quantizer 104, the ADC 118, the offset removal circuit 120, and the FIR decimator 122 to control their respective timing. As another example, the timing and control circuit 124 generates timing and control signals for generating the waveforms and timing diagrams described with respect to Figures 2 and 3. The timing and control circuit 124 may provide timing and control signals for other elements of the circuit 100 (e.g., the CTIA 102, the DAC 106, the summer 108).

[0070] Although the circuit 100 is described with the elements shown, it is understood that the diagram is merely exemplary. Different or additional elements may be added or removed from the circuit 100 to form the disclosed data converter. The elements described may be electrically coupled or configured differently than as shown. For example, the offset removal circuit 120 may be electrically coupled differently than as shown in FIG. 1. The offset removal circuit may be included as part of a CTIA, as described with respect to FIGS. 5 and 6. As another example, although the circuit 100 is shown as converting a single-ended signal, it is understood that the circuit 100 may convert a differential signal (e.g., the elements of the circuit 100 are configured for differential signaling). As yet another example, the circuit 100 may not include a digital filter or FIR decimator 122, and the output of the quantizer 104 and / or the ADC 118 may provide a digital output signal 112, which is output to a subsequent component for further processing.

[0071] As another example, although circuit 100 is shown including a first order CTIA in the first stage and an ADC (e.g., a second order sigma-delta converter) in the second stage, other options for the order of the CTIA or ADC and quantizer options (e.g., single bit vs. multi-bit) may be included in circuit 100. These options may be determined by system requirements (e.g., accuracy, area, sensor type, sensor array size). For example, circuit 100 described with respect to FIG. 1 may be a simpler architecture that may be advantageous for larger sensor arrays where area efficiency may be a significant constraint.

[0072] FIG. 2 illustrates exemplary waveforms of a circuit according to an embodiment of the disclosure. In some embodiments, FIG. 2 illustrates exemplary waveforms of circuit 100, circuit 400, circuit 500, or circuit 600. In some embodiments, the waveforms include an input waveform 202, a conventional CTIA output waveform 204, a CTIA output waveform 206, and a quantizer output waveform 208. In some embodiments, the input waveform 202 is a waveform of an input signal (e.g., input current, input signal 110, input signal 410), the CTIA output waveform 206 is a waveform of a CTIA (e.g., the output voltage of the CTIA 102, the output voltage of the CTIA 402, the output voltage of the circuit 500, the output voltage of the circuit 600), and the quantizer output waveform 208 is a waveform of an output of a quantizer (e.g., the voltage output of the quantizer 104, the voltage output of the quantizer 404). The conventional CTIA output waveform 204 is a waveform (e.g., voltage output) of the output of the CTIA without the described integration used to integrate a signal corresponding to the input waveform 202, and is included for illustrative purposes to show the advantages of the CTIA.

[0073] In some aspects, the operation of the circuit 100 is divided into a quantizer decision time 210 (shown by a lighter vertical dashed line) and a feedback time 212 (shown by a thicker vertical dashed line). In some aspects, a timing and control circuit (e.g., timing and control circuit 124, timing and control circuit 424) provides control signals for these times in the circuit. For example, the timing and control circuit generates a 50% duty cycle square wave clock signal whose rising edge is aligned with the quantizer decision time 210 to control the quantizer decision, and generates the complement of this clock whose rising edge is aligned with the feedback time 212 to control the feedback that reduces the value. It is understood that the clock signals may have different duty cycles and have different shapes.

[0074] As shown, prior to the first quantizer decision time 210A, the input (e.g., corresponding to the input waveform 202, the input of the CTIA, the input signal 110, the input signal 410) charges the feedback capacitor (e.g., the feedback capacitor 116, the feedback capacitor 416, the feedback capacitor 516, the feedback capacitor 616), causing the output of the CTIA to rise. At the first quantizer decision time 210A, the value of the CTIA output waveform 206 is compared to a threshold value 218 (e.g., the threshold value of the quantizer 104 or the quantizer 404). In some aspects, the quantizer compares the value of the CTIA output waveform 206 to the threshold value 218. As shown, at the first quantizer decision time 210A, in accordance with a determination that the CTIA output waveform 206 is equal to or less than the threshold value 218, the quantizer output waveform 208 is a "low" value (e.g., 0, ground, low logic voltage level).

[0075] Between the first quantizer decision time 210A and the first feedback time 212A, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. During the first feedback time 212A, as shown, the DAC (e.g., DAC 106, DAC 406) receives the quantizer decision, and in accordance with the quantizer decision that the CTIA output waveform 206 is below the threshold 218, the DAC does not output a high DAC output signal to the summer (e.g., summer 108, summer 408) (e.g., the circuit ceases reducing the high DAC output signal from the output of the CTIA).

[0076] Between the first feedback time 212A and the second quantizer decision time 210B, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. At the second quantizer decision time 210B, the value of the CTIA output waveform 206 is compared to a threshold value 218 (e.g., a threshold value of the quantizer 104 or the quantizer 404). As shown, at the second quantizer decision time 210B, in accordance with a determination that the CTIA output waveform 206 is greater than the threshold value 218, the quantizer output waveform 208 is a "high" value (e.g., a 1, a high supply value, a high logic voltage level).

[0077] Between the second quantizer decision time 210B and the second feedback time 212B, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. During the second feedback time 212B, as shown, the DAC receives the quantizer decision, and in accordance with the quantizer decision that the CTIA output waveform 206 is greater than the threshold 218, the DAC outputs a high DAC output signal to the summer. A value (e.g., a fixed value 214) is reduced from the output of the CTIA. This reduces the value of the CTIA output waveform 206 by the fixed value 214 during the second feedback time 212B. Although the CTIA output signal is described as being reduced by a fixed value, it will be appreciated that in some aspects, during integration, the CTIA output signal may be reduced by different values ​​at different times of integration.

[0078] Between the second feedback time 212B and the third quantizer decision time 210C, after reducing the value of the CTIA output waveform 206 by a fixed value 214, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. At the third quantizer decision time 210C, the value of the CTIA output waveform 206 is compared to a threshold value 218 (e.g., a threshold value of the quantizer 104 or quantizer 404). As shown, at the third quantizer decision time 210C, in accordance with a determination that the CTIA output waveform 206 is greater than the threshold value 218, the quantizer output waveform 208 is a "high" value (e.g., 1, a high supply value, a high logic voltage level).

[0079] Between the third quantizer decision time 210C and the third feedback time 212C, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. During the third feedback time 212C, as shown, the DAC receives the quantizer decision, and in accordance with the quantizer decision that the CTIA output waveform 206 is greater than the threshold 218, the DAC 106 outputs a high DAC output signal to the summer. A value (e.g., a fixed value 214) is reduced from the output of the CTIA. This causes the value of the CTIA output waveform 206 to be reduced by value 214 during the third feedback time 212C.

[0080] As shown, because the value of the input waveform 202 is the same between the second feedback time 212B and the fourth feedback time 212D, the value of the CTIA output waveform 206 between the third feedback time 212D changes similarly to how the CTIA output waveform 206 changes between the second feedback time 212C and the third feedback time 212C.

[0081] As shown, at the fourth feedback time 212D, the value of the input waveform 202 is reduced from its initial value. Thus, between the fourth feedback time 212D and the fifth quantizer decision time 210E, after reducing the value of the CTIA output waveform 206 by the fixed value 214, the input continues to charge the feedback capacitor and raise the output of the CTIA, but at a slower rate compared to the previous rate (e.g., because the initial value of the input is a higher value than this current value of the input). At the fifth quantizer decision time 210E, the value of the CTIA output waveform 206 is compared to a threshold value 218 (e.g., the threshold value of the quantizer 104 or quantizer 404). As shown, at the fifth quantizer decision time 210E, in accordance with the determination that the CTIA output waveform 206 is greater than the threshold value 218, the quantizer output waveform 208 is a "high" value (e.g., 1, a high supply value, a high logic voltage level).

[0082] Between the fifth quantizer decision time 210E and the fifth feedback time 212E, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise (at this slower rate). At the fifth feedback time 212E, as shown, the DAC receives the quantizer decision, and in accordance with the quantizer decision that the CTIA output waveform 206 is greater than the threshold 218, the DAC outputs a high DAC output signal to the summer. A value (e.g., a fixed value 214) is reduced from the output of the CTIA. This reduces the value of the CTIA output waveform 206 by the fixed value 214 at the fifth feedback time 212E.

[0083] Between the fifth feedback time 212E and the sixth quantizer decision time 210F, after reducing the value of the CTIA output waveform 206 by a fixed value 214, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. At the sixth quantizer decision time 210F, the value of the CTIA output waveform 206 is compared to a threshold value 218 (e.g., a threshold value of the quantizer 104 or quantizer 404). As shown, at the fifth quantizer decision time 210E, in accordance with a determination that the CTIA output waveform 206 is less than or equal to the threshold value 218, the quantizer output waveform 208 is a "low" value (e.g., 0, ground, a low logic voltage level).

[0084] Between the sixth quantizer decision time 210F and the sixth feedback time 212F, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. At the sixth feedback time 212F, as shown, the DAC receives the quantizer decision, and in accordance with the quantizer decision that the CTIA output waveform 206 is below the threshold 218, the DAC does not output a high DAC output signal to the summer (e.g., the circuit ceases reducing the high DAC output signal from the output of the CTIA).

[0085] Between the sixth feedback time 212F and the seventh quantizer decision time 210G, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. At the seventh quantizer decision time 210G, the value of the CTIA output waveform 206 is compared to a threshold value 218 (e.g., the threshold value of the quantizer 104). As shown, at the seventh quantizer decision time 210G, in accordance with a determination that the CTIA output waveform 206 is greater than the threshold value 218, the quantizer output waveform 208 is a "high" value (e.g., one, a high supply value, a high logic voltage level).

[0086] Between the seventh quantizer decision time 210G and the seventh feedback time 212G, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. At the seventh feedback time 212G, as shown, the DAC receives the quantizer decision, and in accordance with the quantizer decision that the CTIA output waveform 206 is greater than the threshold 218, the DAC outputs a high DAC output signal to the summer. A value (e.g., a fixed value 214) is reduced from the output of the CTIA. This reduces the value of the CTIA output waveform 206 by the fixed value 214 at the seventh feedback time 212G.

[0087] Between the seventh feedback time 212G and the eighth quantizer decision time 210H, after reducing the value of the CTIA output waveform 206 by a fixed value 214, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. At the eighth quantizer decision time 210H, the value of the CTIA output waveform 206 is compared to a threshold value 218 (e.g., the threshold value of the quantizer 104). As shown, at the eighth quantizer decision time 210H, in accordance with a determination that the CTIA output waveform 206 is less than or equal to the threshold value 218, the quantizer output waveform 208 is a "low" value (e.g., 0, ground, a low logic voltage level).

[0088] Between the eighth quantizer decision time 210H and the eighth feedback time 212H, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. At the eighth feedback time 212H, as shown, the DAC receives the quantizer decision, and in accordance with the quantizer decision that the CTIA output waveform 206 is below the threshold 218, the DAC does not output a high DAC output signal to the summer (e.g., the circuit ceases reducing the high DAC output signal from the output of the CTIA).

[0089] As shown, at the eighth feedback time 212H, the value of the input waveform 202 is reduced to zero (e.g., the electrically coupled sensor finishes discharging and the readout of the electrically coupled sensor is completed). Thus, after the eighth feedback time 212H, the feedback capacitor stops charging, forcing the output of the CTIA to a constant value. In some aspects, this constant output of the CTIA 102 after the eighth feedback time 212H is a remainder (e.g., remainder 216, a residual voltage, a voltage corresponding to a residual charge). In some aspects, an ADC (e.g., ADC 118, ADC 418) receives the remainder, converts the remainder to a digital value, and provides the digital value of the remainder to an FIR decimator (e.g., FIR decimator 122, FIR decimator 422).

[0090] By integrating portions of the input signal at different times and reducing the CTIA output by a value (e.g., a fixed value 214) after integrating the portions, the CTIA can adaptively integrate advantageously. As an exemplary advantage, as shown by the difference between the conventional CTIA output waveform 204 and the CTIA output waveform 206 (e.g., the feedback capacitor of a conventional CTIA continues to charge until the input is zero), the disclosed circuit and method of operating the circuit may allow for a smaller feedback capacitance value compared to the feedback capacitor of a CTIA that integrates in a conventional manner. A CTIA with a smaller feedback capacitor may be able to integrate the same input as a conventional CTIA with a larger feedback capacitor. Thus, the corresponding output voltage may be higher (e.g., due to the Q=CV relationship), relaxing the resolution or sensitivity requirements of the subsequent circuitry (e.g., an ADC). As another exemplary advantage, because the CTIA can adaptively integrate, the disclosed circuit and method of operating the circuit may accommodate readout of different array sizes, different types of pixels, and / or different dynamic ranges, reducing the need for different CTIAs and reducing the cost of designing specific readout circuitry.

[0091] Further, because the CTIA can adaptively integrate, the CTIA may be configured to obtain variable gain by varying the integration time (e.g., by varying the timing between the quantizer decision time 210 and the feedback time 212), reducing the need for additional feedback capacitors for different gains. In addition, by integrating as described, portions of the input may be converted simultaneously (e.g., a first portion of the input is integrated and then converted while a second portion of the input is integrated), reducing the need for sample-and-hold circuits and additional capacitors without slowing down the conversion speed.

[0092] The area efficiency and flexibility of the disclosed circuits (e.g., enabled by operating the circuits using the disclosed methods) may be advantageously suited to array-type sensors, such as x-ray sensors, visible image sensors, infrared image sensors, MEMS sensors, etc., where a set of signals can be read out and converted to digital form. Without hardware modifications, the disclosed circuits can be advantageously configured to convert data of different array sizes, different types of sensors, or different dynamic ranges (e.g., by adjusting the timing between the quantizer decision time 210 and the feedback time 212) while maintaining the accuracy of a corresponding data conversion circuit that integrates in a conventional manner.

[0093] Although the waveforms in FIG. 2 are shown as having a particular relationship with time, it is understood that the illustrated waveforms are exemplary. The waveforms may have a different relationship with time than that shown. For example, the input waveform 202 may have a different relationship with time than that shown (e.g., exponential decay, a constant value (e.g., by using a variable resistor as disclosed at the input of the circuit), a relationship that depends on the electrical characteristics of the sensor pixel (e.g., sensor pixel capacitance, sensor pixel impedance) and / or the sensor array (e.g., sensor column capacitance, sensor column impedance), a relationship that depends on the readout method). Based on the input waveform 202 and the integration described, the CTIA output waveform 206 and the quantizer output waveform 208 are generated accordingly. As another example, the timing of the integration (e.g., timing of the quantizer decision time 210, timing of the feedback time 212) may be different from that shown based on the system requirements (e.g., sensitivity, resolution, power consumption) and application (e.g., sensor array size, type of sensor).

[0094] 3 illustrates an example timing diagram 300 according to an embodiment of the disclosure. In some embodiments, the timing diagram 300 is an illustration of the operation of the circuit 100, the circuit 400, the circuit 500, or the circuit 600. In some embodiments, the timing diagram 300 includes five sections: a feedback capacitor reset 302, an offset removal 304, a sensor readout 306, an integration 308, and a residue transform and FIR output 310.

[0095] For example, for a sensor array with 512 rows with a frame refresh rate of 30 Hz, the corresponding row time is 65 μs. In this example, the feedback capacitor reset 302 time is 2 μs, the offset removal 304 time is 10 μs, the integration 308 time is 12 μs, and the remainder conversion and FIR output 310 time is 40 μs. For example, for a 3.2 MHz clock, an offset removal time of 10 μs means that 32 samples are taken during offset removal 302, and a remainder conversion and FIR output time of 40 μs means that 128 samples are taken by the ADC (e.g., ADC118, ADC418).

[0096] In some embodiments, during feedback capacitor reset 302, before the sensor pixel begins transferring charge to the CTIA, the feedback capacitor of the CTIA (e.g., feedback capacitor 116, feedback capacitor 416, feedback capacitor 516, feedback capacitor 616) is reset by a reset switch (e.g., reset switch 126, reset switch 426, reset switch 514, reset switch 620) by closing during feedback capacitor reset 302 time to remove any residual charge on the feedback capacitor (e.g., reset the value of the output of the CTIA (e.g., leave the output at an offset value)).

[0097] In some aspects, the offset of the CTIA is removed during offset removal 304. For example, during offset removal 304, an offset removal circuit (e.g., offset removal circuit 120, circuit 400) captures an offset value, which is subtracted from the residual charge or voltage before being provided to an ADC (e.g., ADC 118, ADC 418) to remove the offset from the digital output signal (e.g., digital output signal 112, digital output signal 412) and improve the accuracy of the data conversion of the circuit.

[0098] In some aspects, during offset removal 304, correlated offset removal is performed. For example, the offset removal circuit is configured for correlated double sampling. After the reset switch resets the feedback capacitor (e.g., after feedback capacitor reset 302), random noise may be measured. To remove this random noise, the output of the CTIA is measured (e.g., measured multiple times and averaged) by the offset removal circuit measuring the noise charge once at or before the start of integration and measuring the integrated signal or residual plus noise charge once at the end or after integration is completed. The difference between these two measurements (e.g., the difference between these two measurements excludes the offset) is converted to a digital value using the ADC 118 (e.g., a sigma-delta converter).

[0099] In some aspects, during offset removal 304, the ADC of the circuit (e.g., ADC 118, ADC 418) is configured to convert the offset of the CTIA (e.g., an average value of the offset over multiple samples) to a digital value. A value corresponding to the converted offset is removed from the output signal to better remove the offset component from the digital output signal. For example, before the start of integration, the ADC 418 converts the offset of the CTIA 402 to one or more digital values, and the digital value(s) of the offset are used for offset removal from the digital output signal 412, as described in more detail with respect to FIG. 4.

[0100] In some embodiments, the offset removal 304 time is set so that a low pass filter (e.g., as described with respect to Figures 5 and 6) can sufficiently remove high frequency noise from the offset signal. In some embodiments, the offset removal 304 time is set to be several times (e.g., 2-10 times) larger than the time constant of the low pass filter (e.g., as described with respect to Figures 5 and 6).

[0101] In some embodiments, during sensor readout 306, the sensor pixels are selectively electrically coupled to the circuits for readout (e.g., a row of sensor pixels is selectively electrically coupled to a corresponding number of circuits for readout). In some embodiments, during this time, the sensor pixel charge is transferred to the CTIA for integration (e.g., integration 308). In some embodiments, the transition for a sensor pixel or row of sensor pixels to be selectively coupled to a corresponding circuit is 0.1 μs. In some embodiments, as shown, the sensor readout 306 is performed between integration 308 and remainder transform and FIR output 310. In some embodiments, the sensor readout 306 is performed during a portion of integration 308 and remainder transform and FIR output 310. At the end of the sensor readout 306, the sensor pixel is electrically isolated from the circuit. Exemplary methods of sensor readout can be found in International Applications PCT / US2019 / 027982 and PCT / US2019 / 046066, the entireties of which are incorporated herein by reference in their entirety for all purposes.

[0102] In some embodiments, during integration 308, the integration is performed as described with respect to Figures 1 and 2. The discussion and advantages associated with the described integration will not be repeated here.

[0103] In some aspects, during the remainder conversion and FIR output 310, the CTIA remainder is converted to a digital value by an ADC (e.g., ADC 118, ADC 418) as described with respect to FIG. 1, FIG. 2, and FIG. 4. The digital value of the remainder and the output of the quantizer (e.g., quantizer 104, quantizer 404) (e.g., a sequence of pulses generated from the integration, quantizer output waveform 208) are received by an FIR decimator (e.g., FIR decimator 122, FIR decimator 422). The FIR decimator processes the output of the quantizer or the output of the quantizer and the digital value of the remainder using coefficients determined using the methods described herein to generate a digital output signal (digital output signal 112, digital output signal 412) that is a digital representation of the input signal (e.g., input signal 110, input signal 410).

[0104] Although the timing diagram 300 includes four portions and the four portions are shown as having a particular order, it is understood that the timing diagram 300 may include different portions, different orders of the portions, and / or portions having different timing. For example, the portions of the timing diagram 300 may overlap (e.g., the integration 308 and the residue transform and FIR output 310 steps may occur simultaneously). As another example, the integration continues after the quantizer switching is stopped (e.g., in the case of MASH, the CTIA is electrically coupled to the ADC and continues integrating while the quantizer is turned off).

[0105] 4 illustrates an example circuit 400 according to an embodiment of the present disclosure. In some embodiments, the circuit 400 is a data converter (e.g., a sigma-delta converter). In some embodiments, the circuit 400 includes elements described with respect to the circuit 100 of FIG. For example, the CTIA 402 corresponds to the CTIA 102, the quantizer 404 corresponds to the quantizer 104, the DAC 406 corresponds to the DAC 106, the summer 408 corresponds to the summer 108, the signal 410 at the input 414 corresponds to the signal 110 at the input 114, the feedback capacitor 416 corresponds to the feedback capacitor 116, the reset switch 426 corresponds to the reset switch 126, the ADC 418 corresponds to the ADC 118 (e.g., a sigma-delta converter), the FIR decimator 422 corresponds to the FIR decimator 122 included in the digital filter, the timing and control circuit 424 corresponds to the timing and control circuit 124, the digital output signal 412 corresponds to the digital output signal 112, and the digital output 432 corresponds to the digital output 128. Some of the descriptions and advantages associated with these elements will not be repeated here.

[0106] In some aspects, the ADC 418 is configured to convert the remainder of the CTIA 402 and the offset of the CTIA 402. For example, before the integration begins, the ADC 418 converts the offset of the CTIA 402 to one or more digital values ​​(e.g., an average value of the offset over multiple samples), and the digital value of the offset is used for offset removal from the digital output signal 412. To better remove the offset component from the digital output signal 412 and improve the accuracy of the digital output signal 412 (e.g., when compared to the input 410), a value corresponding to the converted offset is removed from the digital output signal 412.

[0107] In some embodiments, the offset of the CTIA 402 is smaller (e.g., about 20 times smaller) than the remainder of the CTIA 402. In some embodiments, the circuit 400 includes resistors 428, 430. In some embodiments, the offset is scaled (e.g., amplified) by the configuration of the resistors 428, 430. For example, the resistor 428 has a resistance 19 times larger than the resistance of the resistor 430. When the ADC 418 is used to convert the offset signal, the resistors 428, 430 are electrically coupled in parallel (e.g., controlled by the timing and control circuit 424) to amplify the current generated by the offset signal by 20 times compared to when only the resistor 428 is electrically coupled. When the ADC 418 is used to convert the remainder signal, the resistor 428 is electrically coupled. As an example advantage, by amplifying the smaller offset signal, ADC 418 may be used to convert both the offset signal and the remainder signal, and a second, higher resolution ADC may not be needed to convert the smaller offset signal (e.g., an ADC with 10-bit resolution may be needed instead of an ADC with 14-bit resolution that may be needed without the use of resistor 430).

[0108] In some embodiments, instead of resistors 428, 430, the capacitance of the feedback capacitor 416 or the value at which the CTIA output is reduced is reduced to reduce the required resolution of the ADC 418, increasing the sensitivity at the ADC 418 input during offset removal (e.g., offset removal 304).

[0109] FIG. 5 illustrates an exemplary circuit 500 according to an embodiment of the disclosure. In some embodiments, the circuit 500 includes elements described with respect to the circuit 100 of FIG. 1 and the circuit 400 of FIG. 4. For example, the circuit 500 is the CTIA 102 or CTIA 402, the reset switch 514 is the reset switch 126 or the reset switch 426, and the feedback capacitor 516 is the feedback capacitor 116 or the feedback capacitor 416. The capacitor 508 and resistor 510 represent a load at the input of the circuit 500 (e.g., the equivalent capacitance and resistance of a sensor and / or a corresponding column electrically coupled to the input of the circuit, the equivalent capacitance and resistance of the input 114 or the input 414). Some of the descriptions and advantages associated with these elements will not be repeated here.

[0110] In some embodiments, the circuit 500 is a CTIA that includes a feedback capacitor 516 and an offset cancellation circuit. In some embodiments, the offset cancellation circuit is included in the feedback of the CTIA and includes a first switch 502 (shown as closed / conducting), a second switch 504, and an offset sampling capacitor 506. In some embodiments, the capacitance of the offset sampling capacitor 506 is the capacitance of the feedback capacitor 516.

[0111] As an example, after the feedback capacitor 516 is reset (e.g., after feedback capacitor reset 302), the first switch 502 is closed or conducting, causing the offset sampling capacitor 506 and the feedback capacitor 516 to sample the offset voltage of the circuit 500 (e.g., the offset voltage of the CTIA). Because the capacitance of the offset sampling capacitor 506 and the capacitance of the feedback capacitor 516 are equal, both capacitors have sampled the offset voltage. After sampling the offset voltage, the first switch 502 opens or stops conducting and the second switch 504 closes or conducts, transferring the charge stored on the offset sampling capacitor 506 to the input of the amplifier. The transferred charge cancels the offset voltage stored on the feedback capacitor 516 and removes the offset at the output of the circuit 500.

[0112] In some embodiments, the time required to transfer the charge stored on the offset sampling capacitor 506 to the input of the amplifier is limited by the gain-bandwidth product of the amplifier. In some embodiments, the second switch 504 is reopened after the offset is removed at the output of the circuit 500. In some embodiments, the second switch 504 remains closed.

[0113] As an exemplary advantage, the disclosed CTIA may require one feedback capacitor for different applications, and therefore the offset cancellation circuitry for the CTIA may be simplified compared to a conventional CTIA that may require two or more feedback capacitors for different applications. By simply adding the first switch 502 and the second switch 504 and the offset capacitor 516 to the feedback of the CTIA, the offset of the CTIA may be cancelled. Because no additional offset cancellation circuitry may be required, and offset cancellation may be included in the feedback of the CTIA, the circuit area may be reduced compared to a conventional CTIA.

[0114] FIG. 6 illustrates an exemplary circuit 600 according to an embodiment of the disclosure. In some embodiments, the circuit 600 includes elements described with respect to the circuit 100 of FIG. 1, the circuit 400 of FIG. 4, or the circuit 500 of FIG. 5. For example, the circuit 600 is a CTIA 102 or a CTIA 402, the reset switch 620 is a reset switch 126, a reset switch 426, or a reset switch 514, and the feedback capacitor 616 is a feedback capacitor 116, a feedback capacitor 416, or a feedback capacitor 516. The capacitor 608 and the resistor 610 represent a load at the input of the circuit 600 (e.g., the equivalent capacitance and resistance of a sensor and / or a corresponding column electrically coupled to the input of the circuit, the equivalent capacitance and resistance of the input 114 or the input 414). Some descriptions and advantages associated with these elements will not be repeated here.

[0115] In some embodiments, the circuit 600 is a CTIA that includes a feedback capacitor 616, an offset cancellation circuit, and a low pass filter. In some embodiments, the low pass filter is included in the feedback of the circuit 600. In some embodiments, the low pass filter and the offset cancellation circuit are included in the feedback of the circuit 600.

[0116] In some embodiments, the first switch 602, the second switch 604, the capacitor 606, the third switch 608, and the offset sampling capacitor 610 function as a low pass filter and offset removal circuit. In some embodiments, the capacitance of the capacitor 606 is less than the capacitance of the offset sampling capacitor 610. In some embodiments, the first switch 602, the second switch 604, and the capacitor 606 function as a switched capacitor.

[0117] As an example, after feedback capacitor 616 is reset (e.g., after feedback capacitor reset 302), first switch 602 and second switch 604 alternate between being closed or conducting and being open or non-conducting (e.g., the first switch and second switch are controlled by complementary clock signals) to cause capacitor 606 to sample a portion of the offset charge and transfer the sampled offset charge to offset sampling capacitor 610. At the same time, feedback capacitor 616 samples the offset voltage in a manner similar to how feedback capacitor 516 samples the offset voltage as described with respect to FIG.

[0118] In some embodiments, f is the frequency of the clock that controls the first switch 602 and the second switch 604. The effective time constant of the low pass filter is: TIFF2024502327000009.tif10128

[0119] The first switch 602 and the second switch 604 alternately switch to transfer a portion of the offset charge from the capacitor 606 to the offset sampling capacitor 610. Because the capacitance of the offset sampling capacitor 610 and the capacitance of the feedback capacitor 616 are equal, both capacitors sample the offset voltage. After sampling the offset voltage, the third switch 608 closes or conducts, transferring the charge stored on the offset sampling capacitor 610 to the input of the amplifier. The transferred charge cancels the offset voltage stored on the feedback capacitor 616, eliminating the offset at the output of the circuit 600.

[0120] In some embodiments, the time required to transfer the charge stored on the offset sampling capacitor 610 to the input of the amplifier is limited by the gain-bandwidth product of the amplifier. In some embodiments, the third switch 608 is reopened after the offset is removed at the output of the circuit 600. In some embodiments, the third switch 608 remains closed.

[0121] As an exemplary advantage, the disclosed CTIA may require one feedback capacitor for different applications, so the offset cancellation circuit for the CTIA may be simplified, compared to a conventional CTIA that may require two or more feedback capacitors for different applications. Furthermore, a low pass filter may be included in the feedback of the CTIA along with the offset cancellation circuit. By simply adding the first switch 602, the second switch 604, the capacitor 606, the third switch 608, and the offset sampling capacitor 610 to the feedback of the CTIA, the offset and noise of the CTIA may be canceled, and more accurate offset cancellation may be obtained. Since additional offset cancellation and low pass filter circuits may not be required in the parts of the circuit outside the CTIA, and the offset cancellation and low pass filtering may be included in the feedback of the CTIA, the circuit area may be reduced.

[0122] In addition, the low pass filter advantageously reduces Johnson noise or broadband noise (e.g., due to parasitics of the sensor array, the bandwidth of which is determined by the parasitic resistance and capacitance of the sensor array) prior to offset sampling to prevent these noises from being sampled during offset sampling, further improving the accuracy of the offset removal. For example, without the aid of noise removal, the accuracy of the data converter is approximately 1×10 -15 C (e.g., the error between the output and the corresponding input), which may be caused by Johnson noise on the sensor string parasitic capacitance. In contrast, with the aid of noise cancellation using the circuits and methods described herein, the accuracy of the data converter aided by these may be reduced to 1.4×10 -16 Improved accuracy of C (e.g., the error between the output and the corresponding input) may be achieved. If the input is a 10 pC input (e.g., the total amount of charge integrated is 10 pC), the improved data converter may achieve 16 effective number of bits (ENOB).

[0123] For example, without using the disclosed offset cancellation circuit and method, the offset is 4 mV. The low pass filter and offset cancellation circuit described with respect to FIG. 6 is added to the feedback of the CTIA with the following parameters: 610 =0.5pF, f=2MHz, C 606 =0.2pF, τ=1.25us. By adding a low-pass filter and offset removal circuit, the offset is reduced to 1.5mV.

[0124] In some embodiments, a resistor is used in place of the switched capacitor circuit (e.g., first switch 602, second switch 604, capacitor 606) to create a low pass filter with similar advantages as described above. For example, returning to circuit 500 of FIG. 5, a resistor having an appropriate resistance value (e.g., to obtain a desired cutoff frequency) may be electrically coupled (not shown) to first switch 502 to create a low pass filter with similar advantages as described above.

[0125] 7 illustrates an exemplary method 700 according to an embodiment of the disclosure. In some embodiments, method 700 is a method of operating circuit 100, circuit 400, circuit 500, and / or circuit 600. Although method 700 is illustrated as including described steps, it is understood that a different order of steps, additional steps, or fewer steps may be performed to operate the exemplary data converter without departing from the scope of the disclosure. Some of the explanations and advantages associated with the steps of method 700 have been discussed with respect to FIGS. 1-6 and will not be repeated here.

[0126] In some aspects, the method 700 includes integrating an input signal using a CTIA of the circuit (step 702). For example, a first portion of the input signal (e.g., input signal 110, input signal 410, input waveform 202) is integrated by the CTIA (e.g., CTIA 102, CTIA 402, circuit 500, circuit 600) as shown by the CTIA output waveform 206 during adjacent feedback times 212.

[0127] In some embodiments, the method 700 includes using a variable resistor to reduce the current level of the input signal. For example, as described with respect to FIG. 1, a variable resistor (e.g., a MOS transistor controlled by a variable voltage to change the effective resistance of the transistor) is electrically coupled to an input of a circuit (e.g., circuit 100, circuit 400) to reduce the current level of the input signal (e.g., to slow down the rate at which the feedback capacitor charges and prevent the feedback capacitor from saturating when a high current level causes a high charging rate).

[0128] In some embodiments, the method 700 includes electrically coupling a sensor to the CTIA. In some embodiments, the sensor provides an input signal, and the CTIA includes a feedback capacitor, and the capacitance of the feedback capacitor is less than the capacitance of the sensor. For example, during integration (e.g., integration 308), as described herein, a sensor pixel (e.g., a bolometer pixel, an x-ray sensor pixel, a visible image sensor pixel, an infrared image sensor pixel, a MEMS sensor pixel, a sensor pixel that converts information about the environment into an electrical signal) is electrically coupled to the CTIA (e.g., CTIA 102, CTIA 402, circuit 500, circuit 600). The sensor pixel provides an input signal (e.g., input signal 110, input signal 410, input waveform 202). The CTIA includes a feedback capacitor (e.g., feedback capacitor 116, feedback capacitor 416, feedback capacitor 516, feedback capacitor 616), and the capacitance of the feedback capacitor (e.g., 0.5 pF in one example) is less than the capacitance of the sensor (e.g., 2.6 pF in one example). Some of the discussion and advantages associated with the feedback capacitor of the CTIA discussed with respect to Figures 1-6 will not be repeated here.

[0129] In some aspects, the method 700 includes determining whether a CTIA output signal at an output of the CTIA is greater than a threshold (step 704). For example, a quantizer (e.g., quantizer 104, quantizer 404) determines whether the CTIA output signal is greater than a threshold (e.g., threshold 218) at a quantizer decision time (e.g., 210A-210I).

[0130] In some aspects, the method 700 includes, in accordance with a determination that the CTIA output signal is greater than a threshold (step 706), reducing the CTIA output signal (step 708).

[0131] For example, a quantizer (e.g., quantizer 104, quantizer 404) determines that the CTIA output signal (e.g., CTIA output waveform 206) is greater than a threshold (e.g., threshold 218) at a quantizer decision time (e.g., 210B, 210C, 210D, 210E, 210G). In response to this determination, the quantizer (e.g., quantizer 104, quantizer 404) outputs a decision (e.g., a "high" value) to a DAC (e.g., DAC 106, DAC 406), and in response to receiving the quantizer decision, the DAC provides a high DAC output signal and reduces a value from the CTIA output signal (e.g., subtracts a fixed value 214 from the CTIA output signal) (e.g., using summer 108, using summer 408) during a feedback time (e.g., 212B, 212C, 212D, 212E, 212G).

[0132] In some aspects, the method 700 includes generating a high DAC output signal according to a determination that the CTIA output signal is greater than a threshold value. The CTIA output signal is reduced by a value, which is generated based on the high DAC output value. For example, a DAC (e.g., DAC106, DAC406) generates a high DAC output signal according to a determination that the CTIA output signal (e.g., the output of CTIA102, the output of CTIA402, the output of circuit 500, the output of circuit 600) is greater than a threshold value (e.g., the quantizer threshold, threshold 218).

[0133] In some embodiments, the CTIA includes a feedback capacitor (e.g., feedback capacitor 116, feedback capacitor 416, feedback capacitor 516, feedback capacitor 616). The feedback capacitor is configured to accumulate a total charge, and the CTIA output signal is reduced by a value corresponding to a value less than the total charge. For example, the fixed value 214 corresponds to a value less than the total charge that the feedback capacitor can accumulate (e.g., this value is less than or equal to the highest possible level of the CTIA output waveform 206).

[0134] In some embodiments, the method 700 includes, pursuant to determining that the CTIA output signal is less than or equal to the threshold (step 710), ceasing to reduce the CTIA output signal (step 712).

[0135] For example, the quantizer (e.g., quantizer 104, quantizer 404) determines that the CTIA output signal (e.g., CTIA output waveform 206) is less than or equal to the threshold (e.g., threshold 218) at the quantizer decision time (e.g., 210A, 210F, 210H). In accordance with this determination, the quantizer (e.g., quantizer 104, quantizer 404) outputs a decision (e.g., a "low" value) to the DAC (e.g., DAC 106, DAC 406), and in response to receiving the quantizer decision, the DAC ceases to provide a high DAC output signal at the input of the circuit (e.g., the DAC stops providing an output). The CTIA output signal is not reduced from the input signal during the feedback time (e.g., 212A, 212F) (e.g., no high DAC output signal is provided to summer 108, no high DAC output signal is provided to summer 408).

[0136] In some aspects, integrating the input signal includes integrating a first portion of the input signal, and method 700 includes integrating a second portion of the input signal using the CTIA. For example, after the first portion is integrated (e.g., a portion of the input signal is integrated during adjacent feedback times), the CTIA continues to integrate a second portion of the input signal (e.g., a subsequent portion of the input signal is integrated during the next adjacent pair of feedback times).

[0137] In some aspects, whether the CTIA output signal at the output of the CTIA is greater than the threshold is determined while the first portion is being integrated for a first time. For example, referring to FIG. 2, whether the CTIA output signal at the output of the CTIA is greater than the threshold is determined at a quantizer decision time (e.g., quantizers 210A-210I).

[0138] In some aspects, the method 700 includes reducing the CTIA output signal at a second time after the first time in accordance with a determination that the CTIA output signal is greater than the threshold value, and integration of the second portion begins from the reduced CTIA output signal at a third time after the second time. For example, referring to FIG. 2, following a determination by a quantizer (e.g., quantizer 104, quantizer 404) that the CTIA output signal is greater than a threshold at a quantizer time (e.g., quantizer time 210B, 210C, 210D, 210E, 210G), the CTIA output signal is reduced at the feedback time (e.g., the time between feedback times 212B, 212C, 212D, 212E, 212G), and the second portion to be integrated starts from the reduced CTIA output signal at a third time (e.g., during feedback times 212B, 212C, during feedback times 212C, 212D, during feedback times 212D, 212E, during feedback times 212G, 212H).

[0139] In some embodiments, the method 700 includes ceasing to reduce the CTIA output signal at a second time in accordance with a determination that the CTIA output signal is below the threshold. The integration of the second portion starts from the CTIA output signal at a third time. For example, referring to FIG. 2, in accordance with a determination by a quantizer (e.g., quantizer 104, quantizer 404) that the CTIA output signal is below the threshold at a quantizer time (e.g., quantizer time 210A, 210F), the reduction of the CTIA output signal at a feedback time (e.g., feedback time 212A, 212F) is ceased, and the second portion to be integrated starts from the CTIA output signal at a third time (e.g., the time during feedback times 212A, 212B and between feedback times 212F, 212G).

[0140] In some aspects, the operating frequency of the circuit is based on the time between integrations of the input signal, and the sensitivity of the circuit is based on the operating frequency of the circuit. For example, the operating frequency of the circuit (e.g., circuit 100, circuit 400) is based on the timing between the quantizer decision times (e.g., quantizer decision times 210A-210I) and / or feedback times (e.g., feedback times 212A-212I). Based on the timing between the quantizer decision times and / or feedback times, the sensitivity of the circuit is set (e.g., the size of the portion to be integrated is set, thereby setting the resolution of the integration). By having sensitivity adjustability based on the operating frequency, the circuit can be advantageously used in a wider range of applications (e.g., the circuit is suitable for both low-resolution and high-resolution systems).

[0141] In some embodiments, when the CTIA output signal is below the threshold and the level of the input signal is 0, the CTIA output signal corresponds to a remainder. For example, near the end of an integration time (e.g., integration 308), the portion of the input signal being integrated (e.g., the portion of the CTIA output waveform 206 after the feedback time 212G) is the remainder.

[0142] In some aspects, the method 700 includes removing the offset of the CTIA. For example, the offset of the CTIA is removed during offset removal 304. For example, the offset removal circuit 120 captures an offset value. The offset value is reduced from the residual charge or voltage before being provided to the ADC 118 to remove the offset from the digital output signal 112 and improve the accuracy of the data conversion of the circuit 100.

[0143] In some embodiments, the offset removal circuit 120 is configured for correlated double sampling. After the reset switch 126 resets the feedback capacitor 116 (e.g., after feedback capacitor reset 302), random noise may be sampled. In some embodiments, the capacitance of the sensor string may be large, and the noise may be thermal noise in the parasitic string elements, which may cause random charge values. The standard deviation of this random charge is May be approximately equal to TIFF2024502327000010.tif6128.

[0144] In some embodiments, to remove this random noise, the output of the CTIA is measured (e.g., measured multiple times and averaged) by the offset removal circuit 120 measuring the noise charge once at or before the start of integration and measuring the integrated signal or residual plus noise charge once at the end or after integration is completed. The difference between these two measurements (e.g., the difference between these two measurements excludes the offset) is converted to a digital value using the ADC 118 (e.g., a sigma-delta converter).

[0145] In some embodiments, the offset is removed using an offset removal circuit included in the feedback of the CTIA, for example, the offset removal circuit included in circuit 500 or circuit 600 removes the CTIA offset using the methods described with respect to FIGS.

[0146] In some embodiments, the method 700 includes low-pass filtering the offset of the CTIA. In some embodiments, a low-pass filter is included in the feedback of the CTIA to low-pass filter the offset of the CTIA. For example, as described with respect to FIG. 5, a resistor (not shown) having a desired resistance (e.g., to achieve a particular cutoff frequency of the filter) is electrically coupled to the first switch 502 to remove noise associated with the offset. As another example, as described with respect to FIG. 6, a switched capacitor circuit (e.g., first switch 602, second switch 604, capacitor 606) having a desired effective resistance (e.g., to achieve a particular cutoff frequency of the filter) is included in the feedback of the circuit 600 to remove noise associated with the offset.

[0147] In some embodiments, removing the CTIA offset further includes converting the CTIA offset to a digital value of the offset, for example, as described with respect to FIG. 4, the offset is converted to a digital value using ADC 418, and the digital value of the offset is removed from the digital output signal 412 to remove the effect of the CTIA offset during conversion of the input signal.

[0148] In some aspects, converting the offset of the CTIA further includes scaling the offset of the CTIA. For example, as described with respect to FIG. 4, the offset of the CTIA is scaled (e.g., amplified) using resistors 428, 430 to increase the current input to the ADC 418 and reduce the sensitivity requirements of the ADC to convert the offset, prior to converting the offset to a digital value using the ADC 418 and removing the digital value of the offset from the digital output signal 412.

[0149] In some aspects, the method 700 includes generating a digital output signal corresponding to the input signal. For example, the circuit 100 generates the digital output signal 112 or the circuit 400 generates the digital output signal 412. The digital output signal is based on the output of a quantizer (e.g., a binary sequence (e.g., the quantizer output waveform 208) based on a comparison of the CTIA output to a quantizer threshold).

[0150] In some aspects, the input signal is a charge at the input of the circuit and the digital output signal is a digital value of the charge. In some aspects, the input signal is a current at the input of the circuit and the digital output signal is a digital value of the current. In some aspects, the input signal is a voltage at the input of the circuit and the digital output signal is a digital value of the voltage.

[0151] In some aspects, the method 700 includes determining whether readout of the input signal is complete in accordance with a determination that the CTIA output signal is less than or equal to the threshold. The method 700 includes outputting the CTIA output signal as a remainder in accordance with a determination that readout of the input signal is complete. The method 700 includes ceasing to output the CTIA output signal as a remainder in accordance with a determination that readout of the input signal is not complete.

[0152] For example, referring to FIG. 2, at the eighth feedback time 212H, the value of the input waveform 202 is reduced to zero (e.g., the electrically coupled sensor finishes discharging and the readout of the electrically coupled sensor is completed). In response to a determination that the readout of the input signal is completed, after the eighth feedback time 212H, the feedback capacitor stops charging, causing the output of the CTIA to become a constant value. This constant output of the CTIA 102 after the eighth feedback time 212H is a remainder (e.g., remainder 216, a voltage corresponding to a residual charge). In response to a determination that the readout of the input signal is not completed before the eighth feedback time 212H, the circuit (e.g., circuit 100, circuit 400) ceases to output the CTIA output signal as a remainder.

[0153] In some aspects, the input signal is integrated at a first time. For example, referring to FIG. 2, the input signal 202 is integrated at a time between two of the feedback times 212A-212H. In some aspects, whether the readout of the input signal is completed is determined at a second time after the first time. In accordance with the determination that the readout of the input signal is completed, the CTIA output signal is output as a remainder at a third time after the second time. For example, referring to FIG. 2, whether the readout of the input signal is completed is determined at the feedback time 212H. At the feedback time 212H, it is determined that the readout of the input signal is completed (e.g., the electrically coupled sensor finishes discharging and the readout of the electrically coupled sensor is completed). After the feedback time 212H, the feedback capacitor stops charging, allowing the output of the CTIA to be a constant value. This constant output of the CTIA 102 after the eighth feedback time 212H is the remainder (e.g., remainder 216, a voltage corresponding to a residual charge, a residual voltage).

[0154] In some embodiments, the CTIA output signal is refrained from being output as a remainder in accordance with a determination that the readout of the input signal is not complete. For example, referring to FIG. 2, whether the readout of the input signal is complete is determined before the feedback time 212H. Before the feedback time 212H, it is determined that the readout of the input signal is not complete (e.g., the electrically coupled sensor is discharging and the readout of the electrically coupled sensor is occurring), and the circuit (e.g., circuit 100, circuit 400) refrains from outputting the CTIA output signal as a remainder.

[0155] In some aspects, the digital output signal is further based on a remainder. For example, the digital output signal (e.g., digital output signal 112, digital output signal 412) is based on a remainder of a quantizer output and a CTIA (e.g., CTIA 102, CTIA 402), and the remainder (or a digital value of the remainder) of the quantizer output and the CTIA is provided to an FIR decimator (e.g., FIR decimator 122, FIR decimator 422) to generate the digital output signal.

[0156] In some aspects, the method 700 includes generating a binary sequence and providing the binary sequence to an FIR decimator. The digital output signal is generated by the FIR decimator, and the binary sequence is based on a determination of whether the CTIA output signal at the output of the CTIA is greater than a threshold. In some aspects, generating the binary sequence further includes outputting a first binary value according to a determination that the CTIA output signal is greater than the threshold, and outputting a second binary value according to a determination that the CTIA output signal is equal to or less than the threshold. For example, the digital output signal (e.g., digital output signal 112, digital output signal 412) is based on an output of a quantizer. In some aspects, according to a determination that the CTIA output signal is greater than the threshold, the quantizer outputs a high digital value. According to a determination that the CTIA output signal is equal to or less than the threshold, the quantizer outputs a low digital value. The output of the quantizer is provided to an FIR decimator (e.g., FIR decimator 122, FIR decimator 422) to generate a digital output signal.

[0157] In some aspects, the method 700 includes providing the digital value of the remainder to an FIR decimator. The digital output signal is further based on the digital value of the remainder. For example, the digital output signal (e.g., digital output signal 112, digital output signal 412) is based on the output of the quantizer and the remainder of the CTIA (e.g., CTIA 102, CTIA 402), and the output of the quantizer and the digital value of the remainder are provided to an FIR decimator (e.g., FIR decimator 122, FIR decimator 422) to generate the digital output signal.

[0158] In some aspects, the method 700 includes generating a remainder digital value. For example, the CTIA output signal is a remainder, and an ADC (e.g., ADC118, ADC418) generates the remainder digital value (e.g., and provides the remainder digital value to an FIR decimator). In some aspects, the remainder digital value is generated using a sigma-delta ADC (e.g., ADC118 is a sigma-delta ADC, and ADC418 is a sigma-delta ADC).

[0159] In some aspects, the method 700 includes determining coefficients associated with the FIR decimator using at least one of analytical determination, numerical determination based on simulation, and numerical determination based on measurement. Examples of determining coefficients associated with an FIR decimator (e.g., FIR decimator 122, FIR decimator 422) and their advantages are described with respect to FIG. 1. These examples will not be repeated here.

[0160] In some aspects, the method 700 includes operating the circuit as a MASH modulator. In response to operating the circuit as a MASH modulator, ceasing to determine whether the CTIA output signal at the output of the CTIA is greater than a threshold. For example, as described with respect to FIG. 1, in response to operating the circuit as a MASH modulator, the quantizer 104 is turned off while the input signal continues to be integrated.

[0161] By integrating portions of the input signal at different times and reducing the CTIA output by a value after integrating the portions, the CTIA can advantageously integrate adaptively. As an exemplary advantage, the disclosed circuits and methods of operating the circuits may allow for smaller feedback capacitance values ​​compared to the feedback capacitors of CTIAs that integrate in a conventional manner (e.g., associated with a conventional CTIA output waveform 204). A CTIA with a smaller feedback capacitor may be able to integrate the same input as a conventional CTIA with a larger feedback capacitor. Thus, the corresponding output voltage may be higher (e.g., due to the Q=CV relationship), easing the resolution or sensitivity requirements of the subsequent circuitry (e.g., ADC). As another exemplary advantage, because the CTIA can integrate adaptively, the disclosed circuits and methods of operating the circuits may accommodate readout of different array sizes, different types of pixels, and / or different dynamic ranges, reducing the need for different CTIA designs and reducing the cost of designing specific readout circuitry.

[0162] Furthermore, because the feedback capacitor of the CTIA does not saturate while integrating as described (e.g., as a result of operating the circuit using the disclosed method), the feedback capacitor of the CTIA may be used to integrate charge beyond the storage capacity of an equivalent feedback capacitor of a conventional CTIA. In some aspects, the effective capacitance of the CTIA feedback capacitor (e.g., corresponding to the total number of charges that the CTIA feedback capacitor can integrate during integration) may be determined based on a clock that controls a quantizer (e.g., quantizer 104, quantizer 404). For example, if N1 cycles are available for use by the CTIA (e.g., there are N1 quantizer decision times 210 during integration and there are N1 feedback times 212 during integration), then the effective capacitance of the CTIA feedback capacitor is N1 x (capacity of the CTIA feedback capacitor). In some aspects, the number N1 is determined based on the total number N of oversampling ratio (OSR) clock cycles and how the N clock cycles are allocated between the integration time (e.g., integration 308) and the remainder transform (e.g., remainder transform and remainder transform portion of FIR output 310). As an example, N1=16, the capacitance of the feedback capacitor of the CTIA is 0.5 pF, and the effective capacitance of the CTIA feedback capacitor is 16×0.5 pF=8 pF, which means that a CTIA including a 0.5 pF feedback capacitor can have three times the charge capacity compared to a conventional CTIA including a 2.6 pF feedback capacitor.

[0163] Further, because the CTIA can adaptively integrate, the CTIA (e.g., CTIA102, CTIA402, circuit 500, circuit 600) may be configured to obtain variable gain by varying the integration time, reducing the need for additional feedback capacitors for different gains. In addition, by integrating as described, portions of the input may be converted simultaneously (e.g., a first portion of the input is integrated and then converted while a second portion of the input is integrated), reducing the need for sample-and-hold circuits and additional capacitors without slowing down the conversion speed.

[0164] The area efficiency and flexibility of the disclosed circuits (e.g., enabled by operating the circuits using the disclosed methods) may be advantageously suited to array-type sensors, such as x-ray sensors, visible image sensors, infrared image sensors, MEMS sensors, etc., where a set of signals can be read out and converted to digital form. Without hardware modifications, the disclosed circuits can be advantageously configured to convert data of different array sizes, different types of sensors, or different dynamic ranges (e.g., by adjusting the integration time) while maintaining the accuracy of a corresponding data conversion circuit that integrates in a conventional manner.

[0165] As yet another exemplary advantage, the impact of thermal noise (e.g., from the parasitic capacitance of the sensor array) on the disclosed circuitry may be lower due to the sigma-delta oversampling (e.g., by integrating, i.e., by using a sigma-delta converter in ADC 118, as described herein) performed by the disclosed circuitry as compared to the higher bandwidth sample-and-hold circuits used to capture the output of conventional CTIAs.

[0166] In some embodiments, a non-transitory computer-readable storage medium stores one or more programs, the one or more programs including instructions that, when executed by an electronic device having one or more processors and memory (e.g., an electronic device including circuitry described herein), cause the electronic device to perform the methods described with respect to FIGS.

[0167] Although the disclosed circuits are described with illustrated elements, it is understood that the figures are merely exemplary. Different or additional elements may be added or removed from the disclosed circuits to form the disclosed data converters. The depicted elements may be electrically coupled or configured differently than as illustrated. For example, while portions of the circuits are shown as single-ended circuits, it is understood that the disclosed circuits may be configured for differential signaling.

[0168] 8 illustrates a method 800 for manufacturing an electromechanical system, according to one embodiment. As a non-limiting example, the electromechanical system can be associated with circuit 100, 400, 500, or 600 (and / or related methods) (e.g., circuit 100, 400, 500, or 600 is included in the readout circuitry of the electromechanical system). All or some of the process steps in method 800 can also be used, and can be used in a different order, to manufacture the electromechanical system. As a non-limiting example, step 814 can be performed before step 812.

[0169] Method 800 includes step 802, providing a substrate. In some embodiments, the substrate is made of glass. In some embodiments, the substrate is low temperature polycrystalline silicon. In some embodiments, the substrate is a borosilicate that contains additional elements to fine-tune properties. One example of a borosilicate is from Corning Eagle™, which produces alkaline earth boroaluminosilicates (silicates that contain boron, aluminum, and various alkaline earth elements). Other variations are available from Asahi Glass™ or Schott™.

[0170] In some embodiments, a flat panel glass process is used to manufacture the electromechanical system. In some embodiments, a liquid crystal display (LCD) process is used to manufacture the electromechanical system. In some embodiments, an OLED display process or an X-ray panel process is used. Using a flat panel glass process allows for larger substrate sizes, thereby allowing for more electromechanical systems per substrate and reducing processing costs. "Panel level" sizes can include 300mm x 400mm, 360mm x 465mm, 400mm x 500mm, 550mm x 650mm, 620mm x 750mm, 680mm x 880mm, 730mm x 920mm, 1100mm x 1300mm, 1300mm x 1500mm, 1500mm x 1850mm, 1950mm x 2250mm, 2200mm x 2500mm, and 2840mm x 3370mm. Additionally, thin film transistor (TFT) manufacturing at the panel level can also reduce costs, so for example, LCD-TFT processes can be beneficial.

[0171] Some embodiments may include mounting of a readout integrated circuit (ROIC), which may include circuits 100, 400, 500, and / or 600, as well as flex / PCB mounting. The processes and devices described herein may have the additional advantage that the area required for signal processing can be much smaller than the sensing area dictated by the sensing physics. Typically, sensors are integrated on top of CMOS circuits, where area-driven costs lead to technology nodes that are not optimal for the signal processing task. The processes described herein can use more suitable CMOS and reduce the area required for signal processing, freeing the sensor from any area constraints by leveraging the low cost of FPD (flat panel display) manufacturing. In some embodiments, the ROIC is specifically designed to meet the requirements for sensing a particular electromagnetic wavelength (X-ray, THz, LWIR, etc.).

[0172] In some embodiments, the MEMS devices manufactured by the processes herein are bolometers each including a glass substrate and a bolometer pixel bonded to the structure. In some embodiments, the bolometers include MEMS or NEMS devices manufactured by the LCD-TFT manufacturing process.

[0173] Bolometers can be used in a variety of applications. For example, far infrared (LWIR, wavelengths of about 8-14 μm) bolometers can be used in the automotive and commercial security industries. For example, LWIR bolometers with QVGA, VGA, and other resolutions. Terahertz (THz, wavelengths of about 0.1-1.0 mm) bolometers can be used in security (such as airport passenger security screening) and medical (medical imaging). For example, THz bolometers can have QVGA resolution (320×240) or other resolutions. Some electromechanical systems can include x-ray sensors or camera systems. Similarly, LWIR and THz sensors are used in camera systems. Some electromechanical systems have been applied to medical imaging, such as endoscopes and exoscopes.

[0174] Other electromechanical systems include scanners for light detection and ranging (LIDAR) systems. For example, optical scanners that can shape the spatial characteristics of a laser beam (for beam pointing, etc.). Electromechanical systems include inertial sensors (e.g., where the input stimulus is linear or angular motion). Some systems can be used in biosensing and biotherapeutic platforms (e.g., where biochemical agents are detected).

[0175] As used herein, the term "MEMS" may be understood to include electromechanical systems having a size of about 1 mm or less. For example, the term "MEMS" may be understood to include nanoelectromechanical systems ("NEMS").

[0176] Although the disclosed embodiments have been fully described with reference to the accompanying drawings, it should be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications should be understood to be included within the scope of the disclosed embodiments as defined by the appended claims. For example, although the present disclosure has been described primarily with respect to glass MEMS plates / panels, those skilled in the art will recognize that other MEMS plates / panels may be used without departing from the scope of the present disclosure. Such other MEMS plates may include, but are not limited to, organic materials (plastics, polymers) and metals (stainless steel, etc.). As used herein, the terms "plate" and "panel" are synonymous.

[0177] Method 800 includes step 804, adding MEMS to the substrate. Although MEMS is used to illustrate the addition of structures, it should be understood that other structures may be added without departing from the scope of the present disclosure. In some embodiments using panel level processing, the MEMS structures may be added using LCD-TFT processes.

[0178] Step 804 may be followed by optional step 816, sub-plating. Step 816 may be used when the substrate is larger than the processing equipment used in subsequent steps. For example, when using panel level processes (such as LCD), some embodiments include (at step 804) cutting the panel to wafer size for further processing (e.g., using CMOS manufacturing equipment). In other embodiments, the same size substrate is used throughout method 800 (i.e., step 816 is not used).

[0179] The method 800 includes step 806, removing the MEMS from the substrate.

[0180] Method 800 includes step 808, post-detachment processing. Such post-detachment processing may prepare the MEMS structure for further process steps, such as planarization. In wafer-level processing, planarization may include chemical-mechanical planarization. In some embodiments, further process steps include etch-back, where photoresist is spun onto the topography to create a flatter surface, which is then etched. Greater control of etch time can result in a smoother surface profile. In some embodiments, further process steps include "spin-on glass," where an organic binder containing glass is spun onto the topography, and the result is baked to remove the organic solvent, leaving a smoother surface.

[0181] Method 800 optionally includes step 810, vacuum encapsulation of the MEMS structure, which may be beneficial for extending device lifetime.

[0182] Method 800 includes step 812, singulation. Some embodiments may include calibration and chip programming (e.g., of circuits 100, 400, 500, and / or 600), which may take into account the characteristics of the sensor. The methods described herein may be advantageous in glass substrate manufacturing processes, since the uniformity of glass lithography capabilities is limited. As an additional advantage, glass has a lower thermal conductivity, so the glass substrate may be a better insulator, and by fabricating a thin structure that separates the bolometer pixels from the glass substrate, embodiments herein may work better to thermally isolate the glass bolometer pixels from the packaging environment.

[0183] Method 800 includes step 814, mounting of a readout integrated circuit (ROIC), which may include circuits 100, 400, 500, and / or 600, and flex / PCB mounting. The processes and devices described herein may have the additional advantage that the area required for signal processing can be much smaller than the sensing area dictated by the sensing physics. Typically, sensors are integrated on top of CMOS circuits, where the area driving costs lead to technology nodes that are not optimal for the signal processing task. The processes described herein can use more suitable CMOS and reduce the area required for signal processing, freeing the sensor from any area constraints by leveraging the low cost of FPD (flat panel display) manufacturing. In some embodiments, the ROIC is specifically designed to sense a particular electromagnetic wavelength (X-ray, THz, LWIR, etc.).

[0184] 9 shows an exemplary sensor. In some embodiments, the sensor 900 is manufactured using the method 800. In some embodiments, the sensor 900 is read out using the circuits 100, 400, 500, and / or 600.

[0185] In some embodiments, a sensor includes a glass substrate, a structure fabricated from any of the methods described herein and bonded to the glass substrate, and a sensor pixel bonded to the structure.

[0186] In some embodiments, the sensor comprises a MEMS or NEMS device fabricated by an LCD-TFT manufacturing process and a structure fabricated by any of the methods described herein.

[0187] As examples, sensors can include resistive and capacitive sensors. Bolometers can be used in a variety of applications. For example, far infrared (LWIR, wavelengths of about 8-14 μm) bolometers can be used in the automotive and commercial security industries. For example, LWIR bolometers with QVGA, VGA, and other resolutions. Terahertz (THz, wavelengths of about 0.1-3 mm) bolometers can be used in security (such as airport passenger security screening) and medical (medical imaging). For example, THz bolometers with QVGA resolution and other resolutions. Some electromechanical systems can include X-ray sensors or camera sensor systems. Similarly, LWIR and THz sensors are used in camera sensor systems. Some electromechanical systems have been applied in medical imaging, such as endoscopes and exoscopes. X-ray sensors include direct and indirect sensing configurations.

[0188] Other electromechanical systems include scanners for light detection and ranging (LIDAR) systems. For example, optical scanners that can shape the spatial characteristics of a laser beam (for beam pointing, etc.). Electromechanical systems include inertial sensors (e.g., where the input stimulus is linear or angular motion). Some systems can be used in biosensing and biotherapeutic platforms (e.g., where biochemical agents are detected).

[0189] In one aspect, the circuit includes an analog input, a charge transimpedance amplifier (CTIA) electrically coupled to the analog input, a quantizer electrically coupled to an output of the CTIA, a digital-to-analog converter (DAC) electrically coupled to the output of the quantizer, and a summer electrically coupled to the output of the DAC. The CTIA is electrically coupled to the output of the summer, a digital filter electrically coupled to the output of the quantizer, and a digital output electrically coupled to the digital filter.

[0190] In some aspects of the above circuit, the CTIA includes a feedback capacitor, the analog input is electrically coupled to the sensor, and the capacitance of the feedback capacitor is less than the capacitance of the sensor.

[0191] In some aspects of the above circuit, the summer is configured to reduce the CTIA output signal in response to receiving a high DAC output signal at the output of the DAC.

[0192] In some aspects of the above circuit, the summer is further configured to reduce the CTIA output signal by a value in response to receiving a high DAC output signal at the output of the DAC.

[0193] In some aspects of the above circuit, the CTIA includes a feedback capacitor configured to store a total charge, the value corresponding to a charge less than the total charge.

[0194] In some aspects of the above circuit, the quantizer is configured to determine whether the CTIA output signal at the output of the CTIA is greater than a threshold, and to output a first digital value to the DAC in accordance with a determination that the CTIA output signal is greater than the threshold, and to output a second digital value to the DAC in accordance with a determination that the CTIA output signal is less than or equal to the threshold, and the DAC is configured to output a high DAC output signal to the adder in response to receiving the first digital value, and to cease outputting the high DAC output signal to the adder in response to receiving the second digital value.

[0195] In some aspects of the circuit, the circuit further includes an analog-to-digital converter (ADC) electrically coupled to the output of the CTIA. The ADC is configured to receive a voltage corresponding to the residual charge at the output of the CTIA and provide a digital value corresponding to the residual charge. The digital output includes a digital value corresponding to the residual charge.

[0196] In some aspects of the above circuit, the voltage corresponding to the residual charge is less than the quantizer threshold.

[0197] In some aspects of the above circuit, the ADC is a sigma-delta ADC.

[0198] In some aspects of the above circuit, the circuit further includes an offset cancellation circuit configured to cancel an offset from the CTIA output signal.

[0199] In some aspects of the above circuit, the offset cancellation circuit is included in the feedback of the CTIA.

[0200] In some aspects of the above circuit, the ADC is configured to convert an offset from the CTIA output signal to a digital value of the offset.

[0201] In some aspects of the above circuitry, an offset from the CTIA output signal is scaled and the scaled offset is provided to the ADC.

[0202] In some aspects of the above circuit, the circuit further includes a low pass filter included in the feedback of the CTIA.

[0203] In some aspects of the above circuit, the sensitivity of the circuit is based on the operating frequency of the circuit, which in turn is based on the integration time of the CTIA.

[0204] In some aspects of the above circuit, the digital output signal at the digital output is a digital value of the charge at the analog input of the circuit.

[0205] In some aspects of the above circuit, the digital output signal at the digital output is a digital value of the current at the analog input of the circuit.

[0206] In some aspects of the above circuit, the digital output signal at the digital output is a digital value of the voltage at the analog input of the circuit.

[0207] In some aspects of the above circuit, the circuit further includes a variable resistor electrically coupled to the analog input, the variable resistor configured to reduce a signal level of an input signal at the analog input of the circuit.

[0208] In some aspects of the above circuit, the digital filter includes a finite impulse response (FIR) decimator configured to generate a digital output signal at the digital output based on the signal received from the output of the quantizer.

[0209] In some aspects of the above circuit, the FIR decimator is further configured to receive a digital value corresponding to the residual charge at the output of the CTIA, and the FIR decimator is configured to generate a digital output signal further based on the digital value corresponding to the residual charge at the output of the CTIA.

[0210] In some aspects of the above circuitry, coefficients associated with the FIR decimator are determined using at least one of analytical determination, numerical determination based on simulation, and numerical determination based on measurement.

[0211] In some aspects of the above circuitry, the quantizer and the DAC are included in a combined quantizer and DAC of the circuit.

[0212] In one aspect, the method includes integrating an input signal using a CTIA of the circuit, determining whether a CTIA output signal at an output of the CTIA is greater than a threshold, reducing the CTIA output signal in accordance with a determination that the CTIA output signal is greater than the threshold, and ceasing to reduce the CTIA output signal in accordance with a determination that the CTIA output signal is less than or equal to the threshold.

[0213] In some aspects of the above method, the method further includes electrically coupling the sensor to the CTIA, the sensor providing the input signal, the CTIA including a feedback capacitor, the capacitance of the feedback capacitor being less than the capacitance of the sensor.

[0214] In some aspects of the above method, the method further includes generating a digital output signal corresponding to the input signal.

[0215] In some aspects of the above method, the input signal is a charge at an analog input of the circuit and the digital output signal is a digital value of the charge.

[0216] In some aspects of the above method, the input signal is a current at an analog input of the circuit and the digital output signal is a digital value of the current.

[0217] In some aspects of the above method, the input signal is a voltage at an analog input of the circuit and the digital output signal is a digital value of the voltage.

[0218] In some aspects of the above method, the digital output signal is further based on the remainder.

[0219] In some aspects of the above method, the digital output signal is generated by a digital filter.

[0220] In some aspects of the above method, the digital output signal is generated by an FIR decimator. The method further includes generating a binary sequence and providing the binary sequence to the FIR decimator. The generating binary sequence further includes outputting a first binary value in accordance with a determination that the CTIA output signal is greater than a threshold, and outputting a second binary value in accordance with a determination that the CTIA output signal is less than or equal to the threshold.

[0221] In some aspects of the above method, the method further includes providing the digital value of the remainder to an FIR decimator. The digital output signal is further based on the digital value of the remainder.

[0222] In some aspects of the above method, the method further includes determining coefficients associated with the FIR decimator using at least one of an analytical determination, a numerical determination based on a simulation, and a numerical determination based on a measurement.

[0223] In some aspects of the above method, integrating the input signal includes integrating a first portion of the input signal, and the method further includes integrating a second portion of the input signal using a CTIA.

[0224] In some aspects of the above method, whether a CTIA output signal at an output of the CTIA is greater than a threshold is determined while the first portion is being integrated at the first time. The method further includes reducing the CTIA output signal at a second time after the first time and commencing integration of the second portion at a third time after the second time in accordance with a determination that the CTIA output signal is greater than the threshold, and ceasing to reduce the CTIA output signal at the second time and commencing integration of the second portion at the third time in accordance with a determination that the CTIA output signal is equal to or less than the threshold.

[0225] In some aspects of the above method, the operating frequency of the circuit is based on a time of integration of the input signal, and the sensitivity of the circuit is based on the operating frequency of the circuit.

[0226] In some aspects of the above method, when the CTIA output signal is below the threshold and the level of the input signal is zero, the CTIA output signal corresponds to a remainder.

[0227] In some aspects of the above method, the method further includes generating a digital value of the remainder.

[0228] In some aspects of the above method, the residual digital value is generated using a sigma-delta ADC.

[0229] In some aspects of the above method, the method further includes generating a high DAC output signal in response to a determination that the CTIA output signal is greater than the threshold value. The CTIA output signal is reduced by a value, the value being generated based on the high DAC output value.

[0230] In some aspects of the above method, the method further includes ceasing to generate the high DAC output signal in response to determining that the CTIA output signal is below the threshold value.

[0231] In some aspects of the above method, the CTIA includes a feedback capacitor, the feedback capacitor configured to store a total charge, and the CTIA output signal is reduced by a value less than the total charge.

[0232] In some aspects of the above method, the method further includes removing an offset of the CTIA.

[0233] In some aspects of the above method, the offset is removed before integrating the input signal.

[0234] In some aspects of the above method, the offset is removed using an offset removal circuit included in the feedback of the CTIA.

[0235] In some aspects of the above method, removing the offset of the CTIA further includes converting the offset of the CTIA to a digital value of the offset.

[0236] In some aspects of the above method, converting the offset of the CTIA further includes scaling the offset of the CTIA.

[0237] In some aspects of the above method, the method further includes low pass filtering the offset of the CTIA.

[0238] In some aspects of the above method, a low pass filter included in the feedback of the CTIA filters the offset of the CTIA.

[0239] In some aspects of the above method, the method further includes reducing the current level of the input signal using a variable resistor.

[0240] In some aspects of the above method, the method further includes a step of determining whether readout of the input signal is complete in accordance with a determination that the CTIA output signal is below a threshold value, a step of outputting the CTIA output signal as a remainder in accordance with a determination that readout of the input signal is complete, and a step of ceasing to output the CTIA output signal as a remainder in accordance with a determination that readout of the input signal is not complete.

[0241] In some aspects of the above method, the input signal is integrated at a first time, whether readout of the input signal is completed is determined at a second time after the first time, and in accordance with a determination that readout of the input signal is completed, the CTIA output signal is output as a remainder at a third time after the second time, and in accordance with a determination that readout of the input signal is not completed, outputting the CTIA output signal as a remainder is discontinued.

[0242] In some aspects of the above method, the method further includes resetting a feedback capacitor of the CTIA before integrating the input signal.

[0243] In some aspects of the above method, the method further includes operating the circuit as a multi-stage noise shaping (MASH) modulator, and in response to operating the circuit as a MASH modulator, ceasing to determine whether the CTIA output signal at the output of the CTIA is greater than a threshold value.

[0244] In one aspect, a non-transitory computer-readable storage medium stores one or more programs, the one or more programs including instructions that, when executed by an electronic device having one or more processors and memory, cause the device to perform any of the methods described above.

[0245] Although this disclosure uses "electrically coupled" and "coupled" to describe an electrical connection between two elements of a circuit, it is understood that the electrical connection does not necessarily require a direct connection between the terminals of the components that are coupled together. Different combinations and connections of the listed components can achieve the electrical coupling without departing from the scope of this disclosure. For example, electrical routing connects between the terminals of the components that are electrically coupled together. In another example, a closed (conducting) switch connects between the terminals of the components that are coupled together. In yet another example, additional elements connect between the terminals of the components that are coupled together without affecting the characteristics of the circuit. For example, buffers, amplifiers, and passive circuit elements can be added without affecting the characteristics of the readout circuit and without departing from the scope of this disclosure.

[0246] Similarly, when this disclosure describes two elements of a circuit as being electrically disconnected, it is understood that electrical disconnection does not necessarily require a physical open between the terminals of the components being switched. It is also understood that disconnection is not limited to mean preventing electrical energy transfer between the two elements. For example, a high impedance element is connected between the terminals of the components being isolated. In another example, an open (non-conducting) switch is connected between the terminals of the components being isolated, substantially isolating the components.

[0247] Although some elements or quantities are described in an absolute sense without the term "substantially," it is understood that these elements and quantities can have a functionally equivalent quality to the absolute description. For example, in some embodiments, a factor is described as being 3. However, it is understood that this factor can be greater or less than 3, so long as the ratio is within the tolerance of the system (e.g., the accuracy requirements of the system, etc.).

[0248] Although the disclosed aspects have been fully described with reference to the accompanying drawings, it should be noted that various changes and modifications will become apparent to those skilled in the art, and such changes and modifications should be understood to be included within the scope of the disclosed aspects as defined by the appended claims.

[0249] The terms used in the description of the various described embodiments herein are merely for the purpose of describing the particular embodiment and are not intended to be limiting. When used in the description of the various described embodiments and in the appended claims, the singular forms "a", "an" and "the" are intended to include the plural, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated described items. It will also be further understood that the terms "includes", "including", "comprises" and / or "comprising", as used herein, specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

Claims

1. Analog input and a charge transimpedance amplifier (CTIA) electrically coupled to the analog input; a quantizer electrically coupled to an output of the CTIA; a digital-to-analog converter (DAC) electrically coupled to an output of the quantizer; a summer electrically coupled to an output of the DAC, the CTIA being electrically coupled to an output of the summer; a digital filter electrically coupled to the output of the quantizer; a digital output electrically coupled to the digital filter; The circuit includes:

2. the CTIA includes a feedback capacitor; the analog input is electrically coupled to a sensor; The capacitance of the feedback capacitor is smaller than the capacitance of the sensor.

2. The circuit of claim 1.

3. 2. The circuit of claim 1, wherein the summer is configured to reduce a CTIA output signal in response to receiving a high DAC output signal at the output of the DAC.

4. The quantizer determining whether a CTIA output signal at the output of the CTIA is greater than a threshold; outputting a first digital value to the DAC in response to a determination that the CTIA output signal is greater than the threshold; outputting a second digital value to the DAC in response to a determination that the CTIA output signal is less than or equal to the threshold value; It is structured as follows: The DAC is outputting a high DAC output signal to the summer in response to receiving the first digital value; ceasing to output the high DAC output signal to the summer in response to receiving the second digital value. It is configured as follows:

2. The circuit of claim 1.

5. an analog-to-digital converter (ADC) electrically coupled to the output of the CTIA; The ADC, receiving a voltage corresponding to a residual charge at the output of the CTIA; providing a digital value corresponding to the residual charge It is configured as follows: the digital output comprises the digital value corresponding to the residual charge.

2. The circuit of claim 1.

6. 10. The circuit of claim 1, further comprising an offset removal circuit configured to remove an offset from the CTIA output signal.

7. 10. The circuit of claim 1, wherein the ADC is configured to convert an offset from the CTIA output signal to a digital value of the offset.

8. The circuit of claim 1 , further comprising a low pass filter included in the feedback of the CTIA.

9. the sensitivity of the circuit is based on an operating frequency of the circuit; the operating frequency of the circuit is based on an integration time of the CTIA; 2. The circuit of claim 1.

10. 2. The circuit of claim 1, wherein the digital output signal at the digital output is a digital value of the charge at the analog input of the circuit.

11. 2. The circuit of claim 1, wherein the digital output signal at the digital output is a digital value of a current at the analog input of the circuit.

12. 2. The circuit of claim 1, wherein the digital output signal at the digital output is a digital value of the voltage at the analog input of the circuit.

13. 10. The circuit of claim 1, further comprising a variable resistor electrically coupled to the analog input, the variable resistor configured to reduce a signal level of an input signal at the analog input of the circuit.

14. the digital filter comprises a finite impulse response (FIR) decimator; the FIR decimator is configured to generate a digital output signal at the digital output based on the signal received from the output of the quantizer.

2. The circuit of claim 1.

15. 2. The circuit of claim 1, wherein the quantizer and the DAC are included in a combined quantizer and DAC of the circuit.

16. A method comprising the steps of: integrating the input signal through a capacitive transimpedance amplifier (CTIA) of the circuit; determining whether a CTIA output signal at an output of the CTIA via a quantizer of the circuit is greater than a threshold; reducing the CTIA output signal via a digital-to-analog converter (DAC) of the circuit in accordance with a determination that the CTIA output signal is greater than the threshold; and pursuant to determining that the CTIA output signal is less than or equal to the threshold, ceasing to reduce the CTIA output signal via the DAC of the circuit.

17. the CTIA is electrically coupled to a sensor providing the input signal and includes a feedback capacitor; and The capacitance of the feedback capacitor is smaller than the capacitance of the sensor.

17. The method of claim 16.

18. The method of claim 16, further comprising the step of generating a digital output signal corresponding to said input signal via a digital filter in said circuit.

19. the input signal is a charge at an analog input of the circuit; the digital output signal being a digital value of the charge; 20. The method of claim 18.

20. A non-transitory computer-readable storage medium storing one or more programs, the one or more programs including instructions that, when executed by an electronic device having one or more processors and a memory, cause the device to: integrating the input signal using the CTIA of the circuit; determining whether a CTIA output signal at an output of the CTIA is greater than a threshold; reducing the CTIA output signal in accordance with a determination that the CTIA output signal is greater than the threshold; and ceasing to reduce the CTIA output signal in response to a determination that the CTIA output signal is less than or equal to the threshold. A non-transitory computer-readable storage medium for causing a method comprising: