Power Converter Control with Snooze Mode

Abstract

In one example, the device (110) includes a control signal generator (202) and a snooze mode controller (204). The control signal generator includes an error amplifier (208) having a first output, a first input, a second input, and a first snooze input, a first comparator (210) having a second output, a third input coupled to the first output, and a fourth input, and a second comparator (212) having a third output, a fifth input coupled to the third input, a sixth input, and a second snooze input. The control signal generator also includes a logic circuit (218) having a fourth output and a logic circuit input, the first input of the logic circuit input being coupled to the second output, and a pulse generator (220) having a fifth output and a seventh input, the seventh input being coupled to the fourth output. The snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

Description

[Technical field]

[0001] A switched mode power supply (SMPS) transfers power from an input power source to a load by switching one or more power transistors or other switching elements coupled via switch nodes / terminals to energy storage elements (such as inductors, transformer inductances, and / or capacitors) that enable coupling to the load. The power transistors may be included in a power converter, which may include or be coupled to the energy storage elements. The SMPS may include a SMPS controller for providing one or more gate drive signals to the power transistors. [Background technology]

[0002] The input voltage to a converter can be greater than, less than, or equal to the output voltage. If the input voltage is greater than the output voltage, the converter may be called a "step-down" converter / regulator or a "buck converter." If the input voltage is less than the output voltage, the converter / regulator may be called a "step-up" converter / regulator or a "boost converter." If the converter / regulator can perform both step-up and step-down functions, it may be called a "buck-boost converter." Summary of the Invention

[0003] In one example, an apparatus includes a control signal generator and a snooze mode controller. The control signal generator includes an error amplifier having a first output, a first input, a second input, and a first snooze input. The control signal generator also includes a first comparator having a second output, a third input coupled to the first output, and a fourth input. The control signal generator also includes a second comparator having a third output, a fifth input coupled to the third input, a sixth input, and a second snooze input. The control signal generator also includes a logic circuit having a fourth output and a logic circuit input, the first input of the logic circuit input being coupled to the second output. The control signal generator also includes a pulse generator having a fifth output and a seventh input, the seventh input being coupled to the fourth output. The snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

[0004] In one example, an apparatus includes a control signal generator and a snooze mode controller. The control signal generator is configured to determine, with an error amplifier, an error signal indicative of a difference between a reference signal and a feedback signal representative of an output voltage of the power converter, determine whether a value of the error signal is greater than a signal representative of a current of the power converter, provide a comparison result, and provide a control signal for controlling the power converter based on the comparison result. The snooze mode controller is configured to disable at least a portion of the error amplifier in response to determining that a value of the reference voltage scaled by the scaling factor is greater than the feedback signal.

[0005] In one example, a system includes a load, a power converter, and a controller. The power converter is coupled to the load. The power converter is configured to switch power from a power source to the load. The controller is coupled to the power converter. The controller is configured to implement control over the power converter. The controller includes a control signal generator including an error amplifier. The control signal generator is configured to determine, with the error amplifier, an error signal indicative of a difference between a reference signal and a feedback signal representative of an output voltage of the power converter, determine whether a value of the error signal is greater than a signal representative of a current of the power converter, provide a comparison result, and provide a control signal for controlling the power converter based on the comparison result. The snooze mode controller is configured to disable at least a portion of the error amplifier in response to determining that a value of the reference voltage scaled by a scaling factor is greater than the feedback signal. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of an example system.

[0007] [Diagram 2] FIG. 2 is a block diagram of an example controller.

[0008] [Diagram 3] FIG. 2 is a schematic diagram of an example error amplifier.

[0009] [Figure 4] 1 is a schematic diagram of an example fast drop detection circuit.

[0010] [Figure 5A] FIG. 2 is a diagram of an example signal waveform.

[0011] [Figure 5B] FIG. 2 is a diagram of an example signal waveform.

[0012] [Figure 5C]FIG. 2 is a diagram of an example signal waveform.

[0013] [Figure 6] FIG. 2 is a diagram of an example signal waveform.

[0014] [Figure 7] FIG. 2 is a diagram of an example signal waveform.

[0015] [Figure 8] FIG. 2 is a diagram of an example signal waveform. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] A switch mode power supply (SMPS) controller switches power transistors to form a circuit arrangement with an energy storage element to provide a load current to a load and / or an output capacitor to maintain a regulated output voltage. Alternatively, although not shown herein, at least some of the power transistors are implemented as passive switches, such as diodes. The power transistors may be coupled to an energy storage inductor via a switch node / terminal during charging or discharging switching states of the power converter. In at least some examples, the energy storage inductor is switched between a charging switching state and a discharging switching state by the SMPS controller to provide an inductor current (e.g., a current through the energy storage inductor) to the load and the output capacitor to maintain a regulated output voltage. As mentioned above, in at least some examples, one or more power transistors are replaced by passive switches that react based on characteristics of a received input signal and are not switched by the SMPS controller. In some examples, the SMPS may be configured to operate as a constant current source with an energy storage element but no output capacitor. The power converter periodically cycles through a sequence of switching states (e.g., "on" and "off" states). A single on / off cycle may be referred to as a switching cycle.

[0017] The power transistors may be implemented as field effect transistors (FETs), such as metal oxide field effect transistors (MOSFETs), or any other suitable solid-state transistor devices (e.g., bipolar junction transistors (BJTs), etc.). There may be a variety of power converter architectures, each with a specific function, such as step-down, step-up, and step-down / step-up. A step-up topology power converter is described herein. However, this specification is equally applicable to step-down and / or step-down / step-up (inverting and / or non-inverting) topology power converters. This specification may also relate to other circuit architectures that provide a regulated output voltage (VOUT).

[0018] To control the power converter, the SMPS controller provides control signals based on the control mode in which the SMPS controller is implemented. The control mode can be current mode control, voltage mode control, valley control, peak control, average control, etc. Valley control is described herein. However, the present specification is equally applicable to other control modes. The SMPS controller can provide control signals to a driver or logic circuit coupled to the driver, and the driver provides gate control signals to gates of the power transistors to control the mode of operation of the power converter. The gate control signals received by the power transistors control the switching states of the power transistors, such as whether the power transistors are conducting (e.g., on) or non-conducting (e.g., off). Each state of the power converter is associated with a particular combination of power transistors that are conducting and power transistors that are non-conducting. To change the mode of operation of the power converter, the SMPS controller alters the sequence of switching states that it commands the power transistors to assume. In at least some examples, the SMPS controller includes hardware component arrangements that cause values ​​of the control signals to be determined based on these hardware component arrangements.

[0019] Several use cases for an SMPS benefit from quiescent current reduction. Quiescent current is the current consumed by the SMPS itself, independent of the current provided by the SMPS to a load. For example, quiescent current may be the current consumed by the SMPS in a no-load or light (e.g., low) load current condition. If the power source from which the SMPS draws current is a depletable power source, such as a battery, reducing the quiescent current of the SMPS may reduce the power draw from the power source and extend the usable life of the power source before recharging or replacement. If the power source from which the SMPS draws current is a non-depletable power source, such as a main power or power derived from a main power (e.g., the output of a transformer or other power converter, etc.), reducing the quiescent current of the SMPS may reduce costs associated with using the SMPS by reducing the energy consumed by the SMPS.

[0020] Some aspects herein relate to an SMPS that implements a sleep mode. The sleep mode may reduce a clock signal (SNOOZE_CLK) on which V is monitored. For example, in response to V remaining within regulation of a programmed number of cycles or periods of an oscillator signal (CLK), etc., the SMPS may determine that the rate of decrease in the value of V is such that SNOOZE_CLK may be slowed down. By slowing down SNOOZE_CLK, the quiescent current of the SMPS may be reduced compared to an application in which SNOOZE_CLK is not slowed down.

[0021] In at least some examples, the SNOOZE_CLK may be determined as a combination of multiple signals. For example, the SNOOZE_CLK may be determined by performing a logical OR operation between multiple signals. The signals may include a zero crossing detect signal (ZCD), a CLK, and a fast drop detect signal (FDD). In at least some examples, the ZCD is asserted in a valley mode control system in response to a voltage representing an inductor current of the power converter reaching zero before reaching a value of an error signal (Vea) provided by an error amplifier based on a reference signal (Vref) and a feedback signal (Vfb) based on VOUT. The CLK may be provided by an oscillator with an adjustable period programmed according to the application or use of the SMPS. In at least some examples, the FDD may be provided by a circuit that monitors the value of VOUT and provides a periodic signal having a frequency proportional to the rate at which the value of VOUT decreases. Conversely, in some systems, the FDD may be provided by a circuit that monitors the value of VOUT and provides a periodic signal having a frequency proportional to the rate at which the value of VOUT increases. In such examples, the FDD may be renamed as a fast rise detect signal. In response to SNOOZE_CLK being asserted, the SMPS may enter a snooze or sleep mode.

[0022] In some examples, the error amplifier is configured to cause the SMPS to provide a pulse of current in response to the error amplifier receiving a signal to exit the snooze mode. The error amplifier may further include a compensated signal path and an uncompensated signal path, where the uncompensated signal path responds more quickly to transient changes in value of the signal than the compensated signal path.

[0023] 1 is a block diagram of an example system 100. In at least some examples, the system 100 represents any electronic device including a SMPS 102 configured to switch power from a power source 104 to a load 106. For example, the system 100 may be an Internet of Things (IoT) device, a sensor, or any other suitable electronic device. In at least some examples, the power source 104 is a battery. In some examples, the SMPS 102 includes a power converter 108 and a controller 110. The controller 110 is configured to control the power converter 108 to switch the power provided by the power source 104 to the load 106. For example, the controller 110 may receive Vref and control the power converter 108 to provide VOUT to the load 106. While VOUT is in regulation, VOUT has a value approximately equal to Vref.

[0024] In one example of the system 100, the power source 104 is coupled to a power converter 108, which is coupled to a load 106 and a controller 110. The power converter 108 is configured to receive VIN from the power source 104, provide VOUT to the load 106 based on VIN, and implement control by the controller 110 on the power converter 108. The controller 110 can receive Vref and provide a control signal to the power converter 108 that can adjust VOUT to have a value approximately equal to Vref. In some examples, the controller 110 provides the control signal to the power converter 108. In other examples, the controller 110 provides the control signal to a driver (not shown), which drives the power converter 108 based on the control signal.

[0025] The controller 110 may include a snooze mode. In at least some examples, the snooze mode may reduce the quiescent current draw of the SMPS 102 from the power source 104 as compared to the SMPS 102 while the snooze mode is not active. The snooze mode may be activated in response to the SMPS 102 determining that VOUT is a threshold amount greater than a target voltage (e.g., as represented by Vref) remains within regulation for a programmed number of cycles of CLK. In at least some examples, while the SMPS 102 is in the snooze mode, the controller 110 does not monitor VOUT to determine a value of VOUT or a signal representative of VOUT, such as Vfb relative to Vref. In response to expiration of SNOOZE_CLK, the controller 110 may determine a value of VOUT (or Vfb) relative to Vref and control the power converter 108 based on the determination. In at least some examples, SNOOZE_CLK is programmable to have a rate of change of VOUT (e.g., a frequency proportional to the rate of change of VOUT), a fixed frequency, or a value based on the value of an inductor current of an inductor (not shown) of power converter 108. As described above, SNOOZE_CLK may be controlled to have a lower frequency in response to VOUT remaining within regulation for a programmed number of CLK cycles. VOUT remaining within regulation for a programmed number of CLK cycles may, at least in some examples, indicate that the value of VOUT is changing slowly. In response to the value of VOUT changing at a rate that exceeds the programmed rate of change, SNOOZE_CLK may be controlled to have a higher frequency. In at least some examples, in response to VOUT remaining within regulation for a programmed number of CLK cycles, the frequency of SNOOZE_CLK is decreased to reduce the quiescent current draw of SMPS 102.

[0026] 2 is a block diagram of an example controller 110. Although shown as a component of the SMPS 102, in various other examples, the controller 110 may be a component of another device, circuit, or system. In at least some examples, the controller 110 includes a control signal generator 202, a snooze mode controller 204, and an FDD circuit 206. In at least some examples, the controller 110 receives signals representing Vref, Vfb, and the current of the power converter 108 (IL) and provides a control signal (CONTROL) based at least in part on Vref, Vfb, and IL. In at least some examples, other control signals are derived based on the value of CONTROL, such as the logical inverse of the value of CONTROL. In at least some examples, the control signal generator 202 includes an error amplifier 208, a comparator 210, a comparator 212, a timer 214, a timer 216, a logic circuit 218, and a pulse generator 220. In at least some examples, the snooze mode controller 204 includes a clock combiner 222 , a comparator 224 , a logic circuit 226 , and a logic circuit 228 .

[0027] In at least some example architectures of the control signal generator 202, the error amplifier 208 is configured to receive Vref at a first input (e.g., a positive or non-inverting input) and Vfb at a second input (e.g., a negative or inverting input). In some examples, Vfb has a value determined based on VOUT (e.g., such that Vfb is the output signal of a voltage divider having VOUT as an input signal). In other examples, Vfb is substantially the same value as VOUT (e.g., in some implementations, VOUT is used as Vfb). The output of the error amplifier 208 is coupled to a first input (e.g., a positive or non-inverting input) of a comparator 210. In some examples, the error amplifier 208 receives a snooze control signal (SNOOZE) and has a snooze input configured to be turned off (e.g., non-functional) in response to SNOOZE being asserted. The comparator 210 is configured to receive IL at a second input (e.g., a negative or inverting input). The comparator 212 is configured to receive IL at a first input (e.g., a positive or non-inverting input) and a signal having a value of approximately 0 volts (V) at a second input (e.g., a negative or inverting input). In some examples, the comparator 212 is a gated comparator having a snooze input configured to receive SNOOZE and to be turned off (e.g., non-functional) in response to SNOOZE being asserted. In at least some examples, one or both of the error amplifier 208 and / or the comparator 212 receive the inverse of SNOOZE (denoted as SNOOZE_Z). SNOOZE_Z may be provided according to any suitable process or hardware architecture. Although not illustrated herein, in at least one example, SNOOZE_Z is provided by an inverter circuit 230 that receives SNOOZE as an input. In such an example, the inverter circuit may be coupled between an output of the logic circuit 228 and a snooze input of the error amplifier 208. In at least some examples, timer 214 is configured to provide signal TOFF and timer 216 is configured to provide signal TOFF_MAX.In at least some examples, TOFF is asserted in response to the sum of the off time of power converter 108 and a programmed gap or delay time between control of the power transistors of power converter 108 expiring. In at least some examples, TOFF_MAX is asserted in response to the expiration of a maximum off time for power converter 108. Timer 214 has an input coupled to a second output of error amplifier 208. For example, in response to timer 214 receiving ZCD having an asserted value, timer 214 may begin counting and provide TOFF having an asserted value a programmed time (e.g., about 10 μs in some examples) after receiving ZCD having an asserted value. Similarly, in response to timer 216 receiving ZCD having an asserted value, timer 216 may begin counting and provide TOFF_MAX having an asserted value a programmed time after receiving ZCD having an asserted value. In at least some examples, providing TOFF is also based on Vea provided by error amplifier 208, such as being inversely proportional to signal Vpfm, as described hereinafter. Comparator 210, timer 214, and timer 216 each have an output coupled to an input of logic circuit 218. Logic circuit 218 has an output coupled to an input of pulse generator 220, which has an output at which CONTROL is provided. In at least some examples, logic circuit 218 performs a logical OR function between its input signals to provide an asserted output signal in response to any one or more input signals of logic circuit 218 being asserted.

[0028] In at least some example architectures of the snooze mode controller 204, the clock combiner 222 has a first input coupled to the output of the comparator 212 to receive ZCD, a second input coupled to the output of an oscillator (not shown) to receive CLK, and a third input coupled to the output of the FDD circuit 206. The output of the snooze mode controller 204, to which the SNOOZE_CLK is provided, is coupled to a comparator 224. The comparator 224 is configured to receive Vref multiplied by a scaling factor at a first input (e.g., a positive or non-inverting input) and to receive Vfb at a second input (e.g., a negative or inverting input). In at least some examples, the scaling factor is 1.01. In other examples, the scaling factor is any suitable value. The output of the comparator 224 is coupled to an input of a logic circuit 226. The output of the logic circuit 226 is coupled to an input of a logic circuit 228, which has another input coupled to the output of the timer 216 and an output to which the SNOOZE is provided and which is coupled to the error amplifier 208. In at least some examples, logic circuit 226 is an inverter and its logical inverse, and in at least some examples, logic circuit 228 performs a logical AND function between its input signals to provide an output signal that is asserted in response to each of the input signals of logic circuit 228 being asserted.

[0029] In one example of the operation of the controller 110, the error amplifier 208 amplifies the difference between the values ​​of Vref and Vfb to provide Vea. The comparator 210 compares Vea to IL and provides an output signal COMP having an asserted value in response to the value of IL being less than Vea. In response to the assertion of COMP, the logic circuit 218 provides an asserted signal, which causes the pulse generator 220 to provide CONTROL having an asserted value for the programmed on-time determined by the pulse generator 220. In at least some examples, in response to the assertion of CONTROL, a high-side power transistor (not shown) of the power converter 108 is controlled to turn off and a low-side power transistor (not shown) of the power converter 108 is controlled to turn on. In at least some examples, in response to IL decreasing to zero before increasing to reach Vea, the comparator 212 asserts ZCD. In at least some examples, in response to assertion of ZCD, the high-side power transistor of power converter 108 is controlled to be turned off, such as via assertion of TOFF or TOFF_MAX, etc. In response to the value of ZCD decreasing to zero before increasing to Vea, controller 110 controls power converter 108 to operate in accordance with pulse frequency modulation (PFM) in which the off-time of power converter 108 is controlled based on Vea.

[0030] While power converter 108 is operating according to PFM, the off-time of power converter 108 may be a function of Vea. Timer 214 may determine the off-time and provide TOFF based on Vea and / or any other suitable signal or consideration according to any suitable process or using any suitable hardware architecture, the scope of which is not limited herein. In at least some examples, timer 214 may determine the off-time based on Vea and a gap time that defines a waiting time (e.g., gap time) until a low-side power transistor of power converter 108 is turned off after a high-side power transistor of power converter 108 is turned off. In response to expiration of the sum of the off-time determined based on the gap time and Vea, timer 214 may provide TOFF having an asserted value. In at least some examples, the off-time has a value equal to or less than about 10 microseconds. In at least some examples, timer 216 may determine a maximum off-time based at least in part on VIN and VOUT. In response to expiration of the maximum off-time, timer 216 may provide TOFF_MAX having an asserted value. In at least one example, the maximum off-time is approximately equal to VIN / L×T_HS×T_LS / I_OUT, where L is the inductance of the inductor of power converter 108, T_HS is the time that the high-side power transistor of power converter 108 turns on, T_LS is the time that the low-side power transistor of power converter 108 turns on, and I_OUT is the load current of power converter 108. In at least some examples, in response to assertion of any of TOFF_MAX, TOFF, or COMP, logic circuit 218 controls pulse generator 220 to provide CONTROL having an asserted value.

[0031] In at least some examples, under heavy load conditions, the controller 110 may control the power converter 108 according to constant on-time valley current control using pulse width modulation (PWM). As used herein, a heavy load condition may exist when the load 106 draws more than 100 milliamps (mA) of current from the power converter 108. Under medium load conditions, the controller 110 may control the power converter 108 according to constant on-time PFM with variable off-time. As used herein, a medium load condition may exist when the load 106 draws between about 15 mA and about 100 mA of current from the power converter 108. Under light load conditions, the controller 110 may control the power converter 108 to operate in a burst mode with a snooze mode, as described herein, that is active during the burst. As used herein, a light load condition may exist when the load 106 draws less than about 15 mA of current from the power converter 108.

[0032] In one example of the operation of the snooze mode controller 204, the clock combiner 222 provides a SNOOZE_CLK having an asserted value in response to an asserted value in ZCD, CLK, or FDD. For example, in at least one implementation, the clock combiner 222 performs a logical OR operation between ZCD, CLK, and FDD in response to any one or more of ZCD, CLK, or FDD having an asserted value, and provides a SNOOZE_CLK having an asserted value. In another example, the clock combiner 222 provides a SNOOZE_CLK having an asserted pulse whenever a rising edge is detected in ZCD, CLK, or FDD. The comparator 224 may be clocked by the SNOOZE_CLK such that the comparator 224 may compare its input signals and provide an output signal only while the SNOOZE_CLK is asserted. While the SNOOZE_CLK is deasserted, in at least some examples, the comparator 224 may be turned off and disabled. In at least some examples, the comparator 224 may be referred to as a clocked dynamic comparator.

[0033] In response to SNOOZE_CLK becoming asserted, the comparator 224 may compare its input signals (e.g., scaled Vref and Vfb) and provide an output signal. In some examples, Vref is scaled to provide hysteresis to the snooze mode controller 204 to prevent the snooze mode controller 204 from causing the controller 110 to go in and out of the snooze mode frequency due to transient signal noise, etc. In at least some examples, the asserted output signal provided by the comparator 224 may indicate that the value of V has decreased to within about one percent of the programmed value for VOUT and that the controller 110 should control the power converter 108 to provide a burst of current to the load 106. In at least some examples, in response to the output signal provided by the comparator 224 being asserted, SNOOZE may be deasserted and the SMPS 102 may be taken out of snooze mode. Conversely, in response to the output signal provided by comparator 224 being deasserted and TOFF_MAX being asserted, SNOOZE may be asserted and SMPS 102 may be placed or maintained in snooze mode. In response to SNOOZE being deasserted, error amplifier 208 and comparator 212 may turn on and function, and controller 110 may control power converter 108 to provide current to load 106.

[0034] In one example of the operation of the FDD circuit 206, the rate of change of V is monitored and FDD is provided based on the monitoring. For example, the FDD circuit 206 may provide the FDD as a clock signal having a frequency proportional to the rate of change of V. In response to an increase in the rate of change of V, the frequency of the FDD may be increased, and in response to a decrease in the rate of change of V, the frequency of the FDD may be decreased until the rate of change of V is too small to be detected by the FDD circuit 206. In various examples, the FDD circuit 206 may be implemented according to any suitable FDD circuit architecture, the scope of which is not limited herein.

[0035] 3 is a schematic diagram of an example error amplifier 208. Although the error amplifier 208 is shown as a component of the controller 110, in various other examples it may be a component of another device, circuit, or system. In at least some examples, the error amplifier 208 includes an amplifier 302, a resistor 304, a switch 306, a capacitor 308, a transistor 310, a transistor 312, a current source 313, a switch 314, a transistor 316, a resistor 317, a transistor 318, a resistor 319, a current source 320, a transistor 321, a transistor 322, a transistor 324, a transistor 326, a transistor 328, a current source 329, a resistor 330, a capacitor 332, a resistor 334, a transistor 336, a transistor 338, a transistor 340, a resistor 342, a current source 344, a transistor 346, a resistor 348, a comparator 350, an offset voltage source 352, a switch 354, and a pulse generator 356.

[0036] In an example architecture of the error amplifier 208, the amplifier 302 has a first input (e.g., a positive or non-inverting input) configured to receive Vref and a second input (e.g., a negative or inverting input) configured to receive Vfb. The amplifier 302 further has a first and a second output. In at least some examples, the amplifier 302 is a differential amplifier. The resistor 304 is coupled at a first terminal to a first output of the amplifier 302 and at a second terminal to a top plate of the capacitor 308 via a switch 306. In at least some examples, the switch 306 is a normally open switch configured to receive and be controlled by SNOOZE_Z. In other examples, the switch 306 can be a normally closed switch configured to receive and be controlled by SNOOZE. The bottom plate of the capacitor 308 is adapted to be coupled to ground 358. The transistor 310 has a source coupled to the top plate of the capacitor 308, a drain adapted to be coupled to a voltage source 360, and a gate. The transistor 312 has a gate coupled to the top plate of the capacitor 308, a source adapted to be coupled to ground 358, and a drain coupled to the gate of the transistor 310. The current source 313 is adapted to be coupled between the voltage source 360 ​​and the gate of the transistor 310. The switch 314 has a first terminal coupled to the first output of the amplifier 302 and a second terminal. In at least some examples, the switch 314 is a normally open switch configured to receive and be controlled by the SNOOZE_Z. In other examples, the switch 314 can be a normally closed switch configured to receive and be controlled by the SNOOZE. The transistor 316 has a gate coupled to the second terminal of the switch 314, a source coupled to ground 358 via a resistor 317, and a drain. Transistor 318 has a gate coupled to the second terminal of switch 314, a source coupled to ground 358 through resistor 319, and a drain at which Vea is provided.Current source 320 is adapted to be coupled between voltage source 360 ​​and the drain of transistor 316 .

[0037] Transistor 321 has a gate coupled to the drain of transistor 316, a source coupled to the gate of transistor 316, and a drain. Transistor 322 has a drain, a gate coupled to the drain of transistor 321, and a source adapted to be coupled to a voltage source 360. Transistor 324 has a gate coupled to the gate of transistor 322, a source adapted to be coupled to voltage source 360, and a drain. Transistor 326 has a drain, a gate coupled to the drain of transistor 324, and a source adapted to be coupled to ground 358. Transistor 328 has a gate coupled to the gate of transistor 326, a source adapted to be coupled to ground 358, and a drain. Current source 329 is adapted to be coupled between voltage source 360 ​​and the drain of transistor 328. Resistor 330 is coupled between the drain of transistor 328 and a top plate of capacitor 332. The bottom plate of capacitor 332 is adapted to be coupled to ground 358. A resistor 334 is coupled between the drain of transistor 328 and the drain of transistor 336. Transistor 336 further has a source adapted to be coupled to ground 358 and a gate. Transistor 338 has a source coupled to the drain of transistor 328, a drain adapted to be coupled to a voltage source 360, and a gate. Transistor 340 has a gate coupled to the drain of transistor 328, a source adapted to be coupled to ground 358 via resistor 342, and a drain adapted to be coupled to the gate of transistor 338. A current source 344 is adapted to be coupled between voltage source 360 ​​and the drain of transistor 340. Transistor 346 has a gate coupled to the drain of transistor 328, a source adapted to be coupled to ground 358 via resistor 348, and a drain at which the output of error amplifier 208 is provided. Comparator 350 has a first input (eg, a positive or non-inverting input) configured to receive Vref, a second input (eg, a negative or inverting input), and an output.An offset voltage source 352 is coupled to a second input of comparator 350 and provides a voltage offset to Vfb. A switch 354 is adapted to be coupled between a voltage source 360 ​​and a drain of transistor 328. In at least some examples, switch 354 is a normally open switch configured to receive and be controlled by the output signal of comparator 350. A pulse generator 356 has an input configured to receive SNOOZE and an output coupled to the gate of transistor 336.

[0038] In one example of the operation of error amplifier 208, amplifier 302, which may be any suitable transconductance amplifier, receives Vref and Vfb and amplifies the difference in value between Vref and Vfb to provide output signal COMP_PWM. Resistor 304 and capacitor 308 provide compensation to maintain stability in the PWM loop portion of error amplifier 208. Amplifier 302 drives transistor 318 to provide Vea at the drain of transistor 318. A clamp including transistor 316, resistor 317, current source 320, and transistor 321 maintains the value of COMP_PWM at a minimum or clamped voltage regardless of the value of Vref or Vfb. Transistors 322, 324, 326, and 328 together mirror the current from the source of transistor 321 to the drain of transistor 328 to provide COMP_PFM while said clamp is engaged (e.g., COMP_PWM may otherwise have a value less than the clamped voltage in the absence of the clamp). Resistor 330 and capacitor 332 provide compensation to maintain stability of the PFM loop portion of error amplifier 208. A clamp including transistor 338, transistor 340, resistor 342, and current source 344 maintains the value of COMP_PFM at a minimum or clamped voltage regardless of the value of Vref or Vfb. Transistor 346 is driven based on the value of COMP_PFM to provide an output signal Vpfm at the drain of transistor 346. While error amplifier 208 is not in snooze mode, capacitor 308, which may be a compensation capacitor, charges based on COMP_PWM. In at least some examples, in response to error amplifier 208 entering snooze mode, switch 306 opens so that a voltage is held on capacitor 308 during snooze mode. A clamp formed by transistor 310, transistor 312, and current source 313 may maintain the voltage held on capacitor 308 at a minimum or clamped voltage while in snooze mode.Additionally, in response to error amplifier 208 entering snooze mode, switch 314 opens, thereby electrically disconnecting the output of amplifier 302 from the gates of transistors 316 and 318 and the source of transistor 321 .

[0039] In at least some examples, pulse generator 356 is configured to receive SNOOZE and provide a voltage pulse (SNOOZE_EXIT_PULSE) having a programmed width in response to a falling edge of SNOOZE. In at least some examples, the programmed width is about 3 microseconds. In response to the assertion of SNOOZE_EXIT_PULSE for the pulse duration and while SNOOZE_EXIT_PULSE is asserted, transistor 336 may be conductive, pulling down the gate of transistor 340 such that the signal COMP_PFM provided at the gate of transistor 340 is approximately equal to the voltage provided at ground 358. In at least some examples, in response to the gate of transistor 340 being pulled down, error amplifier 208 causes controller 110 to control power converter 108 in accordance with PFM control. In at least some examples, transistor 336 may pull down the gate of transistor 340 to provide a single discontinuous conduction mode (DCM) pulse as a gate control signal to power converter 108. In some examples, the value of VOUT_COMP_LOW may determine whether error amplifier 208 begins operating in PWM mode or PFM mode after assertion of SNOOZE_EXIT_PULSE. For example, in response to comparator 350 determining that the value of Vref is less than Vfb plus an offset provided by offset voltage source 352, comparator 350 provides VOUT_COMP_LOW with an asserted value. In at least some examples, the offset is about 1 percent of Vref (e.g., VOUT_COMP_LOW is asserted when Vfb decreases to less than 99 percent of Vref).In response to VOUT_COMP_LOW having an asserted value, switch 354 may close, pulling up the gate of transistor 340, such that the signal COMP_PFM provided at the gate of transistor 340 is approximately equal to the voltage provided at voltage source 360, and error amplifier 208 provides Vea based on PWM control (e.g., enters high current mode in which PFM mode control is skipped). In other examples, such as when the value of Vref is not less than Vfb plus an offset provided by offset voltage source 352, the DCM pulse may be provided by other circuitry, such as the logic circuit described above, which may receive the output of controller 110 and / or SNOOZE and provide a gate control signal for use in driving the power transistors of power converter 108. For example, in some implementations, the logic circuit may provide a DCM pulse in response to the logic circuit detecting a falling edge transition at SNOOZE, regardless of the output of error amplifier 208 or controller 110.

[0040] 4 is a schematic diagram of an example FDD circuit 206. Although shown as a component of the controller 110, in various other examples, the FDD circuit 206 may be a component of another device, circuit, or system. Also, while shown having a particular architecture, in various examples, the FDD circuit 206 may have any architecture suitable for performing the functions described herein. In at least some examples, the FDD circuit 206 includes a current source 402, a transistor 404, a transistor 406, a transistor 408, a capacitor 410, a switch 412, a capacitor 414, a transistor 416, a transistor 418, a resistor 420, a capacitor 422, a switch 424, a logic circuit 426, and a delay circuit 428.

[0041] In the example architecture of the FDD circuit 206, a current source 402 is adapted to be coupled between the output of the power converter 108 and a drain of a transistor 404. The transistor 404 has a gate coupled to the drain of the transistor 404 and a source adapted to be coupled to ground 358. The transistor 406 has a gate coupled to the gate of the transistor 404, a source adapted to be coupled to ground 358, and a drain. The transistor 408 has a drain, a gate coupled to the drain of the transistor 406, and a source adapted to be coupled to the output of the power converter 108. The capacitor 410 is adapted to be coupled between the output of the power converter 108 and the gate of the transistor 408. The switch 412 is coupled between the gate of the transistor 408 and the gate of the transistor 416. The capacitor 414 is adapted to be coupled between the gate of the transistor 416 and ground 358. The transistor 416 has a source adapted to be coupled to the output of the power converter 108 and a drain. Transistor 418 has a drain coupled to the drain of transistor 416, a gate coupled to the gate of transistor 404, and a source adapted to be coupled to ground 358 via resistor 420. Capacitor 422 is adapted to be coupled between the output of power converter 108 and the source of transistor 418. Switch 424 is adapted to be coupled between the source of transistor 418 and ground 358. Logic circuit 426 has an input coupled to the drain of transistor 418 and an output. Delay circuit 428 has an input coupled to the output of logic circuit 426 and an output. In at least some examples, an output of delay circuit 428 is coupled to switch 412 and switch 424 such that an output signal of delay circuit 428 is provided to and configured to control switch 412 and switch 424.

[0042] In one example of the operation of the FDD circuit 206, VOUT is capacitively coupled to transistor 416 by capacitors 410 and 414 and to transistor 418 by capacitor 422. The default output of the FDD circuit 206 is, at least in some examples, a logic low or deasserted signal. As the value of VOUT decreases, more current flows through transistor 418 than through transistor 416. For example, the gate of transistor 416 is held to ground 358 by capacitor 414. As the value of VOUT received at the source of transistor 416 decreases, the current through transistor 416 decreases. The source of transistor 418 is held to VOUT through capacitor 422. Thus, as the value of VOUT decreases, the voltage provided at the source of transistor 418 also decreases and the gate-to-source voltage (Vgs) of transistor 418 increases. In response to the Vgs of transistor 418 increasing, the current through transistor 418 also increases and the value of the voltage provided at the input of logic circuit 426 begins to decrease from approximately VOUT toward a value approximately equal to the value of the signal provided at ground 358. In response to the current through transistor 418, which is also the current provided at the input of logic circuit 426, reaching a threshold of logic circuit 426, logic circuit 426 trips. In at least some examples, logic circuit 426 implements a logic inversion. Thus, logic circuit 426 may provide a logic high signal in response to tripping based on the current sunk through transistor 418. In at least some examples, the output signal of logic circuit 426 is FDD. Thus, in at least some examples, the output of logic circuit 426 is coupled to an input of clock combiner 222. Delay circuit 428 may be any suitable delay circuit that receives FDD at an input of delay circuit 428 and provides a reset signal (RST) at an output of delay circuit 428 after a programmed amount of time. In at least some examples, RST has substantially the same value as FDD and is configured to control switches 412 and 424 to close, resetting FDD circuitry 206 .In this manner, FDD is provided as a PWM signal having a frequency proportional to the rate of change of VOUT while the rate of change of VOUT is within the sensitivity of FDD circuitry 206. In at least some examples, FDD circuitry 206 may be adapted to provide FDD with a frequency proportional to the rate of change of VOUT when the rate of change of VOUT is greater than about 100 microvolts (μV) per microsecond (μs). In other examples, FDD circuitry 206 may be modified to provide FDD with a frequency proportional to the rate of change of VOUT when the rate of change of VOUT is somewhat less than about 100 μV / μs.

[0043] 5A is an example signal waveform diagram 505. In at least some examples, diagram 505 illustrates signals that may be provided in SMPS 102, as described in connection with various figures herein. Diagram 505 illustrates VOUT, FDD, and CLK for SMPS 102 under a heavy load subset of light load conditions (e.g., less than about 15 mA), as described above. Assuming that the inductance of the inductor of power converter 108 is about 10 microhenries (μH), the value of VOUT may decrease at a rate greater than about 100 μV / μs. As illustrated by diagram 505, as the value of VOUT decreases under heavy load conditions, FDD is asserted in repetitive pulses having a frequency proportional to the rate of change of VOUT.

[0044] 5B is a diagram 510 of example signal waveforms. In at least some examples, diagram 510 illustrates signals that may be provided in SMPS 102, as described in connection with various figures herein. Diagram 510 illustrates VOUT, FDD, and CLK for SMPS 102 under a medium load subset of light load conditions (e.g., less than about 15 mA), as described above. Assuming that the inductance of the inductor of power converter 108 is about 10 μH, the value of VOUT may decrease at a rate greater than about 10 μV / μs but less than 100 μV / us. As illustrated by diagram 510, when the value of VOUT decreases under medium load conditions, the rate of change of VOUT is insufficient to trigger FDD, and FDD has and maintains a logic low or deasserted value. To provide a clock signal to controller 110 to instruct controller 110 to compare the value of Vfb to the value of Vref, controller 110 receives a CLK from an oscillator. In at least some examples, CLK has a period of about 50 μs. In various examples, the period of CLK can be programmed to any value that provides an appropriate amount of precision in detecting the fluctuation from Vref to Vfb.

[0045] 5C is an example signal waveform diagram 515. In at least some examples, diagram 515 illustrates signals that may be provided in SMPS 102 as described in connection with various figures herein. Diagram 515 illustrates VOUT, FDD, and CLK for SMPS 102 under a light-load subset of light-load conditions (e.g., less than about 15 mA), as described above. Assuming that the inductance of the inductor of power converter 108 is about 10 μH, the value of VOUT may decrease at a rate of less than about 10 μV / μs. As illustrated by diagram 515, when the value of VOUT decreases under light-load conditions, the rate of change of VOUT is insufficient to trigger FDD, and FDD has and maintains a logic low or deasserted value. Controller 110 receives CLK from an oscillator to provide a clock signal to controller 110 to instruct controller 110 to compare the value of Vfb to the value of Vref. In at least some examples, CLK has a period of about 50 μs. However, if VOUT remains within regulation for a programmed number of cycles of CLK (e.g., about 32, or any other number appropriate for the application of the SMPS 102), the period of CLK may be increased. For example, the period of CLK may be increased from about 50 μs to about 200 μs. In various examples, the period of CLK may be programmed to any value that provides an appropriate amount of precision in detecting fluctuations from Vref to Vfb. In at least some examples, the component providing the CLK may track the number of cycles that VOUT remains within regulation and provide the CLK at a frequency determined based on that tracking.

[0046] 6 is a diagram 600 of example signal waveforms. In at least some examples, diagram 600 illustrates signals that may be provided in SMPS 102, as described in connection with various figures herein. Diagram 600 illustrates VOUT, SNOOZE_CLK, the frequency of SNOOZE_CLK (shown in diagram 600 as SNOOZE_CLK FREQ), the output of comparator 224 (shown in diagram 600 as SNOOZE_COMP), and the current in the inductor of power converter 108 (shown in diagram 600 as I). VOUT, SNOOZE_CLK, and SNOOZE_COMP are each shown with a vertical axis representing voltage in units of volts (V). SNOOZE_CLK FREQ is shown with a vertical axis representing frequency in units of kilohertz (kHz). I is shown with a vertical axis representing current in units of mA. Each of the signals shown has a horizontal axis in units of milliseconds (ms).

[0047] As shown by diagram 600, power converter 108 is operating under light load conditions where the load current of power converter 108 is approximately equal to 10 microamps (μA). Under light load conditions, SNOOZE_CLK is controlled according to CLK. As further shown by diagram 600, in response to SNOOZE_COMP not being asserted for a programmed number of periods of CLK (e.g., 32, etc.), the frequency of CLK is decreased from approximately 20 kHz to approximately 3.3 kHz. In various examples, other frequencies may be used as discussed above. As further shown by diagram 600, while CLK, and thus SNOOZE_CLK, has a frequency of approximately 20 kHz, the quiescent current (IQ) of SMPS 102 may be approximately equal to 400 nanoamps (nA). However, after decreasing the frequency of CLK, and thus SNOOZE_CLK, the IQ of SMPS 102 may be reduced to less than approximately 100 nA. As further illustrated by diagram 600, in response to the assertion of SNOOZE_COMP, the SMPS 102 exits snooze mode and provides a current pulse through the power converter 108. In at least some examples, SNOOZE_COMP is asserted in response to the value of Vfb becoming greater than the scaled Vref, as described above. Following the assertion of SNOOZE_COMP, CLK returns to the originally programmed frequency until a programmed number of CLK cycles have again elapsed without the assertion of SNOOZE_COMP, after which the frequency of CLK may again be reduced, decreasing IQ.

[0048] 7 is a diagram 700 of example signal waveforms. In at least some examples, diagram 700 illustrates signals that may be provided in SMPS 102, as described in connection with various figures herein. Diagram 700 illustrates VOUT, CLK, FDD, ZCD, SNOOZE_CLK, the output of comparator 224 (shown as SNOOZE_COMP in diagram 700), the current provided by load 106 (shown as I_out in diagram 700), and the current in the inductor of power converter 108 (shown as I in diagram 700). VOUT, CLK, FDD, SNOOZE_CLK, and SNOOZE_COMP are each shown with a vertical axis representing voltage in units of V. I_out and I are shown with a vertical axis representing current, with I_out in units of mA and I in units of Amperes (A). Each of the illustrated signals has a horizontal axis in units of ms.

[0049] As shown by diagram 700, for each rising edge of either CLK, FDD, or ZCD, a corresponding pulse appears in SNOOZE_CLK. If the value of I_out suddenly increases, the value of VOUT decreases and SNOOZE_COMP is asserted. In response to the assertion of SNOOZE_COMP, the SMPS 102 exits snooze mode and the value of I increases to service the increased I_out. As further shown by diagram 700, in at least some instances, the rate of change in VOUT resulting from the increased I_out causes the FDD circuit 206 to assert FDD and send an additional clock pulse of SNOOZE_CLK.

[0050] 8 is a diagram 800 of example signal waveforms. In at least some examples, diagram 800 illustrates signals that may be provided in SMPS 102, as described in connection with various figures herein. Diagram 800 illustrates VOUT, VOUT_COMP_LOW, PWM Error, PFM Error, a current provided by load 106 (shown as I_out in diagram 800), and a current in an inductor of power converter 108 (shown as I in diagram 800). VOUT, VOUT_COMP_LOW, PWM Error, and PFM Error are each shown with a vertical axis representing voltage in units of V. I_out and I are shown with a vertical axis representing current, with I_out in units of mA and I in units of A. Each of the illustrated signals has a horizontal axis in units of ms.

[0051] As shown in diagram 800, VOUT_COMP_LOW is asserted in response to a rapid decrease in the value of VOUT, such as due to a sudden increase in I_out. In response to the assertion of VOUT_COMP_LOW, SMPS 102 exits snooze mode and the value of I is increased to service the increased I_out. For example, in response to the assertion of VOUT_COMP_LOW, PFM Error is asserted. In response to the assertion of PFM Error, TOFF may have a value of zero and controller 110 may control power converter 108 according to a PWM mode of operation. Such control may rapidly increase the value of IL to service the increased I_out, thereby maintaining VOUT within regulation.

[0052] As used herein, the term "couple" may encompass any connection, communication, or signal path that enables a functional relationship consistent with the description herein. For example, if device A provides a signal to control device B to perform an action, (a) in a first example, device A is directly coupled to device B, and (b) in a second example, device A is indirectly coupled to device B via an intermediate component C, whereby the intermediate component C does not substantially change the functional relationship between device A and device B, and thus device B is controlled by device A via the control signal provided by device A.

[0053] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) to perform that function by a manufacturer at the time of manufacture and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through the firmware and / or software programming of the device, or through the configuration and / or layout of the hardware components and interconnections of the device, or through a combination thereof.

[0054] A circuit or device described as including certain components may instead be configured to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current power sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and be configured to be coupled to at least some of the passive elements and / or sources, thereby forming the described structure, either at the time of manufacture or at a time thereafter, e.g., by an end user and / or a third party.

[0055] Although certain components are described herein as being of a particular process technology, these components may be interchangeable with components of other process technologies. The circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to that possible prior to the component replacement. A component illustrated as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the illustrated resistor, unless otherwise noted. For example, a resistor or capacitor illustrated and described herein as a single component may be multiple resistors or capacitors coupled in series or parallel between the same two nodes as a single resistor or capacitor, respectively.

[0056] As used herein, use of the term "ground voltage potential" includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings herein. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means + / - 10 percent of the stated value.

[0057] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. 1. An apparatus comprising: A control signal generator, comprising: an error amplifier having a first output, a first input, a second input and a first snooze input; a first comparator having a second output and a third input and a fourth input coupled to the first output; a second comparator having a third output, a fifth input coupled to the third input, a sixth input, and a second snooze input; a logic circuit having a fourth output and a first logic circuit input coupled to the second output; a pulse generator having a fifth output and a seventh input coupled to the fourth output; the control signal generator, a snooze mode controller having a sixth output coupled to the first snooze input and to the second snooze input; 13. An apparatus comprising:

2. 2. The apparatus of claim 1, the error amplifier further having a seventh output; The control signal generator: a first timer having an eighth input coupled to the third output and an eighth output coupled to a second logic circuit input of the logic circuit; a second timer having a ninth input coupled to the third output, a tenth input coupled to the seventh output, and a ninth output coupled to a third logic circuit input of the logic circuit; Further comprising: An apparatus, wherein the logic circuit performs a logical OR operation between signals received via the logic circuit inputs.

3. 2. The apparatus of claim 1, The snooze mode controller: a clock combiner having an eleventh output and a clock combiner input; a third comparator having a twelfth output, an eleventh input, and a thirteenth input coupled to the twelfth input and the eleventh output; a second logic circuit having a thirteenth output and a fourteenth input coupled to the twelfth output; a third logic circuit having a third logic circuit input coupled to the thirteenth output and a fourteenth output coupled to the first snooze input and the second snooze input; 13. An apparatus comprising:

4. 4. The apparatus of claim 3, The snooze mode controller: receiving a reference voltage scaled according to a scaling factor at said eleventh input; receiving a feedback voltage at the twelfth input; receiving a zero crossing detect signal, a clock signal, and a fast drop detect signal at said clock combiner input; providing a snooze clock having a pulse asserted in response to detection of a rising edge in any one of the zero crossing detect signal, the clock signal, and the fast drop detect signal; comparing the scaled reference voltage to the feedback voltage in response to a rising edge of the snooze clock; providing a snooze mode control signal based on a comparison between the scaled reference voltage and the feedback voltage. The apparatus is configured so as to

5. 5. The apparatus of claim 4, The apparatus, wherein the apparatus is configured to reduce quiescent current in response to assertion of the snooze mode control signal.

6. 2. The apparatus of claim 1, The snooze mode controller: providing a snooze clock signal based on a zero-crossing detection signal, a clock signal, and a fast-drop detection signal, the snooze clock signal including a pulse asserted in response to a rising edge of any of the zero-crossing detection signal, the clock signal, and the fast-drop detection signal; determining whether a scaled reference voltage is greater than a feedback voltage representative of an output voltage of a power converter in response to a rising edge in the snooze clock signal to provide a snooze mode control signal; disabling at least a portion of the error amplifier and the second comparator in response to a change in value of the snooze mode control signal, whereby a quiescent current of the device is reduced by disabling the error amplifier and the second comparator in response to a change in value of the snooze mode control signal, and determining whether the scaled reference voltage is greater than the feedback voltage in response only to a rising edge in the snooze clock signal. The apparatus is configured so as to

7. 2. The apparatus of claim 1, the first comparator is configured to receive a signal representative of a current in a power converter at the fourth input; the second comparator is configured to receive a signal having a voltage of approximately zero at the sixth input; The apparatus, wherein operation of the second comparator is enabled based on a value of an output signal of the snooze mode controller.

8. 1. An apparatus comprising: A control signal generator including an error amplifier, determining, by the error amplifier, an error signal indicative of a difference between a reference signal and a feedback signal representative of an output voltage of a power converter; determining whether a value of the error signal is greater than a signal representative of a current of the power converter to provide a comparison result; providing a control signal for controlling the power converter based on the comparison. the control signal generator configured to a snooze mode controller configured to disable at least a portion of the error amplifier in response to determining that a value of the reference voltage scaled by a scaling factor is greater than the feedback signal; 13. An apparatus comprising:

9. 9. The apparatus of claim 8, The snooze mode controller: a rising edge of a zero-crossing detection signal asserted in response to a current in the power converter decreasing and reaching zero; a rising edge of a clock signal having a fixed frequency; a rising edge of a fast drop detect signal having a frequency proportional to a rate of change of the value of the output voltage of the power converter; . . the apparatus further configured to provide a snooze clock comprising a signal pulse in response to each of the.

10. 10. The apparatus of claim 9, The apparatus, wherein the snooze mode controller is further configured to compare the scaled reference voltage to the feedback signal in response to a rising edge in the snooze clock to provide a snooze comparison result.

11. 11. The apparatus of claim 10, the fixed frequency is reduced in value in response to the snooze comparison result not being asserted for a programmed number of periods of the clock signal.

12. 11. The apparatus of claim 10, the snooze mode controller is further configured to provide a snooze mode control signal based on the snooze comparison result, the snooze mode control signal being configured to disable at least a portion of the error amplifier in response to a change in value of the snooze mode control signal.

13. 13. The apparatus of claim 12, The apparatus, wherein the control signal generator is further configured to control the power converter in response to deassertion of the snooze mode control signal to provide a burst of current.

14. 10. The apparatus of claim 9, An apparatus, wherein the frequency of the snooze clock is variable based on a rate of change of the output voltage of the power converter.

15. 1. A system comprising: Load and a power converter coupled to the load, the power converter configured to switch a power from a power source to the load; a controller coupled to the power converter and configured to implement control over the power converter; A control signal generator including an error amplifier, determining, by the error amplifier, an error signal indicative of a difference between a reference signal and a feedback signal representative of an output voltage of a power converter; determining whether a value of the error signal is greater than a signal representative of a current of the power converter to provide a comparison result; providing a control signal for controlling the power converter based on the comparison. the control signal generator configured to a snooze mode controller configured to disable at least a portion of the error amplifier in response to determining that a value of the reference voltage scaled by a scaling factor is greater than the feedback signal; The controller including: Including, the system.

16. 16. The system of claim 15, The snooze mode controller: a rising edge of a zero-crossing detection signal asserted in response to a current in the power converter decreasing and reaching zero; a rising edge of a clock signal having a fixed frequency determined based on the amount of time that the output voltage of the power converter remains in regulation; a rising edge of a fast drop detect signal having a frequency proportional to a rate of change in value of the output voltage of the power converter; . . the system further configured to provide a snooze clock comprising a signal pulse in response to each of the.

17. 17. The system of claim 16, The system, wherein the snooze mode controller is further configured to compare the scaled reference voltage to the feedback signal in response to a rising edge in the snooze clock to provide a snooze comparison result.

18. 20. The system of claim 17, The system, wherein the snooze mode controller is further configured to provide a snooze mode control signal based on the snooze comparison result, the snooze mode control signal configured to disable at least the portion of the error amplifier.

19. 20. The system of claim 18, The system, wherein assertion of the snooze mode control signal reduces quiescent current consumed by the controller.

20. 20. The system of claim 18, The system, wherein the control signal generator is further configured to control the power converter to provide a burst of current in response to deassertion of the snooze mode control signal.

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