Open packaging for chip sensors

Abstract

In the described example, a device (300) includes an interconnect substrate (308) having an aperture (310) therethrough. An integrated circuit (IC) die (320) having an on-chip element (322) is mounted on the interconnect substrate with the on-chip element aligned with and facing the aperture. The IC die is overmolded with mold compound (306) on only one side of the interconnect substrate such that the aperture remains free of mold compound, allowing access of the on-chip element to the surrounding environment.

Description

[Technical field]

[0001] This application relates to a package for an integrated circuit chip having an open cavity that allows environmental access for sensors on the chip. [Background technology]

[0002] Integrated circuit (IC) chip sensors, such as humidity sensors, gas sensors, pH sensors, light sensors, MEMS (microelectromechanical) sensors, etc., that have a sensor element on the surface of the chip or within the bulk of the chip, require an opening in the package to allow physical / ambient environmental materials to reach the sensor and be measured.

[0003] Techniques such as film-assisted molding (FAM) that can mold open cavities into the package require difficult and expensive setups to achieve a reasonably priced solution. Ceramic packages that provide openings in the package are cost prohibitive for many applications. Summary of the Invention

[0004] In the illustrated example, a device includes an interconnect substrate having an aperture through the interconnect substrate. An integrated circuit (IC) die having an on-chip element is mounted on the interconnect substrate with the on-chip element aligned with and facing the aperture. The IC die is overmolded with mold compound on only one side of the interconnect substrate, such that the aperture remains free of mold compound, allowing the on-chip element access to the ambient environment. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is an isometric view of an example device in which the interconnect substrate includes an aperture for exposing the on-chip sensor to the surrounding environment.

[0006] [Diagram 2]1A-1C are cross-sectional views of an example film-assisted molding technique.

[0007] [Diagram 3] 1 is a cross-sectional view of an example device in which the interconnect substrate includes an aperture for exposing an on-chip sensor.

[0008] [Figure 4] 4 is a cross-sectional view of another example device in which an interconnect substrate includes an aperture for exposing an on-chip sensor in a flip-chip configuration.

[0009] [Figure 5A] 1A-1C are bottom views illustrating the fabrication of apertures in an exemplary interconnect substrate. [Figure 5B] 1A-1C are bottom views illustrating the fabrication of apertures in an exemplary interconnect substrate. [Figure 5C] 1A-1C are bottom views illustrating the fabrication of apertures in an exemplary interconnect substrate.

[0010] [Figure 6A] 1 illustrates the fabrication of an exemplary interconnect substrate. [Figure 6B] 1 illustrates the fabrication of an exemplary interconnect substrate. [Figure 6C] 1 illustrates the fabrication of an exemplary interconnect substrate. [Figure 6D] 1 illustrates the fabrication of an exemplary interconnect substrate. [Figure 6E] 1 illustrates the fabrication of an exemplary interconnect substrate. [Figure 6F] 1 illustrates the fabrication of an exemplary interconnect substrate. [Figure 6G] 1 illustrates the fabrication of an exemplary interconnect substrate. [Figure 6H] 1 illustrates the fabrication of an exemplary interconnect substrate. [Figure 6I] 1 illustrates the fabrication of an exemplary interconnect substrate. [Figure 6J] 1 illustrates the fabrication of an exemplary interconnect substrate. [Figure 6K]1 illustrates the fabrication of an exemplary interconnect substrate.

[0011] [Figure 7] FIG. 2 illustrates a bottom view of an exemplary interconnect substrate with a sealing ring.

[0012] [Figure 8A] 1 illustrates the assembly and encapsulation of an exemplary device having an aperture for exposing an on-chip sensor. [Figure 8B] 1 illustrates the assembly and encapsulation of an exemplary device having an aperture for exposing an on-chip sensor. [Figure 8C] 1 illustrates the assembly and encapsulation of an exemplary device having an aperture for exposing an on-chip sensor. [Figure 8D] 1 illustrates the assembly and encapsulation of an exemplary device having an aperture for exposing an on-chip sensor. [Figure 8E] 1 illustrates the assembly and encapsulation of an exemplary device having an aperture for exposing an on-chip sensor. [Figure 8F] 1 illustrates the assembly and encapsulation of an exemplary device having an aperture for exposing an on-chip sensor. [Figure 8G] 1 illustrates the assembly and encapsulation of an exemplary device having an aperture for exposing an on-chip sensor.

[0013] [Figure 9] 1 is a cross-sectional view of an exemplary interconnect substrate strip illustrating several encapsulated devices prior to singulation.

[0014] [Figure 10] 1 is a schematic diagram of an example device including an on-chip sensor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] In the drawings, like elements are designated by like reference numbers for the sake of consistency.

[0016] Multi-layer routeable leadframe (RLF) interconnect substrates, also known as "molded interconnect substrates," are a packaging technology that enables low-cost packages. No difficult or expensive machining is required to fabricate RLF interconnect substrates, which allows for rapid prototyping and easy creation of package variations. The multi-layer capability provides flexibility in pinout of encapsulated packages.

[0017] An RLF is an interconnect substrate that is manufactured using a series of additive processing steps to form an interconnect substrate having one or more conductive layers patterned into routed leads and covered with an insulating material. An integrated circuit (IC) die can be mounted on the interconnect substrate, and the RLF and IC die are then encapsulated to form an IC device.

[0018] An exemplary RLF interconnect substrate is configured to create an aperture through the interconnect substrate from one surface to the opposite surface. The aperture is formed before an IC die containing a sensor element is attached to the interconnect substrate. After attaching the IC die with the sensor element exposed in the aperture, only the backside of the chip is overmolded. In this manner, the sensor element is exposed to the ambient environment while avoiding processing steps such as direct etching on the sensor element surface.

[0019] 1 is an isometric view of an example sensor device 100 having an aperture 110 for exposing an on-chip sensor 122. The aperture 110 is formed through the interconnect substrate 108 prior to attachment of the IC die 120 to the interconnect substrate 108. The aperture 110 penetrates the interconnect substrate 108 from a surface 109 to an opposite surface (not visible in this view) on which the IC die 120 is mounted. In this example, a lead frame is bonded to the interconnect substrate 108 to provide a set of package contacts, as shown at 104. Only the IC 120 and the backside of the interconnect substrate 108 are overmolded with a mold compound 106 to form the sensor device 100. The surface 109 of the interconnect substrate 108 remains free of the mold compound.

[0020] In this example, the sensor device 100 is mounted on a printed circuit board (PCB) 102 as part of a larger system. The PCB 102 is fabricated using known or later developed PCB technology. The sensor device 100 is bonded to bond pads, and thereby to circuit traces, in the PCB 102 using known or later techniques, such as solder reflow. In other examples, other types of system substrates, such as ceramic substrates, flexible film substrates, etc., can be used in place of the PCB 102.

[0021] In this example, aperture 110 is located on the top side of device 100 to allow sensor element 122 to be exposed to the surrounding environment after device 100 is mounted on a PCB or other type of system board.

[0022] 2 is a cross-sectional view of an exemplary film-assisted molding technique. In this example, an IC die 202 having an on-chip sensor element 204 is mounted on a leadframe die attach pad (DAP) 206 and bonded to leads 207 by bond wires 208. The IC die 202 and DAP 206 are then overmolded with a bottom mold 210 and a top mold 212 into which a mold compound is injected through a port 216 to fill the space 200 surrounding the IC die 202 and DAP 206 and form a packaged sensor device. In this example, a thin film 214 of non-stick ethylene tetrafluoroethylene (ETFE) is used as a mold release agent.

[0023] The upper mold 212 is then pressed against the sensor element 204 so that a portion 218 of the upper mold 212 is substantially in contact with the sensor element 204. The ETFE thin film 214 seals the remaining space between the upper mold 218 and the on-chip sensor 204. In this way, an aperture is formed that allows the on-chip sensor 204 to be exposed to the surrounding environment.

[0024] However, manufacturing sensor devices using the FAM process requires difficult and expensive setups to create the required top and bottom molds.

[0025] 3 is a cross-sectional view of an example device 300 in which an interconnect substrate 308 includes an aperture 310 for exposing an on-chip sensor 322 located on an IC die 320 to the surrounding environment. Example device 300 is similar to example device 100 (FIG. 1).

[0026] Interconnect substrate 308 includes several layers of conductive and insulating materials where the conductive layers are patterned to form interconnect leads. In this example, layers 311 and 313 are conductive layers that are patterned into leads and contact pads. For example, leads 315 represent the various leads in lead layer 311. Contact pads 316 represent the various contact pads in lead layer 311. Vias are formed in via layer 312 to connect between the leads in layer 311 and the leads in layer 313. Insulating material 314 is disposed between the leads to insulate them from one another. In this example, the insulating material is "Ajinomoto™ Build-up Film (ABF)". The process for manufacturing interconnect substrate 308 is described in more detail below.

[0027] An aperture 310 is fabricated in interconnect substrate 308 that extends from a top surface of interconnect substrate 308 to an opposite bottom surface of interconnect substrate 308. The location of aperture 310 is selected to match the location of sensor element 322 when IC die 320 is bonded to interconnect substrate 308.

[0028] In this example, IC die 320 has copper posts formed on each bond pad of IC die 320. Posts 324 represent these copper posts. The copper posts are fabricated using any known or later developed technique for forming posts on a silicon die. IC die 320 is coupled to the interconnect substrate by soldering the copper posts to respective leads. For example, copper posts 324 are soldered to interconnect leads 315 using any known or later developed die attach technique.

[0029] In this example, a continuous copper ring 325 surrounding sensor 322 is fabricated on IC 320 along with copper posts such as copper post 324. Copper ring 325 is positioned to align with copper ring 316 fabricated in layer 311 of interconnect substrate 308. Copper ring 325 is soldered to copper ring 316 at the same time that the copper posts are soldered to the leads using known or later developed die attach techniques. In this manner, a seal is formed between the IC die in the peripheral area around sensor element 322 and the bottom surface of interconnect substrate 308. This seal prevents mold compound from entering aperture 310 when IC die 320 is overmolded with mold compound 306.

[0030] In this example, the leadframe has a set of leadframe contacts represented by leadframe contacts 304, 305. The leadframe contacts are coupled to an interconnect substrate 308 using solder, as are copper posts 324. After the device 300 is overmolded with molding compound 306, the support members of the leadframe are trimmed away to leave the leadframe contacts 304, 305. These leadframe contacts allow the device 300 to be mounted on a PCB, such as PCB 102 (FIG. 1), with an aperture 310 facing away from the PCB.

[0031] An IC die 320 is overmolded on only one side to form a bottom outer surface 307 of device 300. A top surface 309 of interconnect substrate 308 remains free of mold compound, which becomes the opposite top outer surface of device 300. In this manner, aperture 310 remains free of mold compound.

[0032] 4 is a cross-sectional view of another example device 400 in which an interconnect substrate 408 includes an aperture 410 for exposing an on-chip sensor 422 located in an IC die 420 to the ambient environment. In this example, the IC die 420 is mounted in a flip-chip configuration. Interconnect substrate 408 is similar to interconnect substrate 308 (FIG. 3) having layers 411-414 of conductive and insulating material in which the conductive layers are patterned to form interconnect leads, such as interconnect lead 415.

[0033] An aperture 410 is fabricated in interconnect substrate 408 that extends from a top surface of interconnect substrate 408 to an opposite bottom surface of interconnect substrate 408. The location of aperture 410 is selected to match the location of sensor element 422 when IC die 420 is bonded to interconnect substrate 408.

[0034] In this example, IC die 420 has copper posts formed on each bond pad of IC die 420. Posts 424 represent these copper posts. The copper posts are fabricated using any known or later developed technique for forming posts on silicon dies. IC die 420 is coupled to an interconnect substrate by soldering the copper posts to respective leads. For example, copper post 424 is soldered to interconnect lead 415.

[0035] In this example, a continuous seal 430 is formed between the IC die 420 in the peripheral area around the sensor element 422 and the top surface of the interconnect substrate 408. In this example, the seal 430 is a low viscosity epoxy underfill that is applied to fill the gap between the IC die 420 and the interconnect substrate 408. The low viscosity epoxy may be applied, for example, with a syringe. The low viscosity epoxy is drawn into the gap between the IC die 420 and the interconnect substrate 408 by capillary action. After curing, the seal is When IC die 420 is overmolded with mold compound 406 , the mold compound is prevented from entering aperture 410 .

[0036] An IC die 420 is overmolded on only one side to form a top outer surface 407 of device 400. A bottom surface 409 of interconnect substrate 408 remains free of mold compound, which becomes the opposite bottom outer surface of device 400. In this manner, aperture 410 remains free of mold compound.

[0037] In this example, a set of contacts, such as contacts 404, 405, are formed in layer 414. Vias in lead layer 413 and via layer 412 couple contacts 404, 405 to respective leads in lead layer 411. Contacts 404, 405 allow device 400 to be mounted on a PCB, such as PCB 102 (FIG. 1), having an aperture 410 facing the PCB. In this case, a hole aligned with aperture 410 may be needed in the PCB to allow sensor element 422 to be exposed to the ambient environment.

[0038] 5A-5C are bottom views illustrating the fabrication of an aperture 510 in an exemplary interconnect substrate 500. The exemplary interconnect substrate 500 is similar to interconnect substrate 108 (FIG. 1), interconnect substrate 308 (FIG. 3), and interconnect substrate 408 (FIG. 4).

[0039] Figure 5A illustrates a set of copper contact pads, generally designated 504, 505, exposed on a bottom surface of an interconnect substrate 500 that may be used to bond the interconnect substrate to another substrate, such as PCB 102 as shown in Figure 1. In this example, the insulating layer of the interconnect substrate is fabricated using ABF.

[0040] As will be described in more detail with reference to Figures 6A-6K, on ​​each layer of the interconnect substrate 500, a copper cylinder 524 is fabricated as a stack of copper rings. Although shown as circular rings in this example, in other examples the closure structure 524 may have other shapes such as oval, square, rectangular, etc. A residual element 526 is surrounded by the copper cylinder 524.

[0041] FIG. 5B illustrates interconnect substrate 500 after copper cylinder 524 has been removed using an etching process to form an empty cylindrical space 525 that surrounds residual element 526 .

[0042] FIG. 5C illustrates interconnect substrate 500 after removal of residual elements 526 to form apertures 510.

[0043] 6A-6K illustrate the fabrication of an exemplary interconnect substrate 500 (FIG. 5C), which is similar to interconnect substrate 108 (FIG. 1), interconnect substrate 308 (FIG. 3), and interconnect substrate 408 (FIG. 4). Any known or later developed technique for fabricating routeable lead interconnect substrates may be used to fabricate the interconnect substrate. See, for example, "Molded Interconnect Substrate (MIS) Technology for Semiconductor Packaging" by Michael M. Liu, 2002. The following is a brief description of a technique for fabricating the interconnect substrate. [Non-Patent Document 1] “Molded Interconnect Substate (MIS) Technology for Semiconductor Packages,” Michael M. Liu, 2020.

[0044] 6A shows a cross-sectional view of a metal carrier 602 on which interconnect substrates are fabricated. In this example, an interconnect substrate for a single device is shown. A set of interconnect substrates may be fabricated simultaneously as strips of substrates or sheets of substrates. The substrates are then separated after fabrication of the complete device.

[0045] 6B illustrates a metal layer 604, such as copper, plated onto a metal carrier 602 and then patterned and etched using a lithographic process to form a set of horizontal interconnect leads of various configurations, for example to provide interconnects and bond pads for coupling to bond pads on an IC. In this example, a closing ring 524-1 is provided to begin the aperture contour.

[0046] FIG. 6C illustrates a second metal layer 606, such as copper, that is plated, patterned, and etched to form a set of vertical vias to form the vertical interconnects. In the case of a single layer interconnect, the vias may be used for external contacts. In the case of a multi-layer interconnect, the vias may connect the interconnect leads on the first interconnect layer to respective interconnect leads on the second interconnect layer. In this example, a second closed ring 524-2 is fabricated on top of the first ring 524-1.

[0047] 6D illustrates an insulating layer 608 formed over the first interconnect layer 604 and the via layer 606. In this example, the insulating layer 608 is ABF. In another example, the insulating layer 608 can be, for example, an epoxy molding compound.

[0048] 6E illustrates a planarized top surface 610 created by grinding away insulating layer 608. In this way, the tops of the vias and the top of ring 524-2 are exposed.

[0049] 6F shows a second interconnect layer 614, such as copper, that is plated onto the planarized surface 610 and then patterned and etched using a lithographic process to form a second set of horizontal interconnect leads of various configurations. The interconnect leads in the interconnect layer 614 can connect to the tops of the vias in the via layer 606. In this example, a third closed ring 524-3 is fabricated on top of the second ring 524-2.

[0050] 6G illustrates a second metal layer 606, such as copper, that is plated, patterned, and etched to form a set of vertical vias to form vertical interconnects. These vias can be used for external contacts. In this example, a fourth closed ring 524-4 is fabricated on top of the third ring 524-3.

[0051] 6H illustrates a second insulating layer 618 formed over the second interconnect layer 614 and the via layer 616. In this example, the insulating layer 618 is ABF. In another example, the insulating layer may be, for example, an epoxy molding compound.

[0052] 6I illustrates a planarized top surface 620 created by grinding away insulating layer 618. In this manner, the tops of the vias are exposed. Similarly, the tops of cylinders 524 are exposed. Cylinders 524 include rings 524-1, 524-2, 524-3, 524-4 and surround residual elements 526.

[0053] 6J illustrates the empty cylindrical space 525 surrounding the residual element 526 after removing the copper cylinder 524 using an etching process. An etch mask is created on the surface 620 and then patterned to expose only the top of the metal cylinder 524. The metal cylinder 524 is then removed by a full metal etching process.

[0054] 6K illustrates a planarized bottom surface 622 opposite the planarized top surface 620. The bottom surface 622 is formed by etching or grinding away the bulk of the carrier 602 below the now molded / built-up interconnect substrate to expose the horizontal interconnects and die attach pad. The exposed die attach pad may be provided with a surface finish such as NiPdAu, Cu+OSP, and / or a pre-plated leadframe (PPF) configuration. Once the carrier 602 is removed, the residual elements 526 are freed and removed to expose the aperture 510 extending through the top surface 620 and the bottom surface 622.

[0055] In this manner, a two-layer interconnect substrate having opposing planar surfaces is fabricated. Using the same process steps, apertures 510 are fabricated in the interconnect substrate. In other examples, additional interconnect layers may be fabricated in a similar manner. In another example, a single layer interconnect substrate may be fabricated in a similar manner.

[0056] 7 is a bottom view of an example interconnect substrate 308 (FIG. 3) showing continuous sealing ring 316 (see FIG. 3) in more detail. Sealing ring 316 is patterned and etched in first interconnect layer 311 of interconnect substrate 308. As described with respect to FIG. 3, sealing ring 316 is configured to mate with a matching copper ring fabricated on an IC, such as copper ring 325 (FIG. 3) on IC 320 (FIG. 3). In this example, copper ring 316 and copper ring 325 (FIG. 3) are circular. In other examples, different shapes, such as oval, square, rectangular, etc., can also be fabricated.

[0057] 8A-8G illustrate the assembly and encapsulation of an example device 800 having an aperture 810 for exposing an on-chip sensor 822. In this example, interconnect substrate 808 is similar to interconnect substrate 408 (FIG. 4). The interconnect substrate includes areas 840 on each perimeter side that are etched to create recesses that are then plated with a conductive material, such as gold, to form solder-wettable side areas for each contact pad.

[0058] FIG. 8A is a cross-sectional view and FIG. 8B is an isometric view of an example interconnect substrate 808 including an aperture 810 fabricated as illustrated in FIGS. 6A-6K.

[0059] 8C is a cross-sectional view of an example IC die 820 having an on-chip sensor 822. The IC die 820 includes raised copper posts 824 topped with solder paste to facilitate soldering the IC 820 to the interconnect substrate 808.

[0060] FIG. 8D is a cross-sectional view and FIG. 8E is an isometric view of an example IC 820 after it has been soldered to an example interconnect substrate 808 using known or later developed techniques.

[0061] In this example, a continuous seal 830 of sealing compound is placed in the peripheral area around the IC 820 around the sensor element 822 between the bottom surface of the IC 820 and the top surface of the interconnect 808. In this example, the seal 830 is a low viscosity epoxy underfill placed to fill the gap between the IC die 820 and the interconnect substrate 808. This seal prevents the mold compound from entering the aperture 810 when the IC die 820 is overmolded with mold compound 806.

[0062] FIG. 8F is a cross-sectional view and FIG. 8G is an isometric view of the completed exemplary sensor device 800. Mold compound 806 is overmolded onto only a portion of the top surface of IC die 820 and the top surface of interconnect substrate 808. Mold compound 806 forms the top surface of sensor device 800, and a bottom surface of interconnect substrate 808 forms the opposite bottom surface of sensor device 800. A continuous seal 830 around the peripheral region of IC die 820 around sensor element 822 prevents mold compound 806 from entering aperture 810 during the overmolding process. In this manner, aperture 810 penetrates the outer surface of device 800 after overmolding has been performed.

[0063] In this manner, the sensor element is fabricated as a quad flat no-lead (QFN) package with the IC die mounted in a flip-chip configuration with a downward facing aperture for the sensor element. In this example, holes are provided in the PCB to provide access for the on-chip sensor to the environment around the sensor device when it is mounted on the PCB.

[0064] In another embodiment, a similar process can be used to package an IC die having an on-chip sensor element in a face-up configuration using a supplemental lead frame, such as a lead frame having contacts 304, 305 (FIG. 3).

[0065] 9 is a cross-sectional view of an example interconnect substrate strip 908, illustrating several encapsulated devices 9001, 9002, 9003 prior to singulation. In this example, individual IC dies 820 are attached to the interconnect substrate strip 908 using known or later developed die attachment techniques.

[0066] In this example, a continuous seal of sealing compound 830 is placed in a peripheral area around each IC 820 around the sensor element 822 between the bottom surface of the IC 820 and the top surface of the interconnect strip 908. In this example, the seal is a low viscosity epoxy underfill placed to fill the gap between each IC die 820 and the interconnect substrate 908. This seal prevents mold compound from entering apertures 810 when the IC die 820 is overmolded with mold compound 806.

[0067] The entire strip is then overmolded with mold compound 906. Due to the seal in the peripheral area around each IC die 820, aperture areas 810 remain free of mold compound.

[0068] After being overmolded, the strip is then singulated by sawing or by other known or later developed singulation techniques.

[0069] FIG. 10 is a schematic diagram of an example sensor device 1000 including an on-chip sensor. In this example, the sensor device 1000 includes an on-chip relative humidity (RH) sensor 1022 and an on-chip temperature sensor. The relative humidity sensor 1022 must be exposed to the ambient environment through an aperture in the sensor device's package. The aperture is provided through an interconnect substrate, such as the example interconnect substrate 308 (FIG. 3) or interconnect substrate 408 (FIG. 4). In this example, an analog-to-digital converter (ADC) 1051 converts analog signal samples from the RH sensor 1022 and the temperature sensor 1023 into digital data samples, which are then stored in local registers by logic 1052. In this example, an inter-integrated circuit (I2C) interface is configured to allow an external device coupled to the contact pads of the device 1000 to access the sensor data samples. Other Examples

[0070] In a described example, the sensor device has an IC die that is sealed to the interconnect substrate using an epoxy underfill to fill the gap between the IC die and the interconnect substrate. In another described example, a ring formed on the IC die is used to seal the gap between the IC die and the interconnect substrate. In either case, the IC die is mounted in a flip-chip configuration with the sensor element facing down. Either sealing configuration may be used in conjunction with a supporting lead frame so that the sensor element can be facing up in the sealed package.

[0071] In the described example, the sensor device is provided with a round aperture so that the on-chip sensor can access the surrounding environment, in other examples the aperture may be of a different shape such as oval, square, rectangular, etc.

[0072] In the illustrated example, the aperture is defined by a closed metal shape having a central core that is filled with a dielectric. After etching away the closed metal shape, the dielectric core is removed. In another example, the closed metal shape may be solid metal, so that the aperture is exposed after the metal shape is etched away.

[0073] In the described examples, an IC die with on-chip sensor elements is described. In other examples, the IC die has on-chip actuator elements or other types of on-chip elements that must interact with an environment external to the chip package. For example, such on-chip elements can be ultrasonic transducers, laser emitters, microelectromechanical (MEMS) actuators, deformable mirrors, etc.

[0074] In the illustrated example, the interconnect substrate is an RLF, also known as a molded interconnect substrate, which is manufactured using a series of additive processing steps to form an interconnect substrate having one or more conductive layers patterned into routed leads and covered with an insulating material. In another example, the interconnect substrate may be manufactured using other known or later developed techniques, such as multi-layer ceramic interconnect substrates, silicon-based interconnect substrates, etc.

[0075] In the described embodiment, the interconnect substrate is fabricated using copper plating and ABF insulating material. In other examples, different combinations of conductive and insulating materials may be used. For example, epoxy insulating material may be used.

[0076] In the described example, the apertures are formed in the exemplary interconnect substrate using the same process steps used to form the interconnect leads. In another example, the apertures may be formed in the exemplary substrate after the substrate is completed by machining holes by drilling, laser cutting, stamping, or the like.

[0077] In the illustrated example, the surface of the interconnect substrate is ground flat to form a flat surface. In another example, grinding may not be necessary as long as the surface is sufficiently flat to form a continuous seal around the perimeter of the aperture to prevent molding compound from entering the aperture during the overmolding process.

[0078] In the described example, a quad flat no-lead package is formed. In other examples, various types of packages can be formed in which the aperture for the on-chip sensor element penetrates into the interconnect substrate that forms the outer surface of the package, such as quad flat-pack, dual flat-pack, dual flat no-lead, dual in-line, etc.

[0079] In this description, the term "couple" and its derivatives refer to an indirect, direct, optical, and / or wireless electrical connection. Thus, when a first device couples to a second device, the connection may be through a direct electrical connection, through an indirect electrical connection through other devices and connections, through an optical signal connection, etc.

[0080] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. A device, comprising: a substrate having a first surface and a second surface opposite the first surface, the substrate including an aperture extending through the first surface and the second surface; an integrated circuit (IC) die mounted on the first surface, the IC die including an area opposite the aperture; a molding material covering at least a portion of the IC die and adjacent at least a portion of the first surface; Including, the device.

2. 2. The device of claim 1, The device further includes a sealing material around the region and between the IC die and the first surface.

3. 3. The device of claim 2, The device, wherein the sealing material is a metal ring.

4. 3. The device of claim 2, The device, wherein the sealing material is a cured epoxy.

5. 2. The device of claim 1, the substrate further includes at least one of a first contact pad on a first surface, a second contact pad on the second surface, and an interconnect extending from the first surface to a third contact pad; The device, wherein the IC die is mounted on the first contact pads.

6. 6. The device of claim 5, A device wherein the interconnects are external to the molding material.

7. 2. The device of claim 1, The device wherein the region includes an on-chip sensor element.

8. 2. The device of claim 1, The region comprises an on-chip actuator element.

9. 7. The device of claim 6, The device, wherein the substrate is part of a quad flat no-lead (QFN) package and the aperture penetrates a surface of the QFN package.

10. 2. The device of claim 1, The device, wherein the first surface and the second surface are planar surfaces.

11. The device of claim 1, The device wherein the substrate further comprises one or more metal layers covered with an insulating material.

12. The device of claim 11, The device, wherein the one or more metal layers comprise one or more copper layers.

13. The device of claim 11, The device, wherein the insulating material comprises at least one of a ceramic material and an epoxy material.

14. The device of claim 11, A device wherein the substrate is a routeable lead frame (RLF).

15. The device of claim 1, The device, wherein the IC die is mounted on the first surface via copper posts.

16. A packaged integrated circuit (IC), comprising: a package substrate having a first surface and a second surface opposite the first surface, the package substrate including multiple metal layers, metal vias covered by insulating material, and openings extending through the first surface and the second surface; a semiconductor die mounted to the first surface, the semiconductor die including an area opposite the opening; an encapsulant covering at least a portion of the semiconductor die, the encapsulant adjacent at least a portion of the first surface; A packaged IC comprising:

17. The packaged IC of claim 16, A packaged IC, wherein the encapsulation material comprises a molding material.

18. The packaged IC of claim 16, The packaged IC further includes a sealing material around the region and between the semiconductor die and the first surface.

19. The packaged IC of claim 16, the package substrate further includes a first contact pad on the first surface and a second contact pad on the second surface; A packaged IC, wherein the semiconductor die is mounted on the first contact pads.

20. The packaged IC of claim 16, the package substrate further includes a first contact pad on the first surface and an interconnect extending from the first surface to a third contact pad and external to the encapsulation material; A packaged IC, wherein the semiconductor die is mounted on the first contact pads.

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