Duty cycle control for uniformity

Abstract

A method is described for achieving a first uniformity level in a process rate across a surface of a substrate. The method includes receiving a first uniformity level to be achieved across the surface of the substrate and identifying a first plurality of duty cycles associated with a first plurality of states based on the first uniformity level. The first plurality of states are of a variable of a first radio frequency (RF) signal. The method further includes controlling an RF generator to generate the first RF signal having the first plurality of duty cycles.

Description

[Technical field]

[0001] The present embodiments relate to systems and methods for controlling duty cycles to achieve uniformity in the processing of substrates. [Background technology]

[0002] With each generation of semiconductor technology, wafer diameters tend to increase and transistor sizes tend to decrease, resulting in ever-increasing demands for greater precision and repeatability in wafer processing. Semiconductor substrate materials, such as silicon wafers, are processed by techniques that involve the use of plasma chambers. These techniques include plasma applications such as plasma etching, plasma cleaning, and plasma deposition.

[0003] Currently available plasma processing systems are among the semiconductor manufacturing tools that are increasingly demanding improved precision and repeatability in plasma applications, and it is in this context that the embodiments described in this disclosure arise.

[0004] The background discussion provided herein is intended to provide a general context for the present disclosure. Work by the currently named inventors, to the extent described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0005] The embodiments of the present disclosure provide a system, an apparatus, a method, and a computer program for controlling the duty cycle to achieve uniformity in the processing of a substrate. It is noted that the embodiments can be implemented in many ways, such as a process, an apparatus, a system, a device, or a method recorded on a computer readable medium. Some embodiments are described below.

[0006] In one embodiment, a method for achieving a first uniformity level in a process rate across a surface of a substrate is described. The method includes receiving a first uniformity level to be achieved across the surface of the substrate and identifying a first plurality of duty cycles associated with a first plurality of states based on the first uniformity level. The first plurality of states are of a variable of a first radio frequency (RF) signal. The method further includes controlling an RF generator to generate the first RF signal having the first plurality of duty cycles.

[0007] In one embodiment, a method for achieving a first uniformity level in a process rate across a surface of a substrate is described. The method includes receiving a first uniformity level to be achieved across the surface of the substrate and identifying a plurality of duty cycles associated with a plurality of states based on the first uniformity level. The plurality of states are of variables of a plurality of RF signals. The method also includes controlling a plurality of RF generators to generate the plurality of RF signals.

[0008] In one embodiment, a controller for achieving a first uniformity level in a process rate across a surface of a substrate is described. The controller includes a processor that receives a first uniformity level to be achieved across the surface of the substrate. The processor identifies a first plurality of duty cycles associated with a first plurality of states based on the first uniformity level. The first plurality of states are of a variable of a first RF signal. The processor further controls the RF generator to generate the first RF signal having the first plurality of duty cycles. The controller includes a memory device coupled to the processor. The memory device stores the first uniformity level.

[0009] Some advantages of the systems and methods described herein include controlling the uniformity in the processing of a substrate by controlling the duty cycle of an RF signal generated by an RF generator. The duty cycle can be controlled to achieve uniformity in the center region, or the edge region, or both the center and the edge regions of the substrate. The duty cycle is determined before processing of the substrate. Once the duty cycle is determined, an RF signal having that duty cycle is generated during processing of the substrate to achieve uniformity. Further advantages of the systems and methods described herein include determining multiple duty cycles for multiple states of the RF signal. By determining the duty cycle of the states, the uniformity is controlled.

[0010] A further advantage of the systems and methods described herein is that the uniformity is controlled by controlling multiple duty cycles of multiple RF signals generated by multiple RF generators. By controlling the duty cycles of the RF signals, the uniformity is controlled. Furthermore, a duty cycle is determined for each state of each RF signal. The duty cycles are then applied to the RF signals to achieve uniformity.

[0011] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0012] The present embodiments will be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0013] [Figure 1] FIG. 1 is a diagram of one embodiment of a system to illustrate the adjustment of a duty cycle associated with the operation of a radio frequency generator (RFG) during processing of a substrate.

[0014] [Figure 2A]FIG. 2A is one embodiment of a graph to illustrate multiple duty cycles of a variable first RF signal generated by an RF generator.

[0015] [Figure 2B] FIG. 2B is one embodiment of a graph to illustrate the change in duty cycle with respect to one or more states of a variable of an RF signal.

[0016] [Figure 2C] FIG. 2C is one embodiment of a graph to illustrate the change in duty cycle with respect to one or more states of a variable of an RF signal.

[0017] [Diagram 3] FIG. 3 is one embodiment of a graph to illustrate the variation of etch rate of etching a substrate versus radius of the substrate.

[0018] [Figure 4] FIG. 4 is one embodiment of a graph for illustrating the decrease in uniformity of the processing rate of a substrate with increasing duty cycle associated with the state of the first through pth RF signal variables.

[0019] [Figure 5A] FIG. 5A is a diagram of one embodiment of a system for illustrating the generation of a list of uniformity levels and duty cycles.

[0020] [Figure 5B] FIG. 5B is a diagram of one embodiment of a system to illustrate the use of a thickness measurement device to measure intensity values ​​of light emitted by a plasma reflected from the left edge region, center region, and right edge region of a substrate.

[0021] [Figure 6]FIG. 6 is a diagram of one embodiment of a system to illustrate internal components within the RF generator of FIG. 1 for controlling the duty cycle between states S1 through Sn associated with each of the first through pth RF signals.

[0022] [Figure 7A] FIG. 7A is a diagram of one embodiment of a system to illustrate the use of multiple RF generators to power a plasma chamber and control of duty cycles associated with multiple RF signal variables to achieve uniformity in substrate processing rate.

[0023] [Figure 7B] FIG. 7B is one embodiment of a list of duty cycles of states associated with the RF generator of FIG. 7A.

[0024] [Figure 8A] FIG. 8A is an illustration of one embodiment of the graph of FIG. 2B.

[0025] [Figure 8B] FIG. 8B is an illustration of an embodiment of a graph to illustrate multiple duty cycles of a variable RF signal generated by an RF generator.

[0026] [Figure 8C] FIG. 8C is an illustration of an embodiment of a graph to illustrate multiple duty cycles of a variable RF signal generated by an RF generator.

[0027] [Figure 9] FIG. 9 is a diagram of one embodiment of a system for illustrating the generation of the list of FIG. 7B.

[0028] [Figure 10] FIG. 10 is a diagram of one embodiment of a system to illustrate the use of a thickness measurement device to measure plasma light intensity values ​​reflected from the left edge region, center region, and right edge region of a substrate.

[0029] [Figure 11] FIG. 11 is a diagram of one embodiment of a system to illustrate internal components of the RF generator of FIG. 7A for controlling the duty cycle of an RF signal generated by the RF generator.

[0030] [Figure 12A] FIG. 12A is an embodiment of the graph of FIG. 2A.

[0031] [Figure 12B] FIG. 12B is one embodiment of a graph to illustrate that as the pulse repetition rate decreases, the duty cycle of each pulse of the RF signal generated by the RF generator of FIG. 1 increases to achieve the same pulse width.

[0032] [Figure 13] FIG. 13 is a diagram of one embodiment of the graph of FIG. 2A to illustrate the RF signal generated by the RF generator of FIG.

[0033] [Figure 14A] FIG. 14A is a diagram of one embodiment of a desktop computer to illustrate the selection of one of the uniformity levels of FIG. 5A or FIG. 7B.

[0034] [Figure 14B] FIG. 14B is an illustration of one embodiment of a desktop computer for illustrating in graphical form the selection of one of the uniformity levels of FIG. 5A or FIG. 7B. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] The following embodiments describe systems and methods for controlling duty cycles to achieve uniformity in the processing of substrates. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well known operations have not been described in detail so as not to unnecessarily obscure the embodiments.

[0036] FIG. 1 is a diagram of an embodiment of a system 100 for illustrating the adjustment of a duty cycle during operation of an RF generator (RFG) 1 while processing a substrate S, such as a semiconductor wafer. The system 100 includes an RF generator RFG1, an impedance matching circuit 102, a plasma chamber 104, and a host computer 106. An example of the RF generator RFG1 is a low frequency RF generator. Another example of the RF generator RFG1 is a high frequency RF generator. An example of a low frequency RF generator is an RF generator having a low frequency operation of 100 kilohertz (kHz), or 400 kHz, or 2 megahertz (MHz). As an example, the high frequency RF generator has a high frequency operation of 13.56 MHz, 27 MHz, or 60 MHz. Yet another example of a low frequency RF generator is an RF generator having a low frequency operation of 100 kHz.

[0037] As an example, an impedance matching circuit as used herein includes a network of circuit components, such as capacitors, inductors, and resistors. The circuit components are connected to each other. For example, two of the circuit components are connected to each other in series or parallel.

[0038] The plasma chamber 104 includes a substrate support 108, such as an electrostatic chuck (ESC). The plasma chamber 104 further includes an upper electrode 110 disposed above the substrate support 108, forming a gap 112 between the upper electrode 110 and the substrate support 108. A lower electrode embedded in the substrate support 108 is made of a metal, such as aluminum or an alloy of aluminum. The substrate support 108 is made of a metal and a ceramic, such as aluminum oxide (Al2O3). The upper electrode 110 is made of a metal and is connected to a reference potential, such as ground potential or a negative potential. An example of the plasma chamber 104 is a capacitively coupled plasma (CCP) chamber.

[0039] Examples of the host computer 106 include a desktop computer, a laptop computer, a tablet, a smartphone, and a controller. The host computer 106 includes a processor 114 and a memory device 116. By way of example, the processor 114 may be a central processing unit (CPU), a field programmable gate array (FPGA), a programmable logic device (PLD), or a microcontroller. Examples of the memory device 116 include a read-only memory (ROM) and a random access memory (RAM). By way of example, the memory device 116 is a flash memory or a redundant array of independent disks (RAID). The processor 114 is connected to the memory device 116. The processor 114 is connected to the RF generator RFG1 via a transfer cable TC1. Examples of the transfer cable include a cable that allows serial transfer of data, or a cable that allows parallel transfer of data, or a cable that allows transfer of data using the Universal Serial Bus (USB) protocol.

[0040] An output O1 of the RF generator RFG1 is connected to an input I1 of the impedance matching circuit 102 via an RF cable RFC1. Also, an output OIMC of the impedance matching circuit 102 is connected to a bottom electrode of the substrate support 108 via an RF transmission line 122. An example of the RF transmission line 122 is an RF cable surrounded by an RF sheath, with an insulator between the RF cable and the RF sheath.

[0041] The processor 114 stores a list 117 of uniformity levels and duty cycles in the memory device 116. The list 117 is generated using a method described below with reference to FIG. 5A or a method described below with reference to FIG. 5B. The uniformity levels include a uniformity that can be achieved across the top surface 124 of the substrate S during processing of the substrate S in the plasma chamber 104. As an example, each of the uniformity levels includes a value that defines a speed at which the substrate S is processed across the top surface 124 of the substrate S. By way of example, each of the uniformity levels is a plot of a graph. The graph plots the speed at which the substrate S is processed against the radius of the substrate S. The top surface 124 faces the bottom surface of the upper electrode 110, and the bottom surface 126 of the substrate S faces adjacent to the top surface of the substrate support 108. The uniformity levels include a uniformity level UNFM1, a uniformity level UNFM2, a uniformity level UNFM3, etc., up to a uniformity level UNFMp, where p is a positive integer.

[0042] Each uniformity level stored in the memory device 116 corresponds to a number of duty cycles of a number of states of a variable, such as power or voltage or frequency. The states are states of corresponding ones of the first through p-th RF signals generated by the RF generator RFG1. For example, there is a one-to-one mapping or relationship between the uniformity level UNFM1 and a set of duty cycles that define the variable of the first RF signal generated by the RF generator RFG1. The set of duty cycles includes a duty cycle DCS11 of a state S1 that defines the variable of the first RF signal, a duty cycle DCS21 of a state S2 that defines the variable of the first RF signal, and so on, up to a duty cycle DCSn1 of a state Sn that defines the variable of the first RF signal, where n is a positive integer. As another example, there is a one-to-one mapping between the uniformity level UNFM2 and a set of duty cycles of a variable of the second RF signal generated by the RF generator RFG1. The set of duty cycles includes a duty cycle DCS12 that defines a state S1 of a variable of the second RF signal, a duty cycle DCS22 that defines a variable of the second RF signal, and so on up to a duty cycle DCSn2 of a state Sn that defines a variable of the second RF signal. As yet another example, there is a one-to-one mapping between the uniformity level UNFM3 and a set of duty cycles of a third RF signal generated by the RF generator RFG1. The set of duty cycles includes a duty cycle DCS13 of a state S1 that defines a variable of the third RF signal, a duty cycle DCS23 of a state S2 that defines a variable of the third RF signal, and so on up to a duty cycle DCSn3 of a state Sn that defines a variable of the third RF signal. As yet another example, there is a one-to-one mapping between the uniformity level UNFMp and a set of duty cycles that defines a period for applying a variable of the pth RF signal, e.g., RF signal 130. The set of duty cycles includes a duty cycle DCS1p that defines a state S1 of the variable of RF signal 130, a duty cycle DCS2p that defines a state S2 of the variable of RF signal 130, and so on up to a duty cycle DCSnp that defines a state Sn of the variable of RF signal 130.

[0043] It should be noted that in one embodiment, the number of duty cycles DCS11-DCSn1 corresponding to the uniformity level UNFM1 is different from the number of duty cycles DCS1p-DCSnp corresponding to the uniformity level UNFMp. For example, five duty cycles correspond to the uniformity level UNFM1, and three duty cycles correspond to the uniformity level UNFMp. Also, in this example, there are five states S1-S5 corresponding to the uniformity level UNFM1, and three states S1-S3 corresponding to the uniformity level UNFMp. The five states S1-S5 and the duty cycles DCS11-DCS51 corresponding to the uniformity level UNFM1 are repeated with each cycle of the clock signal. Furthermore, the three states S1-S3 and the duty cycles DCS1p-DCS3p corresponding to the uniformity level UNFMp are repeated with each cycle of the clock signal. For example, the number of duty cycles DCS11-DCS51 corresponding to uniformity level UNFM1 does not exceed 5, and the number of duty cycles DCS1p-DCS3p corresponding to uniformity level UNFMp does not exceed 3. The number of states corresponding to a uniformity level is equal to the number of duty cycles corresponding to that uniformity level. Similarly, in this embodiment, the number of duty cycles DCS12-DCSn2 corresponding to uniformity level UNFM2 is different from the number of duty cycles DCS1p-DCSnp corresponding to uniformity level UNFMp. Also, in this embodiment, the number of duty cycles DCS13-DCSn3 corresponding to uniformity level UNFM3 is different from the number of duty cycles DCS1p-DCSnp corresponding to uniformity level UNFMp.

[0044] As an example, the duty cycle of a variable is the period or time interval during which the variable has a state represented by the variable level. For example, a duty cycle DCS1p is the time interval during which the variable has state S1. As another example, a duty cycle DCS2p is the time interval during which the variable has state S2, and a duty cycle DCSnp is the time interval during which the variable has state Sn.

[0045] The processor 114 receives instructions from a user via an input device, such as a signal including a uniformity level UNFMa to be achieved in processing the substrate S. Examples of the input device include a keyboard, a touch screen, a mouse, a stylus, and a keypad. The input device is connected to the processor 114 via a transmission cable.

[0046] Upon receiving the instruction, the processor 114 determines whether the uniformity level UNFMa is within a predetermined range from one of the uniformity levels UNFM1 to UNFMp in the list 117 stored in the memory device 116. For example, the processor 114 analyzes the uniformity level UNFMa to identify a plurality of values ​​for the uniformity level UNFMa. The processor 114 determines whether a majority of the values ​​defining the uniformity level UNFMa are within a predetermined range from a majority of the values ​​defining one of the uniformity levels UNFM1 to UNFMp. Upon determining that a majority of the values ​​defining the uniformity level UNFMa are within a predetermined range from a majority of the values ​​defining one of the uniformity levels UNFM1 to UNFMp, the processor 114 determines that the uniformity level UNFMa is within a predetermined range from one of the uniformity levels UNFM1 to UNFMp. On the other hand, if the processor 114 determines that the majority of the values ​​defining the uniformity level UNFMa are not within the predetermined range from the majority of the values ​​defining one of the uniformity levels UNFM1 to UNFMp, the processor 114 determines that the uniformity level UNFMa is not within the predetermined range from one of the uniformity levels UNFM1 to UNFMp, for example, is outside the range.

[0047] As another example, if the uniformity level UNFMa is a graphical plot, such as a graphical representation or a graphical curve, the processor 114 analyzes the uniformity level UNFMa to identify multiple values ​​of the uniformity level UNFMa. The processor 114 calculates a first statistical value from the values ​​of the uniformity level UNFMa. The processor 114 determines whether the first statistical value is within a predetermined range from the second statistical value calculated from one of the uniformity levels UNFM1 to UNFMp. If the processor 114 determines that the first statistical value is within the predetermined range from the second statistical value, the processor 114 determines that the uniformity level UNFMa is within the predetermined range from one of the uniformity levels UNFM1 to UNFMp. On the other hand, if the processor 114 determines that the first statistical value is not within the predetermined range from the second statistical value, the processor 114 determines that the uniformity level UNFMa is not within the predetermined range from one of the uniformity levels UNFM1 to UNFMp, e.g., is outside the range. Examples of statistical values ​​include the mean and the median. The second statistical value is calculated by the processor 114 from the value of one of the uniformity levels UNFM1 to UNFMp.

[0048] The predetermined range is stored in memory device 116 for access by processor 114. By way of example, the predetermined range is ±1%, or ±2%, or ±3%, or ±4%, or ±5%.

[0049] Upon determining that the uniformity level UNMFa is within a predetermined range from one of the uniformity levels UNFM1-UNFMp in the list 117 stored in the memory device 116, such as the uniformity level UNFMp, the processor 114 identifies from the memory device 116 a set of duty cycles corresponding to one of the uniformity levels UNFM1-UNFMp. For example, the processor 114 identifies from the memory device 116 duty cycles DCS1p-DCSnp as corresponding to the uniformity level UNFMp, such as being linked or mapped to the uniformity level UNFMp. By way of example, the processor 114 goes down the list 117 to find a row p among rows 1-p having duty cycles DCS1p-DCSnp and a uniformity level UNFMp. Upon finding the row p having the duty cycles DCS1p-DCSnp and the uniformity level UNFMp, the processor 114 determines that the duty cycles DCS1p-DCSnp correspond to the uniformity level UNFMp. Row p includes a one-to-one correspondence between duty cycles DCS1p-DCSnp and uniformity levels UNFMp. Processor 114 accesses, eg, reads, duty cycles DCS1p-DCSnp from list 117.

[0050] The processor 114 generates a recipe signal 128 including the variable duty cycles DCS1p-DCSnp of the RF signal 130 and transmits the recipe signal 128 to the RF generator RFG1 via the transfer cable TC1. Upon receiving the duty cycles DCS1p-DCSnp, the RF generator RFG1 stores the duty cycles DCS1p-DCSnp in one or more memory devices within the RF generator RFG1.

[0051] Additionally, the RF generator RFG1 stores variables and parameters for each of the states S1-Sn in one or more memory devices of the RF generator RFG1. For example, the RF generator RFG1 stores multiple variable levels for the states S1-Sn and parameter levels, such as a single parameter level for the states S1-Sn, in one or more memory devices. The variable levels and parameter levels for the states S1-Sn are received by the RF generator RFG1 from the processor 114 via the transfer cable TC1. By way of example, the variable levels and parameter levels for the states S1-Sn are received in the recipe signal 128. The processor 114 receives an input signal indicative of the variable levels and parameter levels for the states S1-Sn from a user via an input device.

[0052] An example of a parameter is frequency. Another example of a parameter is voltage or power. For example, if the variable is power or voltage, the parameter is frequency. As another example, if the variable is frequency, the parameter is power or voltage.

[0053] Further, the processor 114 generates a trigger signal 131 and transmits the trigger signal 131 to the RF generator RFG1 via the transmission cable TC1. An example of the trigger signal 131 is a digital pulse signal. The digital pulse signal is not periodic and does not repeat. After the recipe signal 128 is transmitted to the RF generator RFG1, the trigger signal 131 is transmitted to the RF generator RFG1. Upon receiving the trigger signal 131, the RF generator RFG1 generates an RF signal 130 having variable levels for the states S1-Sn, parameter levels for the states S1-Sn, and duty cycles DCS1p-DCSnp for the states S1-Sn. The RF generator RFG1 provides the RF signal 130 at the output O1.

[0054] An RF signal 130 is provided from output O1 to input I1 of impedance matching circuit 102 via RF cable RFC1. When RF signal 130 is routed through impedance matching circuit 102, the circuit components of impedance matching circuit 102 modify the impedance of RF signal 130 by matching the impedance at the input of a load connected to output OIMC with the impedance at the output of a source connected to input I1. Examples of loads include RF transmission line 122 and plasma chamber 104. Examples of sources include RF cable RFC1 and RF generator RFG1. The impedance of RF signal 130 is modified to output modified RF signal 132 at output OIMC.

[0055] The modified RF signal 132 is provided from the output OIMC via RF transmission line 122 to a bottom electrode of the substrate support 108. Additionally, one or more process gases are provided into the gap 112 such that a plasma is struck or sustained in the gap 112 to process the substrate S. Examples of processing the substrate S include etching the substrate S, depositing one or more material layers on the substrate S, cleaning the substrate S, or sputtering the substrate S. Examples of the one or more process gases include an oxygen-containing gas, a fluorine-containing gas, and combinations thereof.

[0056] In one embodiment, the terms impedance matching circuit, impedance matching network, match, impedance match, matching network, match circuit, and match network are used interchangeably herein.

[0057] In one embodiment, a duty cycle is the time interval during which a variable has a state and transitions to that state from a previous state. For example, a duty cycle DCSnp is the time period during which a variable has a state Sn and transitions from state S(n-1) to state Sn. State Sn is successive to state S(n-1). State S(n-1) precedes state Sn.

[0058] In one embodiment, a duty cycle is the time interval during which a variable has a state and transitions from that state to a successive state. For example, a duty cycle DCS(n-1)p is the time period during which a variable has a state S(n-1) and transitions from state S(n-1) to state Sn. State Sn is successive to state S(n-1). State S(n-1) precedes state Sn.

[0059] In one embodiment, the impedance matching circuit 102 is connected to the upper electrode 110 instead of the substrate support 108 via an RF transmission line 122. In this embodiment, the substrate support 108 is connected to a reference potential.

[0060] It should be noted that in one embodiment, the duty cycle that defines the state of a variable of an RF signal is the period during which an envelope of power or frequency values ​​that delineates the state occurs. Examples of an envelope include variable levels such as peak-to-peak magnitude and zero-to-peak magnitude. Peak-to-peak magnitude is sometimes referred to herein as peak-to-peak amplitude.

[0061] In one embodiment, the number of duty cycles corresponding to the uniformity level UNFMp is greater or less than the number of duty cycles corresponding to the uniformity level UNFM(p-1). For example, the uniformity level UNFM1 has a one-to-one mapping with three duty cycles DCS11, DCS21, and DCS31, and the uniformity level UNFM2 has a one-to-one mapping with two duty cycles DCS12 and DCS22. To illustrate, the uniformity level UNFM1 is realized by controlling the RF generator RFG1 to generate a first RF signal having three duty cycles DCS11, DCS21, and DCS31. In this example, the uniformity level UNFM2 is realized by controlling the RF generator RFG1 to generate a first RF signal having two duty cycles DCS12 and DCS22.

[0062] In one embodiment, a first variable level for a first state, such as state S1, is a first peak-to-peak amplitude or a first zero-to-peak amplitude of the variable and has one or more values. And a second variable level for a second state, such as state S2, is a second peak-to-peak amplitude or a zero-to-peak amplitude of the variable and has one or more values. The first variable level is excluded from the second variable level. For example, the minimum of the one or more values ​​defining the first variable level is greater than the maximum of the one or more values ​​defining the second variable level. In this example, the first variable level is greater than the second variable level.

[0063] In one embodiment, a parameter level for multiple states, such as states S1-Sn, includes one or more values ​​of the parameter.

[0064] In one embodiment, a state represents a variable level, for example a first state has a variable level that is different from the variable level of a second state, the variable level of the first state being greater or less than the variable level of the second state.

[0065] 2A is one embodiment of a graph 200 to illustrate multiple duty cycles defining a variable of a first RF signal generated by RF generator RFG1 (FIG. 1). Graph 200 includes a plot 202 of the variable of the first RF signal generated by RF generator RFG1 versus time t. The variable is plotted on the y-axis and time t is plotted on the x-axis.

[0066] The x-axis of graph 200 is divided into equal time intervals. For example, the x-axis of graph 200 is divided into a first time interval between times t0 and t1, a second time interval between times t1 and t2, a third time interval between times t2 and t3, a fourth time interval between times t3 and t4, a fifth time interval between times t4 and t5, a sixth time interval between times t5 and t6, a seventh time interval between times t6 and t7, and an eighth time interval between times t7 and t8. The x-axis of graph 200 is also divided into a ninth time interval between times t8 and t9, a tenth time interval between times t9 and t10, an eleventh time interval between times t10 and t11, a twelfth time interval between times t11 and t12, a thirteenth time interval between times t12 and t13, a fourteenth time interval between times t13 and t14, a fifteenth time interval between times t14 and t15, and a sixteenth time interval between times t15 and t16.

[0067] The y-axis of graph 200 is divided into variable levels of the first RF signal. For example, the y-axis of graph 200 has a variable level 0, a variable level V1a, a variable level V2a, a variable level V3a, and a variable level V4a. The variable level V4a is greater than the variable level V3a, which is greater than the variable level V2a. The variable level V2a is greater than the variable level V1a, which is greater than the variable level 0.

[0068] The y-axis of graph 200 is also divided into equal variable level intervals. For example, a first interval between variable levels 0 and V1a is equal to a second interval between variable levels V1a and V2a. The second interval is also equal to a third interval between variable levels V2a and V3a. Similarly, the third interval is equal to a fourth interval between variable levels V3a and V4a.

[0069] Plot 202 transitions from variable level V1a to variable level V4a at time t0. Plot 202 has variable level V4a for the period between time t0 and time t2. Plot 202 transitions from variable level V4a to variable level V3a at time t2. Plot 202 remains at variable level V3a for the time interval between time t2 and time t4, and transitions from variable level V3a to variable level V2a at time t4. Plot 202 has variable level V2a for the time interval between time t4 and time t6. Plot 202 transitions from variable level V2a to variable level V1a at time t6, and remains at variable level V1a for the period between time t6 and time t8.

[0070] The variable level V4a of plot 202 defines the state S4 of the variable of the first RF signal. Similarly, the variable level V3a of plot 202 defines the state S3 of the variable of the first RF signal, the variable level V2a of plot 202 defines the state S2 of the variable of the first RF signal, and the variable level V1a of plot 202 defines the state S1 of the variable of the first RF signal.

[0071] The variable levels V4a-V1a of plot 202 are repeated during each cycle of the clock signal. For example, a first instance of variable levels V4a-V1a of plot 202 occurs during cycle 1 of the clock signal, and a second instance of variable levels V4a-V1a occurs during cycle 2 of the clock signal. Cycle 2 is consecutive to cycle 1. Cycle 1 precedes cycle 2.

[0072] The clock signal can be generated in the RF generator RFG1 by a clock source such as a processor or a clock oscillator. As an example, the clock signal is a square wave pulse signal.

[0073] The time interval during which state S4 of the variable of the first RF signal plot 202 occurs is illustrated as duty cycle DCS41. Similarly, the time interval during which state S3 of the variable of the first RF signal plot 202 occurs is illustrated as duty cycle DCS31, the time interval during which state S2 of the variable of the first RF signal plot 202 occurs is illustrated as duty cycle DCS21, and the time interval during which state S1 of the variable of the first RF signal plot 202 occurs is illustrated as duty cycle DCS11.

[0074] In one embodiment, the clock signal is generated by the processor 114 and provided to the RF generator RFG1 via the transmission cable TC1 or a separate cable.

[0075] In one embodiment, the transitions of the variables illustrated in plot 202 of RF signal 130 occur within time intervals. For example, instead of transitioning from variable level V4a to variable level V3a at time t2, plot 202 transitions during a time interval from a first time to a second time. The first time is between time t1.5 and time t2, and the second time is between time t2 and time t2.5. Time t1.5 occurs halfway through the time interval between time t1 and time t2, and time t2.5 occurs halfway through the time interval between time t2 and time t3. In this example, the duty cycle of variable level V3a includes the time interval between occurrences of variable level V3a and the time interval between transitions from variable level V4a to variable level V3a. As another example, the duty cycle of variable level V4a includes the time interval between occurrences of variable level V4a and the time interval between transitions from variable level V4a to variable level V3a.

[0076] 2B is one embodiment of a graph 210 to illustrate the change in duty cycle with respect to one or more states defining a variable of RF signal 130. Graph 210 includes a plot 212 of the variable of RF signal 130 (FIG. 1) versus time t. The variable is plotted on the y-axis of graph 210, and time t is plotted on the x-axis of graph 210.

[0077] The x-axis of graph 200 is divided into equal time intervals as illustrated in graph 200 of FIG. 2A. The y-axis of graph 210 is also divided into equal variable levels as in graph 200. Plot 212 transitions from variable level 0 to variable level V4a at time t0. Plot 212 has variable level V4a for the period between time t0 and time t2.5. Plot 212 transitions from variable level V4a to variable level V3a at time t2.5. Plot 212 remains at variable level V3a for the time interval between time t2.5 and time t4, and transitions from variable level V3a to variable level V2a at time t4. Plot 212 has variable level V2a for the time interval between time t4 and time t6.5, which is halfway through the time interval between time t6 and t7. Plot 212 transitions from variable level V2a to variable level V1a at time t6.5 and remains at variable level V1a for the period between time t6.5 and time t8.

[0078] The variable level V4a illustrated in plot 212 defines state S4 of the variable of RF signal 130. Similarly, the variable level V3a illustrated in plot 212 defines state S3 of the variable of RF signal 130, the variable level V2a illustrated in plot 212 defines state S2 of the variable, and the variable level V1a illustrated in plot 212 defines state S1 of the variable.

[0079] The variable levels V4a-V1a illustrated in plot 212 are repeated during each cycle of the clock signal. For example, a first instance of the variable levels V4a-V1a illustrated in plot 202 occurs during cycle 1 of the clock signal, and a second instance of the variable levels V4a-V1a illustrated in plot 202 occurs during cycle 2.

[0080] The time interval during which state S4 of the variable of plot 212 occurs is illustrated as duty cycle DCS4p. Similarly, the time interval during which state S3 of the variable of plot 212 occurs is illustrated as duty cycle DCS3p, the time interval during which state S2 of the variable occurs is illustrated as duty cycle DCS2p, and the time interval during which state S1 of the variable occurs is illustrated as duty cycle DCS1p.

[0081] It should be noted that duty cycles DCS41, DCS31, DCS21, and DCS11 are adjusted to generate duty cycles DCS4p, DCS3p, DCS2p, and DCS1p. For example, duty cycle DCS4p is greater than duty cycle DCS41 (FIG. 2A) and duty cycle DCS3p is less than duty cycle DCS31 (FIG. 2A). Also, duty cycle DCS2p is greater than duty cycle DCS21 (FIG. 2A) and duty cycle DCS1p is less than duty cycle DCS11 (FIG. 2A).

[0082] In one embodiment, the transitions of the variables illustrated in plot 212 of RF signal 130 occur within time intervals. For example, instead of transitioning from variable level V4a to variable level V3a at time t2.5, plot 212 transitions during a time interval from a first time to a second time. The first time is between time t2 and time t2.5, and the second time is between time t2.5 and time t3. In this example, the duty cycle defining variable level V3a includes the time interval between occurrences of variable level V3a and the time interval between transitions from variable level V4a to variable level V3a. As another example, the duty cycle defining variable level V4a includes the time interval between occurrences of variable level V4a and the time interval between transitions from variable level V4a to variable level V3a.

[0083] 2C is one embodiment of a graph 214 to illustrate the change in duty cycle with respect to one or more states of a variable of a first RF signal generated by RF generator RFG1 (FIG. 1). Graph 214 includes a plot 216 of a variable of the (p-5)th RF signal generated by RF generator RFG1 versus time t. The variable of the (p-5)th RF signal is plotted on the y-axis of graph 214 and time t is plotted on the x-axis of graph 214.

[0084] The x-axis of graph 214 is divided into equal time intervals as illustrated in graph 200 of FIG. 2A. The y-axis of graph 214 is also divided into equal variable levels, similar to that of graph 200. Plot 216 transitions from variable level 0 to variable level V4a at time t0. Plot 216 has variable level V4a for the period between time t0 and time t4. Plot 216 transitions from variable level V4a to variable level V1a at time t4. Plot 216 remains at variable level V1a for the time interval between time t4 and time t8, and transitions from variable level V1a to variable level V4a at time t8.

[0085] The variable level V4a of plot 216 defines the state S2 of the variable of the (p-5)th RF signal. Similarly, the variable level V1a of plot 216 defines the state S1 of the variable of the (p-5)th RF signal. The variable levels V1a and V4a of plot 216 are repeated during each cycle of the clock signal. For example, a first instance of variable levels V1a and V4a of plot 216 occurs during cycle 1, and a second instance of variable levels V1a and V4a occurs during cycle 2.

[0086] The time interval during which state S2 of the variable of the (p-5)th RF signal plot 216 occurs is illustrated as duty cycle DCS2(p-5). Similarly, the time interval during which state S1 of the variable of the (p-5)th RF signal plot 216 occurs is illustrated as duty cycle DCS1(p-5).

[0087] It should be noted that the duty cycles DCS41, DCS31, DCS21, and DCS11 of the first RF signal generated by RF generator RFG1 are adjusted to produce duty cycles DCS2(p-5) and DCS1(p-5) generated by RF generator RFG1. For example, duty cycle DCS41 is adjusted to be zero, duty cycle DCS31 is adjusted to be zero, duty cycle DCS21 is adjusted to be DCS2(p-5), and duty cycle DCS11 is adjusted to be DCS1(p-5).

[0088] In one embodiment, the transitions of variables illustrated in plot 216 of the (p-5)th RF signal occur within a time interval. For example, instead of transitioning from variable level V4a to variable level V1a at time t4, plot 216 transitions during a time interval from a first time to a second time. The first time is between time t3.5 and time t4, and the second time is between time t4 and time t4.5. Time t3.5 occurs halfway through the time interval between time t3 and time t4. Time t4.5 occurs halfway through the time interval between time t4 and time t5. In this example, the duty cycle of variable level V1a includes the time interval of occurrence of variable level V1a and the time interval defining the transition from variable level V4a to variable level V1a. As another example, the duty cycle defining variable level V4a includes the time interval of occurrence of variable level V4a and the time interval of the transition from variable level V4a to variable level V1a.

[0089] FIG. 3 is one embodiment of a graph 300 to illustrate the change in etch rate for etching a substrate S versus the radius of the substrate S (FIG. 1). The etch rate across the radius of the substrate S is an example of a uniformity level in the rate for etching the substrate S. The etch rate is plotted on the y-axis and the radius of the substrate S is plotted on the x-axis. The graph 300 includes multiple plots 302, 304, 306, 308, 310, 312, and 314 to illustrate the change in uniformity, such as the uniformity level in the etch rate across the top surface 124 (FIG. 1), with a change in one or more duty cycles of one or more states of the variables defining the RF signal 130 (FIG. 1). For example, if the RF signal 130 has only two states S1 and S2, and the duty cycle of state S1 is 25%, the uniformity of the etch rate across the top surface 124 is illustrated by plot 314. As another example, when the RF signal 130 has only two states S1 and S2 during each clock cycle of the clock signal, and the duty cycle of state S1 is 75%, the etch rate uniformity across the top surface 124 is illustrated by plot 304.

[0090] Graph 300 includes plots 302-314 that define the duty cycle of a variable of RF signal 310 when RF signal 130 has only two states S1 and S2. Note, however, that plot 302 is generated when state S1 defining the variable of RF signal 130 has a duty cycle of 100%. For example, plot 302 is generated when the variable of RF signal 130 is a continuous wave (CW). By way of example, plot 302 is generated when the variable of RF signal 130 has only state S1.

[0091] Thus, as illustrated in graph 300, etch rate uniformity increases in a central region proximate the center of the substrate S with increasing duty cycle for state S1 and decreases in the central region with decreasing duty cycle. An example of a central region is a region within a predetermined distance from the center of the substrate S. Illustratively, the predetermined distance from the center is ±50 millimeters (mm). As another illustrative example, the predetermined distance from the center is ±25 mm.

[0092] Also, as illustrated in graph 300, the etch rate uniformity increases in an edge region distal to the center region of the substrate S with increasing duty cycle for state S1, and decreases in the edge region with decreasing duty cycle. An example of an edge region distal to the center region is a region within a preset distance from the edge of the substrate S. For example, the preset distance from the edge of the substrate S is ±25 mm. As another example, the preset distance from radius 0 is ±50 mm. The edge region surrounds and is at the periphery of the center region.

[0093] FIG. 4 is an embodiment of a graph 400 for illustrating the decrease in uniformity of the rate for processing a substrate S (FIG. 1) with an increase in the duty cycle of a state S1 defining one of the variables of the first through pth RF signals (FIG. 1). Note that in this embodiment illustrated with graph 400, one of the variables of the first through pth RF signals has only two states, including state S1 and state S2. Graph 400 plots percent center-to-mid (CM) uniformity against the percentage of the duty cycle defining the state S1 of one of the variables of the first through pth RF signals. An example of CM uniformity is the uniformity from the center of the substrate S. Illustratively, the CM uniformity is from the center of the substrate S to 75 mm along the radius of the substrate S. The CM uniformity is plotted on the y-axis and the percentage of the duty cycle defining the state S1 of one of the variables of the first through pth RF signals is plotted on the x-axis. As illustrated in graph 400, as the percentage of the duty cycle defining the state S1 of one of the first to pth RF signals increases, the percentage of CM uniformity, which is a measure of the uniformity of the processing rate of the substrate S, decreases.

[0094] 5A is a diagram of one embodiment of a system 500 for illustrating the generation of the list 117 having uniformity levels and duty cycles. The system 500 includes the host computer 106, an RF generator RFG1, an impedance matching circuit 102, and a plasma chamber 503.

[0095] The plasma chamber 503 has the same components as the plasma chamber 104 (FIG. 1). For example, the plasma chamber 503 includes the substrate support 108 and the upper electrode 110.

[0096] The plasma chamber 503 has a sidewall 502 having a plurality of windows 504, 506, and 508. For example, the windows 504-508 are integrated into the sidewall 502. The plasma chamber 503 has a top wall 510 and a bottom wall 512. The top wall 510 is disposed above the sidewall 502, and the sidewall 502 is disposed above the bottom wall 512.

[0097] Associated with the window 504 are etch rate measurement devices (ERMDs) 514, 516, and 518. For example, the ERMD 514 is attached to the window 504, the ERMD 516 is attached to the window 506, and the ERMD 518 is attached to the window 508. As another example, the ERMD 514 is disposed proximate to the window 504, the ERMD 516 is disposed proximate to the window 506, and the ERMD 518 is disposed proximate to the window 508. As an example, each ERMD includes a spectrophotometer that monitors the plasma in the plasma chamber 102 and measures the intensity of radiation emitted by the plasma generated in the plasma chamber 102. As an example, each window 504, 506, and 508 is made of a transparent material, such as glass, that can pass light emitted by the plasma. In various embodiments, each window 504, 506, and 508 is a semi-transparent window.

[0098] The ERMD 514 is connected to the processor 114 via a transfer cable 520 and has a line of sight to the gap 112 of the plasma chamber 102 through a window 504. The line of sight of the ERMD 514 is directed to a space in which the plasma is generated in the plasma chamber 503. For example, the ERMD 514 includes a spectrophotometer that monitors the plasma in the plasma chamber 102 and measures the intensity of radiation emitted by the plasma through the window 504. The intensity of radiation emitted by the plasma through the window 504 is directly proportional to the etch rate of a left edge region 528 of a substrate 526 that is processed by the plasma in the plasma chamber 102. As an example, the line of sight of the ERMD 514 is directed to the left edge region 528 of the substrate 526. One example of the substrate 526 is a dummy substrate that is not processed to fabricate integrated circuits such as PLDs, FPGAs, and application specific integrated circuits (ASICs). Another example of the substrate 526 is a substrate such as a semiconductor wafer.

[0099] Similarly, the ERMD 516 is connected to the processor 114 via a transfer cable 522 and has a line of sight to the gap 112 of the plasma chamber 102 through a window 506. The line of sight of the ERMD 516 is directed to the space in the plasma chamber 503 where the plasma is generated. For example, the ERMD 516 includes a spectrophotometer that monitors the plasma in the plasma chamber 102 and measures the intensity of radiation emitted by the plasma through the window 506. The intensity of radiation emitted by the plasma through the window 506 is directly proportional to the etch rate of a central region 532 of a substrate 526 being processed by the plasma in the plasma chamber 102. As an example, the line of sight of the ERMD 516 is directed to the central region 532 of the substrate 526.

[0100] The ERMD 518 is also connected to the processor 114 via a transfer cable 524 and has a line of sight to the gap 112 of the plasma chamber 102 through a window 508. The line of sight of the ERMD 518 is directed to the space in the plasma chamber 503 where the plasma is generated. For example, the ERMD 518 includes a spectrophotometer that monitors the plasma in the plasma chamber 102 and measures the intensity of radiation emitted by the plasma through the window 508. The intensity of radiation emitted by the plasma through the window 508 is directly proportional to the etch rate of a right edge region 530 of a substrate 526 being processed by the plasma in the plasma chamber 102. As an example, the line of sight of the ERMD 518 is directed to the right edge region 530 of the substrate 526.

[0101] Note that the left edge region 528 faces one side of the central region 532, and the right edge region 530 faces the opposite side of the central region 532. For example, the left edge region 528 is to the left of the central region 532, and the right edge region 530 is to the right of the central region 532.

[0102] The substrate 526 is placed in the plasma chamber 503. The processor 114 then controls the RF generator RFG1 as described with reference to FIG. 1 to generate a pth RF signal, such as the RF signal 130. The pth RF signal, having a duty cycle DCS1p-DCSnp for the states S1-Sn of the variables of the pth RF signal, is provided to the impedance matching circuit 102, which outputs a modified RF signal 132 to the plasma chamber 503. When the modified RF signal 132 is sent to the plasma chamber 503 and one or more process gases are provided to the gap 112 in the plasma chamber 102, a plasma is generated in the gap 112 of the plasma chamber 503.

[0103] After plasma is generated in gap 112, during time period TP1, ERMD 514 generates intensity signal 534 based on a line of sight to a left edge region 528 of substrate 526 and transmits intensity signal 534 to processor 114 via transfer cable 520. Similarly, during time period TP1, ERMD 516 generates intensity signal 536 based on a line of sight to a center region 532 of substrate 526 and transmits intensity signal 536 to processor 114 via transfer cable 522. Also during time period TP1, ERMD 518 generates intensity signal 538 based on a line of sight to a right edge region 530 of substrate 526 and transmits intensity signal 538 to processor 114 via transfer cable 524.

[0104] The period TP2 occurs a preset period of time after the end of the period TP1. As an example, the period TP2 is equal to the period TP1. As another example, the period TP2 is greater than or less than the period TP1 by a preset amount stored in the memory device 116. During the period TP2, the ERMD 514 generates an intensity signal 540 based on a line of sight toward the left edge region 528 of the substrate 526 and transmits the intensity signal 540 to the processor 114 via the transmission cable 520. Similarly, during the period TP2, the ERMD 516 generates an intensity signal 542 based on a line of sight toward the center region 532 of the substrate 526 and transmits the intensity signal 542 to the processor 114 via the transmission cable 522. Also, during the period TP1, the ERMD 518 generates an intensity signal 544 based on a line of sight toward the right edge region 530 of the substrate 526 and transmits the intensity signal 544 to the processor 114 via the transmission cable 524.

[0105] The processor 114 determines a processing speed for processing the left edge region 528 of the substrate 526 based on the intensity signals 534 and 540 received from the ERMD 514. For example, the processor 114 calculates a ratio of the first difference to the second difference. The first difference is the difference between the intensity value received in the intensity signal 540 and the intensity value received in the intensity signal 534. The second difference is the difference between the periods TP2 and TP1. For example, the second difference is the difference between the end of the period TP2 and the end of the period TP1. For another example, the second difference is the difference between the start of the period TP2 and the start of the period TP1. The ratio of the first and second differences is the processing speed PRpa for processing the left edge region 528 of the substrate 526. The processor 114 stores the processing speed PRpa in the list 117 of the memory device 116.

[0106] Similarly, the processor 114 determines a processing rate for processing the central region 532 of the substrate 526 based on the intensity signals 536 and 542 received from the ERMD 516. For example, the processor 114 calculates a ratio of a first difference to a second difference. The first difference is the difference between the intensity value received in the intensity signal 542 and the intensity value received in the intensity signal 538. The second difference is the difference between the periods TP2 and TP1. The ratio of the first and second differences is the processing rate PRpb for processing the central region 532 of the substrate 526. The processor 114 stores the processing rate PRpb in the list 117 of the memory device 116.

[0107] The processor 114 also determines a processing rate for processing the right edge region 530 of the substrate 526 based on the intensity signals 538 and 544 received from the ERMD 518. For example, the processor 114 calculates a ratio of a first difference to a second difference. The first difference is the difference between the intensity value received in the intensity signal 544 and the intensity value received in the intensity signal 538. The second difference is the difference between the periods TP2 and TP1. The ratio of the first difference to the second difference is the processing rate PRpc for processing the right edge region 530 of the substrate 526. The processor 114 stores the processing rate PRpc in the list 117 of the memory device 116.

[0108] The processor 114 associates the processing rates PRpa-PRpc with the uniformity level UNFMp and stores the uniformity level UNFMp in a list 117 of the memory device 116. For example, the processor 114 determines that the processing rates PRpa-PRpc define or form the uniformity level UNFMp and stores the uniformity level UNFMp in the memory device 116. As another example, the processor 114 generates the uniformity level UNFMp by interpolating, e.g., estimating, data points between the processing rates PRpa and PRPb and between the processing rates PRpb and PRpc, and stores the uniformity level UNFMp in the memory device 116. To illustrate the interpolation, the processor 114 generates a first smooth curve between the processing rates PRpa and PRpb and a second smooth curve between PRpb and PRpc to generate the uniformity level UNFMp. A first smooth curve has processing rates PRpa and PRpb as its endpoints and a second smooth curve has PRpb and PRpc as its endpoints. Interpolation creates a first set of additional processing rates between processing rates PRpa and PRpb, and creates a second set of additional processing rates between processing rates PRpb and PRpc. The processing rates PRpa and PRpb, the data points between processing rates PRpa and PRpb, processing rates PRpb and PRpc, and the data points between processing rates PRpb and PRpc define a uniformity level UNFMp.

[0109] In a manner similar to that described above for determining the process rates PRpa-PRpc, when the first RF signal is provided by the RF generator RFG1, the processor 114 determines a plurality of process rates PR1a, PR1b, and PR1c, and stores the process rates PR1a-PR1c in a list 117 in the memory device 116. The first RF signal has duty cycles DCS11, DCS21, etc., up to duty cycle DCSn1. When the first RF signal is provided to the impedance matching circuit 102, a first modified RF signal is output from the output OIMC of the impedance matching circuit 102 and transmitted to the lower electrode of the substrate support 108 via the RF transmission line 122. Also, when the first modified RF signal is provided to the substrate support 108 of the plasma chamber 503, one or more process gases are provided to the gap 112 of the plasma chamber 503. The processor 114 defines the uniformity level UNFM1 based on the processing rates PR1a-PR1c as described above for defining the uniformity level UMFMp, and stores the uniformity level UNFM1 in a list 117 of the memory device 116.

[0110] Also, in a manner similar to that described above for determining the process rates PRpa-PRpc, when the second RF signal is provided by the RF generator RFG1, the processor 114 determines a plurality of process rates PR2a, PR2b, and PR2c, and stores the process rates PR2a-PR2c in a list 117 in the memory device 116. The second RF signal has duty cycles DCS12, DCS22, etc., up to duty cycle DCSn2. When the second RF signal is provided to the impedance matching circuit 102, the second modified RF signal is output from the output OIMC of the impedance matching circuit 102 and transmitted to the lower electrode of the substrate support 108 via the RF transmission line 122. Also, when the second modified RF signal is provided to the substrate support 108 of the plasma chamber 503, one or more process gases are provided to the gap 112 of the plasma chamber 503. The processor 114 also defines a uniformity level UNFM2 based on the processing rates PR2a to PR2c, as described above for defining the uniformity level UMFMp, and stores the uniformity level UNFM2 in a list 117 of the memory device 116.

[0111] In a manner similar to that described above for determining the process rates PRpa-PRpc, when the third RF signal is provided by the RF generator RFG1, the processor 114 determines a plurality of process rates PR3a, PR3b, and PR3c, and stores the process rates PR3a-PR3c in a list 117 in the memory device 116. The third RF signal has duty cycles DCS13, DCS23, etc., up to duty cycle DCSn3. When the third RF signal is provided to the impedance matching circuit 102, the third modified RF signal is output from the output OIMC and transmitted to the lower electrode of the substrate support 108 via the RF transmission line 122. Also, when the third modified RF signal is provided to the substrate support 108 in the plasma chamber 503, one or more process gases are provided to the gap 112 in the plasma chamber 503. The processor 114 also defines a uniformity level UNFM3 based on the processing rates PR3a to PR3c, as described above for defining the uniformity level UMFMp, and stores the uniformity level UNFM3 in a list 117 of the memory device 116.

[0112] 5B is a diagram of an embodiment of a system 550 to illustrate the use of a thickness measuring device 552 to measure intensity values ​​of light emitted from the plasma reflected from the left edge region 526, the center region 532, and the right edge region 530. The system 550 includes an RF generator RFG1, an impedance matching circuit 102, a plasma chamber 554, a thickness measuring device 552, and a host computer 106. Examples of the thickness measuring device 552 include an electron microscope, an optical ellipsometer, and a metrology tool. By way of example, the metrology tool is manufactured by KLA™. The thickness measuring device 552 is connected to the processor 114 via a transfer cable 556.

[0113] The plasma chamber 554 has the same components as the plasma chamber 104 (FIG. 1). The plasma chamber 554 has a sidewall 558, a top wall 510, and a bottom wall 512. The top wall 510 is disposed above the sidewall 558, which is disposed above the bottom wall 512. The sidewall 558 has an opening 560.

[0114] The substrate 526 is placed in the plasma chamber 554. The processor 114 then controls the RF generator RFG1 as described with reference to FIG. 1 to generate a pth RF signal, such as the RF signal 130. The pth RF signal, having a duty cycle DCS1p-DCSnp for the states S1-Sn of the variables of the pth RF signal, is provided to the impedance matching circuit 102, which outputs a modified RF signal 132 to the plasma chamber 554. When the modified RF signal 132 is sent to the plasma chamber 554 and one or more process gases are provided to the gap 112 in the plasma chamber 102, a plasma is generated in the gap 112 of the plasma chamber 554.

[0115] After the substrate 526 is processed using the plasma generated in the plasma chamber 554, during a period TP1, the substrate 526 is removed from the plasma chamber 554 through the opening 560 and placed under the thickness measuring device 552. When the left edge region 528 of the substrate 526 is placed under the thickness measuring device 552 and the thickness measuring device 552 has a line of sight to the left edge region 528 during the period TP1, the thickness measuring device 552 generates an intensity signal 534. Also, when the center region 532 of the substrate 526 is placed under the thickness measuring device 552 and the thickness measuring device 552 has a line of sight to the center region 532 during the period TP1, the thickness measuring device 552 generates an intensity signal 536. When the right edge region 530 of the substrate 526 is placed under the thickness measuring device 552 and the thickness measuring device 552 has a line of sight to the right edge region 530 during the period TP1, the thickness measuring device 552 generates an intensity signal 538. The intensity signals 534 , 536 , and 538 are transmitted from the thickness measurement device 552 to the processor 114 via a transmission cable 556 .

[0116] After the intensity signals 534, 536, and 538 are generated and transmitted to the processor 114, the substrate 526 is returned to the plasma chamber 554 for further processing. After a preset period of time has elapsed from the period TP1, the substrate 526 is removed from the plasma chamber 554 through the opening 560. During the period TP2, the substrate 526 is removed from the plasma chamber 554 and placed under the thickness measuring device 552. When the left edge region 528 of the substrate 526 is placed under the thickness measuring device 552 and the thickness measuring device 552 has a line of sight to the left edge region 528 during the period TP2, the thickness measuring device 552 generates an intensity signal 540. Also, when the center region 532 of the substrate 526 is placed under the thickness measuring device 552 and the thickness measuring device 552 has a line of sight to the center region 532 during the period TP1, the thickness measuring device 552 generates an intensity signal 542. When the right edge region 530 of the substrate 526 is positioned under the thickness measurement device 552 and the thickness measurement device 552 has a line of sight towards the right edge region 530 during a time period TP1, the thickness measurement device 552 generates an intensity signal 544. The intensity signals 540, 542, and 544 are transmitted from the thickness measurement device 552 to the processor 114 via a transfer cable 556. The processor 114 determines the processing rates PRpa, PRpb, and PRpc from the intensity signals 534, 536, 538, 540, 542, and 544 in the same manner as described above with reference to FIG. 5A, determines a uniformity level UNFMp based on the processing rates PRpa, PRpb, and PRpc, and stores the processing rates PRpa, PRpb, and PRpc and the uniformity level UNFMp in a list 117 of the memory device 116.

[0117] In a manner similar to that described above for determining the process rates PRpa-PRpc with reference to FIG. 5B, when the first RF signal is provided by the RF generator RFG1, the processor 114 determines the process rates PR1a, PR1b, and PR1c and stores the process rates PR1a-PR1c in a list 117 in the memory device 116. The first RF signal has duty cycles DCS11, DCS21, etc., up to duty cycle DCSn1. When the RF generator RFG1 provides the first RF signal to the impedance matching circuit 102, the impedance matching circuit 102 outputs a first modified RF signal to a lower electrode of the substrate support 108 of the plasma chamber 554. When the first modified RF signal is provided to the lower electrode of the substrate support 108 and one or more process gases are provided to the plasma chamber 554, the substrate 526 is processed. After being processed, the substrate 526 is removed from the plasma chamber 554 through the opening 560 and placed under the thickness measurement device 552, which generates a first set of intensity signals. The processor 114 determines processing rates PR1a, PR1b, and PR1c based on the first set of intensity signals in the same manner as described above with reference to FIG. 5B, defines a uniformity level UNFM1 using the processing rates PR1a, PR1b, and PR1c, and stores the processing rates PR1a, PR1b, and PR1c and the uniformity level UNFM1 in a list 117 in the memory device 116.

[0118] Further, in a manner similar to that described above for determining the process rates PRpa-PRpc with reference to FIG. 5B, when the second RF signal is provided by the RF generator RFG1, the processor 114 determines process rates PR2a, PR2b, and PR2c and stores the process rates PR2a-PR2c in a list 117 in the memory device 116. The second RF signal has a duty cycle DCS12, DCS22, etc., up to a duty cycle DCSn2. When the RF generator RFG1 provides the second RF signal to the impedance matching circuit 102, the impedance matching circuit 102 outputs a second modified RF signal to a lower electrode of the substrate support 108 of the plasma chamber 554. When the second modified RF signal is provided to the lower electrode of the substrate support 108 and one or more process gases are provided to the plasma chamber 554, the substrate 526 is processed. After being processed, the substrate 526 is removed from the plasma chamber 554 through the opening 560 and placed under the thickness measurement device 552, which generates a second set of intensity signals. The processor 114 determines processing rates PR2a, PR2b, and PR2c based on the second set of intensity signals in the same manner as described above with reference to FIG. 5B, applies the processing rates PR2a, PR2b, and PR2c to determine a uniformity level UNFM2, and stores the processing rates PR2a, PR2b, and PR2c and the uniformity level UNFM2 in the list 117 of the memory device 116.

[0119] Also, in a manner similar to that described above for determining the process rates PRpa-PRpc with reference to FIG. 5B, when the third RF signal is provided by the RF generator RFG1, the processor 114 determines a plurality of process rates PR3a, PR3b, and PR3c and stores the process rates PR3a-PR3c in a list 117 in the memory device 116. The third RF signal has a duty cycle DCS13, DCS23, etc., up to a duty cycle DCSn3. When the RF generator RFG1 provides the third RF signal to the impedance matching circuit 102, the impedance matching circuit 102 outputs a third modified RF signal to a lower electrode of the substrate support 108 of the plasma chamber 554. When the third modified RF signal is provided to the lower electrode of the substrate support 108 and one or more process gases are provided to the plasma chamber 554, the substrate 526 is processed. After being processed, the substrate 526 is removed from the plasma chamber 554 through the opening 560 and placed under the thickness measurement device 552, which generates a third set of intensity signals. The processor 114 determines the processing rates PR3a, PR3b, and PR3c based on the third set of intensity signals in the same manner as described above with reference to FIG. 5B, associates the processing rates PR3a, PR3b, and PR3c with the uniformity level UNFM3, and stores the processing rates PR3a, PR3b, and PR3c and the uniformity level UNFM3 in the list 117 of the memory device 116.

[0120] 6 is a diagram of an embodiment of a system 600 to illustrate internal components within an RF generator RFG1 for controlling the duty cycle between states S1-Sn of each of the first through pth RF signals. The system 600 includes an RF generator RFG1 and a host computer 106.

[0121] The RF generator RFG1 includes a digital signal processor 1 (DSP1) and a plurality of controllers. The controllers include a duty cycle controller DCC11 for state S1, a duty cycle controller DCC12 for state S2, and so on up to a duty cycle controller DCCn1 for state Sn. Furthermore, the controllers of the RF generator RFG1 include a variable controller VRS11 for state S1, a variable controller VRS21 for state S2, and so on up to a variable controller VRSn1 for state Sn. The controllers of the RF generator RFG1 also include a parameter controller PRS1 for states S1 to Sn.

[0122] As an example, a controller as used herein includes a processor and a memory device, the processor of the controller being connected to the memory device of the controller.

[0123] The RF generator RFG1 further includes a driver system DRVR1 and a power supply PS1. An example of a driver system as used herein includes a driver and an amplifier. The driver of the driver system is connected to the amplifier of the amplifier system. An example of a driver includes one or more transistors connected together. An example of an RF power supply as used herein includes an oscillator circuit capable of generating an oscillating RF signal, such as a sinusoidal RF signal.

[0124] The processor 114 is connected to the DSP1 via a transfer cable TC1. The DSP1 is connected to the duty cycle controllers DCC11-DCCn1, the variable controllers VRS11-VRSn1, and the parameter controller PRS1. The duty cycle controller DCC11 is connected to the variable controller VRS11. The duty cycle controller DCC21 is connected to the variable controller VRS21, and so on, with the duty cycle controller DCCn1 being connected to the variable controller VRSn1. The variable controllers VRS11-VRSn1 and the parameter controller PRS1 are connected to the driver system DRVR1, which is connected to the power supply PS1. The power supply PS1 is connected to the RF cable RFC1.

[0125] The processor 114 accesses the duty cycles DCS1p-DCSnp from the list 117 stored in the memory device 116, generates a recipe signal 128 having the duty cycles DCS1p-DCSnp, and transmits the recipe signal 128 to the DSP1 via the transfer cable TC1. For example, the processor 114 identifies the duty cycles DCS1p-DCSnp as corresponding to the uniformity level UNFMp to be achieved, and generates the recipe signal 128 having the duty cycles DCS1p-DCSnp. Illustratively, the processor 114 embeds the duty cycles DCS1p-DCSnp in the recipe signal 128.

[0126] Processor 114 also includes duty cycle identifiers in recipe signal 128 to indicate that duty cycles DCS1p through DCSnp are duty cycles for the state of the variable defining the pth RF signal. For example, processor 114 embeds a first duty cycle identifier in recipe signal 128 to indicate that duty cycle DCS1p is for state S1 of the variable defining the pth RF signal, embeds a second duty cycle identifier in recipe signal 128 to indicate that duty cycle DCS2p is for state S2 of the variable, and so on, embedding an nth duty cycle identifier in recipe signal 128 to indicate that duty cycle DCSnp is for state Sn of the variable.

[0127] Upon receiving the duty cycles DCS1p-DCSnp embedded in the recipe signal 128, the digital signal processor DSP1 determines from the duty cycle identifier that the recipe signal 128 includes the duty cycles DCS1p-DCSnp, extracts the duty cycles from the recipe signal 128, and transmits the duty cycles DCS1p-DCSnp to the duty cycle controllers DCC11-DCCn1. For example, the digital signal processor DSP1 identifies from the first duty cycle identifier that the recipe signal 128 includes a duty cycle DCS1p for a state S1 of the variable of the pth RF signal. The digital signal processor DSP1 identifies from the second duty cycle identifier that the recipe signal 128 includes a duty cycle DCS2p for a state S2 of the variable of the pth RF signal, and identifies from the nth duty cycle identifier that the recipe signal 128 includes a duty cycle DCSnp for a state Sn of the variable.

[0128] Upon identifying the duty cycles DCS1p-DCSnp for states S1-Sn of the pth RF signal variable, the digital signal processor DSP1 determines from the duty cycle identifiers that the duty cycle DCS1p is to be sent to the duty cycle controller DCC11 for state S1, that the duty cycle DCS2p is to be sent to the duty cycle controller DCC11 for state S2, and so on until it is determined that the duty cycle DCSnp is to be sent to the duty cycle controller DCCn1 for state Sn. The digital signal processor DSP1 sends the duty cycle DCS1p to the duty cycle controller DCC11, sends the duty cycle DCS2p to the duty cycle controller DCC21, and so on until the duty cycle DCSnp is sent to the duty cycle controller DCCn1.

[0129] The duty cycle controllers DCC11-DCCn1 store duty cycles DCS1p-DCSnp. For example, the duty cycle controller DCC11 stores a duty cycle DCS1p in a memory device of the duty cycle controller DCC11. Similarly, the duty cycle controller DCC21 stores a duty cycle DCS2p in a memory device of the duty cycle controller DCC21, and so on, with the duty cycle controller DCCn1 storing a duty cycle DCSnp in a memory device of the duty cycle controller DCCn1.

[0130] In a similar manner as described above with respect to transmitting duty cycles DCS1p-DCSnp to digital signal processor DSP1 in recipe signal 128, processor 114 transmits variable levels for states S1-Sn of RF signal 130 and parameter levels for states S1-Sn to digital signal processor DSP1 in recipe signal 128. Upon receiving the variable level for state S1, digital signal processor DSP1 transmits the variable level for state S1 of RF signal 130 to variable controller VRS11, transmits the variable level for state S2 of RF signal 130 to variable controller VRS12, and so on until the variable level for state Sn of RF signal 130 is transmitted to variable controller VRSn1. Also, upon receiving the parameter levels for states S1-Sn, digital signal processor DSP1 transmits the parameter levels of RF signal 130 to parameter controller PRS1.

[0131] Additionally, the processor 114 transmits an order for the generation of the variable levels of the RF signal 130 to the digital signal processor DSP1 in the recipe signal 128. For example, as illustrated in graph 212 (FIG. 2B), during each clock cycle, a portion of the RF signal 130 having a power level for state S4 is generated first, a portion of the RF signal 130 having a power level for state S3 is generated second, a portion of the RF signal 130 having a power level for state S2 is generated third, and a portion of the RF signal 130 having a power level for state S1 is generated fourth.

[0132] After the duty cycles DCS1p to DCSnp have been stored in the duty cycle controllers DCC11 to DCCn1, the parameter levels for the states S1 to Sn of the RF signal 130 have been stored in the parameter controllers VRS11 to VRSn1, and the parameter levels for the states S1 to Sn of the RF signal 130 have been stored in the parameter controller PRS1, the processor 114 sends a trigger signal 131 to the digital signal processor DSP1.

[0133] Upon receiving the trigger signal 131, the digital signal processor DSP1 transmits a first command signal to a first set of controllers DCC11, VRS11, and PRS1, transmits a second command signal to a second set of controllers DCC21, VRS21, and PRS1, and transmits an nth command signal to an nth set of controllers DCCn1, VRSn1, and PRS1. The first to nth command signals are transmitted from the digital signal processor DSP1 in the execution order of states S1 to Sn of the variable levels of the RF signal 130.

[0134] Upon receiving the first command signal, the duty cycle DCS1p is sent from the duty cycle controller DCC11 to the variable controller VRS11, which provides a variable level for the state S1 of the RF signal 130 for a time interval of the duty cycle DCS1p to the driver system DRVR1. For example, in response to receiving the first command signal, the variable controller VRS11 accesses the duty cycle DCS1p from the duty cycle controller DCC11. As another example, in response to receiving the first command signal, the duty cycle controller DCC11 sends the duty cycle DCS1p to the variable controller VRS11. Also, in response to receiving the first command signal, parameter levels for the states S1 to Sn of the RF signal 130 are sent from the parameter controller PRS1 to the driver system DRVR1.

[0135] Upon receiving the variable level for the state S1 of the RF signal 130 during the duty cycle DCS1p and the parameter levels for the states S1 to Sn of the RF signal 130, the driver of the driver system DRVR1 generates a drive signal for the state S1 for that period. The drive signal for the state S1 is based on the variable level for the state S1 of the RF signal 130 and the parameter levels for the states S1 to Sn of the RF signal 130. The drive signal for the state S1 can be amplified by an amplifier of the driver system DRVR1 to output an amplified signal for the state S1 of the RF signal 130 during the duty cycle DCS1p. The amplified signal for the state S1 for the period of the duty cycle DCS1p is transmitted from the amplifier of the driver system DRVR1 to the power supply PS1. Upon receiving the amplified signal for the state S1 for the period of the duty cycle DCS1p, the power supply PS1 generates a portion of the RF signal 130 for the state S1. The portion of the RF signal 130 for state S1 has parameter levels for state S1 during the duty cycle DCS1p, and has parameter levels for states S1 through Sn during the duty cycle DCS1p.

[0136] Furthermore, upon receiving the second command signal, the duty cycle DCS2p is sent from the duty cycle controller DCC21 to the variable controller VRS21 in the same manner as described above with reference to the controllers DCC11 and VRS11. Upon receiving the duty cycle DCS2p, the variable controller VRS21 provides the driver system DRVR1 with a variable level related to the state S2 for the time interval of the duty cycle DCS2p. Also, upon receiving the second command signal, the parameter controller PRS1 continues to provide the driver system DRVR1 with parameter levels related to the states S1-Sn of the RF signal 130.

[0137] Upon receiving the variable level for the state S2 of the RF signal 130 for the period defining the duty cycle DCS2p and the parameter levels for the states S1 to Sn of the RF signal 130, the driver of the driver system DRVR1 generates a drive signal for the state S2 for that period. The drive signal for the state S2 is based on the variable level for the state S2 of the RF signal 130 and the parameter levels for the states S1 to Sn of the RF signal 130. The drive signal for the state S2 can be amplified by an amplifier of the driver system DRVR1 to output an amplified signal for the state S2 for the period defining the duty cycle DCS2p. The amplified signal for the state S2 for the period defining the duty cycle DCS2p is transmitted from the amplifier of the driver system DRVR1 to the power supply PS1. Upon receiving the amplified signal for the state S2 for the period defining the duty cycle DCS2p, the power supply PS1 generates a portion of the RF signal 130 for the state S2. The portion of the RF signal 130 for state S2 has variable levels for state S2 for a period that defines a duty cycle DCS2p, and has parameter levels for states S1-Sn for that period.

[0138] Also, upon receiving the nth command signal, a duty cycle DCSnp is sent from the duty cycle controller DCCn1 to the variable controller VRSn1 in the same manner as described above with reference to the controllers DCC11 and VRS11. Upon receiving the duty cycle DCSnp, the variable controller VRSn1 provides the driver system DRVR1 with a variable level for the state Sn for the time interval of the duty cycle DCSnp. Also, upon receiving the nth command signal, the parameter controller PRS1 continues to provide the driver system DRVR1 with parameter levels for the states S1-Sn of the RF signal 130.

[0139] Upon receiving the variable level for state Sn for the period defining the duty cycle DCSnp and the parameter levels for states S1 to Sn, the driver of the driver system DRVR1 generates a drive signal for state Sn for the period of the duty cycle DCSnp. The drive signal for state Sn is based on the variable level for state Sn and the parameter levels for states S1 to Sn. The drive signal for state Sn can be amplified by an amplifier in the driver system DRVR1 to output an amplified signal for state Sn for the period defining the duty cycle DCSnp. The amplified signal for state Sn for the period defining the duty cycle DCSnp is transmitted from the amplifier in the driver system DRVR1 to the power supply PS1. Upon receiving the amplified signal for state Sn for the period defining the duty cycle DCSnp, the power supply PS1 generates a portion of the RF signal 130 for state Sn. The portion of the RF signal 130 for state Sn has variable levels for state Sn during the duty cycle DCSnp, and has parameter levels for states S1-Sn for the periods that define the duty cycle DCSnp.

[0140] The states S1 to Sn that define the variables of the RF signal 130 are repeated for each clock cycle of the clock signal. The clock signal is generated by a clock source, such as a clock oscillator or an oscillation circuit of the RF generator RFG1. The clock source is connected to the digital signal processor DSP1 and transmits the clock signal to the digital signal processor DSP1. When it is determined that the cycle 1 has ended and the cycle 2 has started, the digital signal processor DSP1 repeats transmitting the first to n-th command signals to the variable controllers VRS11 to VRSn1 and the parameter controller PRS1 in the above-mentioned order, thereby repeating the generation of the states S1 to Sn of the variable levels and parameter levels that define the RF signal 130 during the cycle 2.

[0141] In one embodiment, functions described herein as being performed by two or more of the controllers DCC11-DCCn1, VRS11-VRSn1, and PCS1 are instead performed by a single controller. For example, functions described herein as being performed by two or more of the controllers DCC11-DCCn1, VRS11-VRSn1, and PCS1 are instead performed by a processor within the single controller.

[0142] In one embodiment, functions described herein as being performed by two or more of the controllers DCC11-DCCn1, VRS11-VRSn1, and PCS1 are instead performed by any other number of controllers.

[0143] 7A is a diagram of one embodiment of a system 700 to illustrate the use of multiple RF generators RFG1, RFG2, etc., through RFGz to power the plasma chamber 104 and control of the duty cycles of the RF signal 130, RF signal 702, and RF signal 704 variables to achieve uniformity in the processing rate of the substrate S. FIG. 7B is one embodiment of a list 750 of duty cycles for multiple states associated with RF generators RFG1, RFG2, through RFGz. The list 750 is generated using the method described below with reference to FIG. 9 or the method described below with reference to FIG. 10. Note that z is an integer greater than 1. For example, z is 3 or 4 or 5.

[0144] Referring to FIG. 7A, the system 700 includes RF generators RFG1, RFG2, etc., up to RF generator RFGz. For example, RF generator RFG1 operates at a low frequency, RF generator RFG2 operates at a medium frequency, and RF generator RFGz operates at a high frequency. The medium frequency is intermediate between the low frequency and the high frequency. As an example, if the low frequency is 400 kHz and the high frequency is 60 MHz, the medium frequency is 13.56 MHz. As another example, if the low frequency is 2 MHz and the high frequency is 60 MHz, the medium frequency is 13.56 MHz or 27 MHz. The system 700 further includes an impedance matching circuit 705, a plasma chamber 104, and a host computer 106. The impedance matching circuit 705 includes inputs I1, I2, etc., up to an input Iz. The impedance matching circuit 704 includes an output OIMC.

[0145] The processor 114 is connected to an RF generator RFG2 via a transmission cable TC2, and so on, with the processor 114 being connected to an RF generator RFGz via a transmission cable TCz. The output O1 is connected to an input I1 via an RF cable RFC1. The output O2 is also connected to an input I2 via an RF cable RFC2, and the output Oz is connected to an input Iz via an RF cable RFCz. The output OIMC is connected to the lower electrode via an RF transmission line 122.

[0146] 7B, the processor 114 stores a list 750 of uniformity levels and duty cycles in the memory device 116. The uniformity levels in the list 750 include uniformity levels UNFM1 through UNFMp.

[0147] Each uniformity level stored in list 750 of memory device 116 corresponds to a plurality of duty cycles for a plurality of states that define a variable of a corresponding one of the first through pth RF signals generated by RF generator RFG1, a plurality of duty cycles for a plurality of states that define a variable of a corresponding one of the first through rth RF signals generated by RF generator RFG2, and a plurality of duty cycles for a plurality of states that define a variable of a corresponding one of the first through uth RF signals generated by RF generator RFGz, where r and u are positive integers. For example, there is a one-to-one mapping or relationship between uniformity level UNFM1 and the set of duty cycles that define a variable of the first RF signal generated by RF generator RFG1, the set of duty cycles that define a variable of the first RF signal generated by RF generator RFG2, and the set of duty cycles that define a variable of the first RF signal generated by RF generator RFGz. In this example, the one-to-one mapping is stored in row 1 of list 750. RF signal 702 is an example of the rth RF signal provided by RF generator RFG2, and RF signal 704 is an example of the uth RF signal provided by RF generator RFGz.

[0148] Continuing with the example, the set of duty cycles of variables defining the first RF signal generated by RF generator RFG2 includes a duty cycle DCS111 of a state S1 defining a variable of the first RF signal, a duty cycle DCS211 of a state S2 defining a variable of the first RF signal, and so on up to a duty cycle DCSq11 defining a state Sq of the variable of the first RF signal, where q is a positive integer. Illustratively, the integer q is equal to the integer n. In this illustration, the number of states of the variables defining the first RF signal generated by RF generator RFG2 is equal to the number of states of the variables defining the first RF signal generated by RF generator RFG1. As another illustration, the integer q is not equal to the integer n. In this illustration, the number of states defining the variables of the first RF signal generated by RF generator RFG2 is not equal to the number of states defining the variables of the first RF signal generated by RF generator RFG1.

[0149] Continuing with the example, the set of duty cycles defining the variable of the first RF signal generated by RF generator RFGz includes duty cycle DCS112 defining state S1 of the variable, duty cycle DCS212 defining state S2 of the variable, and so on up to duty cycle DCSt12 defining state St of the variable, where t is a positive integer. Illustratively, integer t is equal to at least one of integers n and q. In this illustration, the number of states defining the variable of the first RF signal generated by RF generator RFGz is equal to the number of states defining the variable of the first RF signal generated by RF generator RFG1, or to the number of states defining the variable of the first RF signal generated by RF generator RFG2, or to the number of states defining the variable of the first RF signal generated by RF generator RFG2 and the number of states of the variable of the first RF signal generated by RF generator RFGz. As another illustration, integer t is not equal to at least one of integers n and q. In this example, the number of states defining the variables of the first RF signal generated by RF generator RFGz is not equal to the number of states defining the variables of the first RF signal generated by RF generator RFG1, is not equal to the number of states defining the variables of the first RF signal generated by RF generator RFG2, or is not equal to the number of states defining the variables of the first RF signal generated by RF generator RFG1 and is not equal to the number of states defining the variables of the first RF signal generated by RF generator RFG2.

[0150] As another example, in a similar manner, there is a one-to-one mapping between the uniformity level UNFM2 and the set of duty cycles that define the variable of the second RF signal generated by RF generator RFG1, the set of duty cycles that define the variable of the second RF signal generated by RF generator RFG2, and the set of duty cycles that define the variable of the second RF signal generated by RF generator RFGz. The one-to-one mapping is stored in row 2 of list 750. The set of duty cycles that define the second RF signal generated by RF generator RFG2 includes a duty cycle DCS121 that defines a state S1 of the variable of the second RF signal, a duty cycle DCS221 that defines a state S2 of the variable of the second RF signal, and so on, up to a duty cycle DCSq21 that defines a state Sq of the variable of the second RF signal. The set of duty cycles defining the RF signal generated by RF generator RFGz includes a duty cycle DCS122 that defines a state S1 of the variable of the second RF signal, a duty cycle DCS222 that defines a state S2 of the variable of the second RF signal, and so on up to a duty cycle DCSt22 that defines a state St of the variable of the second RF signal.

[0151] As yet another example, there is a one-to-one relationship between the uniformity level UNFM3 and the set of duty cycles of variables defining the third RF signal generated by RF generator RFG1, the set of duty cycles of variables defining the third RF signal generated by RF generator RFG2, and the set of duty cycles of variables defining the third RF signal generated by RF generator RFGz. The one-to-one relationship is stored in row 3 of list 750. The set of duty cycles of the third RF signal generated by RF generator RFG2 includes a duty cycle DCS131 of state S1 that defines a variable of the third RF signal, a duty cycle DCS231 of state S2 that defines a variable of the third RF signal, and so on, up to a duty cycle DCSq31 of state Sq that defines a variable of the third RF signal. The set of duty cycles defining the third RF signal generated by RF generator RFGz includes a duty cycle DCS132 for a state S1 of a variable of the third RF signal, a duty cycle DCS232 for a state S2 of a variable of the third RF signal, and so on up to a duty cycle DCSt32 for a state St of a variable of the third RF signal.

[0152] As another example, there is a one-to-one relationship between the uniformity level UNFMp and the set of duty cycles of variables defining the pth RF signal generated by RF generator RFG1, the set of duty cycles of variables defining the rth RF signal generated by RF generator RFG2, and the set of duty cycles of variables defining the uth RF signal generated by RF generator RFGz. The one-to-one relationship is stored in row p of list 750. The set of duty cycles defining the rth RF signal generated by RF generator RFG2 includes a duty cycle DCS1r1 of state S1 that defines the variable of the rth RF signal, a duty cycle DCS2r1 of state S2 that defines the variable of the rth RF signal, and so on, up to a duty cycle DCSqr1 of state Sq that defines the variable of the rth RF signal. The set of duty cycles defining the uth RF signal generated by RF generator RFGz includes a duty cycle DCS1u2 for state S1 that defines a variable of the uth RF signal, a duty cycle DCS2u2 for state S2 that defines the variable of the uth RF signal, and so on, up to a duty cycle DCStu2 that defines a state St of the variable of the uth RF signal.

[0153] 7A, the processor 114 receives an instruction, such as a signal, from a user via an input device indicating a uniformity level UNFMa to be achieved in processing the substrate S. Upon receiving the instruction, the processor 114 determines whether the uniformity level UNMFa is within a predetermined range from one of the uniformity levels UNFM1 to UNFMp in the list 750 stored in the memory device 116, in the same manner as described above with reference to FIG. 1. Upon determining that the uniformity level UNMFa is within a predetermined range from one of the uniformity levels UNFM1 to UNFMp in the list 750 stored in the memory device 116, such as the uniformity level UNFMp, the processor 114 identifies a set of duty cycles from the list 750 in the memory device 116 that corresponds to one of the uniformity levels UNFM1 to UNFMp. For example, the processor 114 identifies duty cycles DCS1p-DCSnp, DCS1r1-DCSqr1, and DCS1u2-DCStu2 from the memory device 116 as corresponding to the uniformity level UNFMp. Illustratively, the processor 114 examines each row 1-p of the list 750 (FIG. 7B) to determine that the duty cycles DCS1p-DCSnp, DCS1r1-DCSqr1, and DCS1u2-DCStu2 have a one-to-one relationship or mapping with the uniformity level UNFMp.

[0154] As described above with reference to FIG. 1, upon identifying the duty cycles DCS1p-DCSn1 from the list 750, the processor 114 generates a recipe signal 128 including the duty cycles DCS1p-DCSn1 of the variables of the RF signal 130 and transmits the recipe signal 128 to the RF generator RFG1 via the transfer cable TC1. Also, as described above with reference to FIG. 1, the RF generator RFG1 stores corresponding variable levels for each of the states S1-Sn in one or more memory devices of the RF generator RFG1. Also, as described above with reference to FIG. 1, the RF generator RFG1 stores parameter levels for the states S1-Sn in one or more memory devices of the RF generator RFG1. The variable levels for the states S1-Sn and the parameter levels for the states S1-Sn are received by the RF generator RFG1 in the recipe signal 128 from the processor 114 via the transfer cable TC1.

[0155] Further, upon identifying duty cycles DCS1r1-DCSqr1 from list 750, processor 114 generates recipe signal 707 including the variable duty cycles DCS1r1-DCSqr1 of RF signal 702 and transmits recipe signal 707 to RF generator RFG2 via transfer cable TC2. Upon receiving duty cycles DCS1r1-DCSqr1, RF generator RFG2 stores the duty cycles DCS1r1-DCSqr1 in one or more memory devices within RF generator RFG2.

[0156] Additionally, RF generator RFG2 stores corresponding variable levels for each of states S1-Sq in one or more memory devices of RF generator RFG2. RF generator RFG2 also stores parameter levels, such as single parameter levels, for states S1-Sq. The variable levels for states S1-Sq and the parameter levels for states S1-Sq are received by RF generator RFG2 from processor 114 via transfer cable TC2. For example, the variable levels for states S1-Sq and the parameter levels for states S1-Sq are received by RF generator RFG2 in recipe signal 707 from processor 114 via transfer cable TC1. Processor 114 receives an indication of the variable levels for states S1-Sq from a user via an input device.

[0157] The processor 114 also generates a recipe signal 708 including the variable duty cycles DCS1u2-DCStu2 of the RF signal 704 and transmits the recipe signal 708 to the RF generator RFGz via the transfer cable TCz. Upon receiving the duty cycles DCS1u2-DCStu2, the RF generator RFGz stores the duty cycles DCS1u2-DCStu2 in one or more memory devices within the RF generator RFGz.

[0158] Additionally, the RF generator RFGz stores corresponding variable levels for each of the states S1-St in one or more memory devices of the RF generator RFGz. The RF generator RFGz also stores parameter levels, such as single parameter levels, for the states S1-St. The variable levels for the states S1-St and the parameter levels for the states S1-St are received by the RF generator RFGz from the processor 114 via the transfer cable TCz. For example, the variable levels for the states S1-St and the parameter levels for the states S1-St are received by the RF generator RFGz in a recipe signal 708 from the processor 114 via the transfer cable TCz. The processor 114 receives an indication of the variable levels for the states S1-St from a user via an input device.

[0159] Further, the processor 114 generates a trigger signal 131 and transmits the trigger signal 131 to the RF generator RFG1 via the transfer cable TC1, to the RF generator RFG2 via the transfer cable TC2, and to the RF generator RFGz via the transfer cable TCz. For example, the trigger signal 131 is transmitted after the transmission of the recipe signals 128, 707, and 708. Upon receiving the trigger signal 131, the RF generator RFG2 generates an RF signal 702 having variable levels for the states S1-Sq, parameter levels for the states S1-Sq, and duty cycles DCS1r1-DCSqr1 for the states S1-Sq. As an example, the parameter levels for the states S1-Sq are a single parameter level. The RF generator RFG2 provides an RF signal 702 at an output O2. The RF signal 702 is provided from the output O2 to an input I2 of the impedance matching circuit 706 via an RF cable RFC2.

[0160] Also, upon receiving the trigger signal 131, the RF generator RFGz generates an RF signal 704 having variable levels for states S1 to St, parameter levels for states S1 to St, and duty cycles DCS1u2 to DCStu2 for states S1 to St. As an example, the parameter levels for states S1 to St are a single parameter level. The RF generator RFGz provides an RF signal 704 at an output Oz. The RF signal 704 is provided from the output Oz to an input Iz of an impedance matching circuit 705 via an RF cable RFCz.

[0161] The RF signal 130 is routed through a first branch of the impedance matching circuit 705, the RF signal 702 is routed through a second branch of the impedance matching circuit 705, and the RF signal 704 is routed through a z-th branch of the impedance matching circuit 705. The first branch extends from an input I1 to an output OIMC, the second branch extends from an input I2 to an output OIMC, and the z-th branch extends from an input Iz to an output OIMC.

[0162] A branch circuit as used herein includes a network of circuit components. For example, a branch circuit includes one or more series circuits and one or more parallel circuits. The one or more series circuits are connected to one or more parallel circuits. Each series circuit includes a network of one or more capacitors, one or more inductors, one or more resistors, or a combination thereof. Similarly, each parallel circuit includes a network of one or more capacitors, one or more inductors, one or more resistors, or a combination thereof. Each parallel circuit is connected to ground potential at an end.

[0163] When RF signal 130 is routed through a first branch in impedance matching circuit 705, RF signal 702 is routed through a second branch in impedance matching circuit 705, and RF signal 704 is routed through a z-th branch in impedance matching circuit 705, the circuit components of impedance matching circuit 705 match the impedance of the load connected to the output OIMC with the impedance of the source connected to the inputs I1-Iz to modify the impedance of RF signals 130, 702, and 704. Examples of loads connected to the output OIMC of impedance matching circuit 705 include RF transmission line 122 and plasma chamber 104. Examples of sources connected to the inputs I1-Iz include RF cables RFC1-RFCz and RF generators RFG1-RFGz. The impedance of RF signals 130, 702, and 704 is modified to output modified RF signal 710 at the output OIMC.

[0164] The modified RF signal 710 is provided from the output OIMC via RF transmission line 122 to a lower electrode of the substrate support 108. Additionally, one or more process gases are provided into the gap 112 such that a plasma is struck or sustained within the gap 112 to process the substrate S.

[0165] In one embodiment, the impedance matching circuit 705 is connected to the upper electrode 110 instead of the substrate support 108 via the RF transmission line 122. In this embodiment, the substrate support 108 is connected to a reference potential.

[0166] FIG 8A is an illustration of an embodiment of graph 210 for illustrating plot 212. FIG 8B is an illustration of an embodiment of graph 800 for illustrating plot 802 for illustrating duty cycles DCS2r1, DCS3r1, and DCS1r1 that define a variable of RF signal 702 generated by RF generator RFG2 (FIG. 7A). Graph 800 includes a plot 802 illustrating a variable of RF signal 702 versus time t. The variable of RF signal 702 is plotted on the y-axis of graph 802, and time t is plotted on the x-axis of graph 802.

[0167] The x-axis of the graph 800 is divided into equal time intervals as illustrated in the graph 210 of FIG. 8A. The y-axis of the graph 800 is also divided into variable levels of the RF signal 702 (FIG. 7A) generated by the RF generator RFG2. For example, the y-axis of the graph 800 has a variable level 0, a variable level V1b, a variable level V2b, a variable level V3b, a variable level V4b, and a variable level V5b. Note that the first interval between the variable levels 0 and V1b is equal to the second interval between the variable levels V1b and V2b. The second interval is also equal to the third interval between the variable levels V2b and V3b. Similarly, the third interval is equal to the fourth interval between the variable levels V3b and V4b. The fourth interval is also equal to the fifth interval between the variable levels V4b and V5b.

[0168] Plot 802 transitions from variable level V2b to variable level V3b at time t0. Plot 802 has variable level V3b for the time period between time t0 and time t3. Plot 802 transitions from variable level V3b to variable level V5b at time t3. Plot 802 remains at variable level V5b for the time interval between time t3 and time t6 and transitions from variable level V5b to variable level V2b at time t6. Plot 212 has variable level V2b for the time interval between time t6 and time t8.

[0169] The variable level V3b of plot 802 defines the state S2 of the variable of RF signal 702. Similarly, the variable level V5b of plot 802 defines the state S3 of the variable of RF signal 702, and the variable level V2b of plot 802 defines the state S1 of the variable of RF signal 702.

[0170] The variable levels V5b-V2b of plot 802 are repeated during each cycle of the clock signal. For example, a first instance of the variable levels V5b-V2b of plot 802 occurs during cycle 1, and a second instance of the variable levels V5b-V2b of plot 802 occurs during cycle 2.

[0171] The time interval during which state S2 of the variable shown in plot 802 occurs is illustrated as duty cycle DCS2r1. Similarly, the time interval during which state S3 of the variable shown in plot 802 occurs is illustrated as duty cycle DCS3r1, and the time interval during which state S1 of the variable occurs is illustrated as duty cycle DCS1r1.

[0172] It should be noted that duty cycles such as duty cycles DCS311, DCS211, and DCS111 are adjusted to produce duty cycles DCS3r1, DCS2r1, and DCS1r1. For example, duty cycle DCS3r1 is smaller than duty cycle DCS311, and duty cycle DCS2r1 is larger than duty cycle DCS211. Also, duty cycle DCS1r1 is larger than duty cycle DCS111.

[0173] In one embodiment, the transitions of the variables illustrated in plot 802 of RF signal 702 occur within time intervals. For example, instead of transitioning from variable level V3b to variable level V4b at time t3, plot 802 transitions during a time interval from a first time to a second time. The first time is between time t2.5 and time t3, and the second time is between time t3 and time t3.5. In this example, the duty cycle of variable level V5b includes the time interval between occurrences of variable level V5b and the time interval between transitions from variable level V3b to variable level V5b. As another example, the duty cycle of variable level V3b includes the time interval between occurrences of variable level V3b and the time interval between transitions from variable level V3b to variable level V5b.

[0174] 8C is an illustration of one embodiment of a graph 804 to illustrate a plot 806 illustrating the variables duty cycles DCS2u2 and DCS1u2 of the RF signal 704 generated by RF generator RFGz (FIG. 7A). The graph 804 includes a plot 806 versus time t. The variables defining the RF signal 704 are plotted on the y-axis of the graph 804, and time t is plotted on the x-axis of the graph 804.

[0175] The x-axis of the graph 804 is divided into equal time intervals as illustrated in the graph 210 of FIG. 8A. The y-axis of the graph 804 is also divided into variable levels. For example, the y-axis of the graph 804 has variable level 0, variable level V1c, variable level V2c, variable level V3c, variable level V4c, and variable level V5c. Note that the first interval between variable levels 0 and V1c is equal to the second interval between variable levels V1c and V2c. The second interval is also equal to the third interval between variable levels V2c and V3c. Similarly, the third interval is equal to the fourth interval between variable levels V3c and V4c. The fourth interval is also equal to the fifth interval between variable levels V4c and V5c.

[0176] Plot 806 transitions from variable level V1c to variable level V5c at time t0. Plot 806 has variable level V5c for the time period between time t0 and time t4.5. Plot 806 transitions from variable level V5c to variable level V1c at time t4.5. Plot 806 remains at variable level V1c for the time interval between time t4.5 and time t8, and transitions from variable level V1c to variable level V5c at time t8.

[0177] The variable level V5c of plot 806 defines the state S2 of the variable of RF signal 704 (FIG. 7A). Similarly, the variable level V1c of plot 806 defines the state S1 of the variable of RF signal 704.

[0178] The variable levels V5c and V1c of plot 806 are repeated during cycles of the clock signal. For example, a first instance of the variable levels V5c and V1c of plot 806 occurs during cycle 1, and a second instance of the variable levels V5c and V1c of plot 806 occurs during cycle 2.

[0179] The time interval during which state S2 of the variable of plot 806 occurs is illustrated as duty cycle DCS2u2. Similarly, the time interval during which state S1 of the variable of plot 806 occurs is illustrated as duty cycle DCS1u2.

[0180] It should be noted that duty cycles such as duty cycles DCS212 and DCS112 are adjusted to produce duty cycles DCS2u2 and DCS1u2, e.g., duty cycle DCS2u2 is less than duty cycle DCS212 and duty cycle DCS1u2 is greater than duty cycle DCS112.

[0181] In one embodiment, the transitions of the variables illustrated in plot 806 occur within time intervals. For example, instead of transitioning from variable level V5c to variable level V1c at time t4.5, plot 806 transitions during a time interval from a first time to a second time. The first time is between time t4 and time t4.5, and the second time is between time t4.5 and time t5. In this example, the duty cycle of variable level V1c includes the time interval between occurrences of variable level V1c and the time interval between transitions from variable level V5c to variable level V1c. As another example, the duty cycle of variable level V5c includes the time interval between occurrences of variable level V5c and the time interval between transitions from variable level V5c to variable level V1c.

[0182] 9 is a diagram of an embodiment of a system 900 for illustrating the generation of the list of uniformity levels and duty cycles 750. The system 900 includes the host computer 106, RF generators RFG1-RFGz, an impedance matching circuit 705, and a plasma chamber 503.

[0183] The substrate 526 is placed in the plasma chamber 503. The processor 114 then controls the RF generator RFG1 to generate a pth RF signal, such as RF signal 130, as described with reference to FIG. 7A, controls the RF generator RFG2 to generate an rth RF signal, such as RF signal 702, as described with reference to FIG. 7A, and controls the RF generator RFGz to generate a uth RF signal, such as RF signal 704, as described with reference to FIG. 7A. The pth RF signal having duty cycles DCS1p-DCSnp for the states S1-Sn of the variables of the pth RF signal, the rth RF signal having duty cycles DCS1r1-DCSqr1 for the states S1-Sq of the variables of the rth RF signal, and the uth RF signal having duty cycles DCS1u2-DCStu2 for the states S1-St of the variables of the uth RF signal are provided to an impedance matching circuit 705, which outputs a modified RF signal 710 to the plasma chamber 503. When the modified RF signal 710 is transmitted to the plasma chamber 503 and one or more process gases are supplied to the gap 112 within the plasma chamber 503 , a plasma is generated within the gap 112 of the plasma chamber 503 .

[0184] After the plasma is generated in gap 112, during time period TP1, intensity signals 534, 536, and 538 are generated and transmitted from ERMDs 514, 516, and 518 to processor 114 in the same manner as described above with reference to Figure 5A. Additionally, during time period TP2, intensity signals 540, 542, and 544 are generated and transmitted from ERMDs 514, 516, and 518 to processor 114 in the same manner as described above with reference to Figure 5A.

[0185] 5A , the processor 114 determines a processing rate, such as a processing rate PRpa for processing the left edge region 528 of the substrate 526, based on the intensity signals 534 and 540 received from the ERMD 514. The processor 114 stores the processing rate PRpa in a list 750 in the memory device 116.

[0186] 5A , the processor 114 determines a processing rate, such as a processing rate PRpb for processing the central region 532 of the substrate 526, based on the intensity signals 536 and 542 received from the ERMD 516. The processor 114 stores the processing rate PRpb in a list 750 in the memory device 116.

[0187] 5A , the processor 114 determines a processing rate, such as a processing rate PRpc for processing the right edge region 530 of the substrate 526, based on the intensity signals 538 and 544 received from the ERMD 518. The processor 114 stores the processing rate PRpc in a list 750 in the memory device 116.

[0188] The processor 114 defines the processing rates PRpa-PRpc as the uniformity level UNFMp and stores the uniformity level UNFMp in a list 750 of the memory device 114. For example, the processor 114 determines that the processing rates PRpa-PRpc form the uniformity level UNFMp and stores the uniformity level UNFMp in the list 750. As another example, the processor 114 applies interpolation as described above with reference to FIG. 5A to determine the uniformity level UNFMp from the processing rates PRpa-PRpc.

[0189] To determine the processing rates PRpa-PRpc, in a manner similar to that described above with reference to FIG. 5A, when a first RF signal is provided by RF generator RFG1, a first RF signal is provided by RF generator RFG2, and a first RF signal is provided by RF signal RFGz, the processor 114 determines the processing rates PR1a, PR1b, and PR1c and stores the processing rates PR1a-PR1c in a list 750 in the memory device 116. The first RF signal generated by RF generator RFG1 has duty cycles DCS11, DCS21, etc., up to duty cycle DCSn1. And the first RF signal generated by RF generator RFG2 has duty cycles DCS111, DCS211, etc., up to duty cycle DCSq11. The first RF signal generated by RF generator RFGz has duty cycles DCS112, DCS212, etc., up to duty cycle DCSt12. When the first RF signal generated by the RF generator RFG1, the first RF signal generated by the RF generator RFG2, and the first RF signal generated by the RF generator RFGz are provided to the impedance matching circuit 705, a first modified RF signal is output from the output OIMC and transmitted to the lower electrode via the RF transmission line 122. Also, when the first modified RF signal is provided to the substrate support 108, one or more process gases are provided to the gap 112. The processor 114 associates the process rates PR1a-PR1c with the uniformity level UNFM1 and stores the uniformity level UNFM1 in the list 750. For example, the processor 114 determines the uniformity level UNFM1 based on the process rates PR1a-PR1c. To illustrate, the processor 114 determines that the process rates PR1a-PR1c form the uniformity level UNFM1. As another example, the processor 114 applies the above-mentioned interpolation method to determine the uniformity level UNFM1 from the processing speeds PR1a to PR1c.

[0190] Also, in a manner similar to that described above for determining the processing rates PRpa-PRpc, when the second RF signal is provided by RF generator RFG1, the second RF signal is provided by RF generator RFG2, and the second RF signal is provided by RF signal RFGz, the processor 114 determines processing rates PR2a, PR2b, and PR2c and stores the processing rates PR2a-PR2c in a list 750 in the memory device 116. The second RF signal generated by RF generator RFG1 has duty cycles DCS12, DCS22, etc., up to duty cycle DCSn2. And the second RF signal generated by RF generator RFG2 has duty cycles DCS121, DCS221, etc., up to duty cycle DCSq21. The second RF signal generated by RF generator RFGz has duty cycles DCS122, DCS222, etc., up to duty cycle DCSt22. When the second RF signal generated by the RF generator RFG1, the second RF signal generated by the RF generator RFG2, and the second RF signal generated by the RF generator RFGz are provided to the impedance matching circuit 705, a second modified RF signal is output from the output OIMC and transmitted to the lower electrode via the RF transmission line 122. Also, when the second modified RF signal is provided to the substrate support 108 of the plasma chamber 503, one or more process gases are provided to the gap 112 of the plasma chamber 503. The processor 114 associates the process rates PR2a-PR2c with the uniformity level UNFM2 and stores the uniformity level UNFM2 in the list 750 of the memory device 116.

[0191] 10 is a diagram of one embodiment of a system 1000 to illustrate the use of a thickness measurement device 552 to measure intensity values ​​of light emitted from a plasma reflected from a left edge region 528, a center region 532, and a right edge region 530. The system 100 includes RF generators RFG1-RFGz, an impedance matching circuit 705, a plasma chamber 554, a thickness measurement device 552, and a host computer 106.

[0192] The substrate 526 is placed in the plasma chamber 554. The processor 114 then controls the RF generator RFG1 as described with reference to Figure 7A to generate the pth RF signal, such as RF signal 130. The processor 114 also controls the RF generator RFG2 as described with reference to Figure 7A to generate the rth RF signal, such as RF signal 702, and controls the RF generator RFGz as described with reference to Figure 7A to generate the uth RF signal, such as RF signal 704. The pth RF signal having duty cycles DCS1p-DCSnp for states S1-Sn defining the pth RF signal variable, the rth RF signal having duty cycles DCS1r1-DCSqr1 for states S1-Sq defining the rth RF signal variable, and the uth RF signal having duty cycles DCS1u2-DCStu2 for states S1-St defining the uth RF signal variable are provided to an impedance matching circuit 705, which outputs a modified RF signal 710 to the plasma chamber 554. When the modified RF signal 710 is transmitted to the plasma chamber 554 and one or more process gases are provided to the gap 112 in the plasma chamber 102, a plasma is generated in the gap 112 of the plasma chamber 554.

[0193] After the substrate 526 is processed using the plasma generated in the plasma chamber 554, during a period TP1, the substrate 526 is removed from the plasma chamber 554 through the opening 560 and placed under the thickness measuring device 552. During the period TP1, the thickness measuring device 552 generates intensity signals 534, 536, and 538 and transmits the intensity signals 534, 536, and 538 to the processor 114 through the transfer cable 556. After the intensity signals 534, 536, and 538 are generated and transmitted to the processor 114, the substrate 526 is returned to the plasma chamber 554 for further processing. After a preset period has elapsed from the period TP1, the substrate 526 is removed from the plasma chamber 554 through the opening 560. During a period TP2, the substrate 526 is removed from the plasma chamber 554 and placed under the thickness measuring device 552. During time period TP2, thickness measurement device 552 generates intensity signals 540, 542, and 544 and transmits intensity signals 540, 542, and 544 to processor 114 via transmission cable 556. Processor 114 determines processing rates PRpa, PRpb, and PRpc from intensity signals 534, 536, 538, 540, 542, and 544, determines a uniformity level UNFMp from the processing rates PRpa, PRpb, and PRpc, in the same manner as described above with reference to FIG. 5B, and stores the processing rates PRpa, PRpb, and PRpc and the uniformity level UNFMp in list 750 in memory device 116.

[0194] In a manner similar to that described above for determining the processing rates PRpa-PRpc with reference to FIG. 5B, when a first RF signal is provided by RF generator RFG1, a first RF signal is provided by RF generator RFG2, and a first RF signal is provided by RF generator RFGz, processor 114 determines processing rates PR1a, PR1b, and PR1c and stores processing rates PR1a-PR1c in list 175 in memory device 116. The first RF signal generated and provided by RF generator RFG1 has duty cycles DCS11, DCS21, etc., up to duty cycle DCSn1. And the first RF signal generated and provided by RF generator RFG2 has duty cycles DCS111, DCS211, etc., up to duty cycle DCq11. The first RF signal generated and provided by RF generator RFGz has duty cycles DCS112, DCS212, etc., up to duty cycle DCSt12.

[0195] When RF generator RFG1 supplies a first RF signal to impedance matching circuit 705, RF generator RFG2 supplies a first RF signal to impedance matching circuit 705, and RF generator RFGz supplies a first RF signal to impedance matching circuit 705, impedance matching circuit 705 outputs a first modified RF signal to a lower electrode of substrate support 108 of plasma chamber 554. When the first modified RF signal is supplied to the lower electrode of substrate support 108 and one or more process gases are supplied to plasma chamber 554, substrate 526 is processed. After being processed, substrate 526 is removed from plasma chamber 554 through opening 560 and placed under thickness measuring device 552, which generates a first set of intensity signals. The processor 114 determines processing rates PR1a, PR1b, and PR1c based on the first set of intensity signals in the same manner as described above with reference to FIG. 7B, determines a uniformity level UNFM1 based on the processing rates PR1a, PR1b, and PR1c in the manner described above, and stores the processing rates PR1a, PR1b, and PR1c and the uniformity level UNFM1 in a list 750 stored in the memory device 116.

[0196] Further, in a manner similar to that described above for determining processing rates PRpa-PRpc with reference to FIG. 5B, when a second RF signal is provided by RF generator RFG1, a second RF signal is provided by RF generator RFG2, and a second RF signal is provided by RF generator RFGz, processor 114 determines processing rates PR2a, PR2b, and PR2c and stores processing rates PR2a-PR2c in list 175 in memory device 116. The second RF signal generated and provided by RF generator RFG1 has duty cycles DCS12, DCS22, etc., up to duty cycle DCSn2. And, the second RF signal generated and provided by RF generator RFG2 has duty cycles DCS121, DCS221, etc., up to duty cycle DCSq21. The second RF signal generated and provided by RF generator RFGz has a duty cycle DCS122, DCS222, etc., up to a duty cycle DCSt22. When RF generator RFG1 provides the second RF signal, RF generator RFG2 provides the second RF signal, and RF generator RFGz provides the second RF signal to the impedance matching circuit 705, the impedance matching circuit 705 outputs the second modified RF signal to the lower electrode of the substrate support 108 of the plasma chamber 554. When the second modified RF signal is provided to the lower electrode of the substrate support 108 and one or more process gases are provided to the plasma chamber 554, the substrate 526 is processed. After being processed, the substrate 526 is removed from the plasma chamber 554 through the opening 560 and placed under the thickness measuring device 552, which generates a second set of intensity signals. The processor 114 determines processing rates PR2a, PR2b, and PR2c based on the second set of intensity signals, in the same manner as described above with reference to FIG. 5B, associates the processing rates PR2a, PR2b, and PR2c with the uniformity level UNFM2, and stores the processing rates PR2a, PR2b, and PR2c and the uniformity level UNFM2 in a list 750 in the memory device 116.

[0197] 11 is a diagram of one embodiment of a system 1100 illustrating internal components within RF generators RFG1-RFGz for controlling the duty cycle between states S1-Sn of each of the first through p-th RF signals generated by RF generator RFG1, controlling the duty cycle between states S1-Sq of each of the first through r-th RF signals generated by RF generator RFG2, and controlling the duty cycle between states S1-St of each of the first through u-th RF signals generated by RF generator RFGz. System 1100 includes RF generators RFG1-RFGz.

[0198] The internal components of the RF generator RFG1 are illustrated above with reference to FIG. 6. The RF generator RFG2 includes a digital signal processor DSP2 and a plurality of controllers. The controller of the RF generator RFG2 includes a duty cycle controller DCC12 for the state S1 of the variable of the RF signal 702, a duty cycle controller DCC22 for the state S2 of the variable, and so on up to a duty cycle controller DCCq2 for the state Sq of the variable. Furthermore, the controller of the RF generator RFG2 includes a parameter controller VRS12 for the state S1 of the variable of the RF signal 702, a parameter controller VRS22 for the state S2 of the variable, and so on up to a parameter controller VRSq2 for the state Sq of the variable. Also, the controller of the RF generator RFG2 includes a parameter controller PRS2 for the states S1-Sq of the variable of the RF signal 702.

[0199] The RF generator RFG2 further includes a driver system DRVR2 and a power supply PS2. The processor 114 is connected to the DSP2 via a transfer cable TC2. The digital signal processor DSP2 is connected to the duty cycle controllers DCC12-DCCq2, the variable controllers VRS12-VRSq2, and the parameter controller PRS2. The duty cycle controller DCC12 is connected to the variable controller VRS12. The duty cycle controller DCC22 is also connected to the variable controller VRS22, and so on, with the duty cycle controller DCCq2 being connected to the variable controller VRSq2. The variable controllers VRS12-VRSq2 and the parameter controller PRS2 are connected to the driver system DRVR2, which is connected to the power supply PS2. The power supply PS2 is connected to the RF cable RFC2.

[0200] The processor 114 accesses the duty cycles DCS1r1-DCSqr1 from the list 750 stored in the memory device 116, generates a recipe signal 707 having the duty cycles DCS1r1-DCSqr1, and transmits the recipe signal 707 to the digital signal processor DSP2 via the transfer cable TC2. For example, the processor 114 identifies the duty cycles DCS1r1-DCSqr1 as corresponding to the uniformity level UNFMp to be achieved, and generates the recipe signal 707 having the duty cycles DCS1r1-DCSqr1.

[0201] The processor 114 also includes duty cycle identifiers in the recipe signal 707 to indicate that the duty cycles DCS1r1 through DCSqr1 are duty cycles for a state of the variable of the RF signal 702. For example, the processor 114 includes a first duty cycle identifier in the recipe signal 707 to indicate that the duty cycle DCS1r1 is for a state S1 of the variable of the RF signal 702, includes a second duty cycle identifier in the recipe signal 707 to indicate that the duty cycle DCS2r1 is for a state S2 of the variable, and so on, including a qth duty cycle identifier in the recipe signal 707 to indicate that the duty cycle DCSqr1 is for a state Sq of the variable.

[0202] Upon receiving the duty cycles DCS1r1-DCSqr1 embedded within the recipe signal 707, the digital signal processor DSP2 determines from the duty cycle identifier that the recipe signal 707 includes the duty cycles DCS1r1-DCSqr1, extracts the duty cycles from the recipe signal 707, and transmits the duty cycles DCS1r1-DCSqr1 to the duty cycle controllers DCC12-DCCq2. For example, the digital signal processor DSP2 identifies from the first duty cycle identifier that the recipe signal 707 includes the duty cycle DCS1r1 and determines that the duty cycle DCS1r1 is to be transmitted to the duty cycle controller DCC12. The digital signal processor DSP2 identifies from the second duty cycle identifier that the recipe signal 707 includes the duty cycle DCS2r1 and determines that the duty cycle DCS2r1 is to be transmitted to the duty cycle controller DCC22. Digital signal processor DSP2 identifies from the qth duty cycle identifier that recipe signal 707 includes duty cycle DCSqr1, and determines that duty cycle DCSqr1 is to be sent to duty cycle controller DCCq2. Digital signal processor DSP2 sends duty cycle DCS1r1 to duty cycle controller DCC12, sends duty cycle DCS2r1 to duty cycle controller DCC22, and so on until duty cycle DCSqr1 is sent to duty cycle controller DCCq2.

[0203] The duty cycle controllers DCC12-DCCq2 store the duty cycles DCS1r1-DCSqr1. For example, the duty cycle controller DCC12 stores the duty cycle DCS1r1 in a memory device of the duty cycle controller DCC12. Similarly, the duty cycle controller DCC22 stores the duty cycle DCS2r1 in a memory device of the duty cycle controller DCC22, and the duty cycle controller DCCq2 stores the duty cycle DCSqr1 in a memory device of the duty cycle controller DCCq2.

[0204] In a similar manner as described above with respect to sending duty cycles DCS1r1-DCSqr1 to digital signal processor DSP2 in recipe signal 707, processor 114 sends variable levels for states S1-Sq of the RF signal 702 variables and parameter levels, such as single parameter levels, for states S1-Sq to digital signal processor DSP2 in recipe signal 707. Upon receiving the variable levels for states S1-Sq, digital signal processor DSP2 sends the variable level for state S1 to variable controller VRS12, the variable level for state S2 to variable controller VRS22, and so on until the variable level for state Sq has been sent to variable controller VRSq2. Additionally, upon receiving the parameter levels for all states S1-Sq, digital signal processor DSP2 sends the parameter levels for states S1-S1 to parameter controller PRS2.

[0205] Additionally, processor 114 transmits in recipe signal 707 an order of generation of the variable levels of RF signal 702. For example, as illustrated in graph 800 (FIG. 8B), during each clock cycle, a portion of RF signal 702 having a power level for state S2 is generated first, a portion of RF signal 702 having a power level for state S3 is generated second, and a portion of RF signal 702 having a power level for state S2 is generated third.

[0206] After the duty cycles DCS1r1-DCSqr1 are stored in the duty cycle controllers DCC12-DCCq2, the variable levels for states S1-Sq are stored in the variable controllers VRS12-VRSq2, and the parameter levels for states S1-Sq are stored in the parameter controller PRS2, the processor 114 sends a trigger signal 131 to the digital signal processor DSP2. Upon receiving the trigger signal 131, the digital signal processor DSP2 sends a first command signal to a first set of controllers DCC12, VRS12, and PRS2, sends a second command signal to a second set of controllers DCC22, VRS22, and PRS2, and sends a qth command signal to a qth set of controllers DCCq2, VRSq2, and PRS2. The first to qth command signals are sent from the digital signal processor DSP2 in an execution order of states S1-Sq that define the variable levels of the RF signal 702. Upon receiving the first command signal, the variable controller VRS12 accesses the duty cycle DCS1r1 from the duty cycle controller DCC12 and provides the driver system DRVR2 with variable levels for the state S1 for a time interval of the duty cycle DCS1r1. Similarly, upon receiving the first command signal, the parameter controller PRS2 provides the driver system DRVR2 with parameter levels for the states S1-Sq.

[0207] Upon receiving the variable level for state S1 during the duty cycle DCS1r1 and the parameter levels for states S1-Sq, the driver of the driver system DRVR2 generates a drive signal for state S1 during the duty cycle DCS1r1. The drive signal for state S1 is based on the variable level for state S1 that defines the variable of the RF signal 702 and the parameter levels for states S1-Sq that define the variable of the RF signal 702. The drive signal for state S1 can be amplified by an amplifier of the driver system DRVR2 to output an amplified signal for state S1 during the period that defines the duty cycle DCS1r1. The amplified signal for state S1 during the period that defines the duty cycle DCS1r1 is transmitted from the amplifier of the driver system DRVR2 to the power supply PS2. Upon receiving the amplified signal for state S1 during the period that defines the duty cycle DCS1r1, the power supply PS2 generates a portion of the RF signal 702 for state S1. The portion of the RF signal 702 for state S1 has variable levels for state S1 for a period that defines a duty cycle DCS1r1, and has parameter levels for states S1 through Sq for a period that defines the duty cycle DCS1r1.

[0208] Furthermore, upon receiving the second command signal, the variable controller VRS22 accesses the duty cycle DCS2r1 from the duty cycle controller DCC22 and provides the driver system DRVR2 with variable levels for the state S2 for the time interval defining the duty cycle DCS2r1. Similarly, upon receiving the second command signal, the parameter controller PRS2 continues to provide the driver system DRVR2 with parameter levels for the states S1-Sq.

[0209] Upon receiving the variable level for state S2 for the period defining the duty cycle DCS2r1 and the parameter levels for states S1 to Sq, the driver of the driver system DRVR2 generates a drive signal for state S2 for the period defining the duty cycle DCS2p. The drive signal for state S2 defining the variable of the RF signal 702 is based on the variable level for state S2 and the parameter levels for states S1 to Sq. The drive signal for state S2 defining the variable of the RF signal 702 can be amplified by an amplifier of the driver system DRVR2 to output an amplified signal for state S2 for the period defining the duty cycle DCS2r1. The amplified signal for state S2 for the period defining the duty cycle DCS2r1 is transmitted from the amplifier of the driver system DRVR2 to the power supply PS2. Upon receiving the amplified signal for state S2 for the period defining the duty cycle DCS2r1, the power supply PS2 generates a portion of the RF signal 702 for state S2. The portion of the RF signal 702 for state S2 has parameter levels for state S2 for a period that defines a duty cycle DCS2r1, and has parameter levels for states S1 through Sq for a period that defines the duty cycle DCS2r1.

[0210] Furthermore, upon receiving the qth command signal, the variable controller VRSq2 accesses the duty cycle DCSqr1 from the duty cycle controller DCCq2 and provides the driver system DRVR2 with the variable levels for the state Sq for the time interval of the duty cycle DCSqr1. Also, upon receiving the qth command signal, the parameter controller PRS2 continues to provide the driver system DRVR2 with the parameter levels for the states S1-Sq.

[0211] Upon receiving the variable level for the state Sq for the period of the duty cycle DCSqr1 and the parameter level for the state Sq for the period defining the duty cycle DCSqr1, the driver of the driver system DRVR2 generates a drive signal for the state Sq for the period defining the duty cycle DCSqr1. The drive signal for the state Sq is based on the variable level for the state Sq and the parameter levels for the states S1 to Sq. The drive signal for the state Sq can be amplified by an amplifier of the driver system DRVR2 to output an amplified signal for the state Sq for the period defining the duty cycle DCSqr1. The amplified signal for the state Sq for the period defining the duty cycle DCSqr1 is transmitted from the amplifier of the driver system DRVR2 to the power supply PS2. Upon receiving the amplified signal for the state Sq for the period defining the duty cycle DCSqr1, the power supply PS2 generates a portion of the RF signal 702 for the state Sq. The portion of the RF signal 702 for state Sq has variable levels for state Sq for a period that defines a duty cycle DCSqr1, and has parameter levels for states S1 through Sq for a period that defines the duty cycle DCSqr1.

[0212] The states S1 to Sq that define the variables of the RF signal 702 are repeated for each clock cycle of the clock signal. The clock signal is generated by a clock source such as a clock oscillator or an oscillation circuit of the RF generator RFG2. The clock signal generated by the RF generator RFG2 is the same as the clock signal generated by the RF generator RFG1. The clock source of the RF generator RFG2 is connected to the digital signal processor DSP2 and transmits a clock signal to the digital signal processor DSP2. When it is determined that cycle 1 of the clock signal generated by the clock source of the RF generator RFG2 has ended and cycle 2 of the clock signal has begun, the digital signal processor DSP2 repeats transmitting the first to qth command signals to the variable controllers VRS12 to VRSq2 and the parameter controller PRS2 in the above-mentioned order, thereby repeating the generation of the states S1 to Sq that define the variable levels and parameter levels of the RF signal 702 during cycle 2 of the clock signal generated by the RF generator RFG2.

[0213] The RF generator RFGz includes a digital signal processor DSPz and a plurality of controllers. The controller of the RF generator RFGz includes a duty cycle controller DCC1z for state S1, a duty cycle controller DCC2z for state S2, and so on, up to a duty cycle controller DCCtz for state St. Furthermore, the controller of the RF generator RFGz includes a variable controller VRS1z for state S1, a variable controller VRS2z for state S2, and so on, up to a variable controller VRStz for state St. Moreover, the controller of the RF generator RFGz includes a parameter controller PRSz for states S1 to St.

[0214] The RF generator RFGz further includes a driver system DRVRz and a power supply PSz. The processor 114 is connected to the DSPz via a transfer cable TCz. The DSPz is connected to the duty cycle controllers DCC1z-DCCtz, the variable controllers VRS1z-VRStz, and the parameter controller PRSz. The duty cycle controller DCC1z is connected to the variable controller VRS1z. The duty cycle controller DCC2z is also connected to the variable controller VRS2z, and so on, and the duty cycle controller DCCtz is connected to the variable controller VRStz. The variable controllers VRS1z-VRStz and the parameter controller PRSz are connected to the driver system DRVRz, which is connected to the power supply PSz. The power supply PSz is connected to the RF cable RFCz.

[0215] The processor 114 accesses the duty cycles DCS1u2-DCStu2 from the list 750 stored in the memory device 116, generates a recipe signal 708 having the duty cycles DCS1u2-DCStu2, and transmits the recipe signal 708 to the digital signal processor DSPz via the transfer cable TCz. For example, the processor 114 identifies the duty cycles DCS1u2-DCStu2 as corresponding to the uniformity level UNFMp to be achieved, and generates the recipe signal 708 having the duty cycles DCS1u2-DCStu2.

[0216] The processor 114 also includes duty cycle identifiers in the recipe signal 708 to indicate that the duty cycles DCS1u2-DCStu2 are duty cycles for the states of the variables of the RF signal 704. For example, the processor 114 includes a first duty cycle identifier in the recipe signal 708 to indicate that the duty cycle DCS1u2 is for state S1, a second duty cycle identifier in the recipe signal 707 to indicate that the duty cycle DCS2u2 is for state S2, and so on, including the tth duty cycle identifier in the recipe signal 708 to indicate that the duty cycle DCStu2 is for state St.

[0217] Upon receiving the duty cycles DCS1u2-DCStu2 embedded in the recipe signal 708, the digital signal processor DSPz determines from the duty cycle identifier that the recipe signal 708 includes the duty cycles DCS1u2-DCStu2, extracts the duty cycles from the recipe signal 708, and transmits the duty cycles DCS1u2-DCStu2 to the duty cycle controllers DCC1z-DCCtz. For example, the digital signal processor DSPz identifies from the first duty cycle identifier that the recipe signal 708 includes the duty cycle DCS1u2 and determines that the duty cycle DCS1u2 is to be transmitted to the duty cycle controller DCC1z. The digital signal processor DSPz identifies from the second duty cycle identifier that the recipe signal 708 includes the duty cycle DCS2u2 and determines that the duty cycle DCS2u2 is to be transmitted to the duty cycle controller DCC2z. The digital signal processor DSPz identifies from the tth duty cycle identifier that the recipe signal 708 includes a duty cycle DCStu2, and determines that the duty cycle DCStu2 is to be sent to the duty cycle controller DCCtz. The digital signal processor DSPz sends the duty cycle DCS1u2 to the duty cycle controller DCC1z, sends the duty cycle DCS2u2 to the duty cycle controller DCC2z, and so on until the duty cycle DCStu2 is sent to the duty cycle controller DCCtz.

[0218] The duty cycle controllers DCC1z-DCCtz store the duty cycles DCS1u2-DCStu2. For example, the duty cycle controller DCC1z stores the duty cycle DCS1u2 in a memory device of the duty cycle controller DCC1z. Similarly, the duty cycle controller DCC2z stores the duty cycle DCS2u2 in a memory device of the duty cycle controller DCC2z, and the duty cycle controller DCCtz stores the duty cycle DCStu2 in a memory device of the duty cycle controller DCCtz.

[0219] In a similar manner as described above with respect to sending the duty cycles DCS1u2-DCStu2 to the digital signal processor DSPz in the recipe signal 708, the processor 114 sends variable levels for states S1-St of the RF signal 704 variable and parameter levels, such as single parameter levels, for states S1-St to the digital signal processor DSPz in the recipe signal 708. Upon receiving the variable levels for states S1-St of the RF signal 704 variable, the digital signal processor DSPz sends the variable level for state S1 to the variable controller VRS1z, the variable level for state S2 to the variable controller VRS2z, and so on until the variable level for state St is sent to the variable controller VRStz. Additionally, upon receiving the parameter levels for states S1-St, the digital signal processor DSPz sends the parameter levels to the parameter controller PRSz.

[0220] Additionally, the processor 114 transmits in the recipe signal 708 an order of generation of the variable and parameter levels of the RF signal 704. For example, as illustrated in graph 804 (FIG. 8C), during each clock cycle of the clock signal, a portion of the RF signal 704 having a power level associated with state S2 is generated first, and a portion of the RF signal 704 having a power level associated with state S1 is generated second.

[0221] After the duty cycles DCS1u2-DCStu2 are stored in the duty cycle controllers DCC1z-DCCtz, the variable levels for states S1-St are stored in the variable controllers VRS1z-VRStz, and the parameter levels for states S1-St are stored in the parameter controller PRSz, the processor 114 sends a trigger signal 131 to the digital signal processor DSPz. Upon receiving the trigger signal 131, the digital signal processor DSPz sends a first command signal to the first set of controllers DCC1z, VRS1z, and PRSz, a second command signal to the second set of controllers DCC2z, VRS2z, and PRSz, and a t-th command signal to the t-th set of controllers DCCtz, VRStz, and PRSz. The first through t-th command signals are sent from the digital signal processor DSPz in an execution order of the states S1-St that defines the variable and parameter levels of the RF signal 704. Upon receiving the first command signal, the variable controller VRS1z accesses the duty cycle DCS1u2 from the duty cycle controller DCC1z and provides the driver system DRVRz with variable levels for the state S1 for a time interval of the duty cycle DCS1u2. Also, upon receiving the first command signal, the parameter controller PRSz provides the driver system DRVRz with parameter levels for the states S1-St that define the variables of the RF signal 704.

[0222] Upon receiving the variable level for state S1 for the period of duty cycle DCS1u2 and the parameter levels for states S1-St, the driver of the driver system DRVRz generates a drive signal for state S1 for the period defining duty cycle DCS1u2. The drive signal for state S1 is based on the variable level for state S1 of the variable of the RF signal 704 and the parameter levels for states S1-St. The drive signal for state S1 can be amplified by an amplifier of the driver system DRVRz to output an amplified signal for state S1 for the period defining duty cycle DCS1u2. The amplified signal for state S1 for the period defining duty cycle DCS1u2 is transmitted from the amplifier of the driver system DRVRz to the power supply PSz. Upon receiving the amplified signal for state S1 for the period defining duty cycle DCS1u2, the power supply PSz generates a portion of the RF signal 704 for state S1. The portion of the RF signal 704 for state S1 has variable levels for state S1 during a period that defines a duty cycle DCS1u2, and has parameter levels for states S1 through St during a period that defines a duty cycle DCS1u2.

[0223] Furthermore, upon receiving the second command signal, the variable controller VRS2z accesses the duty cycle DCS2u2 from the duty cycle controller DCC2z and supplies the variable levels for the state S2 to the driver system DRVR2 for the time interval of the duty cycle DCS2z. Also, upon receiving the second command signal, the parameter controller PRSz continues to supply the parameter levels for the states S1 to St to the driver system DRVRz.

[0224] Upon receiving the variable level for state S2 for the period defining the duty cycle DCS2u2 and the parameter levels for states S1-St, the driver of the driver system DRVRz generates a drive signal for state S2 for the period defining the duty cycle DCS2u2. The drive signal for state S2 defining the variable of the RF signal 704 is based on the variable level for state S2 and the parameter levels for states S1-St. The drive signal for state S2 defining the variable of the RF signal 704 can be amplified by an amplifier of the driver system DRVRz to output an amplified signal for state S2 for the period defining the duty cycle DCS2u2. The amplified signal for state S2 for the period defining the duty cycle DCS2u2 is transmitted from the amplifier of the driver system DRVRz to the power supply PSz. Upon receiving the amplified signal for state S2 for the period defining the duty cycle DCS2u2, the power supply PSz generates a portion of the RF signal 704 for state S2. The portion of the RF signal 704 for state S2 has parameter levels for state S2 during the duty cycle DCS2u2, and has parameter levels for states S1 through St during the duty cycle DCS2u2.

[0225] Furthermore, upon receiving the tth command signal, the variable controller VRStz accesses the duty cycle DCStu2 from the duty cycle controller DCCtz and provides the driver system DRVRz with variable levels related to the state St for the time interval of the duty cycle DCStu2. Also, upon receiving the tth command signal, the parameter controller PRSz continues to provide the driver system DRVRz with parameter levels related to the states S1-St.

[0226] Upon receiving the variable level for state St for the period of duty cycle DCStu2 and the parameter levels for states S1 to St, the driver of the driver system DRVRz generates a drive signal for state St for the period of duty cycle DCStu2. The drive signal for state St is based on the variable level for state St and the parameter levels for states S1 to St. The drive signal for state St can be amplified by an amplifier of the driver system DRVRz to output an amplified signal for state St for the period of duty cycle DCStu2. The amplified signal for state St for the period of duty cycle DCStu2 is transmitted from the amplifier of the driver system DRVRz to the power supply PSz. Upon receiving the amplified signal for state St for the period defining duty cycle DCStu2, the power supply PSz generates a portion of an RF signal 704 for state St. The portion of the RF signal 704 for state St has a variable level for state St for the period defining duty cycle DCStu2 and has a parameter level for states S1 to St for the period defining duty cycle DCStu2.

[0227] The states S1 to St that define the variables of the RF signal 704 are repeated for each clock cycle of the clock signal. The clock signal is generated by a clock source such as a clock oscillator or an oscillation circuit of the RF generator RFGz. The clock signal generated by the RF generator RFGz is the same as the clock signal generated by the RF generator RFG1. The clock source in the RF generator RFGz is connected to the digital signal processor DSPz and transmits a clock signal to the digital signal processor DSPz. When it is determined that cycle 1 of the clock signal generated by the clock source in the RF generator RFGz has ended and cycle 2 of the clock signal has begun, the digital signal processor DSPz repeats transmitting the first to t-th command signals to the variable controllers VRS1z to VRStz and the parameter controller PRSz in the above-mentioned order, and repeats the generation of the states S1 to St that define the variable levels and parameter levels of the RF signal 704 during cycle 2 of the clock signal generated by the RF generator RFGz.

[0228] In one embodiment, functions described herein as being performed by two or more of controllers DCC12-DCCq2, VRS12-VRSq2, and PRS2 are instead performed by a single controller. For example, functions described herein as being performed by two or more of controllers DCC12-DCCq2, VRS12-VRSq2, and PRS2 are instead performed by a processor within a single controller.

[0229] In one embodiment, functions described herein as being performed by two or more of controllers DCC12-DCCq2, VRS12-VRSq2, and PRS2 are instead performed by any other number of controllers.

[0230] In one embodiment, functions described herein as being performed by two or more of the controllers DCC1z-DCCtz, VRS1z-VRStz, and PRSz are instead performed by a single controller. For example, functions described herein as being performed by two or more of the controllers DCC1z-DCCtz, VRS1z-VRStz, and PRSz are instead performed by a processor within a single controller.

[0231] In one embodiment, functions described herein as being performed by two or more of the controllers DCC1z-DCCtz, VRS1z-VRStz, and PRSz are instead performed by any other number of controllers.

[0232] 12A is one embodiment of a graph 200. Plot 202 has a frequency, such as a pulse repetition rate, of states S1-S4 that defines a variable of a first RF signal generated by RF generator RFG1 (FIG. 1). For example, the repetition rate of plot 202 is 1 / t8. States S1-S4 are repeated at a frequency of 1 / t8. For example, a first instance of each of states S1-S4 occurs during cycle 1 generated by RF generator RFG1, and a second instance of each of states S1-S4 occurs during cycle 2.

[0233] It should be noted that each of the duty cycles DC11-DC41 is 25%. For example, the duration of an occurrence that defines a state S4 of a variable of the first RF signal generated by the RF generator RFG1 is 25% of the total period of cycle 1 of the clock signal generated by the RF generator RFG1. Also, the duration of an occurrence that defines a state S3 of a variable of the first RF signal generated by the RF generator RFG1 is 25% of the total period of cycle 1 of the clock signal generated by the RF generator RFG1. The duration of an occurrence that defines a state S2 of a variable is 25% of the total period of cycle 1 of the clock signal generated by the RF generator RFG1, and the duration of an occurrence that defines a state S1 of a variable is 25% of the total period.

[0234] It should further be noted that the pulse width defining the state S4 of the variable of the first RF signal generated by RF generator RFG1 extends from time t0 to time t2. Similarly, the pulse width defining the state S3 of the variable of the first RF signal generated by RF generator RFG1 extends from time t2 to time t4. Also, the pulse width defining the state S2 of the variable extends from time t4 to time t6, and the pulse width defining the state S1 of the variable extends from time t6 to time t8.

[0235] 12B is an embodiment of a graph 1210 to illustrate that as the pulse repetition rate decreases, the duty cycle of each pulse of the first RF signal generated by RF generator RFG1 increases to achieve the same pulse width. Graph 1210 includes a plot 1212 of a variable of the two-state RF signal generated by RF generator RFG1 versus time t. The variable of the two-state RF signal is plotted on the y-axis of graph 1210 and time t is plotted on the x-axis of graph 1210.

[0236] The x-axis of graph 1210 is divided into equal time intervals in the same manner that the x-axis of graph 200 (FIG. 12A) is divided. The y-axis of graph 1210 is divided into variable levels of the two-state RF signal variable in the same manner that the y-axis of graph 200 is divided.

[0237] Plot 1212 transitions from variable level V2a to variable level V4a at time t0. Plot 1212 has variable level V4a for the time period between time t0 and time t2. Plot 1212 transitions from variable level V4a to variable level V2a at time t2. Plot 1212 remains at variable level V2a for the time interval between time t2 and time t4, and transitions from variable level V2a to variable level V4a at time t4.

[0238] Variable level V4a of plot 1212 defines state S2 representing a variable of the two-state RF signal. Similarly, variable level V2a of plot 202 defines state S1 of the variable of the two-state RF signal. Variable levels V4a-V2a of plot 1212 are repeated during each clock cycle generated by RF generator RFG1. For example, a first instance of variable levels V4a and V2a of plot 1212 occurs during cycle 1 generated by RF generator RFG1, and a second instance of variable levels V4a and V2a occurs during cycle 2.

[0239] The time interval during which state S2 of the variable of plot 1212 occurs is illustrated as duty cycle DCS21. Similarly, the time interval during which state S1 of the variable of plot 1212 occurs is illustrated as duty cycle DCS11.

[0240] The pulse repetition rate, such as the frequency, of occurrence of states S2 and S1 illustrated in plot 1212 is less than the pulse repetition rate of occurrence of states S1-S4 shown in graph 200. For example, the pulse repetition rate of occurrence of states S2 and S1 in plot 1212 is 1 / t4, which is half the pulse repetition rate of plot 202, 1 / t8.

[0241] It should be further noted that the pulse width of the state S2 of the variable of the two-state RF signal generated by RF generator RFG1 extends from time t0 to time t2. Similarly, the pulse width of the pulse of the state S1 of the variable of the two-state RF signal generated by RF generator RFG1 extends from time t2 to time t4.

[0242] Note that each of the duty cycles DC21-DC11 is 50%. For example, the duration of occurrence of state S2 defining a variable of the two-state RF signal generated by RF generator RFG1 is 50% of the total period defining cycle 1 generated by RF generator RFG1. Also, the duration of occurrence of state S1 defining a variable of the two-state RF signal generated by RF generator RFG1 is 50% of the total period defining cycle 1 generated by RF generator RFG1.

[0243] 12A, when the pulse repetition rate is decreased, the duty cycle of the variable generation of the RF signal generated by RF generator RFG1 is increased to achieve the same pulse width. For example, when the pulse repetition rate is decreased from 1 / t8 to 1 / t4, the duty cycle of the first RF signal is increased from 25% to 50% to achieve the pulse width of state S4 of the first RF signal generated by RF generator RFG1 (FIG. 1). When the duty cycle is increased, a two-state RF signal is generated by RF generator RFG1.

[0244] In one embodiment, the transitions of the variables illustrated in plot 1212 of the two-state RF signal occur within time intervals. For example, instead of transitioning from variable level V4a to variable level V2a at time t2, plot 1212 transitions during a time interval from a first time to a second time. The first time is between time t1.5 and time t2, and the second time is between time t2 and time t2.5. In this example, the duty cycle of variable level V2a includes the time interval of occurrence of variable level V2a and the time interval defining the transition from variable level V4a to variable level V2a. As another example, the duty cycle of variable level V4a includes the time interval of occurrence of variable level V4a and the time interval defining the transition from variable level V4a to variable level V2a.

[0245] FIG. 13 is a diagram of one embodiment of a graph 200 to illustrate a first RF signal, such as RF signal 1302, generated by RF generator RFG1 (FIG. 1). Each variable level V1a-V4a is an envelope of RF signal 1302. For example, variable level V4a is a peak-to-peak amplitude of RF signal 1302, and variable level V3a is another peak-to-peak amplitude of RF signal 1302. Note that the frequency of RF signal 1302 is greater than the frequency of repetition of states S1-S4. The frequency of operation of RF generator RFG1 defines the frequency of RF signal 1302. For example, the frequency of operation of RF generator RFG1 is the same as the frequency of RF signal 1302.

[0246] An example of an RF signal used herein is a sinusoidal signal having a sine wave shape. The RF signal oscillates between a positive variable level and a negative variable level. Illustratively, the RF signal 1302 oscillates between a variable level V4a and a negative variable level -V4a during state S4. The RF signal 1302 further oscillates between a variable level V3a and a negative variable level -V3a during state S3, between a variable level V2a and a negative variable level -V2a during state S2, and between a variable level V1a and a negative variable level -V1a during state S1. The negative variable level -V3a is greater than the variable level -V4a. The negative variable level -V2a is greater than the negative variable level -V3a, and the negative variable level -V1a is greater than the negative variable level -V2a. The variable level 0 is greater than the negative variable level -V1a.

[0247] FIG. 14A is a diagram of an embodiment of a desktop computer 1400, which is an example of the host computer 106 (FIG. 1). The desktop computer 1400 illustrates a selection of one of the uniformity levels UNFM1-UNFMp. The desktop computer 1400 includes a monitor 1402, a keyboard 1404, and a mouse 1406. Each of the keyboard 1404 and the mouse 1406 is an example of an input device. The keyboard 1404 and the mouse 1406 are wirelessly connected to the monitor 1402. For example, the keyboard 1404 is connected to the CPU of the monitor 1402 via a wireless connection. Examples of wireless connections include a Bluetooth™ connection and a Wi-Fi™ connection. Similarly, the mouse 1406 is connected to the CPU of the monitor 1402 via a wireless connection.

[0248] Disposed within the housing of monitor 1402 are a CPU, such as processor 114 (FIG. 1), a graphical processing unit (GPU), and a memory device, such as memory device 116 (FIG. 1). Monitor 114 includes a display screen, such as a liquid crystal display (LCD) display screen, a plasma display screen, and a light emitting diode (LED) display screen.

[0249] The GPU displays a list 1408 of uniformity levels UNFM1-UNFMp. Alongside each uniformity level UNFM1-UNFMp, the GPU displays a selection button. For example, along with uniformity level UNFM1, a selection button 1410 is displayed, along with uniformity level UNFM2, a selection button 1412 is displayed, and along with uniformity level UNFMp, a selection button 1414 is displayed.

[0250] A user uses keyboard 1404 or mouse 1406, or a combination thereof, to select one of selection buttons, such as selection buttons 1410-1414, to select one of the uniformity levels UNFM1-UNFMp to be achieved after processing of a substrate S (FIG. 1). Upon receiving a signal indicating a selection of one of the uniformity levels UNFM1-UNFMp via one or more of the wireless connections, a processor of monitor 1402 controls one or more of RF generators RFG1-RFGz. One or more of RF generators RFG1-RFGz are controlled to achieve one of the uniformity levels UNFM1-UNFMp.

[0251] 14B is an illustration of one embodiment of a desktop computer 1400 for illustrating in a graphical format a selection of one of the uniformity levels UNFM1-UNFMp. The GPU displays uniformity level 1420, uniformity level 1422, and uniformity level 1424. Uniformity level 1420 is an example of uniformity level UNFM1, uniformity level 1422 is an example of uniformity level UNFM2, and uniformity level 1424 is an example of uniformity level UNFMp.

[0252] Alongside each uniformity level 1420, 1422, and 1424, the GPU displays a selection button. For example, along with uniformity level 1420, a selection button 1426 is displayed, along with uniformity level 1422, a selection button 1428 is displayed, and along with uniformity level 1424, a selection button 1430 is displayed.

[0253] A user uses keyboard 1404 or mouse 1406, or a combination thereof, to select one of selection buttons, such as selection buttons 1426-1430, to select one of uniformity levels 1420, 1422, and 1424 to be achieved after processing of substrate S (FIG. 1). Upon receiving a signal indicating a selection of one of uniformity levels 1420, 1422, and 1424 via one or more of the wireless connections, a processor of monitor 1402 controls one or more of RF generators RFG1-RFGz. One or more of RF generators RFG1-RFGz are controlled to achieve one of uniformity levels 1420, 1422, and 1424.

[0254] The embodiments described herein may be practiced with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0255] In some embodiments, the controller is part of a system, which may be part of the examples described above. Such systems include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems are integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics may be referred to as a "controller" and may control various components or subparts of one or more systems. The controller is programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow settings, liquid delivery settings, position and motion settings, wafer loading and unloading to and from the tool, and wafer loading and unloading to and from other transport tools and / or load locks connected or interlocked to the system, depending on the processing requirements and / or type of system.

[0256] Broadly speaking, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define parameters, factors, variables, etc. for performing a particular process on, for, or on a semiconductor wafer or system. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0257] The controller, in some embodiments, is part of or connected to a computer that is integrated into the system, connected to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a "cloud" or fab host computer system that allows remote access of wafer processing. The computer allows remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance criteria from multiple manufacturing operations, change parameters of a current process, set processing steps to track a current process, or initiate a new process.

[0258] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system over a network, the network including a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters, factors, and / or variables of each of the processing steps to be performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller is distributed, such as by including one or more individual controllers that are networked together and operate toward a common purpose, such as the processes and controls described herein. One example of a distributed controller for such purposes includes one or more integrated circuits on the chamber that are remotely located (e.g., at the platform level or as part of the remote computer) and communicate with one or more integrated circuits that cooperatively control the processes at the chamber.

[0259] In various embodiments, examples of systems to which the method may be applied include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0260] It is further noted that in some embodiments, the above operations apply to various types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, transformer coupled plasma chambers, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, etc. For example, one or more RF generators are connected to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome coil, a flat coil, etc.

[0261] As described above, depending on the process step or steps being performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used to transport materials to and from containers of wafers to and from tool locations and / or load ports within the semiconductor manufacturing factory.

[0262] With the above embodiments in mind, it should be understood that some of the present embodiments employ various computer-implemented operations involving data stored in computer systems. These operations physically manipulate physical quantities. Any of the operations described herein that form part of the present embodiments are useful machine operations.

[0263] Also, some of the embodiments relate to hardware units or apparatus for performing these operations, which are specially made for special purpose computers. When defined as a special purpose computer, the computer is operable for a special purpose, but also performs other processes, programs, or routines that are not associated with the special purpose.

[0264] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory or cache, or obtained over a computer network. If the data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., in a cloud of computing resources.

[0265] One or more embodiments may also be fabricated as computer readable code on a non-transitory computer readable medium. The non-transitory computer readable medium is any data storage hardware unit, such as a memory device, that stores data, which is subsequently read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disk ROM (CD-ROMs), CD recordables (CD-Rs), CD rewriteables (CD-RWs), magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer readable medium includes computer readable tangible media distributed over network-coupled computer systems such that the computer readable code is stored and executed in a distributed manner.

[0266] Although the method operations described above have been described in a particular order, it should be understood that in various embodiments, other housekeeping operations may be performed between operations, the method operations may be coordinated to occur at slightly different times, may be distributed in a system that allows the method operations to occur at various intervals, or may be performed in an order different from that described above.

[0267] It is further noted that in one embodiment, one or more features from any embodiment described above may be combined with one or more features of any other embodiment described above without departing from the scope described in the various embodiments described in this disclosure.

[0268] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. The present embodiments are therefore to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. 1. A method for achieving a first level of uniformity in a processing rate across a surface of a substrate, comprising: receiving the first uniformity level to be achieved across the surface of the substrate; identifying a first plurality of duty cycles associated with a first plurality of states based on the first uniformity level, the first plurality of states being of a variable of a first radio frequency (RF) signal; controlling an RF generator to generate the first RF signal having the first plurality of duty cycles; A method comprising:

2. 2. The method of claim 1 , accessing from a memory device a list having a one-to-one correspondence between the first uniformity levels and the first plurality of duty cycles; identifying the first plurality of duty cycles includes determining that the first plurality of duty cycles corresponds to the first uniformity level in the list; and controlling the RF generator includes transmitting a recipe signal having the first plurality of duty cycles to the RF generator. method.

3. 3. The method of claim 2, controlling the RF generator includes transmitting a trigger signal to the RF generator after transmitting the recipe signal. method.

4. 2. The method of claim 1 , receiving a second uniformity level to be achieved across the surface of the substrate; identifying a second plurality of duty cycles associated with a second plurality of states based on the second uniformity level, the second plurality of states being of a variable of a second RF signal; controlling the RF generator to generate the second RF signal having the second plurality of duty cycles; The method further comprising:

5. 5. The method of claim 4, wherein the number of the second plurality of states is not equal to the number of the first plurality of states.

6. 5. The method of claim 4, wherein the first plurality of duty cycles and the second plurality of duty cycles are repeated with each clock cycle.

7. The method of claim 1 , wherein the variable is power or frequency.

8. 2. The method of claim 1, wherein each of the first plurality of duty cycles is a period occurring during a clock cycle and each of the first plurality of states represents a peak-to-peak amplitude of the first RF signal.

9. 2. The method of claim 1, wherein the first plurality of states comprises a plurality of variable levels of the variable of the first RF signal, each of the plurality of variable levels being a peak-to-peak envelope of the variable of the first RF signal.

10. 1. A method for achieving a first level of uniformity in a processing rate across a surface of a substrate, comprising: receiving the first uniformity level to be achieved across the surface of the substrate; identifying a plurality of duty cycles associated with a plurality of states of a variable based on the first uniformity level, the plurality of states being of a plurality of radio frequency (RF) signals; controlling a plurality of RF generators to generate the plurality of RF signals; A method comprising:

11. 11. The method of claim 10, wherein the plurality of duty cycles includes a first plurality of duty cycles, a second plurality of duty cycles, and a third plurality of duty cycles, the plurality of states includes a first plurality of states, a second plurality of states, and a third plurality of states, the plurality of RF signals includes a first RF signal, a second RF signal, and a third RF signal, and identifying the plurality of duty cycles includes: identifying the first plurality of duty cycles associated with the first plurality of states based on the first uniformity level, the first plurality of states being of the variable of the first RF signal; identifying the second plurality of duty cycles associated with the second plurality of states based on the first uniformity level, the second plurality of states being of the variable of the second RF signal; identifying the third plurality of duty cycles associated with the third plurality of states based on the first uniformity level, the third plurality of states being of the variable of the third RF signal; A method comprising:

12. 12. The method of claim 11, wherein the plurality of RF generators includes a first RF generator, a second RF generator, and a third RF generator, and controlling the plurality of RF generators comprises: controlling the first RF generator to generate the first RF signal; controlling the second RF generator to generate the second RF signal; controlling the third RF generator to generate the third RF signal; A method comprising:

13. 11. The method of claim 10, wherein the plurality of duty cycles comprises a first plurality of duty cycles, a second plurality of duty cycles, and a third plurality of duty cycles, and the plurality of RF generators comprises a first RF generator, a second RF generator, and a third RF generator, the method comprising: accessing from a memory device a list having a one-to-one correspondence between the first uniformity level and the plurality of duty cycles; identifying the plurality of duty cycles includes determining that the plurality of duty cycles corresponds to the first uniformity level in the list; and controlling the plurality of RF generators transmitting a first recipe signal having the first plurality of duty cycles to the first RF generator; transmitting a second recipe signal having the second plurality of duty cycles to the second RF generator; transmitting a third recipe signal having the third plurality of duty cycles to the third RF generator; A method comprising:

14. 14. The method of claim 13, wherein controlling the plurality of RF generators includes transmitting a trigger signal to the plurality of RF generators after transmitting the first, second, and third recipe signals.

15. 11. The method of claim 10, wherein the plurality of RF signals comprises a first RF signal, a second RF signal, and a third RF signal, the plurality of RF generators comprises a first RF generator, a second RF generator, and a third RF generator, the plurality of states comprises a first plurality of states of the variable of the first RF signal, a second plurality of states of the variable of the second RF signal, and a third plurality of states of the variable of the third RF signal, and controlling the plurality of RF generators comprises controlling the first RF generator to generate the first RF signal having the first plurality of states, the method further comprising: receiving a second uniformity level to be achieved across the surface of the substrate; identifying a fourth plurality of duty cycles associated with a fourth plurality of states based on the second uniformity level, the fourth plurality of states being of the variable of a fourth RF signal; controlling the first RF generator to generate the fourth RF signal having the fourth plurality of duty cycles of the fourth plurality of states of the variable of the fourth RF signal; The method further comprising:

16. a controller for achieving a first level of uniformity in a processing rate across a surface of a substrate, the controller comprising: receiving the first uniformity level to be achieved across the surface of the substrate; Identifying a first plurality of duty cycles associated with a first plurality of states of a variable of a first radio frequency (RF) signal based on the first uniformity level; and Controlling an RF generator to generate the first RF signal having the first plurality of duty cycles. a processor configured to a memory device coupled to the processor and configured to store the first uniformity level; Including, the controller.

17. 17. The controller of claim 16, wherein the processor: configured to access from the memory device a list having a one-to-one correspondence between the first uniformity levels and the first plurality of duty cycles; To identify the first plurality of duty cycles, the processor is configured to determine that the first plurality of duty cycles correspond to the first uniformity level in the list; and the processor is configured to send a recipe signal having the first plurality of duty cycles to the RF generator to control the RF generator; controller.

18. 20. The controller of claim 17, wherein the processor is configured to send a trigger signal to the RF generator after sending the recipe signal to control the RF generator.

19. 17. The controller of claim 16, wherein the processor: receiving a second uniformity level to be achieved across the surface of the substrate; Identifying a second plurality of duty cycles associated with a second plurality of states of a variable of a second RF signal based on the second uniformity level; and Controlling the RF generator to generate the second RF signal having the second plurality of duty cycles. The controller is configured as follows:

20. 20. The controller of claim 19, wherein a number of the second plurality of states is not equal to a number of the first plurality of states.

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