Increasing the randomized entropy of address space layout through page remapping and rotation

Abstract

Various embodiments include methods and devices for generating a memory map configured to map virtual addresses of pages to physical addresses, where pages of the same size are grouped into regions. Embodiments may include adding a first entry for a first additional page to a first region of the memory map, shifting the virtual address of the first region by a sub-page granularity shift amount to correspond to a shift of the virtual address of the first region allocated to code, mapping the shifted virtual address of the first entry for the first additional page to a physical address mapped to a first lowest shifted virtual address page of the first region, and shifting the virtual address of the first region allocated to code by a sub-page granularity shift amount, where the virtual address of the first region allocated to code is partially shifted into the first entry for the first additional page.

Description

[Technical field]

[0001] Related Applications This application claims the benefit of priority to U.S. Non-provisional Application No. 17 / 201,247, filed March 15, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] Code reuse attacks are increasingly becoming a more common attack vector on systems with baseline countermeasures implemented, such as W^X. A code reuse attack reuses existing code in a binary for the attacker's purposes. One form of code reuse is when the attacker is able to call a function of their choice. For example, an attacker may use an overwrite vulnerability to change a pointer in a function pointer table or jump table to a different function that is in the binary but not originally in the table. One common characteristic of all code reuse attacks is that the attacker must know the address of a binary's code or function in advance in order to be able to reuse the code or function.

[0003] One way to defend against such attacks is through Address Space Layout Randomization (ASLR) of binary code segments. In this scheme, the loader loads binary code segments at a random offset in the process's virtual address space on every load. As a result, the code of interest to the attacker is now at a random address on each load. A measure of the effectiveness of ASLR is sometimes called the entropy of the ASLR. Various system factors can limit the entropy of ASLR. Summary of the Invention [Means for solving the problem]

[0004] Various disclosed aspects may include apparatus and methods for generating a memory map configured to map virtual addresses of pages to physical addresses, where pages of the same size are grouped into regions. Various aspects may include adding a first entry for a first additional page to a first region of the memory map, shifting the virtual address of the first region by a sub-page granularity shift amount to accommodate a shift in the virtual address of the first region allocated to code, mapping the shifted virtual address of the first entry for the first additional page to a physical address mapped to a first lowest shifted virtually addressed page of the first region, and shifting the virtual address of the first region allocated to code by a sub-page granularity shift amount, where the virtual address of the first region allocated to code is partially shifted into the first entry for the first additional page.

[0005] Some aspects may include adding a second entry for a second additional page to a second region of the memory map, the second region being virtually addressed higher than the first region; shifting a virtual address of the second region by a sub-page granularity shift amount to correspond to a shift in the virtual address of the second region allocated to the code; mapping the shifted virtual address of the second entry for the second additional page to a physical address mapped to a second lowest shifted virtual address page of the second region; and shifting the virtual address of the second region allocated to the code by a sub-page granularity shift amount, where the virtual address of the second region allocated to the code is partially shifted into the second entry for the second additional page.

[0006] Some aspects may include shifting a virtual address of the second region to accommodate the first entry added to the first region of the memory map, and shifting the virtual address of the second region to align the pages of the second region, including the second added page, with page boundaries of a size page of the pages of the second region.

[0007] Some aspects may include rotating the code due to a shifted virtual address of a first region allocated to the code in physical memory.

[0008] In some aspects, rotating the code for the shifted virtual address of the first region allocated to the code in the physical memory may include loading the code into a mapped physical address from a first lowest virtual address page for the shifted virtual address of the first region allocated to the code; and loading the code into a mapped physical address from a first additional page for the shifted virtual address of the first region allocated to the code, where the mapped physical address for the shifted virtual address of the first region allocated to the code from the first additional page is a lower physical address than the mapped physical address for the shifted virtual address of the first region allocated to the code from the first lowest virtual address page.

[0009] Some embodiments may include adjusting a pointer for the binary code including the code by the amount of the shift in the virtual address of the second region to correspond to a shift in the virtual address of the second region allocated to the code by the shift amount of sub-page granularity.

[0010] Some aspects may include generating program counter relative code and generating binary code from the program counter relative code.

[0011] Further aspects include a computing device having a processor configured to perform the operations of any of the methods summarized above. Further aspects include a computing device having means for performing the functions of any of the methods summarized above. Further aspects include a non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause the processor and other components of the computing device to perform the operations of any of the methods summarized above.

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the various embodiments and, together with the general description above and the detailed description below, serve to explain the features of the claims. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a component block diagram illustrating an example computing device suitable for implementing various embodiments. [Diagram 2] FIG. 1 is a component block diagram illustrating an example memory system suitable for implementing various embodiments. [Figure 3A] FIG. 2 is a block diagram illustrating an example of memory mapping and rotation for sub-page granularity shifting suitable for implementing various embodiments. [Figure 3B] FIG. 2 is a block diagram illustrating an example of memory mapping and rotation for sub-page granularity shifting suitable for implementing various embodiments. [Figure 3C] FIG. 2 is a block diagram illustrating an example of memory mapping and rotation for sub-page granularity shifting suitable for implementing various embodiments. [Figure 3D] FIG. 2 is a block diagram illustrating an example of memory mapping and rotation for sub-page granularity shifting suitable for implementing various embodiments. [Figure 4A]FIG. 13 is a table diagram illustrating an example of memory mapping and rotation for sub-page granularity shifting suitable for implementing various embodiments. [Figure 4B] FIG. 13 is a table diagram illustrating an example of memory mapping and rotation for sub-page granularity shifting suitable for implementing various embodiments. [Diagram 5] 1 is a component block and flow diagram illustrating an example of memory mapping and rotation of sub-page granularity shifts suitable for implementing various embodiments. [Figure 6] FIG. 1 is a process flow diagram illustrating a method for sub-page granularity shifting memory mapping according to one embodiment. [Figure 7] FIG. 1 is a process flow diagram illustrating a method for sub-page granularity shifting memory mapping according to one embodiment. [Figure 8] FIG. 1 is a process flow diagram illustrating a method for memory rotation according to one embodiment. [Figure 9] FIG. 1 is a process flow diagram illustrating a method for memory rotation according to one embodiment. [Figure 10] FIG. 1 is a component block diagram illustrating an exemplary mobile computing device suitable for implementing various embodiments. [Figure 11] FIG. 1 is a component block diagram illustrating an exemplary mobile computing device suitable for implementing various embodiments. [Figure 12] FIG. 1 is a component block diagram illustrating an example server suitable for implementing various embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Various embodiments will now be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to specific examples and implementations are for illustrative purposes only and do not limit the scope of the claims.

[0015] Various embodiments include methods of increasing address space layout randomization (ASLR) entropy through page remapping and rotation, and computing devices implementing such methods. Various embodiments may include generating a subpage granularity shift page map from a page map using the subpage granularity shift amount. In some embodiments, a page virtual address range may be shifted to correspond to the subpage granularity shift amount and mapped to physical addresses in the page map. In some embodiments, a page virtual address range of a region of pages may be shifted to align to a page boundary of the page size of the region. In some embodiments, an additional page map entry may be added for each region of pages of the same size. Some embodiments may include rotating code, data, and / or information stored in physical memory based on the mapping of virtual addresses to physical addresses in the subpage granularity page map. In some embodiments, the virtual address ranges for a first page entry and an additional page entry of a region may be mapped to the same range of physical addresses.

[0016] The terms "computing device" and "mobile computing device" are used interchangeably herein to refer to any one or all of cellular telephones, smartphones, personal or mobile multimedia players, personal digital assistants (PDAs), laptop computers, tablet computers, convertible laptops / tablets (2-in-1 computers), smartbooks, ultrabooks, netblocks, palmtop computers, wireless email receivers, multimedia Internet-enabled cellular telephones, mobile game consoles, wireless game controllers, and similar personal electronic devices that include memory and programmable processors. The term "computing device" may also refer to stationary computing devices including personal computers, desktop computers, all-in-one computers, workstations, supercomputers, mainframe computers, embedded computers (such as in vehicles and other larger systems), servers, multimedia computers, and game consoles.

[0017] For ease and clarity of description, various embodiments are described with respect to code, e.g., processor-executable instructions, but may be equally applicable to any data, e.g., code, program data, or other information stored in memory. The terms "code," "data," and "information" are used interchangeably herein and are not intended to limit the scope of the claims and descriptions to the types of code, data, and information used as examples in describing various embodiments.

[0018] ASLR is a technique used to defend against malicious attacks such as code reuse attacks. A measure of the effectiveness of ASLR is sometimes called the entropy of the ASLR. One way to interpret this measure is the success rate of attackers if they make multiple code reuse attack attempts assuming a particular address. This can be multiple attempts on a particular device of interest, or a broad attack on an entire population of devices. The higher the entropy of the ASLR, the greater the number of attempts required for an attack to succeed, or the lower the success rate of the attack.

[0019] The greater the number of locations where the loader can legally place the start of code, the more difficult it is for an attacker to exploit. The entropy that can be achieved in ASLR is usually heavily limited by the amount of VA (Virtual Address) space available to the loader. The available entropy also has a close relationship to how virtual memory is managed via the Memory Management Unit (MMU) and the Operating System (OS), such as by using a translation lookaside buffer (TLB) or page tables of limited size, which can result in significant constraints. There are systems that support multiple page sizes and where the memory map between virtual and physical addresses is statically determined. This results in alignment constraints that can further lower the available entropy.

[0020] Various embodiments provide an ASLR scheme that may increase entropy by overcoming the limitations on entropy imposed by the above memory mapping and alignment constraints. The ASLR scheme may include shifting a subpage granularity of a virtual address in virtual memory, implementing a corresponding code rotation in physical memory, and mapping the modified virtual memory address to the address of the code in physical memory.

[0021] The subpage granularity shift may be a shift of virtual addresses in a memory map configured to map virtual addresses of code in virtual memory to physical addresses in physical memory. The term "memory map" is used herein to refer to a data or memory structure configured to map virtual addresses in virtual memory to physical addresses in physical memory. For example, a memory map may include a TLB, a page table, an address array, a linked list, etc. In some embodiments, a memory map may map virtual addresses of pages of virtual memory of any number and combination of page sizes to physical addresses of physical memory representing corresponding sized portions of physical memory.

[0022] A subpage granularity shift may be a shift of a virtual address of a code by any amount of the virtual address that is not a multiple of a page size for the virtual memory. For example, a subpage granularity shift may be a shift of a virtual address in a virtual memory by any amount of the virtual address that is not a multiple of a minimum page size for the virtual memory. Thus, a virtual address shifted to a subpage granularity of the code may not align with a virtual address boundary of a page in the virtual memory. A subpage granularity shift of a virtual address of a code may result in a virtual address being shifted across a region of the memory map. The term "region" is used herein to refer to a mapping of a virtual address of a same-sized page in a memory map. A new entry for mapping the virtual address of the additional page may be added to a memory map, such as a region, to accommodate the virtual address of the code being shifted across the region. The new entry may map the virtual address of the additional page to a physical address to which the virtual address of the same-sized page is mapped. For example, the new entry may map the virtual address of the additional page to a physical address to which the virtual address of the first page of the same region is mapped.

[0023] The memory map may have multiple regions. Different regions may map virtual addresses of different size pages to physical addresses. A subpage granularity shift with additional entries to a first region may cause the virtual addresses of pages of the second region to be unaligned with the virtual address page boundary of the size page for the second region. A virtual address hole may be introduced into the memory map to align the virtual addresses of pages of the second region to the virtual addresses of the size page page boundary. The virtual address hole may be introduced by shifting the virtual addresses of pages of the second region by an additional amount of virtual addresses to the subpage granularity shift amount of virtual addresses, any number and combination of additional entries that may align the virtual addresses of pages of the second region to the virtual addresses of the size page page boundary.

[0024] In some embodiments, the subpage granularity shift may leave memory map entries for the page's virtual addresses empty of code, and such entries may be omitted from the memory map. In some embodiments, virtual address holes may result in discontinuous virtual addresses between regions, leaving some virtual addresses between the regions unmapped. In either or both cases, the subpage granularity shift may require one entry for each region added to the memory map. Thus, the memory map growth may be small compared to other ASLR schemes, which may require the addition of more memory map entries.

[0025] The code of the virtual addresses of the additional entries to the memory map that are added in response to the subpage granularity shift may be rotated in physical memory. As explained above, the subpage granularity shift may cause the shifted virtual addresses of the code to be misaligned with the virtual addresses of the page boundaries. Thus, the subpage granularity shift may cause the mapping of the virtual addresses of the code of the page to the physical addresses of the additional entries to be shifted by the same amount, leaving corresponding portions of the virtual and physical addresses of the page empty. The subpage granularity shift may also cause the mapping of the additional entries to regions in memory, the mapping of the virtual addresses of the code of the page to the physical addresses of the additional entries to be correspondingly misaligned with the virtual addresses of the page boundaries. The virtual addresses of the pages may be mapped to the same physical addresses, but the virtual addresses of the code in the pages may be mapped to different portions of the physical addresses. The virtual addresses of the code in the additional entries may be mapped to fill the empty portions of the physical addresses caused by the subpage granularity shift. Thus, when the code is loaded, it may be rotated in physical memory, moving the code in an additional entry to the memory map from one end of a range of physical addresses to another end of the range of physical addresses that corresponds to a region in the memory map.

[0026] In some embodiments, the linker may use the memory map as input and adjust the code pointer accordingly. The code pointer may be adjusted to point to a virtual address by the amount the virtual address is shifted in the memory map. In some embodiments, the code pointer may be adjusted by the virtual address amount of sub-page granularity shift. In some embodiments, the code pointer may be adjusted by the virtual address amount of sub-page granularity shift and any number and combination of virtual address holes. Adjusting the code pointer may allow the loader to be flexible for any code rotation in physical memory without having to consider code changes or page alignment.

[0027] 1 illustrates a system including a computing device 100 suitable for use with various embodiments. The computing device 100 may include a SoC 102 having a central processing unit 104, a memory 106, a communication interface 108, a memory interface 110, a peripheral device interface 120, and a processing device 124. The computing device 100 may further include a communication component 112, such as a wired or wireless modem, a memory 114, an antenna 116 for establishing a wireless communication link, and / or a peripheral device 122. The processor 124 may include any of a variety of processing devices, e.g., several processor cores.

[0028] The term "system on chip" or "SoC" is used herein to generally refer to a set of interconnected electronic circuits including, but not limited to, a processing device, memory, and a communication interface. A processing device may include a variety of different types of processors 124 and / or processor cores, such as a general purpose processor, a central processing unit (CPU) 104, a digital signal processor (DSP), a graphics processing unit (GPU), an accelerated processing unit (APU), a secure processing unit (SPU), an intellectual property unit (IPU), a subsystem processor for a particular component of a computing device, such as an image processor for a camera subsystem or a display processor for a display, an auxiliary processor, a peripheral device processor, a single-core processor, a multi-core processor, a controller, and / or a microcontroller. A processing device may further incorporate other hardware and combinations of hardware, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and / or time references. An integrated circuit may be configured such that the components of the integrated circuit reside on a single piece of semiconductor material, such as silicon.

[0029] The SoC 102 may include one or more CPUs 104 and processors 124. The computing device 100 may include more than one SoC 102, thereby increasing the number of CPUs 104, processors 124, and processor cores. The computing device 100 may also include CPUs 104 and processors 124 that are not associated with the SoC 102. Individual CPUs 104 and processors 124 may be multi-core processors. The CPUs 104 and processors 124 may each be configured for a specific purpose, which may be the same or different from other CPUs 104 and processors 124 of the computing device 100. One or more of the CPUs 104, processors 124, and processor cores of the same or different configurations may be grouped together. A group of CPUs 104, processors 124, or processor cores may be referred to as a multi-processor cluster.

[0030] The memory 106 of the SoC 102 may be a volatile or non-volatile memory configured to store data and processor-executable code for access by the CPU 104, the processor 124, or other components of the SoC 102. The computing device 100 and / or the SoC 102 may include one or more memories 106 configured for various purposes. The one or more memories 106 may include volatile memories, such as random access memory (RAM) or main memory, or cache memory. These memories 106 may be configured to temporarily hold data received from a data sensor or subsystem, data and / or processor-executable code instructions requested from the non-volatile memory and loaded from the non-volatile memory into the memory 106 in anticipation of future access based on various factors, and / or a limited amount of intermediate processing data and / or processor-executable code instructions generated by the CPU 104 and / or the processor 124 that are not stored in the non-volatile memory but are stored temporarily for quick access in the future. In some embodiments, any number and combination of the memories 106 may include one-time programmable or read-only memory.

[0031] The memory 106 may be configured to at least temporarily store data and processor-executable code that is loaded into the memory 106 from another memory device, such as another memory 106 or memory 114, for access by one or more of the CPU 104, processor 124, or other components of the SoC 102. The data or processor-executable code loaded into the memory 106 may be loaded in response to execution of a function by the CPU 104, processor 124, or other components of the SoC 102. Loading of data or processor-executable code into the memory 106 in response to execution of a function may result from a memory access request to the memory 106 that is unsuccessful or a "miss" due to the requested data or processor-executable code not being present in the memory 106. In response to the miss, a memory access request may be made to another memory 106 or memory 114 to load the requested data or processor-executable code into the memory 106 from the other memory 106 or memory 114. The loading of data or processor-executable code into memory 106 in response to the execution of a function may result from a memory access request to another memory 106 or memory 114, and the data or processor-executable code may be loaded into memory 106 for later access.

[0032] The memory interface 110 and the memory 114 may operate simultaneously to enable the computing device 100 to store and retrieve data and processor-executable code to and from a volatile and / or non-volatile storage medium. The memory 114 may be configured much like the embodiments of the memory 106, where the memory 114 may store data or processor-executable code for access by one or more of the CPU 104, the processor 124, or other components of the SoC 102. In some embodiments, the memory 114, being non-volatile, may retain information after the computing device 100 is powered off. When power is applied again and the computing device 100 reboots, the information stored on the memory 114 may be available to the computing device 100. In some embodiments, the memory 114, being volatile, may not retain information after the computing device 100 is powered off. The memory interface 110 may control access to the memory 114 and allow the CPU 104 , the processor 124 , or other components of the SoC 102 to read data from and write data to the memory 114 .

[0033] Some or all of the components of computing device 100 and / or SoC 102 may be arranged and / or combined differently while still performing the functionality of the various embodiments. Computing device 100 may not be limited to one of each of the components, and multiple instances of each component may be included in various configurations of computing device 100.

[0034] 2 illustrates components of a memory system 200 of a computing device (e.g., computing device 100 of FIG. 1) suitable for implementing some embodiments. With reference to FIGs. 1 and 2, memory system 200 may include components configured to implement virtual memory 202 (e.g., on SoC 102, CPU 104, processor 124), memory map 204 (e.g., on SoC 102, CPU 104, processor 124), memory management unit (MMU) 206 (e.g., on SoC 102, CPU 104, processor 124), and physical memory 208 (e.g., memory 106).

[0035] The memory management unit 206 may be configured to manage accesses by a processor (e.g., CPU 104, processor 124) to the physical memory 208 to implement memory access requests, such as read and / or write memory access requests. The processor may implement the virtual memory 202 and execute code based on the virtual addresses of the virtual memory 202. The processor may issue memory access requests to the physical memory 208 based on the virtual addresses of the virtual memory 202. To implement the memory access request, the physical memory 208 may require a physical address of the physical memory 208 to identify a location of the physical memory 208 to implement the memory access request. The virtual address and the physical address may not be the same, and the virtual address may need to be translated to a physical address for the physical memory 208 to implement the memory access request. Furthermore, the processor may require any return from the physical memory 208 for implementation of the memory access request indicating the virtual memory address. The physical address used by the physical memory 208 may need to be translated to a virtual address for the processor to accept the return of the memory access request.

[0036] Memory management unit 206 may generate and / or maintain memory map 204 configured to map virtual addresses in virtual memory 202 to physical addresses in physical memory 206, as described further herein. Memory management unit 206 may use memory map 204 to translate between virtual addresses and physical addresses to enable memory access requests to be fulfilled by physical memory 208 and returned by the processor.

[0037] Additionally, memory management unit 206 may be configured to implement ASLR schemes that may increase ASLR entropy through page remapping and rotation, as described further herein. In some embodiments, memory management unit 206 may shift virtual addresses in memory map 204 by a shift amount of subpage granularity, and add and / or omit entries in memory map 204 that map virtual addresses to physical addresses. In some embodiments, memory management unit 206 may shift virtual addresses in memory map 204 to align the virtual addresses of pages to page boundaries, for any number and combination of page sizes.

[0038] 3A-3D show an example of memory mapping and rotation of sub-page granularity shift suitable for implementing various embodiments. With reference to FIG. 1-3D, memory mapping and rotation of sub-page granularity shift may be implemented on a computing device (e.g., computing device 100 of FIG. 1) via a memory system (e.g., memory system 200) for virtual memory 300 (e.g., on SoC 102, CPU 104, processor 124, virtual memory 202 of FIG. 1) and physical memory 320 (e.g., memory 106 of FIG. 1, physical memory 208 of FIG. 2).

[0039] The virtual memory 300 may include any number and combination of pages 302a, 302b, 302c, 304a, 304b of any number and combination of page sizes. The virtual addresses of the pages 302a, 302b, 302c, 304a, 304b may be allocated to codes 306, 308 of any number and combination of code sizes.

[0040] The physical memory 320 may include a range of physical addresses 326a, 326b, 328a that are mapped to pages 302a, 302b, 302c, 304a, 304b of the virtual memory 300. Code 306, 308 that is assigned virtual addresses may be loaded and stored in the physical memory 320 within the range of physical addresses 326a, 326b, 328a.

[0041] 3A illustrates an example mapping of virtual memory 300 and physical memory 320 before implementing subpage granularity shift memory mapping and rotation. The virtual addresses allocated to code 306, 308 may be within pages 302a, 302b, 304a of virtual memory 300. For example, the virtual addresses allocated to code 306 may be within pages 302a, 302b. The virtual addresses allocated to code 308 may be within page 304a. Any portion or combination of the virtual addresses of pages 302a, 302b, 304a may be allocated to code 306, 308.

[0042] The virtual addresses of pages 302a, 302b, 304a may be mapped to physical addresses within the range of physical addresses 326a, 326b, 328a. The code 306, 308 to which the virtual addresses are assigned may be loaded and stored in the physical memory 320 at physical addresses within the range of physical addresses 326a, 326b, 328a to which the virtual addresses are assigned. For example, the virtual address of page 302a may be mapped to a physical address in the range of physical addresses 326a. The portion of the code 306 to which the virtual address of page 302a may be assigned may be loaded and stored at a physical address in the range of physical addresses 326a. The virtual address of page 302b may be mapped to a physical address in the range of physical addresses 326b. The portion of the code 306 to which the virtual address of page 302b may be assigned may be loaded and stored at a physical address in the range of physical addresses 326b. The virtual address of page 304a may be mapped to a range of physical addresses in physical addresses 328a. The code 308 to which the virtual address of page 304a may be assigned may be loaded and stored at a physical address in the range of physical addresses 328a. The code 306, 308 may be loaded and stored at any portion or combination of physical addresses in the range of physical addresses 326a, 326b, 328a.

[0043] 3B illustrates an example of a virtual memory 300 implementing subpage granularity shifting memory mapping and rotation. A subpage granularity shift may shift virtual addresses allocated to code 306, 308 by a subpage granularity shift amount of virtual addresses that are not a multiple of a page size for the virtual memory 300. For example, a subpage granularity shift may shift virtual addresses in the virtual memory 300 by any amount of virtual addresses that are not a multiple of a minimum page size for the virtual memory. For example, the subpage granularity shift virtual address amount may be larger or smaller than a page. Thus, the subpage granularity shifted virtual addresses allocated to code 306, 308 may not align with virtual address boundaries for pages 302a, 302b, 304a in the virtual memory 300.

[0044] A subpage granularity shift may shift the virtual addresses allocated to code 306, 308 across the boundaries of pages 302a, 302b, 304a. For the lowest address region of pages, adjacent pages of the same size as the region's pages may be allocated to accommodate virtual addresses shifted across the page boundaries. For example, for a region that includes pages 302a, 302b, adjacent page 302c of the same size as pages 302a, 302b may be allocated to accommodate virtual addresses shifted across the boundaries of pages 302a, 302b. In some embodiments where the virtual addresses allocated to code 306 are shifted completely across any of pages 302a, 302b, 302c, the virtual addresses of pages 302a, 302b, 302c may be shifted accordingly while maintaining alignment with the page boundaries. In some embodiments, the virtual addresses of pages 302a, 302b, 302c may be shifted by an amount of virtual addresses equal to the nearest multiple of the page size that is less than the subpage granularity shift amount of the virtual addresses. Page 302c may be allocated such that the shifted virtual addresses allocated to code 306 may be subsumed by pages 302a, 302b, 302c. In some embodiments, page 302c may be allocated prior to allocating code 306 to the allocated virtual addresses of page 302c and may include empty address space 310a.

[0045] A higher address region of pages may have pages of different sizes from a lower address region. Similarly, for a lower address region of pages, adjacent pages of the same size as the pages of the region may be allocated to accommodate virtual addresses shifted across the page boundaries. For example, for a region that includes page 304a, adjacent page 304b of the same size as page 304a may be allocated to accommodate virtual addresses shifted across the boundaries of page 304a. In some embodiments, page 304b may be allocated prior to allocating code 308 to the virtual addresses of page 304b and may include empty address space 312a.

[0046] In some embodiments, the shift of the virtual addresses of the pages in the lower address region may also be applied to the virtual addresses of the pages in the higher address region. In some embodiments, the shift of the virtual addresses of the pages in the higher address region may include an amount of virtual addresses to account for the addition of pages to the lower address region. The shift may cause the virtual addresses of the pages in the higher address region to not be aligned with the virtual address page boundary of the size page for the higher address region. A virtual address hole may be introduced in the virtual memory 300 to align the virtual addresses of the pages in the higher address region with the virtual addresses of the page boundary of the size page. The virtual address hole may be introduced by shifting the virtual addresses of the pages in the higher address region by an additional amount of virtual addresses that may align the virtual addresses of the pages in the higher address region with the virtual addresses of the page boundary of the size page. The additional amount of virtual addresses may be in addition to the shift amount of the virtual addresses of the pages and / or the amount of virtual addresses of the additional pages in the lower address region. For example, page 304a may be an independent region and may be a size larger than each of pages 302a, 302b. Page 304b may be added to the higher address region with page 304a. The virtual address of the region containing pages 304a, 304b may be shifted by the amount that the virtual address of the page in the lower address region is shifted. The virtual address of the region containing pages 304a, 304b may be shifted to accommodate the addition of another page. However, any configuration of shifts may not align pages 304a, 304b with the page boundaries of the size page of pages 304a, 304b. To align pages 304a, 304b with the page boundaries of the size page of pages 304a, 304b, the virtual address of the region containing pages 304a, 304b may be shifted by an additional amount that may align pages 304a, 304b with the page boundaries for the size page of pages 304a, 304b.

[0047] 3C illustrates an example of a virtual memory 300 implementing subpage granularity shift memory mapping and rotation. A subpage granularity shift may shift the virtual addresses allocated to code 306, 308 by a subpage granularity shift amount of the virtual addresses. The subpage granularity shift amount of the virtual addresses may be the same for all regions of the virtual memory 300. For the lowest address region pages, the virtual addresses of the pages may be shifted by the subpage granularity shift amount of the virtual addresses. For example, the virtual addresses of a region having pages 302a, 302b may be shifted by the subpage granularity shift amount of the virtual addresses such that the virtual address assigned to code 306 spans pages 302a, 302b, 302c, and a portion of code 306, code 314 is assigned to additional page 302. The subpage granularity shift may create free address space 310b at the lowest address of the region within page 302a and reduce the amount of free address space 310c at the highest address of the region within page 302c by the amount of the subpage granularity shift in the virtual address.

[0048] In the upper address region of pages, the virtual addresses of the pages that have been shifted to accommodate lower address additional pages such as page 302a and to align the virtual addresses of the pages in the upper address region with the virtual addresses of the page boundaries for size pages may be shifted by the subpage granularity shift amount of the virtual address. For example, as described with reference to FIG. 3B, the virtual address of a region having page 304a may be shifted by the subpage granularity shift amount of the virtual address such that the virtual address assigned to code 308 spans pages 304a, 304b, and a portion of code 308, code 316 is assigned to additional page 304b. The subpage granularity shift may create empty address space 312b at the lowest address of the region in page 304a and reduce the amount of empty address space 312c at the highest address of the region in page 304b by the subpage granularity shift amount of the virtual address.

[0049] 3D illustrates an example of a virtual memory 300 and a physical memory 320 during implementation of memory mapping and rotation with subpage granularity shifting. The subpage granularity shifted virtual addresses of the virtual memory 300 may be remapped to physical addresses of the physical memory 320. The original pages 302a, 302b, 304a may be mapped to the same range of physical addresses 326a, 326b, 328a as before implementing the subpage granularity shift, regardless of whether their virtual addresses are shifted. Address pages 302c, 304b may be mapped to the same range of physical addresses 326a, 328a as the lowest address pages 302a, 304a of the same region.

[0050] The shifted virtual addresses of the code 306, 308 may be mapped such that a rotation of the code is implemented in the physical memory 320. The shifted virtual addresses of the code 306, 308 may be mapped such that the physical addresses of the code 306, 308 are shifted the same amount of addresses as the virtual addresses of the code 306, 308 are shifted within the original pages 302a, 302b, 304a. The shifted virtual addresses of the code 314, 316 may be mapped such that the physical addresses of the code 314, 316 fill an empty portion of the range of physical addresses 326a, 326b, 328a created by shifting the physical addresses of the code 306, 308 the same amount of addresses as the virtual addresses of the code 306, 308 are shifted within the original pages 302a, 302b, 304a. Thus, the code 314, 316 is rotated such that it is loaded and stored in physical memory 320 at addresses in the lower range of physical addresses 326a, 326b, 328a rather than at higher addresses in the range of physical addresses 326a, 326b, 328a where the code 314, 316 would be stored without implementing subpage granularity shifting memory mapping and rotation.

[0051] The examples shown in Figures 3A-3D are used for clarity and simplicity of explanation and do not represent all possible embodiments. These examples do not limit the scope of the claims and the specification. The examples do not limit the number and size of regions, the number and size of pages, the amount of code allocated to any number and combination of pages, such as fully and partially allocated pages, the number and size of physical address ranges, the size of subpage granularity shifts, etc.

[0052] 4A-4B show an example of sub-page granularity shifting memory mapping and rotation suitable for implementing various embodiments. With reference to FIGS. 1-4B, sub-page granularity shifting memory mapping and rotation may be implemented on a computing device (e.g., computing device 100 of FIG. 1) via a memory system (e.g., memory system 200) using any number and combination of memory maps 400a, 400b (e.g., memory map 204 of FIG. 2). FIG. 4A shows an example memory map 400a illustrating a memory map before implementing sub-page granularity shifting memory mapping. FIG. 4B shows an example memory map 400b illustrating a memory map implementing sub-page granularity shifting memory mapping.

[0053] Memory map 400a may include two region pages: a lowest address region of pages and an upper address region of pages. The lowest address region of pages may include four pages of size 4K each. The upper address region of pages may include one page of size 16K. Each of the pages may include a virtual address corresponding to the page size and the page, such that the virtual addresses of different pages do not overlap. All virtual addresses of the pages may be contiguous. The virtual addresses of the pages may be mapped to a corresponding range of physical addresses of the same size as the page. In other words, a 4K sized page may be mapped to a 4K sized range of physical addresses and a 16K sized page may be mapped to a 16K sized range of physical addresses.

[0054] Memory map 400b may be generated from memory map 400a by implementing memory mapping shifts with a granularity of several subpages. In the example shown in FIG. 4B, memory map 400b may be generated using subpage granularity shifts with sizes greater than 8K virtual addresses and less than 12K virtual addresses, such as 10K virtual addresses.

[0055] To accommodate the subpage granularity shift of the 10K virtual addresses, a 4K sized page may be added to the lowest address region of the pages. This additional page may contain virtual addresses that are shifted across the original 4 page boundary of the lowest address region of the pages. A 16K sized page may be added to the higher address region of the pages. This additional page may contain virtual addresses that are shifted across the original 1 page boundary of the higher address region of the pages.

[0056] The virtual addresses of the 4K sized pages in the lowest address region of pages may be shifted to encompass all of the virtual addresses of the original 4K sized pages shifted by the 10K virtual address subpage granularity shift while still being aligned with 4K sized page boundaries. For example, a virtual address shift of 8K allows five 4K sized pages in the lowest address region of pages to encompass all of the virtual addresses of the original 4K sized pages shifted by the 10K virtual address subpage granularity shift while still being aligned with 4K sized page boundaries.

[0057] The virtual addresses of the 16K-sized pages in the upper address region of the page may be shifted to encompass all of the virtual addresses of the original 16K-sized pages shifted by the shift of the granularity of the virtual address subpage of 10K while not overlapping the lowest address region of the page and still aligning with the 16K-sized page boundary. For example, a virtual address shift of 8K allows two 16K-sized pages in the lowest address region of the page to encompass all of the number of virtual addresses of the original 16K-sized pages shifted by the shift of the granularity of the virtual address subpage of 10K. However, the virtual address shift of 8K is insufficient to avoid overlapping the lowest address region of the page because of the added fifth page of the lowest address region of the page. Thus, the virtual address shift of the virtual addresses of the upper address region of the page may include an additional 4K virtual address, the size of the added fifth page of the lowest address region of the page. However, a virtual address shift of 12K (8K+4K) may not align the two 16K pages in the upper address region of the page with the 16K page boundary. Thus, the virtual address shift of the virtual address of the upper address region of the page may additionally include an amount of virtual address to align the page in the upper address region of the page with a page boundary of the page size. The virtual address shift of the virtual address of the upper address region of the page may be 16K (8K+4K+4K) to encompass all of the virtual addresses of the original 16K sized page shifted by the 10K virtual address subpage granularity shift while not overlapping the lowest address region of the page and still aligning with a 16K sized page boundary.

[0058] The shifted virtual addresses of the original pages of the region may be mapped to the same range of physical addresses as they were before they were shifted. The added 4K pages may be mapped to the same range of physical addresses as the lowest addressed page of the region of 4K sized pages. The added 16K pages may be mapped to the same range of physical addresses as the lowest addressed page of the region of 16K sized pages.

[0059] The examples shown in Figures 4A and 4B are used for clarity and ease of explanation and do not represent all possible embodiments. These examples are not intended to limit the scope of the claims and the specification. The examples do not limit the number and size of regions, the number and size of pages, the amount of code allocated to any number and combination of pages, including fully and partially allocated pages, the number and size of physical address ranges, the size of subpage granularity shifts, etc.

[0060] 5 shows an example of a flow of a memory mapping and rotation system 500 for sub-page granularity shifting suitable for implementing various embodiments. With reference to FIGS. 1-5, the memory mapping and rotation system 500 for sub-page granularity shifting may be implemented on a computing device (e.g., computing device 100) by a processor (e.g., CPU 104, processor 124) that executes a compiler 504, a linker 510, and a loader 516, and a physical memory.

[0061] A source code 502 may be received by the subpage granularity shift memory mapping and rotation system 500. A compiler may generate program counter (PC) relative code 508 from the source code 502. The compiler 504 may also generate a memory map 506 (e.g., memory map 204, memory 400b). The memory map 506 may be configured to map virtual addresses of a virtual memory (e.g., virtual memory 202, virtual memory 300 in FIG. 2) and physical addresses of a physical memory 522 (e.g., memory 106, physical memory 208, physical memory 320). The memory map 506 may be generated to correspond to the subpage granularity shift memory mapping. For example, the memory map 506 may be generated by adding extra entries (e.g., mappings of virtual addresses of pages to physical addresses) for each region of the memory map 506 compared to a memory map (e.g., memory map 400a) typically used to execute the PC relative code 508. In another example, the virtual addresses of the pages of a region may be shifted to add extra entries for each region and may not be aligned with the page boundaries of the corresponding size page. Memory map 506 may be generated by shifting the virtual addresses of any number and combination of pages of a region to align the pages of the region with the page boundaries of the size page of the region.

[0062] Linker 510 may receive memory map 506 and PC-relative code 508 as input. Linker 510 may use shifts in virtual addresses from memory map 506 and PC-relative code 508 to generate binary code 514 with subpage granularity shift adjusted pointers. The linker may adjust PC-relative offsets using region-specific shifts in memory map 506 to properly link between PC-relative instructions. The linker may convert the adjusted PC-relative code to binary code 514 with subpage granularity shift effective pointers, which may be configured to work regardless of the value of the virtual address subpage granularity shift amount applied to the virtual address in memory map 506.

[0063] The loader 516 may receive as input the memory map 506 and the binary code with subpage granularity shift valid pointer 514. The loader 516 may apply the subpage granularity shift to the virtual addresses of the memory map 506. In some embodiments, the subpage granularity shift may be predetermined or algorithmically derived, such as by a random number generator algorithm. The subpage granularity shift to the virtual addresses of the memory map 506 may shift the virtual addresses of the memory map 506 by the subpage granularity shift amount of the virtual addresses to generate the subpage granularity shift memory map 518 (e.g., memory map 204, memory 400b). The loader 516 may retrieve code from memory (e.g., memory 106, 114) required for the execution of the binary code with subpage granularity shift valid pointer 514. The loader 516 may use the subpage granularity shift memory map 518 to load and store the code in the physical memory 522. For example, the loader 516 may implement a subpage granularity shift memory rotation of code in physical memory 522 according to the virtual memory to physical memory mapping of the subpage granularity shift memory map 518. The loader may shift and rotate the code retrieved from memory to generate rotated binary code with subpage granularity shift valid pointers 520. The loader 516 may load and store the rotated binary code with subpage granularity shift valid pointers 520 into physical memory 522.

[0064] FIG. 6 illustrates a method 600 for sub-page granularity shifting memory mapping according to one embodiment. With reference to FIGS. 1-6, the method 600 may be implemented in a computing device (e.g., computing device 100), in hardware (e.g., SoC 102, CPU 104, memory 106, processor 124, memory management unit 206), in software executing on a processor (e.g., memory management unit 206, compiler 504, linker 510, loader 516), or in a combination of software configured processors and dedicated hardware including other individual components and various memory / cache controllers (e.g., memory system 200, memory management unit 206, sub-page granularity shifting memory mapping and rotation system 500). To encompass alternative configurations possible in various embodiments, the hardware implementing the method 600 is referred to herein as a "memory control device."

[0065] In block 602, the memory control device may set the sub-page granularity shift amount. In some embodiments, any number and combination of sub-page granularity shift amounts may be predetermined or algorithmically derived, such as by a random number generator algorithm. In some embodiments, the sub-page granularity shift amount may be an amount of virtual addresses of a virtual address space or virtual memory (e.g., virtual memory 202, virtual memory 300). In some embodiments, the memory control device that sets the sub-page granularity shift amount in block 602 may be a processor, a CPU, a memory management unit, and / or a loader.

[0066] In block 604, the memory control device may generate a sub-page granularity shift memory map (e.g., memory map 204, e.g., memory map 400b, sub-page granularity shift memory map 518). The memory control device may apply a sub-page granularity shift to a memory map (e.g., memory map 400b, memory map 506). The sub-page granularity shift may be applied to the memory map to shift virtual addresses assigned to code in the memory map by the sub-page granularity shift amount. The memory map to which the sub-page granularity shift is applied may be a memory map generated in a method 700 described with reference to FIG. 7. In some embodiments, the memory control device that generates the sub-page granularity shift memory map in block 604 may be a processor, a CPU, a memory management unit, and / or a loader.

[0067] In block 606, the memory control device may rotate the code (e.g., code 306, 308, 314, 316) in the physical memory (e.g., memory 106, physical memory 208, physical memory 320, physical memory 522) according to the memory map of the subpage granularity shift. The memory control device may rotate the code in the physical memory by loading and storing the code retrieved from the memory (e.g., memory 106, 114) according to the execution of the code (e.g., binary code 514 with subpage granularity shift valid pointer). The code retrieved from the memory may be loaded and stored in the physical memory according to the mapping of the subpage granularity shift to the memory map in method 900, which is further described with reference to FIG. 9. In some embodiments, the memory control device that rotates the code in the physical memory according to the memory map of the subpage granularity shift in block 606 may be a processor, a CPU, a memory management unit, and / or a loader.

[0068] FIG. 7 illustrates a method for memory mapping with sub-page granularity shifting of memory according to one embodiment. With reference to FIGS. 1-7, the method 700 may be implemented in a computing device (e.g., computing device 100), in hardware (e.g., SoC 102, CPU 104, memory 106, processor 124, memory management unit 206), in software executing on a processor (e.g., memory management unit 206, compiler 504, linker 510, loader 516), or in a combination of software configured processors and dedicated hardware including other individual components and various memory / cache controllers (memory system 200, memory management unit 206, sub-page granularity shifting memory mapping and rotation system 500). To encompass alternative configurations possible in various embodiments, the hardware implementing the method 700 is referred to herein as a "memory control device."

[0069] In block 702, the memory control device may add a memory map entry to a region of a memory map (e.g., memory map 400a). The memory map may include regions of virtual addresses for pages of the same size. In other words, each region may include virtual addresses for a single size of page. The memory map may be generated based on a received source code (e.g., source code 502) to use a virtual memory (e.g., virtual memory 202, virtual memory 300) mapped to a physical memory (e.g., memory 106, physical memory 208, physical memory 320, physical memory 522) to execute the source code, so to speak. The memory control device may add an entry for a page to each region of the memory map of the appropriate page size for the region. The entry for the region may include virtual addresses of pages adjacent to the region. The virtual addresses for the pages of the entry for the region may be mapped to the same range of physical addresses of the lowest virtual address page of the entry for the region. In some embodiments, the memory control device that adds the memory map entry to the region of the memory map in block 702 may be a processor, a CPU, a memory management unit, and / or a compiler.

[0070] At block 704, the memory control device may shift the virtual address range of the pages of the memory map to accommodate one or more additional entries to the memory map. Adding an entry to a region of the memory map may cause the virtual address of the added entry to overlap with the virtual address of another region of the memory map. The memory control device may shift any number and combination of regions of the memory map to avoid overlapping virtual addresses between regions of the memory map. In some embodiments, the memory control device that shifts the virtual address range of the pages of the memory map to accommodate one or more additional entries to the memory map at block 704 may be a processor, a CPU, a memory management unit, and / or a compiler.

[0071] In decision block 706, the memory control device may determine whether the virtual address range of the pages in the region aligns to a page boundary of the corresponding page size. Different regions of the memory map may have different page sizes, and the pages of the region may align to boundaries of page sizes recognized by various software, firmware, and / or hardware. To maintain functionality after shifting the virtual address range of the pages of the memory map to accommodate one or more additional entries to the memory map in block 704, the memory control device may ensure that the virtual address range of the pages in the region aligns to a page boundary of the corresponding page size. For example, the memory control device may compare the virtual addresses of the region and / or pages to a known page boundary of the corresponding page size. In another example, the memory control device may compare the virtual addresses of the region and / or pages to a number of known or calculated page boundaries of the corresponding page size, such as page boundaries prior to the shift of block 704. In some embodiments, the memory control device that determines whether the virtual address range of the pages in the region aligns to a page boundary of the corresponding page size in decision block 706 may be a processor, a CPU, a memory management unit, and / or a compiler.

[0072] In response to determining that the virtual address range of the pages in the region is not aligned to a page boundary of the corresponding page size (i.e., decision block 706="No"), the memory control device may shift the virtual address range of the pages in the region by an amount that aligns the virtual address range to a page boundary of the corresponding page size at block 708. The comparison of decision block 706 may result in an amount by which the virtual address range of the pages in the region is not aligned to a page boundary of the corresponding page size. The memory control device may shift the virtual address range of the pages in the region by an amount that aligns the virtual address range to a page boundary of the corresponding page size. In some embodiments, the memory control device that shifts the virtual address range of the pages in the region by an amount that aligns the virtual address range to a page boundary of the corresponding page size at block 708 may be a processor, a CPU, a memory management unit, and / or a compiler.

[0073] In some embodiments, decision block 706 and block 708 may be implemented recursively for contiguous regions of the memory map. For example, each contiguous region of the memory map may be shifted as the previous region is shifted. The memory control device may implement decision block 706 and block 708 for the contiguous region once the previous region is aligned to the corresponding page size boundary. The recursive implementation of decision block 706 and block 708 may continue until the last region of the memory map is aligned to the corresponding page size boundary.

[0074] In response to determining that the virtual address range of the pages in the region aligns to page boundaries of the corresponding page size (i.e., decision block 706="Yes"), or shifting the virtual address range of the pages in the region by an amount that aligns the virtual address range to page boundaries of the corresponding page size in block 708, below, the memory control device may map the shifted virtual address range of the pages in the region to a range of physical addresses the same size as the page in block 710. Mapping the shifted virtual address range of the pages in the region to a range of physical addresses the same size as the page may include mapping the lowest virtual address page and the highest virtual address page in the region to the same range of physical addresses. In some embodiments, the memory control device that maps the shifted virtual address range of the pages in the region to a range of physical addresses the same size as the page in block 710 may be a processor, a CPU, a memory management unit, and / or a compiler.

[0075] FIG. 8 illustrates a method 800 for memory rotation according to one embodiment. With reference to FIGS. 1-8, the method 800 may be implemented in a computing device (e.g., computing device 100), in hardware (e.g., SoC 102, CPU 104, memory 106, processor 124, memory management unit 206), in software running on a processor (e.g., memory management unit 206, compiler 504, linker 510, loader 516), or in a combination of software configured processors and dedicated hardware, including other individual components and various memory / cache controllers (memory system 200, memory management unit 206, sub-page granularity shift memory mapping and rotation system 500). To encompass alternative configurations possible in various embodiments, the hardware implementing the method 800 is referred to herein as a "memory control device."

[0076] At block 802, a memory control device may generate PC-relative code (e.g., PC-relative code 508) from source code (e.g., source code 502). In some embodiments, the memory control device that generates the PC-relative code from source code at block 802 may be a processor, a CPU, a memory management unit, and / or a compiler.

[0077] In block 804, the memory control device may generate binary code with subpage granularity shift valid pointers (e.g., binary code with subpage granularity shift adjustment pointers 514) using a memory map (e.g., memory map 400b, memory map 506). The memory map may be the memory map generated in the method 700 described with reference to FIG. 7. The memory control device may receive as input the memory map and the PC-relative code generated in block 802. The memory control device may use a shift in the virtual address from the memory map and the PC-relative code to generate the binary code with subpage granularity shift adjustment pointers. The memory control device may adjust the PC-relative offset using a region-specific shift of the memory map to properly link between PC-relative instructions. The memory control device may convert the adjusted PC-relative code into binary code with subpage granularity shift valid pointers, which may be configured to function regardless of the value of the virtual address subpage granularity shift amount applied to the memory map virtual address in block 604 of the method 600 described with reference to FIG. 6. In some embodiments, the memory control device that uses the memory map to generate binary code with shifted valid pointers at sub-page granularity in block 804 may be a processor, a CPU, a memory management unit, and / or a linker.

[0078] In block 806, the memory control device may generate a rotated binary code with subpage granularity shift valid pointers (e.g., rotated binary code with subpage granularity shift valid pointers 520). The memory control device may receive as input the memory map and the binary code with subpage granularity shift valid pointers generated in block 804. The memory control device may generate a subpage granularity shift memory map (e.g., memory map 204, memory map 400b, subpage granularity shift memory map 518) similar to the operation of block 604 of method 600 described with reference to FIG. 6. The memory control device may retrieve code required for execution of the binary code with subpage granularity shift valid pointers from memory (e.g., memory 106, 114). The memory control device may use the subpage granularity shift memory map to load and store code in physical memory (e.g., memory 106, physical memory 208, physical memory 320, physical memory 522). For example, the memory control device may implement a sub-page granularity shift memory rotation of the code in the physical memory according to a virtual memory to physical memory mapping of the sub-page granularity shift memory map, similar to block 606 of method 600 described with reference to Figure 6 and method 900 described with reference to Figure 9. In some embodiments, the memory control device that generates the rotated binary code with sub-page granularity shift valid pointers in block 806 may be a processor, CPU, memory management unit, and / or a loader.

[0079] FIG. 9 illustrates a method 900 for the described memory rotation according to one embodiment. With reference to FIGS. 1-9, the method 900 may be implemented in a computing device (e.g., computing device 100), in hardware (e.g., SoC 102, CPU 104, memory 106, processor 124, memory management unit 206), in software running on a processor (e.g., memory management unit 206, compiler 504, linker 510, loader 516), or in a combination of software-configured processors and dedicated hardware including other individual components and various memory / cache controllers (memory system 200, memory management unit 206, sub-page granularity shift memory mapping and rotation system 500). To encompass alternative configurations possible in various embodiments, the hardware implementing the method 900 is referred to herein as a "memory control device."

[0080] In block 902, the memory control device may load the code of the virtual address of the original page of the region to the physical address according to the mapping of the subpage granularity shift memory map (e.g., memory map 204, memory map 400b, subpage granularity shift memory map 518). The memory control device may interpret the mapping of the subpage granularity shift memory map for the rotated binary code with subpage granularity shift valid pointer (e.g., rotated binary code with subpage granularity shift valid pointer 520) as generated in block 806 of the method 800 described with reference to FIG. 8. For example, the memory control device may interpret the virtual address to physical address mapping of the pages of the region other than the page added to the region in block 702 of the method 700 described with reference to FIG. 7. The pages may have virtual addresses that are shifted and mapped to consecutive, increasing physical addresses. The physical addresses to which the virtual addresses of the original pages are mapped may be shifted by the amount of subpage granularity shift addresses or address space. The memory control device that loads the code of the virtual address of the original page of the area to the physical address according to the mapping of the memory map of the subpage granularity shift in block 902 may be a processor, a CPU, a memory management unit, and / or a loader.

[0081] In block 904, the memory control device loads the code of the virtual address of the added page of the region to the physical address according to the mapping of the memory map of the subpage granularity shift. The memory control device may further interpret the mapping of the memory map of the subpage granularity shift for the rotated binary code with the subpage granularity shift valid pointer. For example, the memory control device may interpret the virtual address to physical address mapping of the added page of the region in block 702 of the method 700 described with reference to FIG. 7. The page may have a virtual address that is shifted and mapped to a physical address that overlaps the physical address of the lowest virtual address page of the region. The physical address to which the virtual address of the added page is mapped may be a physical address that is left vacant by the shift of the physical address by the amount of the address or address space of the subpage granularity shift. The memory control device that loads the code of the virtual address of the added page of the region to the physical address according to the mapping of the memory map of the subpage granularity shift in block 904 may be a processor, a CPU, a memory management unit, and / or a loader.

[0082] Systems according to various embodiments (including but not limited to those described above with reference to FIGS. 1-9) may be implemented in a wide variety of computing systems, including mobile computing devices, one example of a mobile computing device suitable for use with various embodiments is shown in FIG. 10. The mobile computing device 1000 may include a processor 1002 coupled to a touch screen controller 1004 and an internal memory 1006. The processor 1002 may be one or more multi-core integrated circuits, general purpose or designated for specific processing tasks. The internal memory 1006 may be volatile or non-volatile memory, and may be secure and / or encrypted or non-secure and / or non-encrypted memory, or any combination thereof. Examples of memory types that may be utilized include, but are not limited to, DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touchscreen controller 1004 and processor 1002 may also be coupled to a touchscreen panel 1012, such as a resistive-sensing touchscreen, a capacitive-sensing touchscreen, an infrared-sensing touchscreen, etc. Furthermore, the display of the mobile computing device 1000 need not have touchscreen capabilities.

[0083] The mobile computing device 1000 may have one or more wireless signal transceivers 1008 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio, etc.) and antennas 1010 for transmitting and receiving communications, coupled to each other and / or to the processor 1002. The transceivers 1008 and antennas 1010 may be used with the circuits described above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 1000 may include a cellular network wireless modem chip 1016 that enables communication over a cellular network and is coupled to the processor.

[0084] The mobile computing device 1000 may include a peripheral device connection interface 1018 coupled to the processor 1002. The peripheral device connection interface 1018 may be solely configured to accept one type of connection or may be configured to accept various types of common or proprietary physical and communication connections, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 1018 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0085] The mobile computing device 1000 may also include a speaker 1014 for providing audio output. The mobile computing device 1000 may also include a housing 1020 constructed of plastic, metal, or a combination of materials for housing all or a portion of the components described herein. The mobile computing device 1000 may also include a power source 1022 coupled to the processor 1002, such as a disposable or rechargeable battery. The rechargeable battery may be coupled to a peripheral device connection port to receive charging current from a power source external to the mobile computing device 1000. The mobile computing device 1000 may also include a physical button 1024 for receiving user input. The mobile computing device 1000 may include a power button 1024 for turning the mobile computing device 1000 on and off.

[0086] Systems according to various embodiments (including, but not limited to, those described above with reference to FIGS. 1-9) may be implemented in a wide variety of computing systems, including a laptop computer 1100, an example of which is shown in FIG. 11. Many laptop computers include a touchpad touch surface 1117 that serves as the computer's pointing device and may therefore receive drag, scroll, and flick gestures similar to those implemented on the computing devices described above equipped with touchscreen displays. The laptop computer 1100 typically includes a processor 1102 coupled to a volatile memory 1112 and a large capacity non-volatile memory, such as a flash memory disk drive 1113. In addition, the computer 1100 may have one or more antennas 1108 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless data link and / or a cellular telephone transceiver 1116 coupled to the processor 1102. The computer 1100 may also include a floppy disk drive 1114 and a compact disk (CD) drive 1115 coupled to the processor 1102. In a notebook configuration, the computer housing includes a touchpad 1117, a keyboard 1118, and a display 1119, all coupled to the processor 1102. Other configurations of computing devices may include a computer mouse or trackball coupled to the processor (e.g., via a USB input), as is well known, and may also be used with various embodiments.

[0087] Systems according to various embodiments (including but not limited to those described above with reference to FIGS. 1-9) may be implemented in a fixed computing system, such as any of a variety of commercially available servers. An exemplary server 1200 is shown in FIG. 12. Such a server 1200 typically includes one or more multi-core processor assemblies 1201 coupled to large capacity non-volatile memory, such as volatile memory 1202 and disk drive 1204. As shown in FIG. 12, multi-core processor assemblies 1201 may be added to the server 1200 by inserting them into a rack of assemblies. The server 1200 may also include a floppy disk drive, compact disk (CD) or digital versatile disk (DVD) disk drive 1206 coupled to the processor 1201. The server 1200 may also include a network access port 1203 coupled to the multi-core processor assembly 1201 for establishing a network interface connection with a network 1205, such as a local area network, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0088] Example implementations are described in the following paragraphs. Although some of the following example implementations are described with respect to example methods, further example implementations may include the example methods described in the following paragraphs implemented by a computing device comprising a processor configured to cause processor-executable instructions to perform operations of the example methods, the example methods described in the following paragraphs implemented by a computing device including means for performing functions of the example methods, and the example methods described in the following paragraphs implemented as a non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a processor of a computing device to perform operations of the example methods.

[0089] Example 1. A method of generating a memory map configured to map virtual addresses of pages to physical addresses, where pages of the same size are grouped into regions, comprising: adding a first entry for a first additional page to a first region of the memory map, shifting a virtual address of the first region allocated to code by a sub-page granularity shift amount to correspond to a shift, mapping the shifted virtual address of the first entry for the first additional page to a physical address mapped to a first lowest shifted virtual address page of the first region, and shifting the virtual address of the first region allocated to code by a sub-page granularity shift amount, where the virtual address of the first region allocated to code is partially shifted into the first entry for the first additional page.

[0090] Example 2. The method of Example 1 further including the steps of adding a second entry for a second additional page to a second region of the memory map, the second region being virtually addressed higher than the first region, shifting a virtual address of the second region by a sub-page granularity shift amount to correspond to a shift in the virtual address of the second region allocated to code, mapping the shifted virtual address of the second entry for the second additional page to a physical address mapped to a second lowest shifted virtual address page of the second region, and shifting the virtual address of the second region allocated to code by the sub-page granularity shift amount, where the virtual address of the second region allocated to code is partially shifted into the second entry for the second additional page.

[0091] Example 3. The method of any of Examples 1 or 2, further comprising: shifting a virtual address of the second region to accommodate the first entry added to the first region of the memory map; and shifting the virtual address of the second region to align a page of the second region, including the second added page, with a page boundary of a size page of the page of the second region.

[0092] Example 4. The method of any of Examples 1 to 3, further comprising rotating the code to a shifted virtual address of the first region allocated to the code in physical memory.

[0093] Example 5. The method of Example 4, wherein rotating the code for the shifted virtual address of the first region allocated to the code in the physical memory includes loading the code into a mapped physical address from a first lowest virtual address page for the shifted virtual address of the first region allocated to the code, and loading the code into a mapped physical address from a first additional page for the shifted virtual address of the first region allocated to the code, where the mapped physical address for the shifted virtual address of the first region allocated to the code from the first additional page is a lower physical address than the mapped physical address for the shifted virtual address of the first region allocated to the code from the first lowest virtual address page.

[0094] Example 6. The method of any of Examples 1 to 5, further comprising adjusting a pointer for the binary code including the code by an amount of a shift in the virtual address of the second region to correspond to a shift in the virtual address of the second region allocated to the code by an amount of a shift in subpage granularity.

[0095] Example 7. The method of example 6, further comprising generating program counter relative code and generating binary code from the program counter relative code.

[0096] Computer program code or "program code" for execution on a programmable processor to perform operations of various embodiments may be written in a high-level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or a variety of other programming languages. Program code or programs stored on a computer-readable storage medium as used in this application may refer to machine code (such as object code) whose format is understandable by a processor.

[0097] The above method descriptions and process flow diagrams are provided merely as illustrative examples and do not require or imply that the operations of the various embodiments must be performed in the order presented. As will be appreciated by one of ordinary skill in the art, the order of operations in the above-described embodiments may be performed in any order. Words such as "then," "then," and "next" do not limit the order of operations; these words are merely used to guide the reader through the method descriptions. Additionally, any reference to a claim element in the singular, for example using the articles "a," "an," or "the," should not be construed as limiting the element to the singular.

[0098] The various exemplary logic blocks, modules, circuits, and algorithmic operations described with respect to the various embodiments may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various exemplary components, blocks, modules, circuits, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0099] The hardware used to implement the various exemplary logic, logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0100] In one or more embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or codes on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operations of the methods or algorithms disclosed herein may be embodied in a processor-executable software module that may reside on a non-transitory computer-readable storage medium or a non-transitory processor-readable storage medium. A non-transitory computer-readable storage medium or a non-transitory processor-readable storage medium may be any storage medium that may be accessed by a computer or a processor. By way of example and not limitation, such a non-transitory computer-readable medium or a processor-readable medium may include RAM, ROM, EEPROM, FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically and discs reproduce data optically using lasers. Combinations of the above are also included within the scope of non-transitory computer-readable media and non-transitory processor-readable media. Additionally, operations of a method or algorithm may reside as one or any combination or set of code and / or instructions on a non-transitory processor-readable medium and / or a non-transitory computer-readable medium that may be incorporated into a computer program product.

[0101] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the claims. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein, but should be accorded the widest scope consistent with the claims and principles and novel features disclosed herein. [Explanation of symbols]

[0102] 100 computing devices 102 SoC 104 Central Processing Unit (CPU) 106 Memory 108 Communication Interface 110 Memory Interface 112 Communication Components 114 Memory 116 Antenna 120 Peripheral Device Interface 122 Peripheral Devices 124 Processing Devices / Processors 200 Memory System 202 Virtual Memory 204 Memory Map 206 Memory Management Unit (MMU) 208 Physical Memory 300 Virtual Memory Page 302 Page 304 306 Code 308 Code 320 physical memory 326 Physical Address 328 Physical Address 400 Memory Map 502 Source Code 522 physical memory 1000 Mobile Computing Devices 1002 Processor 1004 Touch Screen Controller 1006 Internal Memory 1008 Transceiver 1010 Antenna 1012 Touch Screen Panel 1014 Speaker 1016 Cellular Network Wireless Modem Chip 1018 Peripheral device connection interface 1020 Housing 1022 Power supply 1024 Physical Buttons / Power Button 1102 Processor 1108 Antenna 1100 Laptop Computer 1112 Volatile Memory 1113 Disk Drive 1114 Floppy Disk Drive 1115 Compact Disc (CD) Drive 1116 Wireless Data Link and / or Cellular Telephone Transceivers 1117 Touchpad 1118 Keyboard 1119 Display 1200 Server 1201 Multi-core Processor Assembly 1202 Volatile Memory 1203 Network Access Port 1204 Disk Drive 1205 Network 1206 Digital Versatile Disc (DVD) Disc Drive

Claims

1. 1. A method of generating a memory map configured to map virtual addresses of pages to physical addresses, wherein pages of the same size are grouped into regions, the method comprising: adding a first entry for a first additional page to a first region of the memory map; shifting the virtual address of the first region by a subpage granularity shift amount to correspond to the shift of the virtual address of the first region allocated to the code; mapping a shifted virtual address of the first entry for the first additional page to a physical address mapped to a first lowest shifted virtual address page of the first region; shifting the virtual address of the first region allocated to code by a subpage granularity shift amount, where the virtual address of the first region allocated to code is shifted partially to the first entry for the first additional page; A method comprising:

2. adding a second entry for a second additional page to a second region of the memory map, the second region being virtually addressed higher than the first region; shifting the virtual address of the second region by a shift amount of the subpage granularity to correspond to the shift of the virtual address of the second region allocated to code; mapping a shifted virtual address of the second entry for the second additional page to a physical address mapped to a second lowest shifted virtual address page of the second region; shifting the virtual address of the second region allocated to code by the subpage granularity shift amount, where the virtual address of the second region allocated to code is partially shifted to the second entry for the second additional page; The method of claim 1, further comprising:

3. shifting the virtual address of the second region to correspond to the first entry added to the first region of the memory map; shifting the virtual address of the second region to align the page of the second region, including the second additional page, with a page boundary of a size page of the page of the second region; 3. The method of claim 2, further comprising:

4. 2. The method of claim 1, further comprising rotating the code for the shifted virtual address of the first region allocated to the code in physical memory.

5. rotating the code for the shifted virtual address of the first region allocated to the code in the physical memory, loading code from the first lowest virtual address page to the mapped physical address for the shifted virtual address of the first region allocated to code; loading code for the shifted virtual address of the first region allocated to code from the first additional page to the mapped physical address, wherein the mapped physical address for the shifted virtual address of the first region allocated to code from the first additional page is a lower physical address than the mapped physical address for the shifted virtual address; 5. The method of claim 4, comprising:

6. 2. The method of claim 1, further comprising: adjusting a pointer for binary code including the code by the amount of the shift in the virtual address of the first region to correspond to the shift in the virtual address of the first region allocated to the code by the shift amount of subpage granularity.

7. 1. A computing device comprising: adding a first entry for a first additional page to a first region of a memory map, the memory map being configured to map virtual addresses of pages to physical addresses, with pages of the same size being grouped into a region that includes the first region; shifting a virtual address of the first region allocated to code by a subpage granularity shift amount to correspond to the shift of the virtual address of the first region; Mapping a shifted virtual address of the first entry for the first additional page to a physical address mapped to a first lowest shifted virtual address page of the first region; shifting the virtual address of the first region allocated to code by a subpage granularity shift amount, where the virtual address of the first region allocated to code is partially shifted to the first entry for the first additional page; A computing device comprising a processing device configured to perform the steps of:

8. 8. The computing device of claim 7, wherein the processing device is configured to rotate the code for the shifted virtual address of the first region allocated to the code in physical memory.

9. the processing device comprising: for the shifted virtual address of the first region allocated to code in the physical memory, loading code from the first lowest virtual address page into the mapped physical address for the shifted virtual address of the first region allocated to code; loading code from the first additional page to the mapped physical address for the shifted virtual address of the first region allocated to code, where the mapped physical address for the shifted virtual address of the first region allocated to code from the first additional page is a lower physical address than the mapped physical address for the shifted virtual address; 9. The computing device of claim 8, configured to rotate the code by:

10. 1. A computing device comprising: means for adding a first entry for a first added page to a first region of a memory map, the memory map being configured to map virtual addresses of pages to physical addresses, with pages of the same size being grouped into a region that includes the first region; means for shifting a virtual address of the first region allocated to code by a subpage granularity shift amount to correspond to a shift in the virtual address of the first region; means for mapping a shifted virtual address of the first entry for the first additional page to a physical address mapped to a first lowest shifted virtual address page of the first region; means for shifting the virtual address of the first region allocated to code by a subpage granularity shift amount, the virtual address of the first region allocated to code being partially shifted to the first entry for the first additional page; A computing device comprising:

11. 11. The computing device of claim 10, further comprising: means for rotating the code for the shifted virtual address of the first region allocated to the code in physical memory.

12. means for rotating the code for the shifted virtual address of the first region allocated to the code in the physical memory, the means comprising: means for loading code from the first lowest virtual address page to the mapped physical address for the shifted virtual address of the first region allocated to code; means for loading code from the first additional page to the mapped physical address for the shifted virtual address of the first region allocated to code, wherein the mapped physical address for the shifted virtual address of the first region allocated to code from the first additional page is a lower physical address than the mapped physical address for the shifted virtual address of the first region allocated to code from the first lowest virtual address page; The computing device of claim 11 , comprising:

13. A non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a processing device to perform an operation, the operation comprising: adding a first entry for a first additional page to a first region of a memory map, the memory map being configured to map virtual addresses of pages to physical addresses, with pages of the same size being grouped into a region that includes the first region; shifting the virtual address of the first region by a subpage granularity shift amount to correspond to the shift of the virtual address of the first region allocated to code; Mapping a shifted virtual address of the first entry for the first additional page to a physical address mapped to a first lowest shifted virtual address page of the first region; shifting the virtual address of the first region allocated to code by a subpage granularity shift amount, where the virtual address of the first region allocated to code is partially shifted to the first entry for the first additional page; 16. A non-transitory processor-readable storage medium comprising:

14. 14. The non-transitory processor-readable storage medium of claim 13, wherein the stored processor-executable instructions are configured to cause the processing device to perform operations further including rotating the code for the shifted virtual address of the first region allocated to the code in physical memory.

15. The stored processor-executable instructions cause the processing device to: loading code from the first lowest virtual address page into the mapped physical address for the shifted virtual address of the first region allocated to code; loading code from the first additional page to the mapped physical address for the shifted virtual address of the first region allocated to code, wherein the mapped physical address for the shifted virtual address of the first region allocated to code from the first additional page is a lower physical address than the mapped physical address for the shifted virtual address; 15. The non-transitory processor-readable storage medium of claim 14, configured to cause an operation to be performed to rotate the code for the shifted virtual address of the first region allocated to the code in the physical memory, the operation comprising:

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