Package Having Substrate Including Pad-on-Pad Interconnects - Patent application

Abstract

The package includes a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects, including a plurality of pad-on-pad interconnects, the plurality of pad-on-pad interconnects being embedded through a first surface of the substrate. The plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect including a first pad and a second pad coupled to the first pad. The package further includes a solder resist layer disposed on the first surface of the substrate. The solder resist layer includes a first solder resist layer portion including a first thickness and a second solder resist layer portion including a second thickness less than the first thickness. The second solder resist layer portion is positioned between the at least one dielectric layer and the integrated device.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 210,314, filed in the United States Patent Office on March 23, 2021, the entire contents of which are incorporated by reference herein for all applicable purposes as if fully set forth below.

[0002] Various features relate to packages that include integrated devices, and more particularly, to packages that include integrated devices and substrates. [Background technology]

[0003] The package may include a substrate and an integrated device. The substrate may include a plurality of interconnects. The integrated device may be coupled to the interconnects of the substrate. There is currently a need to provide smaller packages with fine interconnects between the substrate and the integrated device. Summary of the Invention [Means for solving the problem]

[0004] Various features relate to packages that include integrated devices, and more particularly, to packages that include integrated devices and substrates.

[0005] One example provides a package including a substrate and an integrated device coupled to the substrate, the substrate including at least one dielectric layer and a plurality of interconnects including a plurality of pad-on-pad interconnects, the plurality of pad-on-pad interconnects embedded through a first side of the substrate.

[0006] Another example provides an apparatus that includes a substrate including at least one dielectric layer and a plurality of interconnects including a plurality of pad-on-pad interconnects, the plurality of pad-on-pad interconnects embedded through a first side of the substrate.

[0007] In another example, a method for manufacturing a package is provided. The method includes providing a substrate including at least one dielectric layer and a plurality of interconnects including a plurality of pad-on-pad interconnects embedded through a first side of the substrate. The method includes bonding an integrated device to the substrate.

[0008] Various features, nature and advantages may become apparent from the detailed description set forth below when read in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a side view of a package including an integrated device and a substrate having pad-on-pad interconnects. [Diagram 2] FIG. 2 is a side close-up view of a package including an integrated device and a substrate having pad-on-pad interconnects. [Diagram 3] FIG. 2 is a side close-up view of a package including an integrated device and a substrate having pad-on-pad interconnects. [Figure 4] FIG. 2 is a side close-up view of a package including an integrated device and a substrate having pad-on-pad interconnects. [Diagram 5] FIG. 2 is a side close-up view of a package including an integrated device and a substrate having pad-on-pad interconnects. [Figure 6] FIG. 2 is a side close-up view of a package including an integrated device and a substrate having pad-on-pad interconnects. [Figure 7] FIG. 2 is a side view of a package including a substrate having pad-on-pad interconnects. [Figure 8] FIG. 2 is a side view of a package including a substrate having pad-on-pad interconnects. [Figure 9] FIG. 2 is a side view of a package including a substrate having pad-on-pad interconnects. [Figure 10A] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 10B] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 10C] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 10D] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 11] 1 illustrates an example flow diagram of a method for manufacturing a substrate. [Figure 12] 1A-1C illustrate an exemplary sequence for manufacturing a package that includes a substrate that includes pad-on-pad interconnects. [Figure 13] 1 is an example flow diagram of a method for manufacturing a package that includes a substrate that includes pad-on-pad interconnects. [Figure 14] 1A-1C illustrate various electronic devices that may integrate the die, electronic circuits, integrated devices, integrated passive devices (PIDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are given to enable a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring aspects of the present disclosure.

[0011] The present disclosure describes a package including a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects including a plurality of pad-on-pad interconnects. The plurality of pad-on-pad interconnects are embedded through a first surface (e.g., a top surface) of the substrate. The plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect including a first pad and a second pad coupled to the first pad. The package further includes a solder resist layer disposed on the first surface of the substrate. The solder resist layer includes a first solder resist layer portion including a first thickness and a second solder resist layer portion including a second thickness less than the first thickness. The second solder resist layer portion may be located between the at least one dielectric layer and the integrated device.

[0012] Exemplary Package Including Substrate Including Pad-on-Pad Interconnects 1 shows a plan view of a package 100 including a substrate having pad-on-pad interconnects. The package 100 includes a substrate 102 and an integrated device 103. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, a solder resist layer 140, and a solder resist layer 142. The plurality of interconnects 122 includes a plurality of pad-on-pad interconnects (e.g., 122a, 122b).

[0013] As described further below, the plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect including a first pad and a second pad coupled to the first pad. In some implementations, the first pad and the second pad may be considered part of the same pad. In some implementations, there may or may not be an interface between the first pad and the second pad.

[0014] The integrated device 103 is coupled to a first surface (e.g., a top surface) of the substrate 102. For example, the integrated device 103 is coupled to the substrate 102 through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The integrated device 103 is coupled to a plurality of pad-on-pad interconnects (e.g., 122a) through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132.

[0015] As shown in FIG. 1, the solder resist layer 140 is disposed on a first surface (e.g., a top surface) of the substrate 102, and the solder resist layer 142 is disposed on a second surface (e.g., a bottom surface) of the substrate 102. The plurality of interconnects 122 may be disposed in the at least one dielectric layer 120. The plurality of interconnects 122 includes a plurality of pad-on-pad interconnects (e.g., 122a, 122c), an interconnect 122c, and an interconnect 122d. The interconnect 122d may be a surface interconnect. The interconnect 122d may be located on the second surface (e.g., a bottom surface) of the substrate 102. For example, the interconnect 122d may be located on the second surface (e.g., a bottom surface) of the at least one dielectric layer 120. The interconnect 122c is embedded in the first surface of the substrate 102. The interconnects 122c may include traces embedded in a first surface of the at least one dielectric layer 120. The interconnects 122c may include traces disposed in a first surface of the at least one dielectric layer 120 of the substrate 102.

[0016] FIG. 2 shows an enlarged side view of the substrate 102. As shown in FIG. 2, the plurality of pad-on-pad interconnects may include a first pad-on-pad interconnect 122a and a second pad-on-pad interconnect 122b. The first pad-on-pad interconnect 122a is embedded through a first surface (e.g., a top surface) of the substrate 102. The first pad-on-pad interconnect 122a includes a first portion 222a and a second portion 223a. The first portion 222a may include a first pad, and the second portion 223a may include a second pad. The first pad may be coupled to a second pad. In some implementations, the first portion 222a and the second portion 223a may be part of the same pad (e.g., a pad interconnect). In some implementations, there may or may not be an interface between the first portion 222a (e.g., a first pad) and the second portion 223a (e.g., a second pad). The first portion 222a is disposed (e.g., embedded) in the at least one dielectric layer 120. The second portion 223a is disposed on the at least one dielectric layer 120. The first portion 222a may include a first width, and the second portion 223a may include a second width. The width may include a diameter. The first width of the first portion 222a may be different from the second width of the second portion 223a. In FIG. 2, the first width of the first portion 222a is greater than the second width of the second portion 223a. However, the second width may be greater than the first width. In some implementations, the first width may be the same as the second width. The second portion 223a may have a thickness of approximately 15 micrometers or less (e.g., 12-15 micrometers). The first pad-on-pad interconnect 122a is coupled to the interconnect 122h. The interconnect 122h is coupled to the first portion 222a. The interconnects 122 h may be traces disposed within at least one of the dielectric layers 120 .

[0017] As also shown in FIG. 2, the second pad-on-pad interconnect 122b is embedded through the first surface of the substrate 102. The second pad-on-pad interconnect 122b includes a first portion 222b and a second portion 223b. The first portion 222b may include a first pad, and the second portion 223b may include a second pad. The first pad may be coupled to the second pad. In some implementations, the first portion 222b and the second portion 223b may be part of the same pad (e.g., pad interconnect). In some implementations, there may or may not be an interface between the first portion 222b (e.g., a first pad) and the second portion 223b (e.g., a second pad). The first portion 222b is disposed (e.g., embedded) in the at least one dielectric layer 120. The second portion 223b is disposed on the at least one dielectric layer 120. The first portion 222b may include a first width and the second portion 223b may include a second width. The width may include a diameter. The first width may be different from the second width. In some implementations, the first width may be the same as the second width. In FIG. 2, the first width of the first portion 222b is smaller than the second width of the second portion 223b. However, the second width may be smaller than the first width. The second portion 223a may have a thickness of approximately 15 micrometers or less (e.g., 12-15 micrometers). The second pad-on-pad interconnect 122b is coupled to the interconnect 122i. The interconnect 122i is coupled to the first portion 222b. The interconnect 122i may be a via disposed in at least one dielectric layer 120.

[0018] The second portions 223a and / or 223b may be protrusions of the interconnect. That is, the second portions 223a and / or 223b may protrude from at least one dielectric layer 120. The second portions 223a and 223b (e.g., second pads) may include a seed layer. The minimum line width (L) of the pad-on-pad interconnect (e.g., 122a) may be about 10 micrometers. The minimum line spacing (S) between the pad-on-pad interconnects may be about 10 micrometers. The minimum line spacing (S) between the pad-on-pad interconnects and the interconnects may be about 10 micrometers. In some implementations, the minimum pitch between two adjacent pad-on-pad interconnects (having two traces between the adjacent pad-on-pad interconnects) configured to couple to a pillar interconnect is about 60 micrometers. For example, the minimum pitch between pad-on-pad interconnects 122f and 122g (shown in FIG. 3) may be about 60 micrometers.

[0019] There are at least several technical advantages over the configuration shown in FIG. 2. First, the pad-on-pad interconnects help reduce the interconnect pitch for easier signal routing without reducing the signal traces, so more interconnects can be provided in a given area. Second, the protrusions of the pad-on-pad interconnects (e.g., 122a) can help limit the solder interconnects from spreading to adjacent traces, thus reducing the risk of shorts. As described further below, the use of a solder resist layer having thinned portions can further reduce the likelihood of shorts due to solder interconnect spreading. Similar technical advantages are seen in other substrates described in this disclosure.

[0020] FIG. 3 illustrates a substrate 302. The substrate 302 is similar to the substrate 102 of FIGS. 1 and 2 and therefore includes similar components as the substrate 102. As illustrated in FIG. 3, the substrate 302 includes a solder resist layer 140 located on a first surface of the substrate 302 (e.g., located on a first surface of at least one dielectric layer 120). The solder resist layer 140 may include a first solder resist layer portion 340a and a second solder resist layer portion 340b. The first solder resist layer portion 340a has a first thickness and the second solder resist layer portion 340b has a second thickness that is less than the first thickness. The second solder resist layer portion 340b may have a second thickness that is greater than a thickness of a second portion (e.g., 223a) of the pad-on-pad interconnect (e.g., 122a, 122b). The second solder resist layer portion 340b may be located between the at least one dielectric layer 120 and the integrated device 103. A second solder resist layer portion 340b may be located over the interconnect 122c and the first portion 222a of the pad-on-pad interconnect 122a.

[0021] 3, the package 300 includes an integrated device 103 and a substrate 302. The integrated device 103 is coupled to a first surface (e.g., a top surface) of the substrate 302. For example, the integrated device 103 is coupled to the substrate 302 through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The integrated device 103 is coupled to a plurality of pad-on-pad interconnects (e.g., 122a) through the plurality of pillar interconnects 130 and a plurality of solder interconnects 132.

[0022] FIG. 4 illustrates a substrate 402. The substrate 402 is similar to the substrates 102 and 302 of FIG. 1 and FIG. 2, and thus includes similar components to the substrates 102 and 302. As illustrated in FIG. 4, the substrate 402 includes a solder resist layer 140 located on a first surface of the substrate 402 (e.g., located on a first surface of at least one dielectric layer 120). The solder resist layer 140 may include a first solder resist layer portion 440a and a second solder resist layer portion 440b. The first solder resist layer portion 440a has a first thickness, and the second solder resist layer portion 440b has a second thickness that is less than the first thickness. The second solder resist layer portion 440b may have a second thickness that is approximately the same as a thickness of a second portion (e.g., 223a) of the pad-on-pad interconnect (e.g., 122a, 122b). The second solder resist layer portion 440b may have a thickness of 10 ... The second solder resist layer portion 440b may be located between the at least one dielectric layer 120 and the integrated device 103. The second solder resist layer portion 440b may be located on top of the interconnect 122c.

[0023] 4, the package 400 includes an integrated device 103 and a substrate 402. The integrated device 103 is coupled to a first surface (e.g., a top surface) of the substrate 402. For example, the integrated device 103 is coupled to the substrate 402 through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The integrated device 103 is coupled to a plurality of pad-on-pad interconnects (e.g., 122a) through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132.

[0024] FIG. 5 illustrates a substrate 502. The substrate 502 is similar to the substrates 102 and 302 of FIGS. 1 and 2, and thus includes similar components to the substrates 102 and 302. As illustrated in FIG. 5, the substrate 502 includes a solder resist layer 140 located on a first surface of the substrate 502 (e.g., located on a first surface of at least one dielectric layer 120). The solder resist layer 140 may include a first solder resist layer portion 540a and a second solder resist layer portion 540b. The first solder resist layer portion 540a has a first thickness, and the second solder resist layer portion 540b has a second thickness that is less than the first thickness. The second solder resist layer portion 540b may have a second thickness that is less than a thickness of a second portion (e.g., 223a) of the pad-on-pad interconnect (e.g., 122a, 122b). The second solder resist layer portion 540b may be located between the at least one dielectric layer 120 and the integrated device 103. The second solder resist layer portion 540b may be located over the interconnect 122c and the first portion 222a of the pad-on-pad interconnect 122a.

[0025] A thinner solder resist layer can be achieved by using a sandblasting process on some of the solder resist layers. Figures 1-5 show pad-on-pad interconnects having an inverted T-shaped vertical cross-section. In some implementations, the pad-on-pad interconnects can have a T-shaped vertical cross-section. Figures 6-9 show substrates including pad-on-pad interconnects having a T-shaped cross-section.

[0026] 5, the package 500 includes an integrated device 103 and a substrate 502. The integrated device 103 is coupled to a first surface (e.g., a top surface) of the substrate 502. For example, the integrated device 103 is coupled to the substrate 502 through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The integrated device 103 is coupled to a plurality of pad-on-pad interconnects (e.g., 122a) through the plurality of pillar interconnects 130 and a plurality of solder interconnects 132.

[0027] Figure 6 illustrates a substrate 602. Substrate 602 is similar to substrate 102 of Figures 1 and 2 and therefore includes similar components as substrate 102. As shown in Figure 6, substrate 602 includes a plurality of pad-on-pad interconnects 122b and 122e. Pad-on-pad interconnect 122e is similar to the pad-on-pad interconnect described in Figures 1 and 2.

[0028] The pad-on-pad interconnect 122e is embedded through the first side of the substrate 102. The pad-on-pad interconnect 122e includes a first portion 222e and a second portion 223e. The first portion 222e may include a first pad, and the second portion 223e may include a second pad. The first pad may be coupled to the second pad. In some implementations, the first portion 222e (e.g., a first pad) and the second portion 223e (e.g., a second pad) may be part of the same pad (e.g., a pad interconnect). In some implementations, there may or may not be an interface between the first portion 222e and the second portion 223e. The first portion 222e is disposed (e.g., embedded) in the at least one dielectric layer 120. The second portion 223e is disposed on the at least one dielectric layer 120. The first portion 222e may include a first width and the second portion 223e may include a second width. The width may include a diameter. The first width may be different from the second width. In FIG. 6, the first width of the first portion 222e is smaller than the second width of the second portion 223e. However, the second width may be smaller than the first width. The second portion 223e may have a thickness of approximately 15 micrometers or less (e.g., 12-15 micrometers). The first pad-on-pad interconnect 122e is coupled to the interconnect 122j. The interconnect 122j is coupled to the first portion 222e. The interconnect 122j may be a trace disposed in the at least one dielectric layer 120.

[0029] The solder resist layer 140 is located on the first surface of the substrate 302 (e.g., on the first surface of at least one dielectric layer 120). The solder resist layer 140 may include a first solder resist layer portion 340a and a second solder resist layer portion 340b. The first solder resist layer portion 340a has a first thickness, and the second solder resist layer portion 340b has a second thickness that is smaller than the first thickness. The second solder resist layer portion 340b may have a second thickness that is larger than a thickness of a second portion (e.g., 223a) of the pad-on-pad interconnect (e.g., 122a, 122b). The second solder resist layer portion 340b may be located between the at least one dielectric layer 120 and the integrated device 103. The second solder resist layer portion 340b may be located on the interconnect 122c and the first portion 222a of the pad-on-pad interconnect 122a.

[0030] 6, the package 600 includes an integrated device 103 and a substrate 602. The integrated device 103 is coupled to a first surface (e.g., a top surface) of the substrate 602. For example, the integrated device 103 is coupled to the substrate 602 through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The integrated device 103 is coupled to a plurality of pad-on-pad interconnects (e.g., 122e) through the plurality of pillar interconnects 130 and a plurality of solder interconnects 132.

[0031] FIG. 7 illustrates a substrate 702. The substrate 702 is similar to the substrate 102 and the substrate 602 of FIG. 1 and FIG. 2, and thus includes similar components to the substrate 102 and the substrate 602. As illustrated in FIG. 7, the substrate 702 includes a solder resist layer 140 located on a first surface of the substrate 702 (e.g., located on a first surface of at least one dielectric layer 120). The solder resist layer 140 may include a first solder resist layer portion 740a and a second solder resist layer portion 740b. The first solder resist layer portion 740a has a first thickness, and the second solder resist layer portion 740b has a second thickness that is less than the first thickness. The second solder resist layer portion 740b may have a second thickness that is greater than a thickness of a second portion (e.g., 223e) of the pad-on-pad interconnect (e.g., 122e, 122b). The second solder resist layer portion 740b may be located between the at least one dielectric layer 120 and the integrated device 103. The second solder resist layer portion 740b may be located over the interconnect 122c and the first portion 222a of the pad-on-pad interconnect 122a.

[0032] 7, the package 700 includes an integrated device 103 and a substrate 702. The integrated device 103 is coupled to a first surface (e.g., a top surface) of the substrate 702. For example, the integrated device 103 is coupled to the substrate 702 through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The integrated device 103 is coupled to a plurality of pad-on-pad interconnects (e.g., 122e) through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132.

[0033] FIG. 8 illustrates a substrate 802. The substrate 802 is similar to the substrate 102 and the substrate 602 of FIG. 1, FIG. 2, and thus includes similar components to the substrates 102 and 602. As illustrated in FIG. 8, the substrate 802 includes a solder resist layer 140 located on a first surface of the substrate 802 (e.g., located on a first surface of at least one dielectric layer 120). The solder resist layer 140 may include a first solder resist layer portion 840a and a second solder resist layer portion 840b. The first solder resist layer portion 840a has a first thickness, and the second solder resist layer portion 840b has a second thickness that is less than the first thickness. The second solder resist layer portion 840b may have a second thickness that is approximately the same as a thickness of a second portion (e.g., 223e) of the pad-on-pad interconnect (e.g., 122e, 122b). The second solder resist layer portion 840b may be located between the at least one dielectric layer 120 and the integrated device 103. The second solder resist layer portion 840b may be located over the interconnect 122c.

[0034] 8, the package 800 includes an integrated device 103 and a substrate 802. The integrated device 103 is coupled to a first surface (e.g., a top surface) of the substrate 802. For example, the integrated device 103 is coupled to the substrate 802 through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The integrated device 103 is coupled to a plurality of pad-on-pad interconnects (e.g., 122e) through the plurality of pillar interconnects 130 and a plurality of solder interconnects 132.

[0035] FIG. 9 illustrates a substrate 902. The substrate 902 is similar to the substrate 102 and the substrate 602 of FIG. 1, FIG. 2, and thus includes similar components to the substrates 102 and 602. As illustrated in FIG. 9, the substrate 902 includes a solder resist layer 140 located on a first surface of the substrate 902 (e.g., located on a first surface of at least one dielectric layer 120). The solder resist layer 140 may include a first solder resist layer portion 940a and a second solder resist layer portion 940b. The first solder resist layer portion 940a has a first thickness, and the second solder resist layer portion 940b has a second thickness that is less than the first thickness. The second solder resist layer portion 940b may have a second thickness that is less than a thickness of a second portion (e.g., 223e) of the pad-on-pad interconnect (e.g., 122e, 122b). The second solder resist layer portion 940b may be located between the at least one dielectric layer 120 and the integrated device 103. The second solder resist layer portion 940b may be located over the interconnect 122c and the first portion 222a of the pad-on-pad interconnect 122a.

[0036] A thinner solder resist layer can be achieved by using a sandblasting process on some of the solder resist layers.

[0037] 9, the package 900 includes an integrated device 103 and a substrate 902. The integrated device 103 is coupled to a first surface (e.g., a top surface) of the substrate 902. For example, the integrated device 103 is coupled to the substrate 902 through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The integrated device 103 is coupled to a plurality of pad-on-pad interconnects (e.g., 122e) through the plurality of pillar interconnects 130 and a plurality of solder interconnects 132.

[0038] The integrated device (e.g., 103) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 103) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0039] The plurality of pad-on-pad interconnects (e.g., 122a, 122e) may have a first minimum pitch and a first minimum linewidth (L) and spacing (S) (e.g., L / S). In some implementations, the first minimum linewidth and spacing (L / S) for the plurality of pad-on-pad interconnects is approximately 10 / 10 micrometers (μm) (e.g., a minimum linewidth of approximately 10 micrometers (μm), a minimum spacing of approximately 10 micrometers (μm)).

[0040] Various implementations may use different substrates. The substrate (e.g., 102, 302, 402, 502, 602, 702, 802, 902) may include an embedded trace substrate (ETS). The substrate may have a variety of metal layers (e.g., 10 metal layers). At least one dielectric layer 120 may include a prepreg. An example of manufacturing the substrate is further described below in FIGS. 10A-10D. As further described below, in some implementations, the substrate 202 may be manufactured using a modified semi-adaptive process (mSAP) or a semi-adaptive process (SAP).

[0041] Exemplary sequence for manufacturing a substrate including pad-on-pad interconnects In some implementations, manufacturing a substrate includes several processes. Figures 10A-10D show an example sequence for providing or manufacturing a substrate. In some implementations, the sequence of Figures 10A-10D may be used to provide or manufacture substrate 302 of Figure 3. However, the process of Figures 10A-10D may be used to manufacture any of the substrates described in this disclosure (e.g., 102, 402, 502, 602, 702, 802, 902).

[0042] It should be noted that the sequences of Figures 10A-10D may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure.

[0043] Stage 1, as shown in FIG. 10A, illustrates the state after the core layer 1000 is prepared. The core layer 1000 includes a metal layer 1001. The metal layer 1001 may include a seed layer (e.g., a copper seed layer). Another metal layer may be placed on the other side of the core layer. Note that the following process is described through a manufacturing process that forms interconnects and a dielectric layer on one side of the core layer. However, in some implementations, the interconnects and the dielectric layer may be formed on both sides of the core layer 1000. The core layer 1000 is an example of a carrier used as a base. In some implementations, other carriers such as glass or quartz may be used.

[0044] Stage 2 shows the state after interconnects 1002 have been formed over the core layer 1000 and the metal layer 1001. The interconnects 1002 may be patterned from the metal layer. Plating and etching processes may be used to form the metal layer and the interconnects.

[0045] Stage 3 shows the state after a dielectric layer 1020 is formed over the core layer 1000 and the interconnects 1002. The dielectric layer 1020 may include polyimide, although various implementations may use different materials for the dielectric layer.

[0046] Stage 4 shows the state after a plurality of cavities 1010 have been formed in the dielectric layer 1020. The plurality of cavities 1010 may be formed using an etching process (eg, a photoetching process) or a laser process.

[0047] Stage 5 shows the state after interconnects 1012 have been formed in and on the dielectric layer 1020. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0048] Stage 6 shows the state after another dielectric layer 1022 is formed over dielectric layer 1020. Dielectric layer 1022 can be the same material as dielectric layer 1020. However, various implementations may use different materials for the dielectric layers.

[0049] Stage 7, as shown in Figure 10B, illustrates the state after a plurality of cavities 1030 have been formed in the dielectric layer 1022. An etching process or a laser process may be used to form the cavities 1030.

[0050] Stage 8 shows the state after interconnects 1014 have been formed in and on the dielectric layer 1022. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0051] Stage 9 shows the state after another dielectric layer 1024 is formed over dielectric layer 1022. Dielectric layer 1024 can be the same material as dielectric layer 1020. However, various implementations may use different materials for the dielectric layers.

[0052] Stage 10 is shown after a number of cavities 1040 have been formed in the dielectric layer 1024. An etching process or a laser process may be used to form the cavities 1040.

[0053] Stage 11, as shown in Figure 10C, depicts the state after interconnects 1016 have been formed in and on dielectric layer 1024. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0054] Some or all of the interconnects 1002, 1012, 1014 and / or 1016 may define the plurality of interconnects 122 of the substrate 102. The dielectric layers 1020, 1022, 1024 may be represented by at least one dielectric layer 120.

[0055] Stage 12 shows the state after the core layer 1000 has been decoupled (e.g., stripped, polished away) from the dielectric layer 120, leaving the substrate 102 with the metal layer 1001. The metal layer 1001 may include a seed layer.

[0056] Stage 13 shows the state after metal layer 1001 has been patterned to form pad-on-pad. For example, metal layer 1001 may be patterned to form portions 223a and 223b as described in FIG. 3. Portions 223a and 223b may protrude from at least one dielectric layer 120. An etching process may be used to form portions 223a and 223b. Portions 223a and 223b may be part of multiple pad-on-pad interconnects.

[0057] Stage 14 depicts the state after solder resist layer 140 and solder resist layer 142 are formed on substrate 102, as shown in FIG. 10D. Solder resist layer 140 is formed on a first side of dielectric layer 120 (e.g., a first side of the substrate). Solder resist layer 142 is formed on a second side of dielectric layer 120 (e.g., a second side of the substrate). A deposition process may be used to form solder resist layer 140 and solder resist layer 142. Solder resist layer 140 and solder resist layer 142 may be part of substrate 102.

[0058] Stage 15 shows a state after a portion of the solder resist layer 140 has been thinned. After thinning, the solder resist layer 140 includes a solder resist layer portion 340a and a solder resist layer portion 340b. The solder resist layer portion 340a has a first thickness and the solder resist layer portion 340b has a second thickness different from the first thickness. A sandblasting process may be used to form the thinned solder resist layer portions. For example, the portion of the solder resist layer to be thinned may be exposed to a sandblasting process. Various implementations may have different thicknesses for the solder resist layer portion 340b. Stage 15 shows a substrate 302 including pad-on-pad interconnects (e.g., 122a, 122b) and a solder resist layer 140 having various thicknesses.

[0059] Various implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0060] Illustrative Flow Diagram of a Method for Manufacturing a Substrate Including Pad-on-Pad Interconnects In some implementations, manufacturing a substrate includes several processes. FIG. 11 shows an example flow diagram of a method 1100 for providing or manufacturing a substrate. In some implementations, the method 1100 of FIG. 11 can be used to provide or manufacture the substrate of FIG. 1. For example, the method of FIG. 11 can be used to manufacture the substrate 102. The method 1100 of FIG. 11 is used to explain the steps of manufacturing the substrate 302.

[0061] 11 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0062] The method provides (at 1105) a core layer 1000 including a metal layer 1001. Various implementations may use different materials for the core layer. Note that the core layer is one example of a carrier that may be used. However, other carriers may be used. For example, the carrier may include a substrate, glass, quartz, and / or carrier tape. Stage 1 of FIG. 10A illustrates an example of a state after a core layer having a metal layer is provided.

[0063] The method forms (at 1110) a metal layer over the core layer 1000 and the metal layer 1001. The metal layer may be patterned to form the interconnects 1002. A plating process may be used to form the metal layer and the interconnects. Stage 2 of Figure 10A illustrates an example of a state after the metal layer and the interconnects 1002 have been formed.

[0064] The method forms (at 1115) a dielectric layer 1020 over the core layer 1000, the metal layer 1001, and the interconnects 1002. The dielectric layer 1020 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1010) in the dielectric layer 1020. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Stages 3-4 of FIG. 10A show and describe one example of forming the dielectric layer and the cavities in the dielectric layer.

[0065] The method forms (at 1120) interconnects in and on the dielectric layer. For example, interconnects 1012 may be formed in and on dielectric layer 1020. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Stage 5 of FIG. 10A illustrates and describes one example of forming interconnects in and on a dielectric layer.

[0066] The method forms (at 1125) a dielectric layer 1022 over the dielectric layer 1020 and the interconnects. The dielectric layer 1022 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1030) in the dielectric layer 1022. The plurality of cavities may be formed using an etching process or a laser process. Stages 6-7 of Figures 10A-10B illustrate forming the dielectric layer and the cavities in the dielectric layer.

[0067] The method forms (at 1130) interconnects in and / or on the dielectric layer. For example, interconnects 1014 may be formed. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and in the dielectric layer. Stage 8 of FIG. 10B illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0068] The method may form additional dielectric layers and additional interconnects as described at 1125 and 1130. Stages 9-11 of Figures 10B-10C show and describe one example of forming additional interconnects in and on a dielectric layer.

[0069] Once all the dielectric layers and additional interconnects have been formed, the method may decouple (e.g., strip or polish away) the core layer (e.g., 1000) from the dielectric layer 1020, leaving (at 1135) the substrate with the metal layer 1001. The method may also form pad-on-pad interconnects by patterning (at 1135) the metal layer 1001 into a pad. An etching process may be used to pattern the metal layer 1001. Stage 12 of FIG. 10C illustrates and describes an example of the state after decoupling the core layer. Stage 13 of FIG. 10C illustrates and describes an example of patterning the metal layer to form a pad-on-pad.

[0070] The method may include forming (at 1140) a solder resist layer (e.g., 140, 142) on the substrate. A deposition process may be used to form the solder resist layer. Stage 14 of Figure 10D illustrates an example of a state after forming the solder resist layer.

[0071] The method may thin (at 1140) portions of the solder resist layer. For example, the solder resist layer 140 may be thinned in selected locations such that the solder resist layer 140 includes a first solder resist layer portion 340a and a second solder resist layer portion 340b. The first solder resist layer portion 340a may have a first thickness and the second solder resist layer portion 340b may have a second thickness that is less than the first thickness. How much the solder resist layer is thinned may vary with different implementations. In some implementations, a sandblasting process may be used to thin portions of the solder resist layer. Stage 15 of FIG. 10D illustrates and describes an example of a state after the solder resist layer has been thinned.

[0072] Various implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0073] Exemplary sequence for manufacturing a package including a substrate including pad-on-pad interconnects 12 illustrates an example sequence for providing or manufacturing a package including a substrate including pad-on-pad interconnects. In some implementations, the sequence of FIG. 12 can be used to provide or manufacture package 100 including a substrate including pad-on-pad interconnects of FIG. 1 or any of the packages described in this disclosure (e.g., 300, 400, 500, 600, 700, 800, 900).

[0074] It should be noted that the sequence of FIG. 12 may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure. The sequence of FIG. 12 may be used to manufacture one package or several packages simultaneously (as part of a wafer).

[0075] As shown in FIG. 12, stage 1 shows a state after the substrate 102 is prepared. The substrate 102 may be provided by a supplier or may be manufactured. A process similar to the process shown in FIGS. 10A-10D may be used to manufacture the substrate 102. However, various implementations may use different processes to manufacture the substrate 102. Examples of processes that may be used to manufacture the substrate 102 include semi-additive process (SAP) and modified semi-additive process (mSAP). The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 may include pad-on-pad interconnects (e.g., 122a, 122b). The substrate 102 may include an embedded trace substrate (ETS). In some implementations, the at least one dielectric layer 120 may include a prepreg layer.

[0076] Stage 2 shows the state after the integrated device 103 is bonded to a first surface (e.g., top surface) of the substrate 102. The integrated device 103 may be bonded to the substrate 102 through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The plurality of pillar interconnects 130 and a plurality of solder interconnects 132 are bonded to a plurality of pad-on-pad interconnects (e.g., 122a). A solder reflow process may be used to bond the integrated device 103 to the plurality of pad-on-pad interconnects through the plurality of pillar interconnects 130 and a plurality of solder interconnects 132.

[0077] Stage 3 shows the state after the plurality of solder interconnects 150 are bonded to the substrate 102. The plurality of solder interconnects 150 may be bonded to interconnects (e.g., 122d) located on the second side of the at least one dielectric layer 120. A solder reflow process may be used to bond the plurality of solder interconnects 150 to the substrate 102. Stage 3 may show the package 100. The packages (e.g., 100) described in this disclosure may be manufactured one at a time or may be manufactured together as part of one or more wafers and then singulated into individual packages.

[0078] Illustrative flow diagram of a method for manufacturing a package including a substrate including pad-on-pad interconnects In some implementations, manufacturing a package including a substrate including pad-on-pad interconnects includes several processes. Figure 13 shows an example flow diagram of a method 1300 for providing or manufacturing a package including a substrate including pad-on-pad interconnects. In some implementations, the method 1300 of Figure 13 may be used to provide or manufacture the package 100 of Figure 1 described in this disclosure. However, the method 1300 may be used to provide or manufacture any of the packages described in this disclosure (e.g., 300, 400, 500, 600, 700, 800, 900).

[0079] 13 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing a package that includes a substrate that includes pad-on-pad interconnects. In some implementations, the order of the processes may be changed or modified.

[0080] The method provides (at 1305) a substrate (e.g., 202) having pad-on-pad interconnects. The substrate 102 may be provided by a supplier or may be manufactured. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 may include pad-on-pad interconnects. The substrate 102 may include an embedded trace substrate (ETS). In some implementations, the at least one dielectric layer 120 may include a prepreg layer. Different implementations may have different substrates. A process similar to that shown in FIGS. 10A-10D may be used to manufacture the substrate 102. However, different implementations may use different processes to manufacture the substrate 102. Stage 1 of FIG. 12 illustrates an example of providing a substrate having pad-on-pad interconnects.

[0081] The method includes (at 1310) bonding at least one integrated device (e.g., 103) to a first side of a substrate (e.g., 102). For example, the integrated device 103 may be bonded to the substrate 102 through a plurality of pillar interconnects 130 and a plurality of solder interconnects 132. The plurality of pillar interconnects 130 and a plurality of solder interconnects 132 are bonded to a plurality of pad-on-pad interconnects (e.g., 122a). A solder reflow process may be used to bond the integrated device 103 to the plurality of pad-on-pad interconnects through the plurality of pillar interconnects 130 and a plurality of solder interconnects 132. Stage 2 of FIG. 12 illustrates and describes an example of an integrated device bonded to a substrate.

[0082] The method includes (at 1315) bonding the plurality of solder interconnects (e.g., 150) to the second side of the substrate (e.g., 102). A solder reflow solder process may be used to bond the plurality of solder interconnects to the substrate. Stage 3 is illustrated and described with an example of bonding the solder interconnects to the substrate.

[0083] Exemplary Electronic Devices FIG. 14 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1402, a laptop computer device 1404, a fixed location terminal device 1406, a wearable device 1408, or an automobile 1410 may include a device 1400 as described herein. The device 1400 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1402, 1404, 1406, and 1408 and the vehicle 1410 illustrated in FIG. 14 are merely examples. Other electronic devices may also feature device 1400, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0084] One or more of the components, processes, features, and / or functions shown in Figures 1-9, 10A-10D, and / or 11-14 may be rearranged and / or combined into a single component, process, feature, or function, or may be combined into several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from the present disclosure. It is also noted that Figures 1-9, 10A-10D, and / or 11-14 and corresponding descriptions thereof in the present disclosure are not limited to dies and / or ICs. In some implementations, Figures 1-9, 10A-10D, and / or 11-14 and corresponding descriptions thereof may be used to manufacture, fabricate, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0085] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some examples, the figures may not be to scale. In some examples, for clarity, not all components and / or parts are shown. In some examples, the positions, locations, sizes and / or shapes of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0086] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, object A and object C may still be considered to be coupled to each other even if they do not physically contact each other directly. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not have an electric current traveling between the two objects. The use of the terms "first", "second", "third" and "fourth" (and / or more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The term "encapsulate" means that an object may partially encapsulate or fully encapsulate another object. The terms "top" and "bottom" are arbitrary. A component placed on top may be placed on top of a component placed on the bottom. A top component may be considered a bottom component and vice versa. As described in this disclosure, a first component placed "on" a second component may mean that the first component is placed above or below the second component, depending on how bottom or top is arbitrarily defined.In another example, a first component may be disposed over (e.g., above) a first surface of a second component, and a third component may be disposed over (e.g., below) a second surface of the second component, the second surface facing the first surface. It is further noted that the term "over" as used herein in the context of one component being disposed over another component may be used to mean a component that is disposed on and / or within (e.g., disposed on a surface of or embedded in) the other component. Thus, for example, a first component disposed over a second component may mean (1) that the first component is disposed over, but not in direct contact with, the second component, (2) that the first component is disposed on (e.g., on a surface of) the second component, and / or (3) that the first component is disposed within (e.g., embedded in) the second component. A first component that is located "in" a second component may be located partially within the second component or may be located completely within the second component. As used in this disclosure, the term "about "the value of X"" or "approximately the value of X" means within 10 percent of the "value of X". For example, a value of about 1 or approximately 1 means a value in the range of 0.9 to 1.1.

[0087] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Various implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the interconnects.

[0088] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process is terminated when its operations are completed.

[0089] In the following, further examples are described to facilitate understanding of the invention.

[0090] Aspect 1: A package including a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects including a plurality of pad-on-pad interconnects. The plurality of pad-on-pad interconnects are embedded through a first side of the substrate.

[0091] Aspect 2: The package of Aspect 1, wherein the plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect including a first pad and a second pad coupled to the first pad.

[0092] Aspect 3: The package of aspect 2, wherein the first pad has a first width and the second pad has a second width.

[0093] Aspect 4: The package of aspect 3, wherein the first width is different from the second width.

[0094] Aspect 5: The package of aspects 2-4, wherein the second pad is disposed within the at least one dielectric layer and the first pad is disposed on a surface of the at least one dielectric layer.

[0095] Embodiment 6: The package of embodiments 2 to 5, wherein the first pad and the second pad are part of the same pad.

[0096] Example 7: The package of Examples 2 to 6, wherein the second pad has a thickness of 15 micrometers or less.

[0097] Embodiment 8: The package of embodiments 2-7, wherein the second pad includes a seed layer.

[0098] Example 9: The package of Examples 1-8, wherein the plurality of interconnects includes a plurality of surface interconnects disposed on the second side of the substrate.

[0099] Embodiment 10: The package of embodiments 1 to 9, wherein the integrated device is coupled to a plurality of pad-on-pad interconnects of the substrate.

[0100] Aspect 11: The package of aspects 1-10, wherein the plurality of pad-on-pad interconnects comprises a minimum width of 10 micrometers and a minimum spacing of 10 micrometers.

[0101] Example 12: The package of Examples 1 to 11, wherein the minimum spacing between the pad-on-pad interconnect and the interconnect is 10 micrometers.

[0102] Example 13: The package of Examples 1-12, further comprising a solder resist layer disposed on the first surface of the substrate.

[0103] Aspect 14: The package of aspect 13, wherein the solder resist layer includes a first solder resist layer portion having a first thickness and a second solder resist layer portion having a second thickness less than the first thickness.

[0104] Aspect 15: The package of aspect 14, wherein the second solder resist layer portion is located between the at least one dielectric layer and the integrated device.

[0105] Aspect 16: An apparatus comprising: a substrate including at least one dielectric layer and a plurality of interconnects including a plurality of pad-on-pad interconnects, the plurality of pad-on-pad interconnects being embedded through a first surface of the substrate.

[0106] Example 17: The apparatus of Example 16, wherein the plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect including a first pad and a second pad coupled to the first pad.

[0107] Example 18: The apparatus of Example 17, wherein the first pad has a first width and the second pad has a second width.

[0108] Example 19: The apparatus of Example 18, wherein the first width is different from the second width.

[0109] Example 20: The apparatus of Examples 17-19, wherein the second pad is disposed within the at least one dielectric layer and the first pad is disposed on a surface of the at least one dielectric layer.

[0110] Embodiment 21: The device of embodiments 17 to 20, wherein the first pad and the second pad are part of the same pad.

[0111] Example 22: The device of Examples 16-21, wherein the plurality of interconnects comprises a plurality of surface interconnects disposed on the second side of the substrate.

[0112] Aspect 23: The apparatus of aspects 16 to 22, wherein the apparatus comprises a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0113] A method for manufacturing a package, the method comprising providing a substrate including at least one dielectric layer and a plurality of interconnects including a plurality of pad-on-pad interconnects embedded through a first side of the substrate, the plurality of pad-on-pad interconnects being embedded through a first side of the substrate, and bonding an integrated device to the substrate.

[0114] Example 25: The method of example 24, wherein the plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect including a first pad and a second pad coupled to the first pad.

[0115] Example 26: The method of Example 25, wherein the first pad has a first width and the second pad has a second width.

[0116] Example 27: The method of Example 26, wherein the first width is different from the second width.

[0117] Example 28: The method of Examples 25 to 27, wherein the second pad is disposed in the at least one dielectric layer and the first pad is disposed on a surface of the at least one dielectric layer.

[0118] Embodiment 29: The method of embodiments 25 to 28, wherein the first pad and the second pad are part of the same pad.

[0119] Example 30: The method of Examples 24-29, wherein the plurality of interconnects comprises a plurality of surface interconnects disposed on the second side of the substrate.

[0120] Various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and is not intended to limit the scope of the claims. Thus, the present teachings can be easily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0121] 100 packages 102 Substrate 103 Integrated Devices 120 Dielectric layer 122 Interconnection 122a First pad-on-pad interconnect 122b Second pad-on-pad interconnect 122c Pad-on-Pad Interconnect 122d Interconnect 122e first pad-on-pad interconnect 122f Pad-on-Pad Interconnect 122g pad-on-pad interconnect 122h Interconnect 122i Interconnect 122j Interconnect 130 Pillar Interconnect 132 Solder Interconnects 140 Solder resist layer 142 Solder resist layer 150 Solder Interconnects 202 Substrate 222a: First portion of first pad-on-pad interconnect 122a 222b First portion of second pad-on-pad interconnect 122b 223a: second portion of first pad-on-pad interconnect 122a 223b second portion of second pad-on-pad interconnect 122b 300 packages 302 Substrate 340a First solder resist layer portion 340b second solder resist layer portion 400 packages 402 Substrate 440a First solder resist layer portion 440b Second solder resist layer portion 500 packages 502 Substrate 540a First solder resist layer portion 540b Second solder resist layer portion 600 packages 602 Substrate 700 packages 700 packages 702 Substrate 740a First solder resist layer portion 740b Second solder resist layer portion 800 packages 802 Substrate 840a First solder resist layer portion 840b Second solder resist layer portion 900 Packages 902 Substrate 940a First solder resist layer portion 940b Second solder resist layer portion 1000 Core Layer 1001 Metal layer 1002 Interconnection 1010 Cavity 1012 Interconnection Cormorant 1014 Interconnection 1016 Interconnection 1020 Dielectric layer 1022 Dielectric layer 1024 Dielectric layer 1030 Cavity 1040 Cavity 1100 methods 1300 methods 1400 devices 1402 Mobile Phone Devices 1404 Laptop Computer Device 1406 Fixed Location Terminal Device 1408 Wearable Devices 1410 Automobiles

Claims

1. A substrate, At least one dielectric layer; and A plurality of interconnects including a plurality of pad-on-pad interconnects, the plurality of pad-on-pad interconnects being embedded through a first surface of the substrate. A substrate comprising: an integrated device coupled to the substrate through a first one of the plurality of pad-on-pad interconnects and a second one of the plurality of pad-on-pad interconnects; A package comprising: The substrate is traces embedded in the first surface of the substrate forming a planar common surface between the first pad-on-pad interconnect and the second pad-on-pad interconnect; a solder resist layer at least partially overlying the first surface of the substrate, a first solder resist layer portion having a first thickness and located adjacent to the second pad-on-pad interconnect; a second solder resist layer portion having a second thickness and positioned over the trace, the second thickness being less than the first thickness; the solder resist layer comprising: The package further includes:

2. 2. The package of claim 1, wherein the first pad-on-pad interconnect includes a first pad and a second pad coupled to the first pad.

3. 3. The package of claim 2, wherein the first pad has a first width and the second pad has a second width.

4. The package of claim 3 , wherein the first width is different from the second width.

5. the second pad is disposed within the at least one dielectric layer; The package of claim 2 , wherein the first pad is located on a surface of the at least one dielectric layer.

6. The package of claim 2 , wherein the first pad and the second pad are part of the same pad.

7. The package of claim 2 , wherein the second pad has a thickness of 15 micrometers or less.

8. The package of claim 2 , wherein the second pad comprises a seed layer.

9. The package of claim 1 , wherein the plurality of interconnects comprises a plurality of surface interconnects disposed on a second side of the substrate.

10. The package of claim 1 , wherein the integrated device is coupled to the plurality of pad-on-pad interconnects of the substrate.

11. 2. The package of claim 1, wherein the plurality of pad-on-pad interconnects include a minimum width of 10 micrometers and a minimum spacing of 10 micrometers.

12. 10. The package of claim 1, wherein the minimum spacing between a pad-on-pad interconnect and an interconnect is 10 micrometers.

13. The package of claim 1 , wherein the second solder resist layer portion is located between the at least one dielectric layer and the integrated device.

14. 1. A method for manufacturing a package, comprising: Providing a substrate, At least one dielectric layer; and A plurality of interconnects including a plurality of pad-on-pad interconnects, the plurality of pad-on-pad interconnects being embedded through a first surface of a substrate. Providing a substrate comprising: coupling an integrated device to the substrate through a first pad-on-pad interconnect of the plurality of pad-on-pad interconnects and a second pad-on-pad interconnect of the plurality of pad-on-pad interconnects; The substrate is traces embedded in the first surface of the substrate forming a planar common surface between the first pad-on-pad interconnect and the second pad-on-pad interconnect; a solder resist layer at least partially overlying the first surface of the substrate, a first solder resist layer portion having a first thickness and located adjacent to the second pad-on-pad interconnect; a second solder resist layer portion having a second thickness and positioned over the trace, the second thickness being less than the first thickness; A solder resist layer comprising: The method further comprising:

15. The method of claim 14 , wherein the plurality of interconnects comprises a plurality of surface interconnects disposed on a second side of the substrate.

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