Method for forming a FinFET structure

Abstract

A method for fabricating a FET semiconductor structure includes providing a substrate with at least one source / drain contact of at least one FET, the at least one source / drain contact being formed adjacent to a dummy gate of the at least one FET. A TiSi2 film having a C54 structure is selectively deposited on a vertical sidewall of a gate spacer between the at least one source / drain contact and the dummy gate, directly on and completely covering the at least one source / drain contact. The dummy gate is replaced with a replacement metal gate.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This disclosure claims the benefit of U.S. Provisional Patent Application No. 63 / 179,092, filed April 23, 2021, the entire contents of which are incorporated by reference herein.

[0002] The present invention relates generally to the field of semiconductors, and more particularly to methods for fabricating FET semiconductor devices. [Background technology]

[0003] Advances in semiconductor technology depend on continuous improvements in manufacturing fabrication techniques. Innovations in semiconductor technology have led to the introduction of new types of structures, such as Fin Field Effect Transistor (FinFET) devices and stacked structures (e.g., 3D NAND devices). The inventors recognized that in traditional FinFET process flows, source / drain damage, etch stop layer residues formed on the source / drain, and thermal budget limitations for forming metal gates may result in poor quality contacts on the source / drain, and uncontrolled variations in device electrical performance. In addition, the inventors recognized that with aggressive device scaling at 5nm and beyond nodes, low contact resistance requirements using traditional integration methods cannot meet device performance requirements due to the ever-decreasing contact area. Summary of the Invention [Means for solving the problem]

[0004] The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices.

[0005] Aspect (1) provides a method for manufacturing a FET semiconductor structure, the method comprising providing a substrate including at least one source / drain contact of at least one FET, the at least one source / drain contact being formed adjacent to a dummy gate of the at least one FET. A TiSi2 film having a C54 structure is selectively deposited on a vertical sidewall of a gate spacer between the at least one source / drain contact and the dummy gate, directly on and completely covering the at least one source / drain contact. The dummy gate is then replaced with a replacement metal gate.

[0006] An embodiment (2) includes the method of embodiment (1), wherein selectively depositing a TiSi2 film is performed before replacing the dummy gate with a replacement metal gate.

[0007] An embodiment (3) includes the method of embodiment (1), wherein selectively depositing a TiSi2 film includes exposing the substrate to a process gas including a titanium-containing precursor gas and a silicon-containing precursor gas.

[0008] An embodiment (4) includes the method of embodiment (3), wherein the titanium-containing precursor gas includes TiCl4.

[0009] Example (5) includes the method of example (3), wherein the silicon-containing precursor gas includes at least one of SiH 4 , SiH 2 Cl 2 , SiHCl 3 , and SiCl 4 .

[0010] An embodiment (6) includes the method of embodiment (3), wherein the process gas includes TiCl4 and SiH4.

[0011] Example (7) includes the method of example (3), wherein the process gas further includes H2 gas.

[0012] Example (8) includes the method of example (3), further including maintaining the gas pressure at about 1 mTorr to about 50 mTorr or about 5 mTorr to about 20 mTorr and maintaining the substrate temperature at about 700°C to about 800°C.

[0013] Example (9) includes the method of example (1), further including, after depositing the TiSi2 film, depositing an etch stop layer over the at least one source / drain contact, the dummy gate, the gate spacer, and the TiSi2 film.

[0014] An embodiment (10) includes the method of embodiment (9), further including depositing a dielectric over the etch stop layer.

[0015] Example (11) includes the method of example (1), further including cleaning the at least one source / drain contact using a cleaning process prior to selectively depositing the TiSi2 film.

[0016] Example (12) includes the method of example (11), wherein the cleaning process includes exposing the source / drain contacts to hot H gas at a gas pressure of about 100 mTorr to about 700 mTorr, at a substrate temperature of about 600° C. to about 800° C., for a period of about 10 seconds to about 60 seconds.

[0017] Example (13) includes the method of example (11), wherein the cleaning process includes exposing the source / drain contacts to thermal NH3 and HF gas at a gas pressure of about 1 Torr to about 3 Torr, at a substrate temperature of about 35° C. to about 100° C., for a period of about 10 seconds to about 60 seconds.

[0018] Example (14) includes the method of example (11), wherein the cleaning process includes exposing the source / drain contacts to thermal NF3 and H2 gas at a gas pressure of about 1 Torr to about 3 Torr, at a substrate temperature of about 20° C. to about 100° C., for a period of about 10 seconds to about 60 seconds.

[0019] An embodiment (15) includes the method of embodiment (1), wherein an annealing step is not performed between the selectively depositing step and the replacing step.

[0020] An embodiment (16) includes the method of embodiment (1), further including an annealing step performed between the selectively depositing step and the replacing step.

[0021] Embodiment (17) includes a FET semiconductor device including a substrate including at least one source / drain contact of at least one FET, the at least one source / drain contact being formed adjacent to a gate of the at least one FET and including an upper portion that is line-of-sight from the top of the substrate and a lower portion that is line-of-sight from the bottom of the substrate. A TiSi2 film having a C54 structure conformally covers both the top and bottom of the at least one source / drain contact.

[0022] An embodiment (18) includes the FET of embodiment (17), wherein the source / drain contacts include epitaxial Si.

[0023] Example (19) includes the FET of example (17), further including a gate spacer between the at least one source / drain contact and the gate.

[0024] An embodiment (20) includes the FET of embodiment (19), wherein the gate spacer comprises SiN.

[0025] It should be noted that this "Summary" section does not specify all embodiments and / or inherently novel aspects of the disclosure or the claimed disclosure. Rather, the "Summary" merely provides a preliminary description of various embodiments and corresponding novelties over the prior art. For additional details and / or anticipated aspects of the disclosure and embodiments, the reader is directed to the "Description of Embodiments" section of the present disclosure and corresponding figures, which are discussed further below.

[0026] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard industry practice, various features have not been drawn to scale, and in fact, dimensions of various features may be expanded or reduced for clarity of discussion. [Brief description of the drawings]

[0027] [Figure 1] 1 illustrates a comparison of a conventional method for FinFET fabrication with a FinFET fabrication method according to an exemplary embodiment of the present disclosure. [Diagram 2] 1 shows a schematic diagram of a FinFET structure according to an exemplary embodiment of the present disclosure. [Fig. 3A-3J] 1 illustrates various process steps of a conventional method for manufacturing FinFETs. [Fig. 4A-4H] 1 illustrates various process steps of a novel method for fabricating a FinFET according to an exemplary embodiment of the present disclosure. [Figure 5A-5B] 1 illustrates a comparison of a conventional FinFET structure with a FinFET structure according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. It should be understood that these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact with each other, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact with each other. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purposes of brevity and clarity and does not in itself address the relationship between the various embodiments and / or configurations discussed. Furthermore, for ease of explanation, spatially relative terms such as "top," "bottom," "lower," "below," "lower," "lower," "upper," "above," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein similarly interpreted accordingly.

[0029] The present invention will be described in terms of various exemplary processes for fabricating FET semiconductor structures on a circuit supporting substrate. These fabrication processes may be used to fabricate planar FET semiconductor devices, FinFET semiconductor devices, or both types of semiconductor devices on the circuit supporting substrate.

[0030] FIG. 1 illustrates a process flow for a conventional gate-first FinFET fabrication process 300 compared to a FinFET fabrication method 400 according to an embodiment of the present invention. The conventional FinFET fabrication is represented by steps 3A-3J and includes the formation of a replacement metal gate (RMG) in step 3D, prior to the formation of a titanium silicide (TiSi2) film on the source / drain contacts in steps 3G-3I. The formation of the TiSi2 film is achieved by non-selective physical vapor deposition (PVD) of Ti metal on the epitaxial Si of the source / drain contacts in step 3G, followed by deposition of a TiN liner on the Ti metal in step 3H, and then performing an anneal in step 3I to react the Ti metal with the Si in the source / drain contacts to form a low-resistance titanium silicide (i.e., TiSi2 with a C54 structure). Ti metal PVD is a line-of-site deposition method, and therefore Ti metal deposition cannot be used for wrap-around deposition on the source / drain contacts. Additional details relating to conventional FinFETs are discussed with reference to correspondingly numbered Figures 3A-3J.

[0031] Conventional FinFET fabrication methods have several potentially troublesome challenges that can lead to poor quality TiSi2 formation, such as residual contact etch stop layer (CESL) SiN, damaged epitaxial Si after reactive ion etching (RIE), reduced metal contact area, and partial formation of TiSi2 by thermal annealing due to the thermal budget of the (WF) material.

[0032] In contrast, embodiments of the present disclosure provide a FinFET fabrication method in which the RMG is formed after a titanium silicide film is formed on the source / drain contacts, as shown in exemplary process steps 4A-4H of FIG. 1. Additional details related to these steps are discussed with reference to correspondingly numbered FIGS. 4A-4H. The titanium silicide can be deposited as a fully formed TiSi2 film having a C54 structure, whereby a subsequent anneal is optional. The titanium silicide can be selectively deposited on the source / drain contacts by, for example, exposing the substrate to a process gas that includes a titanium-containing precursor gas and a silicon-containing precursor gas. For example, the process gas can include SiH4 and TiCl4.

[0033] The disclosed embodiments provide a one-step, wrap-around TiSi2 film formation on the source / drain contacts with significantly improved interface quality compared to conventional methods. The TiSi2 film is formed completely with low electrical resistivity and does not rely on Si diffusion from the source / drain contacts. The method enables a novel integrated process flow that eliminates damage to epitaxial Si source / drain contacts, eliminates the formation of etch stop layer residues on the source / drain contacts, and reduces source / drain contact resistance.

[0034] FIG. 2 shows a schematic of a FinFET. The FinFET includes a fin 201, an epitaxial Si source / drain (S / D) contact 203 on the fin 201, a gate dielectric 205 on the fin 201, and a metal gate 207 on the gate dielectric 205. Fin cross section A-A' is shown across the epitaxial Si source / drain 203 and fin 201, and gate cross section B-B' is shown along the length of the fin 201. Fin and gate cross sections across the FinFET are shown in FIGS. 3A-3J and 4A-4H and are described later in this specification.

[0035] 3A-3J are schematic diagrams illustrating a conventional method of forming a FinFET by a gate-first process. Each of FIGS. 3A-3J includes a top gate cross-sectional view, such as B-B' in FIG. 2, and a bottom fin cross-sectional view, such as A-A' in FIG. 2. Unlike the FinFET of FIG. 2, the gate cross-sectional view of FIGS. 3A-3J shows three adjacent gates, and the fin cross-sectional view shows two adjacent S / D contacts. FIG. 3A shows S / D contacts 301, gate spacer 303, dummy gate 305, contact hole 306, and fin 307. For example, S / D contact 301 can include epitaxial Si, fin 307 can include Si, gate spacer 303 can include SiN, and / or dummy gate 305 can include poly-Si. While the fin cross-sections of Figures 3A-3J show that the S / D contacts 301 are physically connected to each other to form a common S / D for two fin devices, the S / D contacts 301 may also be separated from each other and associated with a corresponding single fin device.

[0036] 3B shows the FinFET after deposition of a conformal etch stop layer (ESL) 309. As shown, the ESL 309 is deposited on the downward facing surfaces of the S / D contacts 301, except for the middle regions that are not exposed to deposition gases due to the physical connection of the S / D contacts 301 to a common S / D as described above. In embodiments including a single S / D contact, or adjacent S / D contacts that are physically separated from one another, the ESL 309 is deposited on all downward facing surfaces that are exposed to the gas environment for depositing the ESL. In one example, the ESL 309 can include SiN.

[0037] FIG. 3C shows the FinFET after blanket deposition of a dielectric 311 layer over ESL 309, thereby filling contact hole 306.

[0038] FIG. 3D shows the FinFET after planarization and replacing the dummy gate 305 with a replacement metal gate (RMG) 313.

[0039] FIG. 3E shows the FinFET after an anisotropic oxide etch that exposes the ESL 309 in the contact hole 306 .

[0040] FIG. 3F shows the FinFET after an anisotropic nitride etch that exposes the S / D contacts 301 in the contact holes 306.

[0041] FIG. 3G shows the FinFET after deposition of Ti metal 315 into contact holes 306 by PVD, which deposits the Ti metal 315 only on the S / D contacts 301 and not on the sidewalls.

[0042] FIG. 3H shows the FinFET after conformal deposition of a TiN layer 317 into contact hole 306.

[0043] FIG. 3I shows the FinFET after annealing to form a TiSi2 layer 319 by reaction of Ti metal 315 with the Si of the epitaxial Si S / D contact 301.

[0044] FIG. 3J shows the FinFET after contact holes 306 have been filled with metal 321.

[0045] 4A-4H are schematic diagrams illustrating a method of forming a FinFET with a gate-last process according to an embodiment of the present disclosure. Each of FIGS. 4A-4H includes a top gate cross-sectional view, such as B-B' in FIG. 2, and a bottom fin cross-sectional view, such as A-A' in FIG. 2. Unlike the FinFET of FIG. 2, the gate cross-sectional views of FIGS. 4A-4J show three adjacent gates and the fin cross-sectional views show two adjacent S / D contacts. FIG. 4A shows S / D contacts 401, gate spacer 403, dummy gate 405, contact hole 406, and fin 407. For example, S / D contact 401 can include epitaxial Si, fin 407 can include Si, gate spacer 403 can include SiN, and / or dummy gate 405 can include poly-Si. While the fin cross-sections of Figures 4A-4H show that the S / D contacts 401 are physically connected to each other to form a common S / D for two fin devices, the S / D contacts 401 may also be separated from each other and associated with a corresponding single fin device.

[0046] The surface of the epitaxial Si S / D contact 401 may be cleaned to remove any SiO2 using a cleaning process. A cleaning process that provides good selectivity between SiO2 and SiN gate spacer 403 may be used. The cleaning process promotes good subsequent deposition of a TiSi2 film on the epitaxial Si. In one embodiment, the cleaning process may include exposure to thermal H2 gas at a gas pressure of about 600 mTorr to about 700 mTorr, a substrate temperature of about 700°C to about 800°C, and a duration of about 10 seconds to about 30 seconds. In another embodiment, the cleaning process may include exposure to thermal H2 gas at a gas pressure of about 100 mTorr to about 700 mTorr, a substrate temperature of about 600°C to about 800°C, and a duration of about 10 seconds to about 60 seconds. In another example, the cleaning process may include exposure to thermal NH3 and HF gases at a gas pressure of about 1 Torr to about 3 Torr, a substrate temperature of about 35° C. to about 100° C., and a duration of about 10 seconds to about 30 seconds, or alternatively a duration of about 10 seconds to about 60 seconds. In yet another example, the cleaning process may include exposure to thermal NF3 and H2 gases at a gas pressure of about 1 Torr to about 3 Torr, a substrate temperature of about 20° C. to about 100° C., and a duration of about 10 seconds to about 30 seconds, or alternatively a duration of about 10 seconds to about 60 seconds.

[0047] FIG. 4B shows the FinFET after selectively depositing a TiSi2 film 409 with C54 structure directly on and completely covering the S / D contact 401 on the vertical sidewalls of the gate spacer 403 between the S / D contact 401 and the dummy gate 405. Importantly, the TiS2 film 419 can be deposited as a fully formed TiSi2 film 419 with C54 structure, making subsequent annealing optional. The TiSi2 film 419 wraps around the S / D contact 401 including the underside that is not line-of-sight from above the substrate. The selective deposition can include exposing the substrate to a process gas that includes a titanium-containing precursor gas and a silicon-containing precursor gas. For example, the titanium-containing precursor gas can include TiCl4. For example, the silicon-containing precursor gas can include SiH4, SiH2Cl2, SiHCl3, or SiCl4. In one embodiment, the process gas can include SiH4 and TiCl4. The process gas may further include H2 gas. The gas pressure may be, for example, about 1 mTorr to about 50 mTorr, or about 5 mTorr to about 20 mTorr. The substrate temperature may be, for example, about 700°C to about 800°C.

[0048] 4C shows the FinFET after deposition of a conformal etch stop layer (ESL) 409. As shown, the ESL 409 is deposited on the downward facing surfaces of the S / D contacts 401, except for the middle regions that are not exposed to deposition gases due to the physical connection of the S / D contacts 401 to a common S / D as described above. In embodiments including a single S / D contact, or adjacent S / D contacts that are physically separated from one another, the ESL 409 is deposited on all downward facing surfaces that are exposed to the gas environment for depositing the ESL. In one example, the ESL 409 can include SiN.

[0049] FIG. 4D shows the FinFET after blanket deposition of a dielectric 411 layer filling contact hole 406.

[0050] 4E shows the FinFET after replacing the dummy gate 405 with a replacement metal gate (RMG) 413. In one embodiment, the replacement may be performed by planarizing the structure to the ESL 409 using chemical mechanical planarization (CMP), forming a patterned mask to expose the dummy gate 405, forming a recessed feature by removing the dummy gate 405 (e.g., poly-Si) with a plasma etch process, depositing a conformal high-k dielectric layer (not shown) in the recessed feature, partially filling the recessed feature with tungsten (W) metal, and filling the remaining portion of the recessed feature with SiN.

[0051] FIG. 4F shows the FinFET after an anisotropic etch that exposes the ESL 409 in the contact hole 406 .

[0052] FIG. 4G shows the FinFET after an anisotropic etch that exposes the TiSi2 film 419 on the S / D contacts 401 in the contact holes 406.

[0053] 4H shows the FinFET after filling the contact holes 406 with metal 415. As can be seen, after the TiSi2 film 409 is deposited, the dummy gate 405 is replaced with RMG 414 so that the FinFET now has the TiSi2 film 409 deposited around the entire periphery of the S / D contacts 401 (except for the portion of the periphery that contacts the fins 407). This direct formation of the TiSi2 film 409 on the S / D contacts 401 improves interface quality, reduces contact resistance due to the increased contact area, and may alleviate thermal budget concerns due to the high thermal stability of the TiSi2 film 409.

[0054] It can therefore be understood that the devices and variations thereof discussed herein can be considered as systems. In one embodiment, a FET semiconductor device comprises a substrate including at least one source / drain contact of at least one FET, the at least one source / drain contact being formed adjacent to a gate of the at least one FET, and a TiSi2 film having a C54 structure that is directly on and completely covers the at least one source / drain contact with respect to a vertical sidewall of a gate spacer between the at least one source / drain contact and the gate. An example of such a system is shown in FIG. 4H.

[0055] FIG. 5A is a schematic diagram of a structure resulting from a conventional FinFET fabrication method. As shown, the structure includes a contact etch stop layer (CESL) SiN 387 remaining after a reactive ion etching (RIE) process, and damaged epitaxial Si 381. The TiSi2 layer 385 is only partially formed due to the low thermal budget of the (WF) material. Additionally, the TiSi2 has a reduced metal contact area 383. FIG. 5B is a schematic diagram of a structure resulting from a FinFET fabrication method according to an embodiment disclosed herein, where the RMG is formed after forming a titanium silicide film on the source / drain contacts, as discussed in FIGS. 4A-4H. As shown, the TiSi2 film 419 is completely formed, along with the bottom portion 419' that is not line-of-sight from the top of the substrate. This allows for low electrical resistance and does not rely on Si diffusion from the source / drain contacts. Additionally, the disclosed method eliminates damage to epitaxial Si source / drain contacts, eliminates the formation of etch stop layer residues on the source / drain contacts, and reduces source / drain contact resistance.

[0056] In the above description, specific details have been described, such as the particular shape of the processing system and a description of various components and processes used therein. However, it should be understood that the technology of the present invention may be implemented in other embodiments that differ from these specific details, and such details are for the purpose of explanation and are not intended to limit the present invention. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numbers, materials, and configurations have been described so as to obtain a thorough understanding. Nevertheless, the embodiments may be implemented without such specific details. Components having substantially the same functional structure are labeled with similar reference numerals, and therefore any redundant description may be omitted.

[0057] To facilitate understanding of various embodiments, various techniques have been described as multiple discrete operations. The order of description should not be construed as to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The described operations may be performed in different orders than in the described embodiments. In additional embodiments, various additional operations may be performed and / or described operations may be omitted.

[0058] As used herein, "substrate" or "wafer" refers generally to an object to be processed according to the present invention. The substrate may include any material portion or structure of a device, particularly a semiconductor device or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer on or overlying the base substrate structure, such as a thin film. Thus, the substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but rather is intended to include any such layer or base structure, and any combination of layers and / or base structures. Although the description may refer to a particular type of substrate, this is for illustrative purposes only.

[0059] Those skilled in the art will also appreciate that many modifications can be made to the operation of the techniques described above and still achieve the same objectives of the invention. Such variations are intended to be encompassed within the scope of the present disclosure. Thus, the above description of embodiments of the invention is not intended to be limiting. Rather, any limitations to the embodiments of the invention are presented in the following claims.

Claims

1. 1. A method of manufacturing a FET semiconductor structure, comprising: providing a substrate having at least one source / drain contact of at least one FET, the at least one source / drain contact being formed adjacent a dummy gate of the at least one FET; a vertical sidewall of a gate spacer between the at least one source / drain contact and the dummy gate, and a TiSi having a C54 structure directly on and completely covering the at least one source / drain contact; ２ Selectively depositing a film; replacing the dummy gate with a replacement metal gate; having The method, wherein selectively depositing the TiSi 2 film comprises exposing the substrate to a process gas comprising a titanium-containing precursor gas and a silicon-containing precursor gas.

2. The TiSi ２ 2. The method of claim 1, wherein selectively depositing a film is performed before replacing the dummy gate with the replacement metal gate.

3. The titanium-containing precursor gas is TiCl ４ The method of claim 1 , comprising:

4. The silicon-containing precursor gas is SiH ４ , SiH ２ C ２ , SiHCl ３ , and SiCl ４ The method of claim 1 , comprising at least one of:

5. The process gas is TiCl ４ and SiH ４ The method of claim 1 , comprising:

6. The process gas is H ２ The method of claim 1 further comprising a gas.

7. maintaining a gas pressure between about 1 mTorr and about 50 mTorr; maintaining a substrate temperature between about 700° C. and about 800° C.; The method of claim 1 further comprising:

8. The TiSi ２ After the step of depositing a film, the at least one source / drain contact, the dummy gate, the gate spacer, and the TiSi ２ The method of claim 1 , further comprising depositing an etch stop layer over the membrane.

9. The method of claim 8 further comprising depositing a dielectric over the etch stop layer.

10. The TiSi ２ 10. The method of claim 1, further comprising cleaning the at least one source / drain contact using a cleaning process prior to selectively depositing a film.

11. 11. The method of claim 10, wherein the cleaning process comprises exposing the source / drain contacts to thermal H2 gas at a gas pressure between about 100 mTorr and about 700 mTorr, at a substrate temperature between about 600° C. and about 800° C., for a period between about 10 seconds and about 60 seconds.

12. 11. The method of claim 10, wherein the cleaning process comprises exposing the source / drain contacts to thermal NH3 and HF gases at a gas pressure between about 1 Torr and about 3 Torr, at a substrate temperature between about 35° C. and about 100° C., for a period between about 10 seconds and about 60 seconds.

13. 11. The method of claim 10, wherein the cleaning process comprises exposing the source / drain contacts to thermal NF3 and H2 gases at a gas pressure between about 1 Torr and about 3 Torr, at a substrate temperature between about 20° C. and about 100° C., for a period between about 10 seconds and about 60 seconds.

14. The method of claim 1 , wherein no annealing step is performed between the selectively depositing step and the replacing step.

15. The method of claim 1 , further comprising an annealing step performed between the selectively depositing step and the replacing step.

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