Power Semiconductor Modules

Abstract

The present disclosure relates to a power semiconductor module (1), comprising at least two groups (2, 3; 31, 32, 33, 34) of semiconductor switches (4) connected in parallel, the semiconductor switches (4) of each group being connected in parallel within the group (2, 3; 31, 32, 33, 34), a module gate contact (5), group gate contacts (6, 7) of each group, a first branch point (8) connected to the module gate contact (5) and the group gate contact (6, 7), a gate path between the module gate contact (5) and the first branch point (8) shared for the at least two groups (2, 3; 31, 32, 33, 34) of semiconductor switches, and a compensation structure (9; 39) for increasing an inductance of a connection path in the connection path between the first branch point (8) and a gate terminal (10) of a semiconductor switch (4) of at least one group (3) of the semiconductor switches (4).

Description

[Technical field]

[0001] explanation The present disclosure relates to a power semiconductor module comprising at least two parallel groups of semiconductor switches, the semiconductor switches of each group being connected in parallel. From EP 3113223 A1 a power semiconductor module is known in which several power semiconductor switches are connected using separate substrate metallizations arranged in a stacked manner. [Background technology]

[0002] To obtain lower switching losses in power modules, it is in principle an option to use wide bandgap semiconductors with fast switching operation. However, the use of fast switching semiconductors poses new challenges for the design of the module. In addition, the area of ​​a typical wide bandgap semiconductor device is much smaller than that of today's Si devices, and therefore many of them need to be connected in parallel if higher current ratings are targeted.

[0003] US 2011 / 233608 discloses a switching device with a balancing unit arranged outside the semiconductor module. JP 2005-129826 shows a switching arrangement with a compensation resistor. US 2020 / 185359 is directed to a semiconductor module with compensation means. US 2018 / 123478 discloses a switching arrangement with an artificially extended connection path. EP 3113223 shows a power semiconductor module with a stacking arrangement of several layers. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a power semiconductor module that is based on a wide band gap semiconductor, has a large number of semiconductor switches connected in parallel, and has a high-speed switching operation. [Means for solving the problem]

[0005] According to one embodiment, this object is achieved by a semiconductor module, comprising: at least two groups of semiconductor switches connected in parallel, the semiconductor switches of each group being connected in parallel within the group; - a module gate contact; - group gate contacts for each group; a first inner branch point connected to a module gate contact and a group gate contact; a connection path between the outer gate contact and the inner branch point, the connection path being shared for at least two groups of semiconductor switches; a compensation structure in a connection path between the first branch point and gate terminals of at least one group of semiconductor switches, for increasing the inductance of said connection path; Equipped with.

[0006] The described embodiment has an improved gate connection because the proposed compensation structure allows a better matching of the gate inductances of different groups of semiconductor switches. Improved switching behavior with shorter switching times, less oscillations and less power losses can be achieved even for a large number of semiconductor switches connected in parallel.

[0007] The compensation structure results in an artificial lengthening of the gate path. The artificial lengthening means that the connection is longer than required for the electrical connection and is suitable to substantially affect the inductance of the path between the first branch point and the gate terminal of the at least one group of semiconductor switches. A substantial effect means that the inductance is increased, for example by more than 5%, or more than 10%, or more than 20%, compared to said gate path section without such artificial lengthening. If higher compensation is required, the lengthening can also exceed 50%, 100% or 150%.

[0008] An advantage of this embodiment is that the connections between the module gate contacts and the branch points can be used to connect all the gate terminals, therefore minimizing the space required within the module.

[0009] In addition, the connection between the group gate contact and the gate terminal of the semiconductor switch can also be configured without additional corrective measures. In order to obtain better switching performance, it is mainly important to adjust the connection between the branch point and the group gate contact.

[0010] It is also an advantage of the proposed embodiment that the absolute value of the inductance does not need to be minimized, but the improvement can be achieved simply by reducing the difference in inductance of the connection paths to the different groups of semiconductor switches.

[0011] A further advantage of the proposed embodiment is that resistors that are typically used to damp oscillations between the semiconductor switches can be omitted or at least reduced, which improves the switching behavior leading for example to reduced losses.

[0012] By reducing the vibrations sufficiently, it may at least be possible to replace the thick film resistors with semiconductor based resistors, making the module easier to manufacture and reducing manufacturing costs.

[0013] According to more detailed embodiments, the compensation structure comprises a serpentine structure formed in the metallization layer, a spiral structure formed in the metallization layer, and / or a serpentine wire connecting islands formed in the metallization layer, or it can be a separate device, for example an inductor. All these techniques allow good tuning of the inductance without requiring a lot of additional space in the module.

[0014] According to a further embodiment, at least one group gate contact is configured with a compensation structure. Such a group gate contact is often provided with a relatively large surface area sufficient for forming the compensation structure. Thus, no additional space is required within the module.

[0015] In an alternative embodiment, the compensation structure is disposed between the first branch point and at least one group gate contact, allowing flexible configuration without changing the group gate contact configuration.

[0016] In a further embodiment, the compensation structure is implemented only for those groups of semiconductor switches that have a shorter geometric distance to the branch point than the other groups, meaning that the inductance of the shorter connection paths is adjusted to better match the longer connection paths.

[0017] In a further embodiment, essentially the same compensation structure is applied to group gate contacts of several groups of semiconductor switches. The compensation effect is selective, i.e. individual for each of the associated groups, attenuated or nullified by at least partially excluding the compensation structure from the gate path. For example, a short cut by a bond wire can nullify or attenuate the compensation effect depending on where the group of semiconductor switches is located in the module. The structure of the metallization layer of the group gate contacts is the same for all groups, which can reduce manufacturing costs.

[0018] In the described embodiment, it is advantageous to use as semiconductor switches at least one of MOSFETs, MISFESTs, JFETs or IGBTs based on Si or wide bandgap materials such as SiC or GaN.

[0019] The present disclosure includes a further aspect of the improvement of the gate connection, which is the reduction of the inductance of the connections in the module. According to this aspect, the bond wire connections of the gate and source paths are replaced by interconnect bridges where a conductive layer is used for the gate and source paths. The proposed layer structure comprises an insulating layer disposed between the conductive layers. The gate and source paths belong to the same control loop, which allows the inductance to be reduced according to the physics of parallel conductors. The thickness of the insulating layer is less than 150 μm, and even better less than 80 μm.

[0020] This aspect can be applied in addition to the increase in inductance as described above. This allows the inductance to be reduced in some gate connections and increased in some others, thus reducing the overall gate inductance. This allows the difference between the maximum and minimum inductance to be almost zero. However, the reduction of the inductance difference is also a very effective means to avoid oscillations and to enable high-speed switching operations. In very good cases, gate resistors provided to suppress oscillations can be omitted. This further improves the performance of the power semiconductor module.

[0021] All features described with respect to one of the embodiments are also disclosed herein with respect to the other embodiments, even if each feature is not explicitly mentioned in the context of a particular embodiment.

[0022] The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referenced with the same reference numerals. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. [Brief description of the drawings]

[0023] [Figure 1] 1 is a schematic diagram of a first embodiment of a power semiconductor module; [Diagram 2] FIG. 4 is a diagram illustrating the effect of the first embodiment on gate inductance. [Diagram 3] 2 illustrates a second exemplary embodiment. [Figure 4] 4 shows a vertical configuration of the embodiment of FIG. 3. [Diagram 5] 1 illustrates an exemplary embodiment of a compensation structure. [Figure 6] 1 illustrates an exemplary embodiment of a compensation structure. [Figure 7] 1 illustrates an exemplary embodiment of a compensation structure. [Figure 8] 1 illustrates an embodiment of a compensation structure with damping of the compensation effect. [Figure 9] FIG. 2 is a schematic diagram of a further embodiment of a power module. [Figure 10] A compensation structure having two compensation outputs is shown. [Figure 11] 4 is a further embodiment having an additional interconnect bridge. [Figure 12] 1 shows an interconnection bridge. [Figure 13] FIG. 13 shows details of the interconnection bridge of FIG. 12. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] FIG. 1 is a schematic diagram of a power module 1 including two groups 2, 3 of semiconductor switches 4. Gate terminals 10 of the semiconductor switches 4 are connected to module gate contacts 5. The length of the conduction path between the module gate contacts 5 and the gate terminals 10 of the semiconductor switches 4 depends on the geometric arrangement of the components in the module. For example, if more than one group of semiconductor switches is provided, the connection paths cannot be of equal length for each group of semiconductor switches.

[0025] The unequal lengths of the conductive paths became an issue when the use of wide bandgap semiconductors such as silicon carbide (SiC) or gallium nitride (GaN) became more common to overcome the limitations of silicon-based power semiconductor devices. Illustratively, silicon carbide and gallium nitride based devices are attractive due to their fast switching capability and therefore low switching losses. When many wide bandgap semiconductor switches were used in modules, strong oscillations in the modules were observed. To damp such oscillations, resistors are typically used in the gate paths. In many cases, a 5 Ω resistor is sufficient to suppress the oscillations. However, providing such resistors requires the use of thick film technology, which means that additional manufacturing steps are required. Although it is possible to suppress the oscillations in this way, the initial advantage of wide bandgap semiconductors, namely their fast switching capability, cannot be fully utilized.

[0026] According to the present disclosure, the objective is not to suppress vibrations, but to avoid them by providing an improved design, whereby the approach is not to minimize the inductances in the connection paths, which is difficult with only limited design options, but to equalize them. The switching capability of a power semiconductor module also depends on the total inductance of the gate paths, while vibrations strongly depend on the inductance difference in the paths to different groups of semiconductor switches.

[0027] In other words, to be able to switch quickly, the stray inductance of the module must be low enough to avoid critical voltage overshoots, and the inductance imbalance must be low to avoid oscillations between the semiconductor switches.

[0028] The inductance of the gate path of the first group 2 can be expressed as shared inductance L_shared + interconnect inductance L_interconnect + inductance L1, and the inductance of the second gate path can be expressed as shared inductance L_shared + L2. As can be seen from Figure 1, the path to the second group 3 comprises a compensation structure 9 used to increase the inductance of this connection path in order to equalize the total inductance of the gate paths to the first group 2 and the gate paths to the second group 3.

[0029] Assuming that 1 mm of a typical bond wire increases the inductance of the gate path by about 1 nH, we can see that the difference in gate inductance between semiconductor switches can easily exceed 10 nH. In a particular module design, for example, the inductance difference within a group of semiconductor switches may be negligible, but the shared inductance may dominate. This means that for a more balanced inductance situation, the focus should be on the interconnect inductance.

[0030] The proposed features are useful, for example, in the design of complex high-power modules based on many silicon carbide or gallium nitride devices arranged on several substrates and connected in parallel, but can also be implemented in other smaller power modules such as those shown in Figure 1.

[0031] In the schematic diagram of FIG. 1, group gate contacts 6 and 7 are implemented. In the context of the present application, the group gate contact is the common point of connection to the gate terminals of the semiconductor switches belonging to this group. If several similar semiconductor switches are arranged on a common substrate, each substrate has a common group gate contact. It is also possible to combine several substrates into submodules. The geometric arrangement of the group gate contacts for the semiconductor switches of a group is often similar for all groups contained in the power semiconductor module 1, but the length of the connection path from the module gate contact to the group gate contact may differ between the groups. It should be noted that the above-mentioned shared inductance L_shared means that a first part of the connection path to the gate terminal is used in common up to the branching point where the paths to the different groups branch off.

[0032] 1 is much longer than the connection paths to the second group 3, so that the total inductance of the first group 2 is higher than the total inductance of the second group 3. A compensation structure 9 is thereby implemented in the connection paths between the branch points 8 and the gate terminals of the semiconductor switches 4 of the second group 3. In this embodiment, the compensation structure 9 comprises a serpentine structure formed in a metallization layer.

[0033] FIG. 2 illustrates the effect of the compensation structure in such an embodiment. For example, ten semiconductor switches (4) on one board of the module can be grouped with another ten semiconductor switches (4) on the other board of the module. The twenty semiconductor devices (4) located on both boards are connected in parallel. In the case of a half-bridge module configuration, two such boards represent the upper or lower side of the module. Two other such boards connected in parallel form the other semiconductor switches of this half-bridge module. Thus, in such an embodiment, there are 40 semiconductor switches arranged in four groups (two and two connected in parallel).

[0034] In the diagram of FIG. 2, the maximum relative gate inductance (%) is plotted for each semiconductor switch arranged on one of the two substrates connected in parallel. The semiconductor switches 1 to 10 belong to a first group and are arranged on one substrate in this embodiment, while the semiconductor switches 11 to 20 belong to a second group and are arranged on the other substrate. As can be seen from the dashed line 17 showing the gate inductance of the power semiconductor module without the compensation structure, the maximum difference in gate inductance is 22%, while the difference within the group is only 7%. The use of the compensation structure 9 results in a larger inductance of the gate path of the second group, as can be seen from the solid line 18. In the arrangement with the compensation structure, the maximum difference in gate inductance is only 11 nH, which means about half the gate inductance difference without the compensation structure.

[0035] An additional effect is that oscillations are reduced, which can increase the switching speed. Applicant's measurements show that the amplitude of gate voltage oscillations can be reduced by about 70%. Because oscillations are reduced, the power loss over the switching time can also be reduced.

[0036] Another positive effect of using the concepts of the present disclosure is that resistors can be reduced to values ​​at least below 2 ohms, which can be implemented as semiconductor-based resistors and do not require additional manufacturing steps during module assembly.

[0037] 3 shows a more detailed view of a group of semiconductor switches 4. The semiconductor switches 4 are arranged on a metallization layer 12 of a common substrate 11. A first metallization layer 12 is used as a drain connection. In the stacked configuration of the present embodiment, a second substrate 20 having a second metallization layer 21 is arranged on the first metallization layer 12 or on the first substrate 11. A source terminal 22 of the semiconductor switch 4 is connected to the second metallization layer 21 by a bond wire 25.

[0038] On the metallization layer 21 is disposed a third substrate 23 having a third metallization layer 24. The third metallization layer 24 is used as a bus bar for connecting the gate terminal 10 of the semiconductor switch 4. The connection between the gate terminal 10 and the metallization layer is performed by a bond wire 26. A smaller portion of the third metallization layer 24 is separated and constitutes the group gate contact 6. The third metallization layer 24 is connected to the group gate contact 6 via a resistor 29 and a bond wire.

[0039] The second group 3 is substantially the same as the first group 2, except that the first group 2 is not provided with a structuring structure and the group gate contacts 7 of the second group 3 are modified with a compensation structure 9. Details of the compensation structure are shown in Figures 5 to 9.

[0040] The vertical structure of the configuration of FIG. 3 is shown in FIG. 4. This exemplary embodiment concerns a MOSFET-based configuration using SiC. The main advantages are envisaged for such wide bandgap semiconductors. However, this solution can also be beneficial and considered for Si-based power modules and other types of semiconductor switches if an improved balance of gate inductance is required.

[0041] The bottom surface is provided with a substrate 11 having a metallization layer 12 on its top surface. Disposed on metallization layer 12 is a semiconductor switch 4 having a source terminal 22 and a gate terminal 10. The source terminal 22 is connected to a second metallization layer 21 by a bond wire 25, and the gate terminal 10 is connected to metallization layer 24 by a bond wire 26.

[0042] 5, 6 and 7 show different configurations of the compensation structure 9 that can be applied to the group gate contact 7 of FIG. 3. The metallization layer 24 on the third substrate 23 is designed to form a serpentine-like structure. As is clear from FIG. 5, the current path from the first contact 27 to the second contact 28 is much longer than a straight line from point 27 to point 28. The configuration of FIG. 5 can easily be used as a replacement or modification of the group gate contact 6 or 7. The trace coming from the module gate contact 5 is connected to the contact 27 of the compensation structure 9, while the contact 28 is connected via another bond wire to a resistor 29 and then to the third metallization layer 24, or if a resistor is not used, the contact 28 is directly in contact with the metallization layer 24.

[0043] An alternative embodiment is shown in Figure 6, in which islands 16 are provided on a substrate 23 and incoming contacts 27 are connected to the islands via bond wires 15, for example in a serpentine configuration.

[0044] 7, a spiral configuration is used with the same purpose to increase the inductance of the path between contacts 27 and 28. Contact 27 is connected by bond wire 17 to the center point of the spiral.

[0045] The inductance of the gate path can also be increased by adding discrete devices that increase the inductance.

[0046] It should be noted that the configurations of Figures 5, 6 and 7 may be combined in further embodiments.

[0047] In further embodiments, the effect of the compensation structure can be attenuated or nullified by excluding or partially excluding it from the gate path. This is shown in FIG. 8, where the bond wire 18 is connected to approximately the middle of the spiral path rather than to the center point of the spiral compensation structure, so that the connection path through the compensation structure is still longer than the straight line between points 27 and 28, but not as long as possible. Such a configuration can be used, for example, when essentially the same structure in the metallization layer is to be applied to several group gate contacts, but the increase in inductance must vary depending on the location of the group of semiconductor switches in the module and the length of the conductive path to the gate contact of the module.

[0048] Another embodiment is shown in Figure 9. According to this embodiment, four semiconductor groups 31 to 34 are provided. Two groups each form a sub-module 35 and 36. An additional group of semiconductor switches can be arranged on the rear side of the sub-modules. In such an embodiment, eight groups of semiconductor switches are used. A similar configuration can be used for power semiconductors with fewer or more groups.

[0049] In the embodiment of FIG. 9, two levels of branch points are provided. Between the module gate contact 5 and the first branch point 8, the gate path is shared for all semiconductor switches. At the first branch point 8, the gate path is divided for the first submodule 35 and the second submodule 36. In the left branch, a second branch point 37 is provided, where the gate path is divided for the first group of semiconductor switches 31 and the second group 32. The same is true for the second submodule 36, where a third branch point 38 is provided. While the third branch point 38 is a simple connection point, the second branch point 37 is formed as a construction structure 39 that is effective for increasing the gate inductance of the first and second groups 31, 32.

[0050] The configuration of the compensation structure 39 is shown in more detail in FIG. 10. It shows a serpentine structure with an "incoming" contact 40 connected to the module gate contact 5 and two "outgoing" contacts 41 and 42 connected to the second group 32 or the first group 31, respectively. As is clear from FIG. 10, the connection path from contact 40 to contact 41 is shorter than the connection path from contact 40 to contact 42. In this way, different lengths of the paths from the branch point 37 to the group gate contacts 6 can be compensated separately, i.e. the additional inductance can be configured to be higher for the second group 32 than for the first group 31.

[0051] FIG. 11 shows an embodiment including the second aspect of the disclosure described above. Groups of semiconductor switches 51 and 52 are integrated in a submodule 53. Two additional groups of semiconductor switches 54 and 55 are integrated in a second submodule 56. Each of the submodules 53 and 56 includes a connection between the groups via an interconnection bridge 57 as described below in connection with FIG. 12 and FIG. 13. Also, the gate and source connections between the submodules 53 and 56 can be implemented as an interconnection bridge 57. The technical background of the use of the interconnection bridge 57 is that the compensation structure may not be able to sufficiently equalize the gate inductance. In some cases, it is possible to increase the inductance to reach this goal, but the total inductance becomes too high, resulting in oscillations or very slow switching times.

[0052] By means of the interconnection bridge it is possible to reduce the inductance of some gate paths, so that on the one hand some low inductances can be increased and some high inductances reduced. For the functionality of the interconnection bridge it is important that the source path, i.e. the path between the module source contact 19 and the source terminal of the semiconductor switch, must be included. If instead of the MOESFET other types of semiconductor switches are used, the source terminal can have a different name, but the same technical effect is achieved. Overall, a sufficient equalization of the gate inductances can be achieved without facing a high total inductance.

[0053] The interconnect bridge is a first conductive layer for the gate connection, a second conductive layer for the source connection, and - a layer structure including an insulating layer disposed between a first conductive layer and a second conductive layer; Equipped with.

[0054] The interconnect bridge is connected within the control loop of the semiconductor switch, i.e., current flowing through the first conductive layer to the gate terminal also flows at least partially through the second conductive layer, but in the opposite direction.

[0055] It should be noted that for the technical effect of the interconnect bridge 57, connection paths for the gate and source are required, but only the gate path needs to be modified for the compensation structure.

[0056] FIG. 12 shows a detail of the embodiment of FIG. 11 with respect to the interconnect bridge 57. The interconnect bridge 57 comprises two conductive layers 60 and 61. Layer 60 is used as the gate connection, whereas layer 61 is used as the source connection. Both layers are separated by an insulating layer, not shown in this figure. On either side of the interconnect bridge 57, a leg 62 for the gate connection and a leg 63 for the source connection are provided. These legs are connected to the gate or source terminals of the semiconductor switches, respectively, via traces on the substrate on which the semiconductor switches are placed. One or more additional layers can be applied to increase the mechanical stability of the bridge, or adhesive can be added to provide additional support. This may be necessary, for example, for very long interconnect bridges.

[0057] FIG. 13 shows a more detailed view of the interconnect bridge 57. As can be seen, the conductive layers 60 and 61 are separated by an insulating layer 64. The closer the conductive layers 60 and 61 are, the better the inductive coupling between them. The better the coupling, the lower the inductance of the gate connection. Thus, a thin insulating layer is beneficial for the performance of the power semiconductor module. It is beneficial for the thickness of the insulating layer to be less than 150 μm, or even less than 80 μm.

[0058] The embodiments shown in the above-mentioned Figures 1 to 13 represent exemplary embodiments of the improved configuration of the power semiconductor module. Therefore, they do not constitute a complete list of all embodiments according to the improved configuration. The actual apparatus and method may differ from the embodiments shown with respect to the apparatus and device. [Explanation of symbols]

[0059] Reference sign 1 Power Semiconductor Module 2 Groups of semiconductor switches 3 Groups of Semiconductor Switches 4. Semiconductor Switches 5 Module Gate Contacts 6 Group Gate Contacts 7 Group Gate Contacts 8 The first turning point 9 Compensation structure 10 Gate terminal 11 First substrate 12 First Metallization Layer 13 Serpentine structure 14 Spiral structure 15 Wired serpentine structure 16 Island 17 Bond Wire 18 Bond wire 19 Module Source Contact 20 Second substrate 21 Second Metallization Layer 22 Source terminal 23 Third Board 24 3rd Metallization Layer 25 Bond Wire 26 Bond Wire 27 First Contact Point 28 The second point of contact 29 Resistor 31 Semiconductor Switch Group 32 Group of semiconductor switches 33 Semiconductor Switch Group 34 Semiconductor Switch Group 37 The second turning point 38 The third turning point 39 Compensation structure 40 "Iriki" contact point 41 "Departure" contact 42 "Departure" contact 43 Gate inductance without compensation structure 44 Gate inductance with compensation structure 51 Semiconductor Switch Group 52 Semiconductor Switch Group 53 Submodules 54 Semiconductor Switch Group 55 Semiconductor Switch Group 56 Submodules 57 Interconnecting Bridges 60 Conductive Layer 61 Conductive layer 62 Legs 63 Legs 64 Insulating Layer

Claims

1. A power semiconductor module (1), at least two groups (2, 3; 31, 32, 33, 34) of semiconductor switches (4) connected in parallel, said semiconductor switches (4) of each group being connected in parallel within said group (2, 3; 31, 32, 33, 34); - a module gate contact (5), - group gate contacts (6, 7) for each group; a first branch point (8) connected to said module gate contact (5) and to said group gate contacts (6, 7); a gate path between said module gate contact (5) and said first branch point (8), which is shared for said at least two groups (2, 3; 31, 32, 33, 34) of semiconductor switches; a compensation structure (9; 39) in the connection path between said first branch point (8) and a gate terminal (10) of said semiconductor switch (4) of at least one group (3) of said semiconductor switches (4) for increasing the inductance of said connection path; A power semiconductor module (1).

2. 2. A power semiconductor module (1) according to claim 1, characterized in that the compensation structure (9; 13; 14; 15; 39) comprises an artificial lengthening of the gate path.

3. 3. The power semiconductor module (1) according to claim 2, characterized in that the artificial elongation exceeds 5%, 10% or 20%.

4. Said compensation structure (9; 13; 14; 15; 39) has the following characteristics: formed in the metallization of a ceramic substrate or PCB, - formed by wire bonds, or - formed as a discrete device, 4. A power semiconductor module (1) according to claim 2 or 3, characterized in that it is formed by one or more of:

5. 4. The power semiconductor module (1) according to claim 1, wherein the compensation structure (9) is formed in a metallization layer (12; 24) by one or more of the following features: a serpentine structure (13) or a spiral structure (14).

6. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that the compensation structure (15) comprises wires connecting islands (16) formed in a metallization layer (12; 24).

7. Power semiconductor module (1) according to any one of claims 1 to 3, characterized in that at least one group gate contact (6) is configured with the compensation structure (9).

8. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that the compensation structure (9) is arranged between the first branch point (8) and at least one group gate contact (6, 7).

9. 4. The power semiconductor module (1) according to claim 1, characterized in that the geometrical distance between the first branch point (8) and the group gate contacts (6, 7) is different for at least two groups (2, 3; 31, 32, 33, 34) of semiconductor switches (4), and the compensation structure (9) is implemented only for those groups of semiconductor switches (4) which have a smaller geometrical distance than the maximum.

10. 8. A power semiconductor module (1) according to claim 7, characterized in that by at least partially excluding the compensation structure (14) from the gate path, an identical compensation structure (9) is formed for each of several groups of gate contacts (6, 7), except that the compensation effect is selective, i.e. attenuated or nullified individually for each of the associated groups.

11. 4. The power semiconductor module (1) according to claim 1, characterized in that the inductance of a compensation structure in the form of a first compensation structure for a first group of semiconductor switches (4) differs from the inductance of a compensation structure in the form of a second compensation structure for a second group of semiconductor switches (4).

12. Power semiconductor module (1) according to any one of claims 1 to 3, characterised by at least one second branch point (37, 38) in the gate path.

13. 4. A power semiconductor module (1) according to claim 1, characterized in that several semiconductor switches (4) of a group of semiconductor switches are arranged on a substrate (11) having a first metallization layer (12), a stacked second substrate (20) having a second metallization layer (21) as a source connection layer and a stacked third substrate (23) having a third metallization layer (24) as a gate connection layer.

14. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that the semiconductor switch (4) is at least one of a MOSFET, a MISFET, a JFET or an IGBT based on Si or a wide band gap material.

15. The power semiconductor module (1) according to any one of claims 1 to 3, characterized in that the group gate contacts (6, 7) are connected to the gate terminals (10) of the semiconductor switches (4) belonging to the group directly or via a semiconductor-based resistor (29) having a resistance of less than 3 Ω.

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