RF impedance matching network with clamp circuit - Patents.com

Abstract

In one embodiment, an RF impedance matching circuit is disclosed. The matching circuit includes at least one electronically variable capacitor (EVC). Each EVC includes a fixed capacitor, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor into and out of the fixed capacitor to change the total capacitance of the EVC. Each switching circuit includes a switch including a PIN or NIP diode, a driver circuit operably coupled to the switch, a filter operably coupled between the driver circuit and the switch, and a clamp circuit operably coupled between the filter and the switch. The clamp circuit includes a blocking device having a first terminal operably coupled to a clamp power supply and a separate second terminal operably coupled to a terminal of the filter.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Provisional Application No. 63 / 192,602, filed May 25, 2021, which is incorporated by reference herein in its entirety. [Background technology]

[0002] In the manufacture of semiconductor devices such as microprocessors, memory chips, and other integrated circuits, the semiconductor device manufacturing process uses plasma processing at different stages of manufacture. Plasma processing involves energizing a gas mixture by imparting energy to the gas molecules by introducing RF (radio frequency) energy into the gas mixture. The gas mixture is typically contained within a vacuum chamber, also called a plasma chamber, and RF energy is introduced into the chamber through electrodes or other means. In a typical plasma process, a radio frequency power source generates power at a desired RF frequency and RF power, which is transmitted to the plasma chamber through RF cables and networks.

[0003] To provide efficient transfer of power from the RF power source to the plasma chamber, an RF matching network is positioned between the RF power source and the plasma chamber. The purpose of the RF matching network is to transform the plasma impedance to a value suitable for the RF power source. In many cases, especially in semiconductor manufacturing processes, RF power is transmitted through a 50 ohm coaxial cable, and the system impedance (output impedance) of the RF power source is also 50 ohms. Meanwhile, the impedance of the plasma driven by RF power varies based on the plasma chemistry and other conditions inside the plasma chamber. This impedance must be transformed to a non-reactive 50 ohms (i.e., 50+j0) for maximum power transmission. The RF matching network performs this task of continuously transforming the plasma impedance to 50 ohms for the RF power source. In most cases, this transformation is performed so that the impedance at the input side of the RF matching network is 50+j0 ohms, i.e., a purely resistive 50 ohms.

[0004] The RF matching network may include a variable capacitor and a microprocessor-based control circuit for controlling the capacitor. The value and size of the variable capacitor are influenced by the power handling capability, operating frequency, and impedance range of the plasma chamber. The primary variable capacitor used in RF matching networks is the vacuum variable capacitor (VVC). The VVC is an electromechanical device consisting of two concentric metal rings that move relative to each other to change the capacitance. In complex semiconductor processes where impedance changes are very fast, the rapid and frequent movements stress the VVC, leading to its failure. The VVC-based RF matching network is one of the last electromechanical components in the semiconductor manufacturing process.

[0005] However, as semiconductor devices shrink in size and become more complex, feature geometries become very small. As a result, the processing times to fabricate these features also become very small, typically in the range of 5-6 seconds. Current RF matching networks take 1-2 seconds to tune a process, which leads to unstable process parameters for a significant portion of the process time. Electronically Variable Capacitor (EVC) technology (see, for example, U.S. Pat. No. 7,251,121, which is incorporated by reference in its entirety) allows for the reduction of this semiconductor process tuning time from 1-2 seconds to less than 500 microseconds. EVC-based matching networks are a type of solid-state matching network. As the tuning time is reduced, the available stable processing time increases significantly, thereby improving yield and performance.

[0006] While EVC technology is known, it has not yet been developed as an industry-accepted replacement for VVC. Because EVC is a purely electronic device, it is not a one-to-one VVC replacement in RF matching networks. Therefore, further advances are needed to more fully utilize EVC as part of an RF matching network. Summary of the Invention

[0007] The present disclosure may be directed to a radio frequency (RF) impedance matching circuit, the matching circuit comprising: an RF input configured to operably couple to an RF source providing an RF signal; an RF output configured to operably couple to a plasma chamber; at least one electronically variable capacitor (EVC), each EVC of the at least one EVC comprising a fixed capacitor, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor in and out to change a total capacitance of the EVC; and a control circuit configured to cause switching of the fixed capacitor in and out of each EVC to enable impedance matching, each switching circuit for each fixed capacitor of each EVC comprising a switch including a PIN diode or a NIP diode, a driver circuit operably coupled to the switch, a filter operably coupled between the driver circuit and the switch, and a clamp circuit operably coupled between the filter and the switch, the clamp circuit comprising an interruption device having a first terminal operably coupled to a clamp power supply and a separate second terminal operably coupled to a terminal of the filter.

[0008] In another aspect, a method for impedance matching includes coupling a radio frequency (RF) input of a matching circuit to an RF source providing an RF signal, and coupling an RF output of the matching circuit to a plasma chamber, the matching circuit comprising at least one electronically variable capacitor (EVC), each EVC of the at least one EVC comprising a fixed capacitor, each fixed capacitor comprising a corresponding switching circuit for switching an input and an output of the fixed capacitor to change a total capacitance of the EVC, and a control circuit configured to cause switching of the input and output of the fixed capacitor of each EVC to enable impedance matching, each switching circuit for each fixed capacitor of each EVC comprising a control circuit configured to cause switching of the input and output of the fixed capacitor of each EVC to enable impedance matching, and coupling the switching circuit to a switching power supply including a switch including a PIN or NIP diode, a driver circuit operably coupled to the switch, a filter operably coupled between the driver circuit and the switch, and a clamp circuit operably coupled between the filter and the switch, the clamp circuit comprising an interruption device having a first terminal operably coupled to a clamp power supply and a separate second terminal operably coupled to a terminal of the filter; and matching impedance by at least one of the switching circuits of the at least one EVC to switch the input and output of its corresponding fixed capacitor to vary the total capacitance of the EVC.

[0009] In another aspect, a semiconductor processing tool includes a plasma chamber configured to deposit material on or etch material from a substrate; an impedance matching circuit operably coupled to the plasma chamber, the matching circuit having an RF input configured to operably couple to an RF source providing an RF signal; an RF output configured to operably couple to the plasma chamber; at least one electronically variable capacitor (EVC), each EVC of the at least one EVC comprising a fixed capacitor, each fixed capacitor having a corresponding switching circuit for switching the fixed capacitor in and out of the fixed capacitor to change a total capacitance of the EVC; and a control circuit configured to cause switching of the fixed capacitor in and out of each EVC to enable impedance matching, each switching circuit for each fixed capacitor of each EVC comprising a switch comprising a PIN diode or a NIP diode; a driver circuit operably coupled to the switch; a filter operably coupled between the driver circuit and the switch; and a clamp circuit operably coupled between the filter and the switch, the clamp circuit comprising an interrupt device having a first terminal operably coupled to a clamp power supply and a separate second terminal operably coupled to a terminal of the filter.

[0010] In another aspect, a method of fabricating a semiconductor includes placing a substrate in a plasma chamber configured to deposit a layer of material on or etch a layer of material from the substrate; energizing a plasma in the plasma chamber by coupling RF power from an RF source to the plasma chamber to perform the deposition or etching; and performing impedance matching with an impedance matching circuit coupled between the plasma chamber and the RF source while energizing the plasma, the matching circuit comprising an RF input configured to operably couple to the RF source, an RF output configured to operably couple to the plasma chamber, and at least one electronically variable capacitor (EVC), each EVC of the at least one EVC comprising a fixed capacitor, the fixed capacitor each of which comprises at least one electronically variable capacitor having a corresponding switching circuit for switching the fixed capacitor in and out to change the total capacitance of the EVC, and a control circuit configured to cause switching of the fixed capacitor in and out of each EVC to enable impedance matching, wherein each switching circuit for each fixed capacitor in each EVC includes a switch including a PIN or NIP diode, a driver circuit operably coupled to the switch, a filter operably coupled between the driver circuit and the switch, and a clamp circuit operably coupled between the filter and the switch, the clamp circuit comprising a blocking device having a first terminal operably coupled to a clamp power supply and a separate second terminal operably coupled to a terminal of the filter. [Brief description of the drawings]

[0011] The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:

[0012] [Figure 1] FIG. 1 is a block diagram of one embodiment of a semiconductor processing system. [Diagram 2] FIG. 2 is a block diagram of one embodiment of a semiconductor processing system having an L-configuration matching network. [Diagram 3]FIG. 3 is a block diagram of one embodiment of a semiconductor processing system having a pi-configuration matching network. [Figure 4] FIG. 4 is a block diagram of one embodiment of a circuit for providing variable capacitance using an electronically variable capacitor. [Diagram 5] FIG. 5 is a schematic diagram of a variable capacitance system for switching individual capacitors in and out of an electronically variable capacitor. [Figure 6] FIG. 6 is a block diagram of one embodiment of a switching circuit for an EVC. [Figure 7] FIG. 7 is a flow chart of an exemplary process for matching impedance by varying variable capacitance. [Figure 8] FIG. 8 is a flow chart of an exemplary process for matching impedance using a parameter matrix to vary variable capacitance. [Figure 9] FIG. 9 is a simulation schematic of a switching circuit without a clamp circuit, according to one embodiment. [Figure 10] 10A-D show waveforms of the circuit simulation of FIG. 9 during the on-to-off transition of the driver circuit. [Figure 11] FIG. 11 is a close-up of the PIN diode avalanche waveform of FIG. 10D. [Figure 12] FIG. 12 is a schematic diagram of a portion of the switching circuit of FIG. 6 with the addition of a clamp circuit to prevent PIN diode avalanching. [Figure 13] FIG. 13 is a simulation schematic of a switching circuit utilizing a clamp circuit, according to one embodiment. [Figure 14] 14A-D show waveforms of the circuit simulation of FIG. 13 during the on-to-off transition of the driver circuit. [Figure 15] FIG. 15 is a close-up of the PIN diode clamp waveform of FIG. 14D. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The following description of the preferred embodiments is merely exemplary in nature and is not intended to limit the invention in any way. The description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are to be considered as part of the entire written description. Any reference to direction or orientation in the description of the exemplary embodiments disclosed herein is intended merely for convenience of description and is not intended to limit the scope of the invention in any way. The discussion herein describes and illustrates several possible and non-limiting combinations of features that may exist alone or in combination with other features. Furthermore, the term "or" as used herein should be interpreted as a logical operator that yields true if one or more of its operands are true. Furthermore, the word "based on" as used herein should be interpreted as meaning "based at least in part on" and therefore is not limited to the interpretation of "fully based on".

[0014] Features of the invention may be implemented in software, hardware, firmware, or a combination thereof. The computer programs described herein are not limited to any particular embodiment and may be implemented in an operating system, an application program, a foreground or background process, a driver, or any combination thereof. The computer programs may be executed on a single computer or server processor, or on multiple computer or server processors.

[0015] The processors described herein may be any central processing unit (CPU), microprocessor, microcontroller, computing device, or programmable device or circuitry configured to execute computer program instructions (e.g., code). The various processors may be embodied in any suitable type of computer and / or server hardware (e.g., desktop, laptop, notebook, tablet, mobile phone, etc.) and may include all the usual ancillary components necessary to form a functional data processing device, including, but not limited to, buses, software and data storage such as volatile and non-volatile memory, input / output devices, graphical user interfaces (GUIs), removable data storage devices, and wired and / or wireless communication interface devices including Wi-Fi, Bluetooth, LAN, etc.

[0016] The computer-executable instructions or programs (e.g., software or code) and data described herein may be programmed and tangibly embodied in a non-transitory computer-readable medium accessible to and retrievable by each processor as described herein, which configures and directs the processor to perform desired functions and processes by executing instructions encoded on the medium. A device embodying a programmable processor configured with such non-transitory computer-executable instructions or programs may be referred to as a "programmable device" or "device," and multiple programmable devices in communication with each other may be referred to as a "programmable system." A non-transitory "computer-readable medium" as referred to herein includes, but is not limited to, any suitable volatile or non-volatile memory, including random access memory (RAM) and its various types, read-only memory (ROM) and its various types, USB flash memory, and magnetic or optical data storage devices (e.g., internal / external hard disks, floppy disks, magnetic tapes, CD-ROMs, DVD-ROMs, optical disks, ZIP® drives, Blu-ray disks, and the like) that can be written to and / or read by a processor operatively connected to the medium.

[0017] In certain embodiments, the present invention may be embodied in the form of computer-implemented processes and apparatuses, such as processor-based data processing and communication systems or computer systems for performing those processes. The present invention may also be embodied in the form of software or computer program code embodied in a non-transitory computer-readable storage medium, where the computer program code segments, when loaded into and executed by the data processing and communication system or computer system, configure a processor to create specific logic circuits configured to implement the processes.

[0018] In the following description, where circuits are shown and described, those skilled in the art will recognize that for clarity, not all peripheral circuits or components are shown in the figures or described in the description. Additionally, the terms "coupled" and "operably coupled" can refer to a direct or indirect coupling of two components of a circuit.

[0019] The following description of the preferred embodiments is merely exemplary in nature and is not intended to limit the invention in any way. The description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are to be considered as part of the entire written description. Any reference to direction or orientation in the description of the exemplary embodiments disclosed herein is intended merely for convenience of description and is not intended to limit the scope of the invention in any way. Relative terms such as "lower", "upper", "horizontal", "vertical", "above", "below", "up", "down", "left", "right", "top", "bottom", "front" and "rear", as well as derivatives thereof (e.g., horizontally", "downwardly", "upwardly", etc.) should be construed as referring to the orientation being described or shown in the drawings under consideration. These relative terms are for convenience of description only and do not require that a device be constructed or operated in a particular orientation unless expressly indicated. Terms such as "attached," "affixed," "connected," "coupled," "interconnected," "secured," and other similar terms refer to both a relationship in which structures are fixed or attached to one another, either directly or indirectly through an intervening structure, as well as a movable or rigid attachment or relationship, unless expressly stated otherwise. The discussion herein describes and illustrates several possible and non-limiting combinations of features that may exist alone or in combination with other features. Furthermore, the term "or" as used herein should be interpreted as a logical operator that yields true if one or more of its operands are true. Furthermore, the word "based on" as used herein should be interpreted as meaning "based at least in part on," and thus is not limited to being interpreted as "fully based on."

[0020] Ranges used throughout are used as a shorthand expression to describe all values ​​within the range. Any value within the range can be selected as the end of the range. Furthermore, all references cited herein are incorporated herein by reference in their entirety. In the event of discrepancy between the definitions in this disclosure and those of the references cited, this disclosure shall prevail.

[0021] Semiconductor Processing Systems 1, there is shown a semiconductor device processing system 5 that utilizes a radio frequency power source 15. The system 85 includes a radio frequency power source 15 and a semiconductor processing tool 86. The semiconductor processing tool 86 includes a matching network 11 and a plasma chamber 19. In other embodiments, the generator 15 or other power source may form part of the semiconductor processing tool.

[0022] The semiconductor device may be a microprocessor, a memory chip, or other type of integrated circuit or device. The substrate 27 may be placed in the plasma chamber 19, which is configured to deposit a layer of material on the substrate 27 or etch a layer of material from the substrate 27. Plasma processing involves energizing a gas mixture by imparting energy to the gas molecules by introducing RF energy into the gas mixture. This gas mixture is typically contained within a vacuum chamber (plasma chamber 19), and RF energy is typically introduced into the plasma chamber 19 through electrodes. Thus, a plasma may be energized by coupling RF power from an RF source 15 to the plasma chamber 19 to perform deposition or etching.

[0023] In a typical plasma process, the high frequency power source 15 generates power at a radio frequency, typically in the range of 3 kHz to 300 GHz, which is transmitted to the plasma chamber 19 through RF cables and networks. To provide efficient transfer of power from the high frequency power source 15 to the plasma chamber 19, an intermediate circuit is used to match the fixed impedance of the high frequency power source 15 to the variable impedance of the plasma chamber 19. Such intermediate circuits are commonly referred to as RF impedance matching networks, or more simply, RF matching networks. The purpose of the RF matching network 11 is to transform the variable plasma impedance to a value that more closely matches the fixed impedance of the high frequency power source 15. Commonly owned U.S. Publication Nos. 2021 / 0183623 and 2021 / 0327684, the disclosures of which are incorporated herein by reference in their entireties, provide examples of such matching networks.

[0024] Matching Network 2 is a block diagram of one embodiment of a semiconductor processing system 85 having a processing tool 86 that includes an L-configuration RF impedance matching network 11. As discussed in further detail below, the exemplary matching network 11 utilizes electronically variable capacitors (EVCs) for both the shunt variable capacitor 33 and the series variable capacitor 31. Note that the invention is not so limited. For example, one of the EVCs (e.g., the shunt EVC 33) may be a mechanically variable VVC or may be replaced with a variable inductor.

[0025] The exemplary matching network 11 has an RF input 13 connected to an RF source 15 and an RF output 17 connected to a plasma chamber 19. An RF input sensor 21 can be connected between the RF impedance match network 11 and the RF source 15. An RF output sensor 49 can be connected between the RF impedance match network 11 and the plasma chamber 19 such that the RF output from the impedance match network and the plasma impedance presented by the plasma chamber 19 can be monitored. Certain embodiments may include only one of the input sensor 21 and the output sensor 49. The functions of these sensors 21, 49 are described in more detail below.

[0026] As mentioned above, RF impedance matching network 11 helps maximize the amount of RF power transferred from RF source 15 to plasma chamber 19 by matching the impedance at RF input 13 to a fixed impedance of RF source 15. Matching network 11 can consist of a single module in a single housing designed for electrical connection to RF source 15 and plasma chamber 19. In other embodiments, components of matching network 11 can be located in different housings, some components can be outside of a housing, and / or some components can share a housing with components outside of the matching network.

[0027] As known in the art, the plasma in the plasma chamber 19 typically undergoes certain variations outside of operational control such that the impedance presented by the plasma chamber 19 is a variable impedance. Because the variable impedance of the plasma chamber 19 cannot be fully controlled, an impedance matching network may be used to create an impedance match between the plasma chamber 19 and the RF source 15. Additionally, the impedance of the RF source 15 may be fixed to a set value by the design of the particular RF source 15. Although the fixed impedance of the RF source 15 may undergo slight variations during use, for example due to temperature or other environmental variations, the impedance of the RF source 15 is still considered a fixed impedance for purposes of impedance matching because the variations do not significantly change the fixed impedance from the originally set impedance value. Other types of RF sources 15 may be designed such that the impedance of the RF source 15 can be set at the time of use or during use. The impedance of these types of RF sources 15 is still considered fixed because it may be controlled by the user (or at least by a programmable controller) and the impedance set point may be known at any point during operation, so that the set point is effectively a fixed impedance.

[0028] RF source 15 may be a type of radio frequency power source known in the art, and generates an RF signal at a frequency and power appropriate for the process being performed in plasma chamber 19. RF source 15 may be electrically connected using a coaxial cable to an RF input 13 of RF impedance matching network 11, which will have the same fixed impedance as RF source 15 for impedance matching purposes.

[0029] The plasma chamber 19 includes a first electrode 23 and a second electrode 25 which, in conjunction with a suitable control system (not shown) and a plasma within the plasma chamber, enable one or both of the deposition of material onto and the etching of material from the substrate 27 in processes well known in the art.

[0030] In the exemplary embodiment, RF impedance matching network 11 includes series variable capacitor 31, shunt variable capacitor 33, and series inductor 35 forming an “L” type matching network. Although shunt variable capacitor 33 is shown as being shunted to a reference potential (ground 40 in this case) between series variable capacitor 31 and series inductor 35, those skilled in the art will recognize that RF impedance matching network 11 may be configured with shunt variable capacitor 33 shunted to a reference potential at RF input 13 or RF output 17.

[0031] Alternatively, the RF impedance matching network 11 may be configured in other matching network configurations, such as a "T" configuration or a "π" or "pi" configuration, as shown in Figure 3. In certain embodiments, the variable capacitors and switching circuitry described below may be included in any configuration suitable for an RF impedance matching network.

[0032] In an exemplary embodiment, each of the series variable capacitor 31 and the shunt variable capacitor 33 may be an electronically variable capacitor (EVC) as described in U.S. Pat. No. 7,251,121, where the EVC is effectively a capacitor array formed by a number of individual capacitors. The series variable capacitor 31 is coupled in series between the RF input 13 and the RF output 17 (which is also in parallel between the RF source 15 and the plasma chamber 19). The shunt variable capacitor 33 is coupled in parallel between the RF input 13 and ground 40. In other configurations, the shunt variable capacitor 33 may be coupled in parallel between the RF output 19 and ground 40. Other configurations may also be implemented without departing from the functionality of the RF matching network. In yet other configurations, the shunt variable capacitor 33 may be coupled in parallel between a reference potential and one of the RF input 13 and the RF output 19.

[0033] The series variable capacitor 31 is connected to the series RF choke and filter circuit 37 and to the series driver circuit 39. Similarly, the shunt variable capacitor 33 is connected to the shunt RF choke and filter circuit 41 and to the shunt driver circuit 43. Each of the series driver circuit 39 and the shunt driver circuit 43 is connected to a control circuit 45, which may be configured with a suitable processor and / or signal generating circuit to provide input signals for controlling the series driver circuit 39 and the shunt driver circuit 43. A power supply 47 is connected to each of the RF input sensor 21, the series driver circuit 39, the shunt driver circuit 43, and the control circuit 45 to provide operating power to each of these components at a designed current and voltage. The voltage levels provided by the power supply 47, and therefore the voltage levels employed by each of the RF input sensor 21, the series driver circuit 39, the shunt driver circuit 43, and the control circuit 45, may be selected to suit the design to perform their respective specific tasks. In other embodiments, various electronic components may be used to enable the control circuit 45 to send instructions to the variable capacitors. Additionally, while the driver circuitry and the RF chokes and filters are shown separate from the control circuitry 45, these components may also be considered to be parts that form the control circuitry 45.

[0034] In an exemplary embodiment, the control circuitry 45 includes a processor. The processor may be any type of appropriately programmed processing device (or a collection of two or more processing devices working together), such as a computer or microprocessor, configured to execute computer program instructions (e.g., code). The processor may be embodied in any suitable type of computer and / or server hardware (e.g., desktop, laptop, notebook, tablet, mobile phone, etc.) and may include all the usual ancillary components necessary to form a functional data processing device, including, but not limited to, buses, software and data storage such as volatile and non-volatile memory, input / output devices, graphical user interfaces (GUIs), removable data storage devices, and wired and / or wireless communication interface devices including Wi-Fi, Bluetooth, LAN, etc. The processor of the exemplary embodiment is configured with certain algorithms that enable the matching network to perform the functions described herein.

[0035] With the combination of the series variable capacitor 31 and the shunt variable capacitor 33, the combined impedance of the RF impedance match network 11 and the plasma chamber 19 can be controlled to match, or at least substantially match, the fixed impedance of the RF source 15 using the control circuit 45, the series driver circuit 39, and the shunt driver circuit 43.

[0036] The control circuit 45 is the brains of the RF impedance matching network 11 because it receives multiple inputs from sources such as the RF input sensor 21 and the series variable capacitor 31 and the shunt variable capacitor 33, performs the necessary calculations to determine the changes to the series variable capacitor 31 and the shunt variable capacitor 33, and delivers commands to the series variable capacitor 31 and the shunt variable capacitor 33 to create the impedance matching. The control circuit 45 is a type of control circuit commonly used in semiconductor manufacturing processes and is therefore known to those skilled in the art. The difference of the control circuit 45 compared to the prior art control circuits arises in the programming differences because of the speed at which the RF impedance matching network 11 can perform the switching and impedance matching of the variable capacitors 31, 33.

[0037] The series RF choke and filter circuit 37 and the shunt RF choke and filter circuit 41 are each configured to allow DC signals to pass between the series driver circuit 39 and the shunt driver circuit 43 and the respective series variable capacitor 31 and shunt variable capacitor 33, while blocking RF signals from the RF source 15 and preventing RF signals from leaking to the outputs of the series driver circuit 39 and the shunt driver circuit 43 and the output of the control circuit 45. The series RF choke and filter circuit 37 and the shunt RF choke and filter circuit 41 are of a type known to those skilled in the art.

[0038] Figure 3 is a block diagram of one embodiment of a semiconductor processing system 85A having a pi-configuration matching network 11A, which contrasts with the L-configuration matching network of Figure 2. For ease of understanding, this diagram omits the RF chokes and filters, driver circuits, and power supplies of Figure 2. Where the same reference numbers are used in Figure 3 as those of Figure 2, it will be understood that the associated components may have similar features to those discussed with respect to Figure 2.

[0039] The most notable difference between the L and pi configurations is that the L configuration utilizes a series capacitor 31 and a shunt capacitor 33, while the pi configuration utilizes two shunt capacitors 31A, 33A. Nevertheless, the control circuit can vary the capacitance of these shunt variable capacitors 31A, 33A to provide impedance matching. Each of these shunt variable capacitors 31A, 33A can be an EVC as described above. They can be controlled by chokes, filters, and drivers similar to the method described above with respect to FIG. 2.

[0040] EVC Capacitor Array 4 is a block diagram of one embodiment of an electronic circuit 150 for providing variable capacitance using an electronically variable capacitor 151. The circuit 150 utilizes an EVC 151 that includes two capacitor arrays 151a, 151b. The exemplary first capacitor array 151a includes a first plurality of discrete fixed capacitors, each of which has a first capacitance value. The exemplary second capacitor array 151b includes a second plurality of discrete fixed capacitors, each of which has a second capacitance value. The first capacitance value is different from the second capacitance value such that the EVC 151 provides coarse and fine control of the capacitance generated by the EVC 151. The first and second capacitor arrays are coupled in parallel between the signal input 113 and the signal output 130.

[0041] The first and second capacitance values ​​may be any values ​​sufficient to provide a desired overall capacitance value for the EVC 151. In one embodiment, the second capacitance value is less than or equal to one-half (½) of the first capacitance value. In another embodiment, the second capacitance value is less than or equal to one-third (⅓) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-quarter (¼) of the first capacitance value.

[0042] The electronic circuit 150 further includes a control circuit 145, which may have similar features to the control circuit 45 described above. The control circuit 145 is operably coupled to the first capacitor array 151a and the second capacitor array 151b by a command input 129, which is operably coupled to the first capacitor array 151a and the second capacitor array 151b. In an exemplary embodiment, the command input 129 has a direct electrical connection to the capacitor arrays 151a, 151b, although in other embodiments, this connection may be an indirect connection. The coupling of the control circuit 145 to the capacitor arrays 151a, 151b is described in more detail below.

[0043] The control circuit 145 is configured to vary the variable capacitance of the EVC 151 by controlling the on and off states of (a) each individual fixed capacitor of the first plurality of individual fixed capacitors and (b) each individual fixed capacitor of the second plurality of individual fixed capacitors. As mentioned above, the control circuit 145 can have features similar to those described with respect to the control circuit 45 of the preceding figures. For example, the control circuit 145 can receive inputs from the capacitor arrays 151a, 151b, perform calculations to determine changes to the capacitor arrays 151a, 151b, and deliver commands to the capacitor arrays 151a, 151b to vary the capacitance of the EVC 151. The EVC 151 of FIG. 4 can include multiple electronic switches. Each electronic switch can be configured to activate and deactivate one or more individual capacitors.

[0044] Similar to the control circuit 45 of the previous figure, the control circuit 145 can also be connected to the driver circuit 139 and the RF choke and filter circuit 137. The control circuit 145, the driver circuit 139, and the RF choke and filter circuit 137 can have capabilities similar to those discussed with respect to the previous figure. In an exemplary embodiment, the driver circuit 139 is operably coupled between the control circuit 145 and the first capacitor array 151a and the second capacitor array 151b. The driver circuit 139 is configured to vary the variable capacitance based on a control signal received from the control circuit 145. The RF filter 137 is operably coupled between the driver circuit 139 and the first capacitor array 151a and the second capacitor array 151b. In response to the control signal transmitted by the control unit 145, the driver circuit 139 and the RF filter 137 are configured to transmit a command signal to the command input 129. The command signal is configured to vary the variable capacitance by directing at least one of the electronic switches to activate or deactivate (a) at least one individual capacitor of the first plurality of individual capacitors, or (b) at least one individual capacitor of the second plurality of individual capacitors.

[0045] In an exemplary embodiment, the driver circuit 139 is configured to switch the on or off state of the high voltage source in less than 15 μs, and the high voltage source controls the electronic switches of each of the first and second capacitor arrays to vary the variable capacitance, however, the EVC 151 can be switched by any of the means or speeds discussed in this application.

[0046] The control circuit 145 can be configured to calculate the coarse and fine capacitance values ​​provided by each capacitor array 151a, 151b. In an exemplary embodiment, the control circuit 145 is configured to calculate a coarse capacitance value provided by controlling the on and off states of the first capacitor array 151a. Additionally, the control circuit is configured to calculate a fine capacitance value provided by controlling the on and off states of the second capacitor array 151b. In other embodiments, the capacitor arrays 151a, 151b can provide alternative levels of capacitance. In other embodiments, the EVC can utilize additional capacitor arrays.

[0047] The EVC 151 of FIG. 4 can be used in a variety of systems requiring varying capacitance. For example, the EVC 151 can be used as a series EVC and / or a shunt EVC in an L matching network, or as one or both of the shunt EVCs in a pi matching network. It is often desirable for the difference between the capacitance values ​​to allow both a fine enough resolution of the overall capacitance of the circuit and a wide range of capacitance values ​​to allow better impedance matching at the input of the RF matching network, and the EVC 151 allows this.

[0048] Switching individual capacitors in and out to vary EVC capacitance As mentioned above, an EVC is a type of variable capacitor that can use multiple switches (each of which is used to create an open circuit or a short circuit) along with individual series capacitors to vary the capacitance of the variable capacitor. The switches can be mechanical (such as relays) or solid state (such as PIN diodes, transistors, or other switching devices). Below is a discussion of methods for configuring an EVC or other variable capacitor to provide a varying capacitance.

[0049] In what is sometimes called the "accumulation setup" of an EVC or other variable capacitor, the approach to linearly increasing the capacitor value from a minimum starting point (where all switches are open) is to progressively increase the number of fine tuning capacitors switched into the input to the circuit. Once the maximum number of fine tuning capacitors have been switched into the input to the circuit, the coarse tuning capacitors are switched into the input and the fine tuning capacitors are switched into the output. The process begins again with increasing numbers of fine tuning capacitors switched into the input to the circuit until all fine and coarse tuning capacitors have been switched into the input, at which point another coarse tuning capacitor is switched into the input and a fine tuning capacitor is switched into the output. This process can continue until all coarse and fine tuning capacitors have been switched into the input.

[0050] In this embodiment, all of the fine tuning capacitors have the same or substantially similar values, and all of the coarse tuning capacitors have the same or substantially similar values. Furthermore, the capacitance value of one coarse tuning capacitor is approximately equal to the combined capacitance value of all of the fine tuning capacitors and the additional fine tuning capacitors into the circuit, thus allowing for a linear increase in capacitance. However, the embodiment is not so limited. The fine tuning capacitors (and the coarse tuning capacitors) need not have the same or substantially similar values. Furthermore, the capacitance value of one coarse tuning capacitor need not be equal to the combined capacitance value of all of the fine tuning capacitors and the additional fine tuning capacitors. In one embodiment, the coarse capacitance value and the fine capacitance value have a ratio substantially similar to 10:1. In another embodiment, the second capacitance value is less than or equal to half (1 / 2) of the first capacitance value. In another embodiment, the second capacitance value is less than or equal to one third (1 / 3) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-quarter (1 / 4) of the first capacitance value.

[0051] An example of the above embodiment in an ideal setting is when the fine tuning capacitor is equal to 1 pF and the coarse tuning capacitor is equal to 10 pF. In this ideal setting, when all switches are open, the capacitance is equal to 0 pF. When the first switch is closed, there is 1 pF in the circuit. When the second switch is closed, there is 2 pF in the circuit, and this continues until 9 fine tuning switches are closed, giving 9 pF. Then the first 10 pF capacitor is switched to the input to the circuit and the 9 fine tuning switches are opened, giving a total capacitance of 10 pF. Then the fine tuning capacitor is switched from 11 pF to 19 pF to the input to the circuit. Then another coarse tuning capacitor can be switched to the input to the circuit and all the fine tuning capacitors can be switched to the output from the circuit, giving 20 pF. This process can be repeated until the desired capacitance is reached.

[0052] This can also be taken one step further. Using the previous embodiment with nine 1 pF capacitors and nine 10 pF capacitors, the variable capacitor circuit can have an even larger value of 100 pF to switch the input and output of the circuit. This allows the previous capacitor array to go up to 99 pF, and then the 100 pF capacitor can be used for the next increment. This can be repeated further using larger increments and can also be used with any counting system. According to the cumulative setup, increasing the total capacitance of the variable capacitor is achieved by switching more fine tuning capacitors or fine tuning capacitors to the input than are already switched to the input, without switching the coarse tuning capacitors already switched to the input to the output. Furthermore, when the variable total capacitance increases and the control circuit does not switch more coarse tuning capacitors to the input than are already switched to the input, the control circuit switches more fine tuning capacitors to the input than are already switched to the input, without switching the fine tuning capacitors already switched to the input to the output. U.S. Patent Nos. 10,431,428 and 11,195,698, which relate to cumulative setups, are incorporated herein by reference in their entirety. Note that the claimed invention is not limited to the use of cumulative setups. For example, U.S. Patent Nos. 10,679,824 and 10,692,699, which are incorporated herein by reference in their entirety, discuss alternative configurations such as "partial binary."

[0053] FIG. 5 is a schematic diagram of a variable capacitance system 155 for switching input and output of individual fixed capacitors of an electronically variable capacitor. Where this figure uses reference numbers similar to those of FIG. 4, it is understood that the associated components may have features similar to those discussed in FIG. 4. The variable capacitance system 155 comprises a variable capacitor 151 for providing a varying capacitance. The variable capacitor 151 has an input 113 and an output 130. The variable capacitor 151 includes a plurality of individual fixed capacitors 153 operably coupled in parallel. The plurality of capacitors 153 includes a first (fine tuning) capacitor 151a and a second (coarse tuning) capacitor 151B. Additionally, the variable capacitor 151 includes a plurality of switches 161. One of the switches 161 is operably coupled in series with each of the plurality of capacitors to switch the input and output of each capacitor, thereby enabling the variable capacitor 151 to provide a varying total capacitance. Variable capacitor 151 has a variable total capacitance that increases when an individual capacitor 153 is switched to an input, and decreases when an individual capacitor 153 is switched to an output.

[0054] The switch 161 may be coupled to a switch driver circuit 139 to drive the switch on and off. The variable capacitance system 155 may further include a control unit 145 operably coupled to the variable capacitor 151. In particular, the control unit 145 may be operably coupled to the driver circuit 139 to command the driver circuit 139 to switch one or more of the switches 161, thereby turning one or more of the capacitors 153 on or off. In one embodiment, the control unit 145 may form part of a control unit that controls the variable capacitors (such as a control unit that commands the variable capacitors of a matching network to change capacitance to achieve impedance matching). The driver circuit 139 and the control unit 145 may have features similar to those described above with reference to FIG. 4, and therefore may also utilize RF chokes and filters as discussed above.

[0055] Electronically variable capacitor switching circuit 6 illustrates one embodiment of a switching circuit 140A for the EVC 151 of a matching network, according to one embodiment. In an exemplary embodiment, the EVC 151 is the EVC 151 of FIG. 5, but is not so limited, as the EVC of the present invention can have any of the other features discussed herein, including a different number of individual fixed capacitors 153, and individual fixed capacitors of different values ​​than those discussed with respect to FIG. 5. Furthermore, the EVC can form part of any type of matching network, including the various types of matching networks discussed herein. The exemplary matching network is coupled between an RF source and a plasma chamber, for example, as shown in the previous figures.

[0056] The exemplary EVC comprises a plurality of individual fixed capacitors 153A, 153B coupled to the first terminal 113. Each individual capacitor 153A, 153B has a corresponding switch 161A, 161B configured to switch the individual capacitor in (or "on") and to switch the individual capacitor out (or "off") to vary the total capacitance of the EVC 151. In the exemplary embodiment, the switch 161A is in series with the individual capacitor 153A, but the invention is not so limited. Further, in the exemplary embodiment, the switch 161A is a PIN diode, but the invention is not so limited and may be another type of switch, such as a NIP diode. In still other embodiments, the switch may be a MOSFET, a JFET, or another type of switch. Further, in the exemplary embodiment, the PIN diodes have a common anode configuration such that the anode of each PIN diode 161A, 161B is coupled to ground 40, which may be any common node. However, the invention is not so limited as in other embodiments the EVC may use a common cathode configuration such that the cathode of each PIN diode is tied to ground 40 (and the driver circuit components are changed accordingly). Additionally, it should be noted that two or more switches may be used in series to increase the voltage rating and / or two or more switches may be used in parallel to increase the current rating of a channel.

[0057] Each PIN diode switch 161A, 161B has its own switching circuit 140A, 140B, which is connected to control circuit 145. Switching circuit 140B is shown to include switch 161B, filter 141B (which may be similar to filter circuits 37, 41 discussed above), and driver circuit 139B. Filter 141B may be, for example, an LC circuit similar to filter circuit 9 of U.S. Pat. No. 10,340,879, or the filter circuit by output 207 of FIG. 6A of U.S. Pat. No. 9,844,127. Each of these patents is incorporated herein by reference in its entirety.

[0058] Exemplary switching circuit 140A has the same components as switching circuit 140B, but shows driver circuit 139A in more detail. Driver circuit 139A may be integrated with PIN diode 161A (or other type of switch) or may be integrated with discrete fixed capacitors of the EVC of the matching network. Those skilled in the art will recognize that certain components of driver circuit 139A may be replaced with other components that perform the same essential functions while allowing greater variability in other circuit parameters (e.g., voltage range, current range, etc.).

[0059] The exemplary driver circuit 139A has two inputs 105A-1, 105A-2 for receiving control signals from a control circuit to control the voltage at the common output 107A that is connected to and drives the PIN diode 161A. The voltage at the common output 107A switches the PIN diode 161A between an on state and an off state, and thus switches the individual capacitor 153A to which the PIN diode 161A is connected input / on and output / off. In this exemplary embodiment, the state of the individual capacitor follows the state of the corresponding PIN diode, such that when the PIN diode is on, the individual capacitor is also input / on, and similarly, when the PIN diode 161A is off, the individual capacitor is also output / off. Thus, any description herein of the state of the PIN diode 161A essentially describes the simultaneous state of the corresponding individual capacitor 153A of the EVC 151.

[0060] In a preferred embodiment, each of the first power switch 111A and the second power switch 113A is a MOSFET with a body diode, although in other embodiments, either of the power switches can be another type of switch, including any other type of semiconductor switch. The present invention may utilize a variety of switching circuit configurations. For example, the present invention may utilize any of the switching circuits disclosed in U.S. Patent Application No. 9,844,127 (such as the switching circuits shown in Figures 3, 6A, and 6B) and any of the switching circuits disclosed in U.S. Patent Application No. 10,340,879 (such as the switching circuit shown in Figure 18). As noted above, each of these patents is incorporated herein by reference in its entirety.

[0061] In an exemplary embodiment, the high voltage power supply 115A is connected to the first power switch 111A and provides a high voltage input switchably connected to the common output 107A. The low voltage power supply 117A is connected to the second power switch 113A and provides a low voltage input switchably connected to the common output 107A as well. In the configuration of the driver circuit 139A shown, the low voltage power supply 117A may provide a low voltage input of approximately -3.3V. Such a low voltage, with a negative polarity, is sufficient to provide a forward bias for switching the PIN diode 161A. For other configurations of the driver circuit 139A, higher or lower voltage inputs may be used, and the low voltage input may have a positive polarity, depending on the configuration and type of electronic switch being controlled.

[0062] In the exemplary switching circuit 140A, the first power switch 111A and the second power switch 113A are configured to asynchronously connect the high voltage power supply 115A and the low voltage power supply 117A to the common output 107A for the purpose of switching the PIN diode 161A between an on state and an off state, thereby switching the corresponding individual fixed capacitor 153A in and out. The high voltage power supply 115A provides a reverse bias DC voltage for the PIN diode switch 161A. This may also be referred to as a "blocking voltage" since it reverse biases the PIN diode 161A and therefore prevents current from flowing, thus switching its corresponding individual capacitor 153A to the output. The term "blocking voltage" as used herein refers to any voltage used by a switch to switch its corresponding individual capacitor in and out. It is further noted that the switching circuit is not limited to that shown in FIG. 6, but may be any circuit for switching an individual capacitor in and out, such as the capacitors shown in U.S. Pat. No. 9,844,127, which is incorporated herein by reference in its entirety.

[0063] In an exemplary embodiment, the control circuit provides separate control signals to separate inputs 105A-1, 105A-2 of the driver circuit 139A. In this embodiment, the separate inputs 105A-1, 105A-2 are coupled to the first and second power switches 111A, 113A, respectively. The control signals to the separate inputs may be of opposite polarity. In a preferred embodiment, the first power switch 161A and the second power switch 113A are MOSFETs, and the separate control signals go to separate drivers to power the MOSFETs. In an alternative embodiment, the control circuit 145 provides a common input signal. The common input signal may asynchronously control the on and off states of the first power switch 111A and the second power switch 113A, so that when the first power switch 111A is in an on state, the second power switch 113A is in an off state, and similarly, when the first power switch is in an off state, the second power switch 113A is in an on state. In this manner, the common input signal controls the first power switch 111A and the second power switch 113A to asynchronously connect the high and low voltage inputs to the common output for the purpose of switching the PIN diode 161A between its on and off states, although the invention is not limited to such asynchronous control.

[0064] Inputs 105A-1, 105A-2 may be configured to receive any type of appropriate control signal for the switch types selected for first power switch 111A and second power switch 113A, which may be, for example, a +15V control signal. In a preferred embodiment, the driver circuit has separate drivers for driving each of first power switch 111A and second power switch 112A. In another embodiment, first power switch 111A and second power switch 113A are selected to receive a common input signal.

[0065] In an exemplary embodiment, power supply 118 is coupled to the input of low voltage power supply 117A. In a preferred embodiment, power supply 118 provides 24 VDC, however, the invention is not so limited as other power sources may be utilized.

[0066] In an exemplary embodiment, when the second power switch 113A is on, a current 163A flows between the PIN diode 161A and the low voltage power supply 117A. At the same time, current flows from the power supply 118 to the input of the low voltage power supply 117A and to ground 40. A sensor may be positioned at a node of the switching circuit 140A to measure a parameter associated with the current 163A flowing between the low voltage power supply 117A and the PIN diode switch 161A. In an exemplary embodiment, the sensor 164A is positioned at the input of the low voltage power supply 117A to measure a current 167A flowing from the power supply 118 to the input, which is related to the current 163A. In other embodiments, the sensor may be positioned at other locations of the switching circuit 140A, such as at a location at node 165A (the output of the low voltage power supply) or node 166A (the anode of the PIN diode 161A) or in the path of the filter 141A between the driver circuit and the switch (e.g., at the driver output 107A or the output of the filter 141A). In an exemplary embodiment, the parameter is the value of the current flowing at the node, but in other embodiments, the measured parameter may be any parameter (including voltage) associated with the current flowing through the switch(es), and in yet other embodiments, the parameter is any parameter associated with the driver circuit.

[0067] It should be noted that the matching networks discussed herein may incorporate a bias circuit, such as the bias circuit discussed in PCT / US22 / 23395, filed April 5, 2022, which is incorporated by reference in its entirety. For example, a bias inductor of the bias circuit may be used to switch a fixed discrete capacitor of an EVC into a series position, where the EVC is not grounded.

[0068] Determining Capacitance Values ​​to Achieve Matching FIG. 7 is a flow chart illustrating a process 500A for matching impedance according to one embodiment. The matching network may include components similar to those discussed above. In one embodiment, the matching network of FIG. 3 is utilized. In a first step of the illustrated process 500A of FIG. 7, an input impedance at the RF input 13 is determined (step 501A). The input impedance is based on an RF input parameter detected by an RF input sensor 21 at the RF input 13. The RF input sensor 21 may be any sensor configured to detect an RF input parameter at the RF input 13. The input parameter may be any measurable parameter at the RF input 13, including a voltage, a current, or a phase at the RF input 13. In an exemplary embodiment, the RF input sensor 21 detects the voltage, the current, and the phase at the RF input 13 of the matching network 11. Based on the RF input parameter detected by the RF input sensor 21, the control circuit 45 determines the input impedance.

[0069] Next, the control circuit 45 determines the plasma impedance presented by the plasma chamber 19 (step 502A). In one embodiment, the determination of the plasma impedance is based on the input impedance (determined in step 501A), the capacitance of the series EVC 31, and the capacitance of the shunt EVC 33. In another embodiment, the determination of the plasma impedance can be made using a power sensor 49 operably coupled to the RF output, the RF power sensor 49 configured to detect an RF power parameter. The RF power parameter can be any measurable parameter at the RF output 17, including the voltage, current, or phase at the RF output 17. The RF power sensor 49 may detect the output parameter at the RF output 17 of the matching network 11. Based on the RF power parameter detected by the RF power sensor 21, the control circuit 45 may determine the plasma impedance. In yet another embodiment, the determination of the plasma impedance can be based on both the RF power parameter and the RF input parameter.

[0070] Once the variable impedance of the plasma chamber 19 is known, the control circuit 45 can determine changes to make to the variable capacitance of one or both of the series and shunt EVCs 31, 33 in order to achieve impedance matching. Specifically, the control circuit 45 determines a first capacitance value for the series variable capacitance and a second capacitance value for the shunt variable capacitance (step 503A). These values ​​represent new capacitance values ​​for the series EVC 31 and the shunt EVC 33 to enable impedance matching, or at least substantial impedance matching. In an exemplary embodiment, the determination of the first and second capacitance values ​​is based on the variable plasma impedance (determined in step 502A) and the fixed RF source impedance.

[0071] Once the first and second capacitance values ​​have been determined, the control circuit 45 generates a control signal to change at least one of the series variable capacitance and the shunt variable capacitance to the first capacitance value and the second capacitance value, respectively (step 504A). This occurs at approximately t=-5 μsec. The control signal instructs the switching circuit to change the variable capacitance of one or both of the series EVC 31 and the shunt EVC 33.

[0072] In an exemplary embodiment, the RF source continues to provide an RF signal to the RF input to the matching network while the EVC is being changed. It is not necessary to stop providing the RF signal before changing the EVC. The determination of the new capacitance value and the change in the EVC can be made continuously (and repeatedly) while the RF signal continues to be provided to the matching network.

[0073] The change in EVC 31, 33 takes a total of about 9-11 μs compared to a time of about 1-2 seconds for an RF matching network using VVC. Once the switch to a different variable capacitance is complete, there is a wait period as the additional individual capacitors that make up the EVC couple and charge the circuit. This portion of the match tuning process takes about 55 μs. Finally, RF power profile 403 shows a decrease from a peak-to-peak value of about 380 mV to a peak-to-peak value of about 100 mV just before t=56 μs. This decrease in RF power profile 403, which represents a decrease in reflected power 407, occurs over a period of about 10 μs, at which point the match tuning process is considered complete.

[0074] Varying the series and shunt variable capacitances may include sending control signals to a series driver circuit 39 and a shunt driver circuit 43 to control the series and shunt variable capacitances, respectively, with the series driver circuit 39 operably coupled to the series EVC 31 and the shunt driver circuit 43 operably coupled to the shunt EVC 43. When the EVCs 31, 33 are switched to their desired capacitance values, the input impedance may match a fixed RF source impedance (e.g., 50 ohms), thus providing impedance matching. If sufficient impedance matching does not occur due to variations in plasma impedance, the process of 500A may be repeated one or more times to achieve impedance matching, or at least substantial impedance matching.

[0075] Using an RF matching network 11 (such as that shown in FIG. 3), the input impedance can be expressed as:

number

[0076] In the formula, Z 入力 is the input impedance, and Z P is the plasma impedance, and Z L is the series inductor impedance, Z 直列 is the series EVC impedance, and Z 分路 is the shunt EVC impedance. In an exemplary embodiment, the input impedance (Z 入力 ) is determined using the RF input sensor 21. The EVC impedance (Z 直列 and Z 分路 ) is known at any given time by the control circuitry, since the control circuitry is used to command the various individual fixed capacitors of each of the series and shunt EVCs to turn on or off. Additionally, the series inductor impedance (Z L ) are fixed values. Therefore, the system uses these values ​​to calculate the plasma impedance (Z P ) can be solved.

[0077] This determined plasma impedance (Z P ) and the known desired input impedance (Z´ 入力 ) (typically 50 ohms) and a known series inductor impedance (Z L ) and the system uses a new series EVC impedance (Z´ 直列 ) and shunt EVC impedance (Z´ 分路 ) can be determined.

number

[0078] Newly calculated series EVC variable impedance (Z´ 直列 ) and shunt EVC variable impedance (Z´ 分路 ), the system can determine a new capacitance value for the series variable capacitance (first capacitance value) and a new capacitance value for the shunt variable capacitance (second capacitance value). When these new capacitance values ​​are used in the series EVC 31 and the shunt EVC 33, respectively, impedance matching can be achieved.

[0079] The exemplary method of calculating the desired first and second capacitance values ​​and arriving at those values ​​in one step is significantly faster than moving the two EVCs stepwise to either zero the error signal or minimize the reflected power / reflection coefficient. In semiconductor plasma processing where faster tuning schemes are desired, this approach provides a significant improvement in the tuning speed of the matching network. It should be noted that the methods for determining the new EVC capacitance values ​​discussed herein are merely examples. In other embodiments, other parameters and / or methods may be used to determine the new EVC capacitance values. For example, the parameters on which the new capacitance values ​​are based may be any parameters related to the plasma chamber.

[0080] Determining Capacitance Values ​​Using a Parameter Matrix FIG. 8 provides an alternative process 500 for matching impedance using a parameter matrix. In the exemplary process, control circuitry 45 (see FIG. 3 for matching network components) is configured and / or programmed to perform each of the steps. As one of two initial steps, RF parameters are measured at the RF input 13 by the RF input sensor 21, and the input impedance at the RF input 13 is calculated using the measured RF parameters (step 501). For this exemplary process 500, forward voltage and forward current are measured at the RF input 13. In certain other embodiments, RF parameters may be measured at the RF output 17 by the RF output sensor 49, although in such embodiments different calculations than those described below may be required. In still other embodiments, RF parameters may be measured at both the RF input 13 and the RF output 17.

[0081] The impedance matching circuit coupled between the RF source 15 and the plasma chamber 19 may be characterized by one of several types of parameter matrices known to those skilled in the art, including a two-port parameter matrix. S-parameter matrix and Z-parameter matrix are two examples of such parameter matrices. Other examples include, but are not limited to, Y-parameter matrix, G-parameter matrix, H-parameter matrix, T-parameter matrix, and ABCD-parameter matrix. Those skilled in the art will also recognize that these various parameter matrices may be mathematically transformed into one another for electrical circuits such as matching networks. The second initial step of the exemplary process 500 is to look up the parameter matrix for an existing configuration of the impedance matching circuit in a parameter lookup table (step 502). The existing configuration of the impedance matching circuit is defined by the existing operating parameters of the impedance matching circuit, specifically the existing array configuration for both the series EVC 31 and the shunt EVC 33. To achieve impedance matching, the existing configuration of the impedance matching circuit is changed to a new configuration of the impedance matching circuit as part of the exemplary process 500.

[0082] The parameter lookup table includes multiple parameter matrices, each parameter matrix associated with a particular configuration of the series EVC 31 and the shunt EVC 33. The parameter lookup table may include one or more of the aforementioned types of parameter matrices. In the exemplary process 500, the parameter lookup table includes at least multiple S-parameter matrices. In certain embodiments, the parameter lookup table may include at least multiple Z-parameter matrices. In embodiments in which the parameter lookup table includes multiple types of parameter matrices, the different types of parameter matrices are associated within the parameter lookup table in a manner that eliminates the need for mathematical conversion between the different types of parameter matrices. For example, T-parameter matrices may be included as part of the parameter lookup table, with each T-parameter matrix associated with an associated S-parameter matrix that results from the conversion between the two matrices.

[0083] The input impedance calculation (step 501) and parameter matrix lookup (step 502) may be performed in any order. After the input impedance is calculated (step 501) and the parameter matrix for an existing configuration of the impedance matching circuit is identified in the parameter lookup table (step 502), the plasma or load impedance may be calculated using the calculated input impedance and the parameter matrix for the existing configuration (step 503). Next, from the calculated plasma impedance, matching configurations of the series EVC 31 and the shunt EVC 33 that will achieve impedance matching, or at least substantial impedance matching, between the RF source 15 and the plasma chamber 19 are looked up in the array configuration lookup table (step 504). These matching configurations from the array configuration lookup table are array configurations that result in new capacitance values ​​for the series EVC 31 and the shunt EVC 33, and impedance matching is achieved with the new array configuration and the associated new capacitance values. The array configuration lookup table is a table of array configurations of the series EVC 31 and the shunt EVC 33, and includes each possible array configuration of the series EVC 31 and the shunt EVC 33 when used in combination. As an alternative to using the array configuration lookup table, the actual capacitance values ​​of the EVCs 31, 33 may be calculated during the process, but such real-time calculation of capacitance values ​​is inherently more time consuming than searching for a matching configuration in the array configuration lookup table. After the matching configurations of the series EVC 31 and the shunt EVC 33 are identified in the array configuration lookup table, one or both of the series array configuration and the shunt array configuration are changed to the identified matching configuration of the series EVC 31 and the shunt EVC 33, respectively (step 505).

[0084] Changing the series and shunt array configurations (step 505) may include the control circuit 45 sending control signals to the series driver circuit 39 and the shunt driver circuit 43 to control the series and shunt array configurations, respectively, with the series driver circuit 39 operably coupled to the series EVC 31 and the shunt driver circuit 43 operably coupled to the shunt EVC 43. When the EVCs 31, 33 are switched to the matched configuration, the input impedance may match a fixed RF source impedance (e.g., 50 ohms), thus providing impedance matching. If sufficient impedance matching does not occur due to variations in the plasma impedance, the process of 500 may be repeated one or more times to achieve impedance matching, or at least substantial impedance matching.

[0085] The look-up tables used in the above process are compiled prior to the RF matching network being used in conjunction with the plasma chamber 19. In creating the look-up tables, the RF matching network 11 is tested prior to use in the plasma chamber to determine at least one parameter matrix of each type and load impedance associated with each array configuration of the series EVCs 31 and shunt EVCs 33. The parameter matrices resulting from the testing are compiled into a parameter look-up table such that at least one parameter matrix of each type is associated with the respective array configuration of the EVCs 31, 33. Similarly, the load impedances are compiled into an array configuration look-up table such that each parameter matrix is ​​associated with the respective array configuration of the EVCs 31, 33. The compiled look-up tables may take into account a fixed RF source impedance (e.g., 50 ohms), the power output of the RF source, and the operating frequency of the RF source, among other factors related to the operation of the RF matching network. Thus, each look-up table may have tens of thousands or more entries to account for all possible configurations of the EVCs 31, 33. The number of possible configurations is determined primarily by the number of individual fixed capacitors that make up each of the EVCs 31, 33. In compiling the look-up table, possible safety limitations, such as maximum allowable voltages and currents at critical points in the matching network, can be taken into account, which may serve to exclude one or more entries in the look-up table for a particular configuration of the EVCs 31, 33.

[0086] As is known in the art, an S-parameter matrix is ​​made up of components called scattering parameters, or S-parameters for short. The S-parameter matrix of an impedance matching circuit consists of four S-parameters: S 11 , S 12 , S 21 , S 22, each of which represents the ratio of the voltages at the RF input 13 and the RF output 17. All four of the S-parameters of the impedance matching circuit are pre-determined and / or calculated such that the entire S-parameter matrix is ​​known. Parameters of other types of parameter matrices may be similarly pre-determined and / or calculated and incorporated into the parameter matrix. For example, the Z-parameter matrix of the impedance matching circuit may be determined in advance and / or calculated, and incorporated into the parameter matrix. 11 , Z 12 , Z 21 , Z 22 has.

[0087] By compiling the parameter lookup table in this manner, the entire time cost of a particular calculation is incurred during a testing phase of the RF matching network, and not during actual use of the RF matching network 11 with the plasma chamber 19. Furthermore, because looking up a value in a lookup table may take less time than calculating that same value in real time, using the lookup table may help reduce the overall time required to achieve an impedance match. In a plasma deposition or etch process that potentially involves hundreds or thousands of impedance matching adjustments throughout the process, this time savings may translate directly into cost savings in the overall manufacturing process.

[0088] From the start of the match tuning process, which begins with the control circuit determining the variable impedance of the plasma chamber and determining the series and shunt match configuration, to the end of the match tuning process, where the RF power reflected back toward the RF source is reduced, the entire match tuning process of the RF impedance matching network using the EVC has an elapsed time of about 110 μs, or about 150 μs or less. This short elapsed time for a single iteration of the match tuning process represents a significant increase over the VVC matching network. Furthermore, because of this short elapsed time for a single iteration of the match tuning process, the RF impedance matching network using the EVC may perform the match tuning process iteratively, repeating the two determination steps to generate another control signal for further change of the array configuration of one or both of the electronically variable capacitors. By iteratively repeating the match tuning process, it is expected that a better impedance match may be created within about 2 to 4 iterations of the match tuning process. Furthermore, it is expected that 3 to 4 iterations may be performed in 500 μs or less, depending on the duration of each iteration of the match tuning process. Considering the 1-2 second matching time for a single iteration of the matching tuning process for an RF impedance matching network using VVC, this ability to perform multiple iterations in a fraction of the time represents a significant advantage of an RF impedance matching network using EVC.

[0089] Those skilled in the art will recognize that several factors may contribute to the sub-millisecond elapsed time of the impedance matching process of an RF impedance matching network using an EVC. These factors may include the power of the RF signal, the configuration and design of the EVC, the type of matching network used, and the type and configuration of the driver circuit used. Other factors not listed may also contribute to the overall elapsed time of the impedance matching process. Therefore, the duration of the entire match tuning process for an RF impedance matching network with an EVC is expected to be about 500 μs or less to complete from the start of the process (i.e., measuring by the control circuit and calculating the adjustments required to create the impedance match) to the end of the process (the point at which the efficiency of the RF power coupled into the plasma chamber increases due to the impedance match and reduced reflected power). Even with a match tuning process on the order of 500 μs, this process time still represents a significant improvement over an RF impedance matching network using a VVC.

[0090] Table 1 presents data comparing the operating parameters of one example of an EVC with the operating parameters of one example of a VVC. As can be seen, the EVC offers several advantages in addition to allowing fast switching for an RF impedance matching network. [Table 1]

[0091] As can be seen, in addition to the high speed switching capabilities enabled by EVCs, EVCs also provide reliability advantages, current handling advantages, and size advantages. Further advantages of EVCs and / or RF impedance matching networks using the switching circuitry itself for EVCs include: Because the disclosed RF impedance matching network does not contain any moving parts, the possibility of mechanical failure is reduced to that of other complete electrical circuits that may be used as part of a semiconductor manufacturing process. For example, a typical EVC may be formed from a durable ceramic substrate with copper metallization to form individual capacitors. The elimination of moving parts also increases resistance to breakdown due to thermal variations during use. EVCs are compact in size compared to VVCs, and the resulting weight and volume reduction can save valuable space within manufacturing facilities. · The design of EVCs provides an increased ability to customize RF matching networks for the specific design needs of a particular application. EVCs may be configured with custom capacitance ranges, one example of which is a non-linear capacitance range. Such custom capacitance ranges can provide better impedance matching for a wider range of processes. As another example, custom capacitance ranges may provide more resolution in a particular region of impedance matching. Custom capacitance ranges may also allow for the generation of higher ignition voltages for easier plasma strike. The short match tuning process (approximately 500 μsec or less) allows the RF impedance matching network to better withstand plasma changes within the manufacturing process, thereby increasing plasma stability and resulting in more controlled power to the manufacturing process. · The use of digitally controlled EVCs rather than mechanical devices in RF impedance matching networks provides more opportunities to fine-tune the control algorithm through programming. · EVC exhibits superior low frequency (kHz) performance compared to VCC.

[0092] Clamp circuit for EVC switching circuit As mentioned above, PIN diodes may be used as solid-state switches in RF matching networks. (It is understood that the discussion of PIN diodes herein may also apply to NIP diodes.) PIN diodes can be in an on or off state. A forward bias current may be used to turn on the PIN diode switch. In high power applications, this current may be, for example, 0.5 A. This forward bias current may place the PIN diode in a low resistance conducting state. In the off or blocking state, the PIN diode may receive a reverse voltage from the cathode to the anode that is greater than the peak RF potential of the circuit. This ensures that the PIN diode remains in a reverse bias state and does not conduct forward. A driver circuit provides the forward and reverse bias voltages. Such a driver circuit 139A is shown in FIG. 6 above.

[0093] Referring again to FIG. 6, the PIN diode switch 161A switches the capacitor 153A. In this embodiment, a common anode-shunt RF switch configuration is used, but the invention is not so limited. In the driver circuit 139A, the first power switch 111A is turned on and the second power switch 113A is turned off, placing the PIN diode in an off or blocked state. This applies a potential from the HV power supply 115A to the PIN diode 161A cathode. In one embodiment, the HV power supply 115A is 1200V. If the peak RF potential at the fixed capacitor 153A is less than the voltage at the HV power supply 115A, the PIN diode will not conduct and will remain in an off state.

[0094] During the on or conductive state, the first power switch 111A is off and the second power switch 113A is on. This allows current to flow through the diode 161A, the filter 141A, the second power switch 113A to the LV power supply 117A. In this embodiment, the LV power supply 117A is a forward biased power supply. It may be, for example, −3.3V. When in the on state, RF current can flow through the diode 161A and the fixed capacitor 153A.

[0095] In an exemplary embodiment, filter 141A comprises a resistor and an inductor in series, similar to resistor R2 and inductor L1 of FIG. 9, which will be discussed in more detail below, although the filter is not so limited. Filter 141A is between driver circuit 139A and PIN diode switch 161A. The filter blocks RF voltage and current from driver circuit 139A at PIN diode switch 161A. A series limiting resistor may also be used to control the amount of forward bias current. The filter circuit typically consists of an inductor that has a large inductive reactance at the RF operating frequency. The inductor of filter 141A stores energy defined by the following equation:

number

[0096] where L is the inductance of the filter in henries, I is the forward bias current in amps, and E is in joules. This energy is released into the circuit when it goes from an on state to an off state.

[0097] When the flow of current through an inductor is suddenly interrupted, the back EMF therein attempts to keep the current constant. During this time, the voltage across the inductor is defined as

number

[0098] where V is the voltage across the inductor in volts, L is the inductance of the filter in henries,

number

[0099] PIN diodes have a breakdown voltage rating from cathode to anode. If the rating is exceeded, the device will avalanche and be irreversibly damaged. If the circuit described above creates a voltage during an on-to-off transition that exceeds the breakdown voltage of the PIN diode from cathode to anode, the PIN diode will avalanche and fail. During circuit operation in the presence of RF, the RF potential is superimposed on the ringing described in the previous section above. This increases the likelihood that the PIN diode will avalanche. Thus, the potential created by the inductor ringing does not need to exceed the breakdown voltage from cathode to anode for it to be an issue. The first power switch 111A and the second power switch 113A are switched quickly to minimize switching losses. The inductor of the filter 141A is large to block the RF current, and the bias current in the PIN diode is sufficient to keep losses low. In such a switching circuit, a snubber circuit may be placed at the output of the filter inductor to ground. This would consist of a large capacitor and a series resistor. This will dissipate the energy stored in the inductor and minimize ringing. However, this type of circuit is not ideal for PIN diode switch applications. For a PIN diode to be a good RF switch, it is generally desirable for it to have a low capacitance in the off state. Adding a large capacitor across it to dissipate the stored inductor energy may compromise the isolation properties of the PIN diode switch. All these constraints make it very difficult to eliminate inductor ringing.

[0100] (Circuit simulation without clamp circuit) 9 is a simulation schematic diagram of a switching circuit 140A-1 without a clamp circuit according to one embodiment. The schematic diagram is similar to that shown in FIG. 6. V1 corresponds to the HV power supply 115A, M1 corresponds to the first power switch 11A, V4 corresponds to the LV power supply 117A, M2 corresponds to the second power switch 113A, D1 corresponds to the diode 161A, C1 corresponds to the fixed capacitor 153A, and R2 and L1 collectively correspond to the filter 141A. In this example, V1 is 1200V and V4 is -3.3V.

[0101] 10A-D show waveforms of the circuit simulation of FIG. 10 during the on-to-off transition of the driver circuit. The on-to-off transition is shown in the left third of the plot at approximately 45 milliseconds. The plot in FIG. 10A shows the drive signals going to M1 (M1 drive signal 201) and M2 (M2 drive signal 202). Initially M2 is on and M1 is off. Then M2 turns off and M1 remains off. This is defined as the dead time. After the dead time M1 turns on, M2 remains off. This is the off state of the driver circuit.

[0102] As soon as M2 is turned off, the current through L1 stops. The rate of change of the current is directly controlled by the switching speed of M2. The plot in FIG. 10B shows the current through M2 (waveform 203). It is clearly visible where the current is turned off. The plot in FIG. 10C shows the inductor L1 current (waveform 204). During the on state, the current is less than 0.5A. After it is turned off, the energy stored in the inductor L1 is transferred to the circuit capacitance. The current continues to ring at the natural resonant frequency of the circuit until all the energy in the inductor is dissipated. The plot in FIG. 10D shows the voltage across the cathode to anode of the PIN diode D1 (waveform 205). When the circuit is on, the voltage across the diode D1 is less than 1V and is defined by the forward VI characteristic of the diode. When the diode D1 is switched off, the voltage increases rapidly, in this case exceeding the 3kV voltage breakdown of the diode in the circuit. The diode avalanches. This can be seen in FIG. 10D where the diode voltage peak is flat on top.

[0103] Figure 11 is a closer view of the PIN diode avalanche waveform 205 of Figure 10D. It more clearly shows the avalanche event 206. The upper limit of the first cycle 205-1 of the ringing 205 is 3 kV. This is the reverse breakdown voltage of the diode. The diode will be damaged.

[0104] (Switching circuit with clamp circuit) FIG. 12 is a schematic diagram of a portion 140A-2 of the switching circuit 140A of FIG. 6 with the addition of a clamp circuit 124A to prevent PIN diode avalanche. Where similar reference numbers are used, it is understood that components may have the same features as those described with respect to FIG. 6. The main difference with respect to FIG. 6 is the addition of the clamp circuit 124A. The clamp circuit 124A is operably coupled between the filter 141A and the switch 161A, and the clamp circuit comprises a diode 126A having a first terminal 126A-1 operably coupled to the clamp power supply 128A and a second terminal 126A-2 operably coupled to a terminal 141A-2 of the filter 141A. In this embodiment, the diode 126A is a PIN diode. The diode 126A may alternatively be a NIP diode, an ultrafast diode, or another blocking device configured to block voltage in one direction and conduct in the other direction. In a preferred embodiment, the diode is fast enough to clamp the ringing and has a low enough off-state capacitance (e.g., a few picofarads) so as not to affect the off-state shielding of the switch or otherwise affect the RF characteristics of the circuit.

[0105] In the exemplary embodiment, the first terminal 126A-1 of the diode is the cathode and the second terminal 126A-2 of the diode is the anode, although the invention is not so limited, as will be understood by one of ordinary skill in the art. The node between the fixed capacitor 153A and the switch 161A is identified by node 144A. Note that if a NIP diode were used, certain adjustments would be necessary. For example, the positioning of the diode 161-A would be reversed. The power supplies 115A, 117A (see FIG. 6) would be swapped. In this embodiment, the forward bias 117A would be positive instead of negative, and the high voltage supply 115A would be negative instead of positive. The clamp diode 126A would be reversed in direction and tied to the negative clamp supply instead of positive. Those of ordinary skill in the art would understand such necessary modifications to the circuit to accommodate the NIP diode.

[0106] In this embodiment, the second terminal 126A-2 of the diode 126A of the clamp circuit 124A is electrically connected between the filter 141A, the fixed capacitor 153A, and the switch 161A. Further, the filter 141A includes an inductor 143A and a resistor 142A coupled in series. However, it is understood that the invention is not so limited. For example, the resistor 142A may be omitted. Furthermore, the inductor 143A may have a capacitor in parallel therewith to form a resonant filter, as described in U.S. Patent Application No. 17 / 723,702, filed April 19, 2022, which is incorporated herein by reference in its entirety.

[0107] The voltage of the clamp power supply 128A can be set to a safe level below the avalanche rating of the PIN diode 161A. In a preferred embodiment, the voltage of the clamp power supply is greater than the high voltage power supply 115A to prevent the clamp diode from shorting out the high voltage power supply. This keeps the clamp diode reverse biased during normal operation. The clamp circuit 124A limits the maximum voltage at the filter output 141A-2 to a value equal to the voltage of the clamp power supply 128A plus the forward drop of the diode. This circuit clamps both the RF potential and circuit ringing to a maximum value equal to the voltage of the clamp power supply 128A.

[0108] (Circuit simulation with clamp circuit) Figure 13 is a simulation schematic diagram of a switching circuit 140A-2 utilizing a clamp circuit similar to that shown in Figure 12. D2 corresponds to diode 126A, V5 corresponds to clamp power supply 128A, filter inductor L1 corresponds to inductor 143A, and filter resistor R2 corresponds to resistor 142A.

[0109] In this simulation, the component values ​​are similar to those of the simulation schematic of FIG. 9. With the clamp circuit added, V5 is 2500V. FIGS. 14A-D show the same waveforms as FIGS. 10A-D, but for the simulation schematic 13 including the clamp circuit. The plot in FIG. 14A shows the drive signals going to M1 (M1 drive signal 207) and M2 (M2 drive signal 208). The plot in FIG. 14B shows the current through M2 (waveform 209). The plot in FIG. 14C shows the inductor L1 current (waveform 210). The plot in FIG. 14D shows the voltage across the PIN diode D1 from cathode to anode (waveform 211), where the maximum voltage across the PIN diode is 2500V. This was the value chosen for V5.

[0110] Figure 15 is a close-up of the PIN diode clamp waveform 211 of Figure 14D, showing the voltage across the PIN diode D1 when the clamp circuit is present. The waveform in Figure 15 looks like that of Figure 11. Both have a choppy sine waveform. The main difference is that the choppy 206 in Figure 11 is due to the avalanche of D1, while the choppy 213 in Figure 15 is due to the activation of the clamp circuit.

[0111] Finally, it should be noted that the clamp circuits described above may also be used to clamp RF overshoots from an RF source, such as RF source 15 in FIGS. 1-3. These clamp circuits would prevent large RF overshoots from the RF source from damaging the PIN / NIP diode switches of the switching circuit. Excess RF energy is dumped into the clamp power supply. Overshoot from the RF source may occur during tuning of the matching network. This can cause the RF source to go into and out of foldback. When the RF source comes out of foldback, it may overshoot significantly. The variations on the clamp circuits described above in the context of the switching circuit may also be applied to clamp circuits used to clamp RF overshoots.

[0112] It should be noted that while the matching network embodiments discussed herein have used an L or pi configuration, the claimed matching networks may be configured in other matching network configurations, such as a "T" configuration. Unless otherwise noted, the variable capacitors, switching circuits, and methods discussed herein may be used in any configuration suitable for an RF impedance matching network.

[0113] It should be noted that while the embodiments discussed herein use one or more variable capacitors in a matching network to achieve impedance matching, any variable reactance element can be used. The variable reactance element can include one or more discrete reactance elements, which can be capacitors or inductors or similar reactive devices.

[0114] This application incorporates by reference the entireties of commonly owned U.S. Patent No. 10,460,912, U.S. Patent Publication No. US2021 / 0327684, U.S. Patent Publication No. US2021 / 0327684, and U.S. Patent No. 10,984,985.

[0115] Although the present invention has been described in terms of specific examples, including currently preferred implementations of the invention, those skilled in the art will appreciate that there are numerous variations and modifications of the above-described systems and techniques. It is to be understood that other embodiments may be utilized, and structural and functional modifications may be made, without departing from the scope of the present invention. Thus, the spirit and scope of the present invention should be construed broadly as set forth in the appended claims.

Claims

1. A radio frequency (RF) impedance matching circuit, comprising: an RF input configured to be operably connected to an RF source that provides an RF signal; an RF output configured to be operably connected to a plasma chamber; at least one electronically variable capacitor (EVC), each EVC of the at least one EVC comprising a fixed capacitor, each of the fixed capacitors having a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC; a control circuit configured to cause the switching of the input and output of the fixed capacitor of each EVC to enable impedance matching; and for each switching circuit of each EVC, a switch including a PIN diode or a NIP diode; a driver circuit operably connected to the switch; a filter operably connected between the driver circuit and the switch; a clamp circuit operably connected between the filter and the switch, the clamp circuit comprising a blocking device having a first terminal operably connected to a clamp power supply and a separate second terminal operably connected to a terminal of the filter.

2. The matching circuit according to claim 1, wherein for each switching circuit, the blocking device of the clamp circuit is a PIN diode or a NIP diode.

3. The matching circuit according to claim 1 or 2, wherein for each switching circuit, the blocking device of the clamp circuit has a low off-state capacitance so as not to affect the insulation of the off state of the switch.

4. The matching circuit according to claim 1, wherein for each switching circuit, the second terminal of the blocking device of the clamp circuit is electrically connected between the filter, the fixed capacitor, and the switch.

5. The matching circuit according to claim 1, wherein for each switching circuit, the filter comprises an inductor.

6. The matching circuit according to claim 5, wherein the filter comprises the inductor and a resistor connected in series.

7. For each switching circuit, the driver circuit, A first power switch configured to receive a reverse bias voltage and to be switchably connected to a common output the received reverse bias voltage in response to a received input signal; A second power switch configured to receive a forward bias voltage and to be switchably connected to a common output the received forward bias voltage in response to a received input signal, and A first terminal of a resonance filter is electrically connected to the common output, and A second terminal of the resonance filter, different from the first terminal of the resonance filter, is electrically connected to both a terminal of the cutoff device of the clamp circuit and a node between the fixed capacitor and the switch. The matching circuit according to claim 1.

8. For each switching circuit, a DC current flows from the forward bias voltage through the switch to switch the switching circuit on, thereby switching the corresponding fixed capacitor to the input. The matching circuit according to claim 7.

9. The forward bias voltage and the switch are operably connected to a common ground. The matching circuit according to claim 8.

10. A method of impedance matching, comprising: Connecting an RF input of a matching circuit to an RF source that provides an RF signal; and Connecting an RF output of the matching circuit to a plasma chamber, wherein the matching circuit At least one electronically variable capacitor (EVC), each EVC of the at least one EVC comprising a fixed capacitor, each of the fixed capacitors having a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC; A control circuit configured to cause the switching of the input and output of the fixed capacitor of each EVC to enable impedance matching; and Each switching circuit for each fixed capacitor of each EVC comprises A switch including a PIN diode or a NIP diode; A driver circuit operably connected to the switch; and A filter operably connected between the driver circuit and the switch; A clamping circuit operably connected between the filter and the switch, the clamping circuit comprising a blocking device having a first terminal operably connected to a clamping power supply and a separate second terminal operably connected to a terminal of the filter. A method including impedance matching by at least one of the switching circuits of the at least one EVC and switching the input and output of the corresponding fixed capacitor to change the total capacitance of the EVC. **Claim 11** The method according to claim 10, wherein for each switching circuit, the blocking device of the clamping circuit is a PIN diode or a NIP diode. **Claim 12** The method according to claim 10 or 11, wherein for each switching circuit, the blocking device of the clamping circuit has a low off-state capacitance so as not to affect the insulation in the off state of the switch. **Claim 13** The method according to claim 12, wherein for each switching circuit, the second terminal of the blocking device of the clamping circuit is electrically connected between the filter, the fixed capacitor, and the switch. **Claim 14** The method according to claim 10, wherein the filter comprises an inductor and a resistor connected in series. **Claim 15** A semiconductor processing tool, A plasma chamber configured to deposit material on a substrate or etch material from the substrate, An impedance matching circuit operably connected to the plasma chamber, the impedance matching circuit comprising: An RF input configured to be operably connected to an RF source that provides an RF signal, An RF output configured to be operably connected to the plasma chamber, At least one electronically variable capacitor (EVC), each EVC of the at least one EVC comprising a fixed capacitor, each of the fixed capacitors having a corresponding switching circuit for switching the input and output of the fixed capacitor to change the total capacitance of the EVC, A control circuit configured to cause the switching of the input and output of the fixed capacitor of each EVC to enable impedance matching, For each switching circuit for each fixed capacitor of each EVC, A switch including a PIN diode or an NIP diode, A driver circuit operably connected to the switch, A filter operably connected between the driver circuit and the switch, A clamp circuit operably connected between the filter and the switch, the clamp circuit comprising a cutoff device having a first terminal operably connected to a clamp power supply and a separate second terminal operably connected to a terminal of the filter. A semiconductor processing tool comprising the clamp circuit.

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