A package including an integrated device and a bridge connecting a top surface of the integrated device - Patent 7023635

Abstract

The package includes a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge, and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top of the first integrated device and to a top of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 357,811, filed in the U.S. Patent and Trademark Office on June 24, 2021, the entire contents of which are incorporated herein by reference for all applicable purposes as if fully set forth below.

[0002] Various features relate to a package that contains the integrated device. [Background technology]

[0003] A package may include a substrate and several integrated devices. The integrated devices may communicate with each other through the substrate. That is, electrical input and output signals may travel between the integrated devices through the substrate. The performance of the package may relate to how fast these electrical signals may travel between the integrated devices and / or the integrity of the signals between the integrated devices. There is currently a need to provide better performing packages. Summary of the Invention [Means for solving the problem]

[0004] Various features relate to a package that contains the integrated device.

[0005] One example provides a package including a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge, and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top of the first integrated device and to a top of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0006] Another example provides an apparatus including a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a means for a first bridge interconnection, and a means for a second bridge interconnection. The means for the first bridge interconnection is coupled to the first integrated device and the second integrated device. The means for the first bridge interconnection is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The means for the first bridge interconnection is coupled to a top of the first integrated device and to a top of the second integrated device. The means for the second bridge interconnection is coupled to the first integrated device and the second integrated device. The means for the second bridge interconnection is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0007] Another example provides a method for manufacturing a package. The method includes providing a substrate. The method includes bonding a first integrated device to the substrate. The method includes bonding a second integrated device to the substrate. The method includes bonding a first bridge to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top of the first integrated device and to a top of the second integrated device. The method includes bonding a second bridge to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0008] Various features, nature and advantages may become apparent from the detailed description set forth below when read in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a cross-sectional side view of a package including a bridge coupled to an integrated device. [Diagram 2] 13 is a cross-sectional side view of another package including a bridge coupled to an integrated device. [Diagram 3] 13 is a cross-sectional side view of another package including a bridge coupled to an integrated device. [Figure 4] FIG. 13 is a cross-sectional side view of another package including a bridge coupled to stacked dies. [Diagram 5] FIG. 2 is a cross-sectional side view of a bridge die. [Figure 6] FIG. 2 is a cross-sectional side view of a bridge structure. [Figure 7] 1 is an example graph of signal integrity for signals between integrated devices using a non-bridge connection. [Figure 8] 1 is an example graph of signal integrity for signals between integrated devices using a bridge connection. [Figure 9A]1A-1C illustrate an exemplary sequence for manufacturing a package including a bridge coupled to an integrated device. [Figure 9B] 1A-1C illustrate an exemplary sequence for manufacturing a package including a bridge coupled to an integrated device. [Figure 9C] 1A-1C illustrate an exemplary sequence for manufacturing a package including a bridge coupled to an integrated device. [Figure 10] 1 illustrates an example flow diagram of a method for manufacturing a package that includes a bridge coupled to an integrated device. [Figure 11A] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 11B] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 11C] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 12] 1 illustrates an example flow diagram of a method for manufacturing a substrate. [Figure 13] FIG. 1 illustrates various electronic devices that may integrate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are given to enable a thorough understanding of various aspects of the disclosure. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the disclosure.

[0011] The present disclosure describes a package including a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge, and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top of the first integrated device and to a top of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device. The second bridge may be at least partially disposed within the substrate. The second bridge may be disposed above the substrate. The first integrated device may include one or more dies. The second integrated device may include one or more dies. The package may provide better signal integrity for input / output signals between the integrated devices, resulting in a better performing package.

[0012] Exemplary Package Including a Bridge Coupled to an Integrated Device 1 shows a cross-sectional side view of a package 100 including a substrate 102, an integrated device 105 (e.g., a first integrated device), an integrated device 107 (e.g., a second integrated device), a bridge 110, and a bridge 130. Package 100 is coupled to a board 106 through a number of solder interconnects 124. Board 106 may include a printed circuit board (PCB).

[0013] The substrate 102 includes at least one dielectric layer 120 and a number of interconnects 122. Different substrates may have different numbers of metal layers. Different implementations may use different substrates for the substrate 102. The substrate 102 may include an embedded trace substrate (ETS), a laminate substrate, a coreless substrate, and / or a cored substrate. The substrate 202 may be manufactured using a variety of processes including an ETS process, a semi-additive process (SAP), and / or a modified semi-additive process (mSAP).

[0014] The bridge 130 may be at least partially located within the substrate 102. In some implementations, the bridge 130 may be located within a cavity in the substrate 102. The bridge 130 may be embedded within the substrate 102. The bridge 130 may be a second bridge. The bridge 130 may include at least one bridge interconnect 132. As described further below, the bridge 130 may include a bridge die and / or a bridge structure. The bridge 130 may be a means for a second bridge interconnect. In some implementations, the bridge 130 may be located on top of the substrate 102. In some implementations, the bridge 130 may not be located within the substrate 102.

[0015] The integrated device 105 is coupled to the substrate 102 through a plurality of solder interconnects 154. The integrated device 105 is also coupled to the bridge 130 through at least one solder interconnect 154a from the plurality of solder interconnects 154. The integrated device 107 is coupled to the substrate 102 through a plurality of solder interconnects 174. The integrated device 107 is also coupled to the bridge 130 through at least one solder interconnect 174a from the plurality of solder interconnects 174. The bridge 130 may be configured to provide at least one second electrical path between the integrated device 105 and the integrated device 107. For example, the at least one second electrical path between the integrated device 105 and the integrated device 107 may include at least one solder interconnect 154a, at least one bridge interconnect 132, and / or at least one solder interconnect 174a.

[0016] The bridge 110 may be coupled to the top of the integrated device 105 through at least one solder interconnect 125. The bridge 110 may also be coupled to the top of the integrated device 107 through at least one solder interconnect 127. The bridge 110 may be a first bridge. The bridge 110 may include at least one bridge interconnect 112. As described further below, the bridge 110 may include a bridge die and / or a bridge structure. The bridge 110 may be a means for a first bridge interconnect. The bridge 110 may be configured to provide at least one first electrical path between the integrated device 105 and the integrated device 107. For example, the at least one first electrical path between the integrated device 105 and the integrated device 107 may include at least one solder interconnect 125, at least one bridge interconnect 112, and / or at least one solder interconnect 127. In some implementations, one or more input / output (I / O) signals between the integrated device 105 and the integrated device 107 may be configured to travel through the bridge 110 (e.g., configured to travel through at least one solder interconnect 125, at least one bridge interconnect 112, and at least one solder interconnect 127). In some implementations, the input / output signals traveling through the bridge 110 may have better signal integrity because the path is located further away from interconnects configured as electrical paths for other currents (e.g., power). In some implementations, the bridge 110 provides a short electrical path between the integrated device 105 and the integrated device 107, thus providing improved package performance. In some implementations, the bridge 110 opens up solder interconnects to the substrate to be used for power and / or ground, resulting in improved power distribution network (PDN) performance. In some implementations, signals between integrated device 105 and integrated device 107 may be configured to travel through a back surface of integrated device 105 and / or a back surface of integrated device 107. In some implementations, the top of integrated device 105 may include the back surface of integrated device 105.In some implementations, the top of the integrated device 107 may include a back surface of the integrated device 107. The back surface of the integrated device may be a side of the integrated device that includes a substrate (e.g., silicon). The front surface of the integrated device may be a side opposite the back surface of the integrated device.

[0017] 2 shows a cross-sectional side view of a package 200 that includes a substrate 102, an integrated device 105 (e.g., a first integrated device), an integrated device 107 (e.g., a second integrated device), a bridge 110, and a bridge 130. Package 200 is similar to package 100. However, bridge 110 and bridge 130 may be coupled to integrated device 105 and integrated device 107 through multiple pillar interconnects.

[0018] The integrated device 105 is coupled to the substrate 102 through a plurality of pillar interconnects 254 and a plurality of solder interconnects 154. The integrated device 105 is coupled to the bridge 130 through at least one pillar interconnect 254a and at least one solder interconnect 154a. The integrated device 107 is coupled to the substrate 102 through a plurality of pillar interconnects 274 and a plurality of solder interconnects 174. The integrated device 107 is coupled to the bridge 130 through at least one pillar interconnect 274a and at least one solder interconnect 174a. At least one second electrical path between the integrated device 105 and the integrated device 107 may include at least one pillar interconnect 254a, at least one solder interconnect 154a, at least one bridge interconnect 132 (of the bridge 130), at least one pillar interconnect 274a, and / or at least one solder interconnect 174a.

[0019] The bridge 110 is coupled to a top of the integrated device 105 through at least one pillar interconnect 225 and at least one solder interconnect 125. The bridge 110 is coupled to a top of the integrated device 107 through at least one pillar interconnect 227 and at least one solder interconnect 127. At least one first electrical path between the integrated device 105 and the integrated device 107 may include at least one solder interconnect 125, one pillar interconnect 225, at least one bridge interconnect 112 (of the bridge 110), at least one pillar interconnect 227, and / or at least one solder interconnect 127.

[0020] As described further below, integrated device 105 may include one or more integrated devices (e.g., dies). Similarly, integrated device 107 may include one or more integrated devices (e.g., dies).

[0021] FIG. 3 shows a cross-sectional side view of a package 300 that includes a substrate 102, an integrated device 305 (eg, a first integrated device), an integrated device 307 (eg, a second integrated device), a bridge 110, and a bridge 130.

[0022] The integrated device 305 may be a package including a first die 351, a second die 353, and an encapsulation layer 356. The first die 351 and / or the second die 353 may be examples of an integrated device. The second die 353 may be coupled to the first die 351 through a plurality of solder interconnects 354. The first die 351 may be disposed on (e.g., above) the second die 353. The encapsulation layer 356 may be disposed between the first die 351 and the second die 353. In some implementations, the encapsulation layer 356 may at least partially encapsulate the first die 351 and / or the second die 353. The integrated device 305 is coupled to the substrate 102 and the bridge 130 through a plurality of solder interconnects 154.

[0023] As described further below, the first die 351 and the second die 353 may be aligned and positioned in various orientations within the integrated device 305. The first die 351 may include a front side and a back side. The second die 353 may also include a front side and a back side. In some implementations, the front side of the first die 351 may face the front side of the second die 353. In some implementations, the front side of the second die 353 may face the back side of the first die 351. In some implementations, the back side of the second die 353 may face the front side of the first die 351. The back side of the die may be the side of the die that includes the die substrate (e.g., silicon). The front side of the die may be the side opposite the back side of the die.

[0024] The integrated device 307 may be a package including a third die 371, a fourth die 373, and an encapsulation layer 376. The third die 371 and / or the fourth die 373 may be examples of an integrated device. The fourth die 373 may be coupled to the third die 371 through a plurality of solder interconnects 374. The third die 371 may be disposed on (e.g., above) the fourth die 373. The encapsulation layer 376 may be disposed between the third die 371 and the fourth die 373. In some implementations, the encapsulation layer 376 may at least partially encapsulate the third die 371 and / or the fourth die 373. The integrated device 307 is coupled to the substrate 102 and the bridge 130 through a plurality of solder interconnects 174. The encapsulation layer (e.g., 356, 376) may include a mold, a resin, and / or an epoxy. The encapsulation layers (eg, 356, 376) can be a means for encapsulation.

[0025] As described further below, the third die 371 and the fourth die 373 may be aligned and positioned in various orientations within the integrated device 307. The third die 371 may include a front side and a back side. The fourth die 373 may also include a front side and a back side. In some implementations, the front side of the third die 371 may face the front side of the fourth die 373. In some implementations, the front side of the fourth die 373 may face the back side of the third die 371. In some implementations, the back side of the fourth die 373 may face the front side of the third die 371.

[0026] Various implementations may arrange the dies in the package 300 differently. In some implementations, a back surface of the first die 351 and / or a back surface of the third die 371 may face the bridge 110. In some implementations, a front surface of the first die 351 and / or a front surface of the third die 371 may face the bridge 110. In some implementations, a back surface of the second die 353 and / or a back surface of the fourth die 373 may face the bridge 130 and / or the substrate 102. In some implementations, a front surface of the second die 353 and / or a front surface of the fourth die 373 may face the bridge 130 and / or the substrate 102.

[0027] The bridge 110 is coupled to the first die 351 through at least one solder interconnect 125. The bridge 110 is coupled to the third die 371 through at least one solder interconnect 127. The first die 351 may be configured to be electrically coupled to the third die 371 through the bridge 110. At least one first electrical path (e.g., for input / output signals) between the first die 351 and the third die 371 may include at least one solder interconnect 125, at least one bridge interconnect 112, and / or at least one solder interconnect 127. The bridge 110 provides a shorter electrical path between the first die 351 and the third die 371 by not having to go through the second die 353, the substrate 102, the bridge 130, and / or the fourth die 373.

[0028] The bridge 130 is coupled to the second die 353 through at least one solder interconnect 154a. The bridge 130 is coupled to the fourth die 373 through at least one solder interconnect 174a. The second die 353 may be configured to be electrically coupled to the fourth die 373 through the bridge 130. At least one second electrical path (e.g., for input / output signals) between the second die 353 and the fourth die 373 may include at least one solder interconnect 154a, at least one bridge interconnect 132, and / or at least one solder interconnect 174a.

[0029] In some implementations, power to the integrated device 305, including power to the first die 351 and / or the second die 353, may be supplied through the substrate 102 (e.g., the plurality of interconnects 122) and the at least one solder interconnect 154. In some implementations, power to the first die 351 may be supplied through the substrate 102 (e.g., the plurality of interconnects 122), the at least one solder interconnect 154, the second die 353, and the at least one solder interconnect 354. In some implementations, power to the integrated device 307, including power to the third die 371 and / or the fourth die 373, may be supplied through the substrate 102 (e.g., the plurality of interconnects 122) and the at least one solder interconnect 174. In some implementations, power to the third die 371 may be supplied through the substrate 102 (e.g., the multiple interconnects 122), the at least one solder interconnect 174, the fourth die 373, and the at least one solder interconnect 374. Note that the integrated device 305 may include three or more stacked dies. Similarly, the integrated device 307 may include three or more stacked dies.

[0030] 4 illustrates a cross-sectional side view of an implementation of the package 300. As illustrated in FIG. 4, the first die 351 is bonded to the second die 353 such that the front side of the first die 351 faces the front side of the second die 353. The back side of the die may be the side that includes the die substrate (e.g., silicon). The front side of the die may be the side that faces the back side of the die. The first die 351 includes a plurality of through-substrate vias (TSVs) 451. The plurality of TSVs 451 may be disposed in the back side of the first die 351. The second die 353 includes a plurality of through-substrate vias (TSVs) 453. The plurality of TSVs 453 may be disposed in the back side of the second die 353.

[0031] Similarly, the third die 371 is coupled to the fourth die 373 such that a front surface of the third die 371 faces a front surface of the fourth die 373. The third die 371 includes a plurality of through substrate vias (TSVs) 471. The plurality of TSVs 471 may be disposed in a back surface of the third die 371. The fourth die 373 includes a plurality of through substrate vias (TSVs) 473. The plurality of TSVs 473 may be disposed in a back surface of the fourth die 373.

[0032] In some implementations, a back side of the first die 351 and a back side of the third die 371 may face the bridge 110. In some implementations, a front side of the first die 351 and a front side of the third die 371 may face the substrate 102 and / or the bridge 130. In some implementations, at least one current (e.g., an input / output signal) may travel between the first die 351 and the third die 371 through the multiple TSVs 451, at least one solder interconnect 125, at least one bridge interconnect 112, at least one solder interconnect 127, and the multiple TSVs 471.

[0033] In some implementations, at least one current (e.g., an input / output signal) may travel between the second die 353 and the fourth die 373 through multiple TSVs 453, at least one solder interconnect 154a, at least one bridge interconnect 132, at least one solder interconnect 174a, and multiple TSVs 473.

[0034] In some implementations, the first die 351 and the second die 353 may each be configured to be electrically coupled to the substrate 102. In some implementations, at least one current (e.g., power) between the first die 351 and the substrate 102 may travel through the plurality of solder interconnects 154, the plurality of TSVs 453, the second die 353, and the plurality of solder interconnects 354. In some implementations, at least one current (e.g., power) between the second die 353 and the substrate 102 may travel through the plurality of solder interconnects 154 and the plurality of TSVs 453.

[0035] In some implementations, the third die 371 and the fourth die 373 may each be configured to be electrically coupled to the substrate 102. In some implementations, at least one current (e.g., power) between the third die 371 and the substrate 102 may travel through the plurality of solder interconnects 174, the plurality of TSVs 473, the fourth die 373, and the plurality of solder interconnects 354. In some implementations, at least one current (e.g., power) between the fourth die 373 and the substrate 102 may travel through the plurality of solder interconnects 174 and the plurality of TSVs 473.

[0036] 4 shows one example of how stacked dies may be implemented. However, as discussed above, the dies may be arranged in various orientations and may include various numbers of dies. This disclosure shows and describes a bridge 130 that is at least partially located (e.g., embedded) within the substrate 102. However, in some implementations, the bridge 130 may be located above the substrate 102. For example, the bridge 130 may be located between the integrated device and the substrate 102. Thus, in some implementations, the bridge 130 is not located within the substrate 102.

[0037] 3 and 4 show examples of packages in which the first integrated device (e.g., 305) includes two dies and the second integrated device (307) includes two dies. However, the package may include other configurations and combinations of integrated devices. For example, the first integrated device may include one die and the second integrated device may include two dies. In another example, the first integrated device may include two dies and the second integrated device may include three or more dies. In some implementations, the package may include a first integrated device, a second integrated device, a third integrated device, and a fourth integrated device, all of which are coupled to a substrate. A bridge may be coupled to the top of the first integrated device and the second integrated device. Another bridge may be coupled to the top of the third integrated device and the fourth integrated device. The top of the integrated device may include a surface of the integrated device that faces away from the substrate.

[0038] The integrated devices (e.g., 105, 107, 305, 307) may include a die (e.g., a semiconductor bare die). The integrated devices may include chips, chiplets, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, GaAs-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, processors, memories, power management integrated devices, and / or combinations thereof. The integrated devices (e.g., 105, 107, 305, 307) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0039] FIG. 5 shows a diagram of a bridge 500. The bridge 500 may be a bridge die. The bridge 500 may be a passive bridge die. The bridge 500 may represent the bridge 110 and / or the bridge 130 in this disclosure. The bridge 500 may be a means for bridge interconnection. The bridge 500 includes a die substrate 510 (e.g., a bridge die substrate), at least one bridge interconnect 512, a passivation layer 520, a plurality of under-bump interconnects 514, and a plurality of solder interconnects 530. The die substrate 510 may include silicon (Si). The at least one bridge interconnect 512 may be coupled to the plurality of under-bump interconnects 514. In some implementations, the at least one bridge interconnect 512 may include a row of bridge interconnects. The plurality of solder interconnects 530 may be coupled to the plurality of under-bump interconnects 514. It should be noted that the multiple under-bump interconnects 514 may be considered part of a bridge interconnect for the bridge 500. Thus, a bridge interconnect may also be referred to as at least one under-bump interconnect of the bridge. The bridge 500 is configured to allow one or more currents (e.g., input / output signals) to travel through the under-bump interconnect 514a, the at least one bridge interconnect 512, and the under-bump interconnect 514b.

[0040] FIG. 6 shows a diagram of a bridge 600. The bridge 600 may be a bridge structure and / or a bridge substrate. The bridge 600 may represent the bridge 110 and / or the bridge 130 in this disclosure. The bridge 600 may be a means for bridge interconnection. The bridge 600 includes at least one dielectric layer 610, at least one bridge interconnect 612, and a plurality of solder interconnects 530. The at least one bridge interconnect 612 includes a bridge interconnect 612a (e.g., a bridge via, a bridge pad), a bridge interconnect 612c (e.g., a bridge trace), and a bridge interconnect 612b (e.g., a bridge via, a bridge pad). The bridge 600 is configured to allow one or more currents (e.g., input / output signals) to pass through the bridge interconnect 612a, the bridge interconnect 612c, and the bridge interconnect 612b. In some implementations, there are several rows of bridge interconnects 612a, bridge interconnects 612c, and bridge interconnects 612b.

[0041] 7 and 8 show example signal integrity graphs between two integrated devices. FIG. 7 shows an example graph 700 of signal integrity between two integrated devices, where the signal goes through a non-bridge connection. FIG. 8 shows an example graph 800 of signal integrity between two integrated devices, where the signal goes through a bridge coupled to the top of the integrated devices. Graph 700 shows eye opening 710. Graph 800 shows eye opening 810. Eye opening 810 is larger than eye opening 710, which may indicate that signals going through the bridge may have better signal integrity, including signals with less crosstalk, improved differential insertion loss, improved intra-pair skew, and / or improved mode conversion, relative to signals not going through the bridge. These improvements in signal integrity may be due to shorter routing distances between the integrated devices and / or higher availability of power and ground bumps for the integrated devices. That is, bumps and / or solder interconnects between integrated devices and substrates that are normally used for signal routing may instead be used for power and ground, which may ultimately help improve the power distribution network (PDN) performance of integrated devices and packages.

[0042] Having described the various packages, the sequence for manufacturing the packages will now be described below.

[0043] Exemplary sequence for manufacturing a package including a bridge coupled to an integrated device 9A-9C show an example sequence for providing or manufacturing a package including a bridge coupled to an integrated device. In some implementations, the sequence of FIG. 9A-9C can be used to provide or manufacture package 300 of FIG. 3 or any of the packages described in this disclosure.

[0044] It should be noted that the sequences of Figures 9A-9C may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing the package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the spirit of the disclosure. Different implementations may manufacture the package differently.

[0045] As shown in FIG. 9A, stage 1 depicts the state after the substrate 102 is prepared. The substrate 102 may be manufactured or provided by a supplier. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a variable number of metal layers. The substrate 102 may include a laminate substrate, a cored substrate, and / or a coreless substrate (e.g., ETS). An example of manufacturing a substrate is further described below in at least FIGS. 11A-11C.

[0046] Stage 2 shows the state after the cavity 930 is formed in the substrate 102. Different implementations may form the cavity 930 differently. In some implementations, a laser process (e.g., laser cutting) may be used to form the cavity 930. Different implementations may have cavities with different sizes, shapes and depths. Note that the cavity 930 may already be formed in the substrate 102 when the substrate 102 is provided in stage 1 of FIG.

[0047] As shown in FIG. 9B , stage 3 shows a state after the bridge 130 is at least partially installed within the cavity 930 of the substrate 102. In some implementations, an adhesive (not shown) may be used to install and bond the bridge 130 to the substrate 102. The bridge 130 includes at least one bridge interconnect 132. The bridge 130 may include a bridge 500 or a bridge 600. It should be noted that the bridge 130 may be provided during different stages of the process. For example, the bridge 130 may be bonded to an integrated device before the bridge 130 is bonded to the substrate 102. In some implementations, the bridge 130 may be bonded to an integrated device after the integrated device is bonded to the substrate 102.

[0048] Stage 4 shows the state after the integrated device 305 and the integrated device 307 are bonded to the substrate 102. The integrated device 305 is bonded to the substrate 102 through a plurality of solder interconnects 154. The integrated device 305 is also bonded to the bridge 130 through a plurality of solder interconnects 154. The integrated device 307 is bonded to the substrate 102 through a plurality of solder interconnects 174. The integrated device 307 is also bonded to the bridge 130 through a plurality of solder interconnects 174. As shown in stage 4, the integrated device 305 includes a first die 351 and a second die 353. Similarly, the integrated device 307 includes a third die 371 and a fourth die 373. A solder reflow process may be used to bond the integrated device 305 and the integrated device 307 to the substrate 102 and the bridge 130. It should be noted that in some implementations, multiple pillar interconnects (described in FIG. 2 ) may be used to couple the integrated devices 305 and 307 to the substrate 102 and the bridge 130. Thus, in some implementations, coupling the integrated devices 305 and 307 to the substrate 102 may also include coupling the integrated devices 305 and 307 to the bridge 130. However, in some implementations, the integrated devices 305 and 307 may be coupled to the bridge 130 during a different sequence. For example, the bridge 130 may be coupled to the integrated devices 305 and 307, and then the combined integrated devices 305, 307, and bridge 130 may be coupled to the substrate 102. In another example, the bridge 130 may be coupled to the integrated devices 305 and 307 after the integrated devices 305 and 307 are coupled to the substrate 102. For example, a cavity extending through the substrate 102 may exist in the substrate 102. The integrated devices 305 and 307 may be coupled to the substrate 102 , and the bridge 130 may be coupled to the integrated devices 305 and 307 through a cavity that extends through the substrate 102 .

[0049] As shown in FIG. 9C , stage 5 shows the state after the bridge 110 is coupled to the top of the integrated device 305 and to the top of the integrated device 307. The bridge 110 may be coupled to the integrated device 305 through at least one solder interconnect 125. The bridge 110 may be coupled to the integrated device 307 through at least one solder interconnect 127. A solder reflow process may be used to couple the bridge 110 to the integrated device 305 and the integrated device 307. Note that in some implementations, multiple pillar interconnects (described in FIG. 2 ) may be used to couple the bridge 110 to the integrated device 305 and the integrated device 307.

[0050] Stage 6 shows the solder interconnects 124 bonded to the bottom side of the substrate 102. A solder reflow process may be used to bond the solder interconnects 124 to the substrate 102. The solder interconnects 124 may be bonded to the pad interconnects from the interconnects 122. Stage 6 may show a package 300.

[0051] Illustrative flow diagram of a method for manufacturing a package including a bridge coupled to an integrated device In some implementations, manufacturing the package includes several processes. Figure 10 shows an example flow diagram of a method 1000 for providing or manufacturing a package including a bridge coupled to an integrated device. In some implementations, the method 1000 of Figure 10 can be used to provide or manufacture the package 300 of Figure 3. However, the method 1000 of Figure 10 can be used to manufacture any package in the present disclosure.

[0052] It should be noted that the method of Figure 10 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing the package. In some implementations, the order of the processes may be changed or modified.

[0053] The method includes (at 1005) providing a substrate (e.g., 102). The substrate 102 may include at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a variable number of metal layers. The substrate 102 may include a laminate substrate, a cored substrate, and / or a coreless substrate (e.g., ETS). The substrate may be provided by a supplier or may be manufactured. An example of manufacturing a substrate is further described below in at least FIGS. 11A-11C. Stage 1 of FIG. 9A is described to illustrate an example of providing a substrate.

[0054] The method forms (at 1010) a cavity (e.g., 930) in a substrate (e.g., 102). Different implementations may form the cavity 930 differently. In some implementations, a laser process (e.g., laser cutting) may be used to form the cavity 930. Different implementations may have cavities with different sizes, shapes and depths. In some implementations, the cavity 930 may extend all the way through the substrate 102. Note that the cavity 930 may already be formed in the substrate 102 when the substrate 102 is provided (at 1005). Stage 2 of FIG. 9A illustrates and describes one example of a cavity formed in a substrate.

[0055] The method places and bonds (at 1015) a bridge (e.g., 130) within the cavity 930 of the substrate 102. The bridge 130 may be at least partially placed within the cavity 930. In some implementations, an adhesive (not shown) may be used to place and bond the bridge 130 within the cavity 930 of the substrate 102. The bridge 130 includes at least one bridge interconnect 132. The bridge 130 may include a bridge 500 or a bridge 600. It should be noted that the bridge 130 may be variously bonded to the substrate 102. In some implementations, the bridge 130 may be bonded to the integrated device before being bonded to or disposed on the substrate 102. Stage 3 of FIG. 9B illustrates and describes an example of a bridge at least partially placed within a cavity of a substrate.

[0056] The method bonds (at 1020) a plurality of integrated devices (e.g., 105, 107, 305, 307) to the substrate 102 and the bridge 130. The plurality of integrated devices may be bonded to the substrate 102 and the bridge 130 through a plurality of solder interconnects (e.g., 154, 174) and / or a plurality of pillar interconnects (e.g., 254, 274). A solder reflow process may be used to bond the integrated devices (e.g., 105, 107, 305, 307) to the substrate 102 and the bridge 130. In some implementations, the bridge 130 may be bonded to the integrated devices before the integrated devices are bonded to the substrate 102. Note that in some implementations, a plurality of pillar interconnects (described in FIG. 2) may be used to bond the integrated devices to the substrate 102 and the bridge 130. Stage 4 of FIG. 9B illustrates and describes an example of bonding the integrated devices to the substrate and the bridge.

[0057] The method includes (at 1025) coupling a bridge (e.g., 110) to the top of the integrated devices. For example, the bridge 110 may be coupled to the top of the integrated device 305 and to the top of the integrated device 307. The bridge 110 may be coupled to the integrated device 305 through at least one solder interconnect 125. The bridge 110 may be coupled to the integrated device 307 through at least one solder interconnect 127. A solder reflow process may be used to couple the bridge 110 to the integrated device 305 and the integrated device 307. Note that in some implementations, multiple pillar interconnects (described in FIG. 2) may be used to couple the bridge 110 to the integrated device 305 and the integrated device 307. Stage 5 of FIG. 9C illustrates and describes an example of coupling the bridge to the integrated device.

[0058] The method includes (at 1030) bonding a plurality of solder interconnects (e.g., 124) to a bottom surface of a substrate (e.g., 102). A solder reflow process may be used to bond the plurality of solder interconnects 124 to the substrate 102. The plurality of solder interconnects 124 may be bonded to pad interconnects from the plurality of interconnects 122 of the substrate 102. Stage 6 of FIG. 9C illustrates and describes an example of a solder interconnect bonded to a substrate.

[0059] Exemplary Sequence for Manufacturing a Substrate In some implementations, manufacturing a substrate includes several processes. FIGS. 11A-11C show an example sequence for providing or manufacturing a substrate. In some implementations, the sequence of FIGS. 11A-11C may be used to provide or manufacture substrate 202 and / or substrate 204 of FIG. 2. However, the process of FIGS. 11A-11C may be used to manufacture any of the substrates described in this disclosure. In some implementations, at least some aspects of the process of FIGS. 11A-11C may be used to manufacture bridge 600.

[0060] 11A-11C may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure.

[0061] 11A, stage 1 shows a state after a carrier 1100 is provided and a metal layer is formed on the carrier 1100. The metal layer may be patterned to form interconnects 1102. Plating and etching processes may be used to form the metal layer and the interconnects. In some implementations, the carrier 1100 may be provided with a metal layer that is patterned to form the interconnects 1102.

[0062] Stage 2 shows the state after a dielectric layer 1120 has been formed over the carrier 1100 and the interconnects 1102. A deposition and / or lamination process may be used to form the dielectric layer 1120. The dielectric layer 1120 may include polyimide. However, various implementations may use different materials for the dielectric layer.

[0063] Stage 3 shows the state after the multiple cavities 1110 have been formed in the dielectric layer 1120. The multiple cavities 1110 may be formed using an etching process (eg, a photoetching process) or a laser process.

[0064] Stage 4 shows the state after interconnects 1112 have been formed in and on the dielectric layer 1120, including in and on the plurality of cavities 1110. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0065] Stage 5 shows the state after another dielectric layer 1122 is formed on top of the dielectric layer 1120. A deposition and / or lamination process may be used to form the dielectric layer 1122. The dielectric layer 1122 may be the same material as the dielectric layer 1120. However, various implementations may use different materials for the dielectric layers.

[0066] 11B, after a plurality of cavities 1130 have been formed in the dielectric layer 1122. An etching process or a laser process may be used to form the cavities 1130.

[0067] Stage 7 shows the state after interconnects 1114 have been formed in and over the dielectric layer 1122, including in and over the plurality of cavities 1130. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0068] Stage 8 shows the state after another dielectric layer 1124 is formed on top of the dielectric layer 1122. A deposition and / or lamination process may be used to form the dielectric layer 1124. The dielectric layer 1124 may be the same material as the dielectric layer 1120. However, various implementations may use different materials for the dielectric layers.

[0069] Stage 9 shows the state after a number of cavities 1140 have been formed in the dielectric layer 1124. An etching process or a laser process may be used to form the cavities 1140.

[0070] 11C, stage 10 depicts the state after interconnects 1116 have been formed in and over the dielectric layer 1124, including in and over a plurality of cavities 1140. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0071] Some or all of the interconnects 1102, 1112, 1114 and / or 1116 may define the plurality of interconnects 122 of the substrate 102. The dielectric layers 1120, 1122, 1124 may be represented by at least one dielectric layer 120.

[0072] Stage 11 shows the state after the carrier 1100 has been decoupled (e.g., removed or polished away) from the dielectric layer 1150 and separated from the substrate 102 which includes at least one dielectric layer 120 and multiple interconnects 122.

[0073] Stage 12 shows the state after a first solder resist layer 1160 and a second solder resist layer 1162 have been formed on the substrate 102. A deposition process may be used to form the first solder resist layer 1160 and the second solder resist layer 1162. In some implementations, no solder resist layer or one solder resist layer may be formed on the at least one dielectric layer 1150.

[0074] Various implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0075] Illustrative Flowchart of a Method for Manufacturing a Substrate In some implementations, manufacturing a substrate includes several processes. Figure 12 shows an example flow diagram of a method 1200 for providing or manufacturing a substrate. In some implementations, the method 1200 of Figure 12 can be used to provide or manufacture the substrate of Figures 1-4. For example, the method 1200 of Figure 12 can be used to manufacture the substrate 102.

[0076] 12 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0077] The method provides (at 1205) a carrier 1100. Various implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or carrier tape. Stage 1 of Figure 11A illustrates and describes one example of a provided carrier.

[0078] The method forms (at 1210) a metal layer on the carrier 1100. The metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier may include the metal layer. The metal layer on the carrier may be patterned to form the interconnects (e.g., 1102). Stage 1 of FIG. 11A illustrates and describes one example of a metal layer and interconnects formed on the carrier.

[0079] The method forms (at 1215) a dielectric layer 1120 over the carrier 1100 and the interconnects 1102. A deposition and / or lamination process may be used to form the dielectric layer. The dielectric layer 1120 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1110) in the dielectric layer 1120. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Stages 2-3 of FIG. 11A illustrate an example of forming the dielectric layer and the cavities in the dielectric layer.

[0080] The method forms (at 1220) interconnects in and on the dielectric layer. For example, interconnects 1112 may be formed in and on dielectric layer 1120. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnects may also include forming the interconnects in cavities in the dielectric layer. Stage 4 of FIG. 11A illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0081] The method forms (at 1225) a dielectric layer 1122 over the dielectric layer 1120 and the interconnects. A deposition and / or lamination process may be used to form the dielectric layer. The dielectric layer 1122 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1130) in the dielectric layer 1122. The plurality of cavities may be formed using an etching process or a laser process. Stages 5-6 of Figures 11A-11B illustrate an example of forming the dielectric layer and the cavities in the dielectric layer.

[0082] The method forms (at 1230) interconnects in and / or on the dielectric layer. For example, interconnects 1114 may be formed. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and in the dielectric layer. Forming the interconnects may also include forming the interconnects in cavities in the dielectric layer. Stage 7 of FIG. 11B illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0083] The method may form additional dielectric layers and additional interconnects as described at 1225 and 1230. Stages 8-10 of Figures 11B-11C show and describe an example of forming additional dielectric layers and interconnects in and on the dielectric layer.

[0084] Once all the dielectric layers and additional interconnects have been formed, the method may decouple (e.g., remove or polish away) the carrier (e.g., 1100) from the dielectric layers 120, leaving the substrate. In some implementations, the method may form a solder resist layer (e.g., 1160, 1162) over the substrate.

[0085] Various implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0086] Exemplary Electronic Devices FIG. 13 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1302, a laptop computer device 1304, a fixed location terminal device 1306, a wearable device 1308, or an automotive vehicle 1310 may include a device 1300 as described herein. The device 1300 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1302, 1304, 1306, and 1308 and the vehicle 1310 illustrated in FIG. 13 are merely examples. Other electronic devices may also feature device 1300, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0087] One or more of the components, processes, features, and / or functions shown in Figures 1-6, 9A-9C, 10, 11A-11C, and / or 12-13 may be rearranged and / or combined into a single component, process, feature, or function, or may be combined into several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from the present disclosure. It is also noted that Figures 1-6, 9A-9C, 10, 11A-11C, and / or 12-13 and corresponding descriptions thereof in the present disclosure are not limited to dies and / or ICs. In some implementations, Figures 1-6, 9A-9C, 10, 11A-11C, and / or 12-13 and corresponding descriptions thereof may be used to manufacture, fabricate, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0088] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some examples, the figures may not be to scale. In some examples, for clarity, not all components and / or parts are shown. In some examples, the position, location, size and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0089] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, object A and object C may still be considered to be coupled to each other even if they do not directly physically contact each other. Coupling component A to component B may mean that component A is coupled to component B and / or component B is coupled to component A. The term "electrically coupled" may mean that two objects are coupled together, directly or indirectly, such that an electric current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not have an electric current traveling between the two objects. The use of the terms "first", "second", "third" and "fourth" (and / or more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The term "encapsulate" means that an object may partially encapsulate or fully encapsulate another object. The terms "top" and "bottom" are arbitrary. A component placed on top may be placed on top of a component placed on the bottom. A top component may be considered a bottom component and vice versa. As described in this disclosure, a first component placed "on" a second component may mean that the first component is placed above or below the second component, depending on how bottom or top is arbitrarily defined.In another example, a first component may be disposed over (e.g., above) a first surface of a second component, and a third component may be disposed over (e.g., below) a second surface of the second component, with the second surface facing the first surface. It is further noted that the term "over" as used in this application in the context of one component being disposed over another component may be used to mean a component on and / or within (e.g., on a surface of or embedded in) another component. Thus, for example, a first component over a second component may mean (1) that the first component is over but not in direct contact with the second component, (2) that the first component is on (e.g., on a surface of) the second component, and / or (3) that the first component is within (e.g., embedded in) the second component. A first component that is located "in" a second component may be located partially within the second component or may be located completely within the second component. As used in this disclosure, the term "about 'the value of X'" or "approximately the value of X" means within 10 percent of the 'value of X'. For example, a value of about 1 or approximately 1 means a value in the range of 0.9 to 1.1.

[0090] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a redistribution metal layer, and / or an under bump metallization (UBM) layer. An interconnect may include one or more metal components (e.g., a seed layer + a metal layer). In some implementations, an interconnect is a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal, ground, or power). An interconnect may be part of a circuit. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. Various implementations may use similar or different processes to form the interconnect. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process to form the interconnect. For example, a sputtering process, a spray painting process and / or a plating process may be used to form the interconnects.

[0091] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process is terminated when its operations are completed.

[0092] The following provides a summary of aspects of the disclosure.

[0093] Aspect 1: A package including a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge coupled to the first integrated device and to the second integrated device, the first bridge configured to provide at least one first electrical path between the first integrated device and the second integrated device, the first bridge coupled to a top of the first integrated device and to a top of the second integrated device, and a second bridge coupled to the first integrated device and to the second integrated device, the second bridge configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0094] Embodiment 2: The package of embodiment 1, wherein the at least one first electrical pathway includes a back surface of the first integrated device and a back surface of the second integrated device.

[0095] Aspect 3: The package of aspects 1 to 2, wherein the first integrated device includes a first die and a second die coupled to the first die.

[0096] Example 4: The package of example 3, wherein the second integrated device includes a third die and a fourth die coupled to the third die.

[0097] Aspect 5: The package of aspect 4, wherein the first die is disposed over the second die, the second die is bonded to the substrate, the third die is disposed over the fourth die, and the fourth die is bonded to the substrate.

[0098] Aspect 6: The package of aspects 4 to 5, wherein the first die is configured to be electrically coupled to the third die through a first bridge.

[0099] Embodiment 7: The package of embodiments 4 to 6, wherein the first integrated device includes a first encapsulation layer and the second integrated device includes a second encapsulation layer.

[0100] Embodiment 8: The package of embodiments 3 to 7, wherein a front surface of the first die faces a front surface of the second die.

[0101] Embodiment 9: The package of embodiments 3 to 7, wherein a front side of the first die faces a back side of the second die.

[0102] Embodiment 10: The package of embodiments 3 to 7, wherein a back surface of the first die faces a front surface of the second die.

[0103] Example 11: The package of Examples 1-10, wherein the first bridge includes a bridge die including a die substrate and at least one bridge interconnect.

[0104] Example 12: The package of Examples 1 to 10, wherein the first bridge comprises a bridge structure including at least one dielectric layer and at least one bridge interconnect.

[0105] Aspect 13: A package as described in aspects 1 to 12, wherein the first bridge is configured to provide at least one first electrical path for input / output (I / O) signals between the first integrated device and the second integrated device.

[0106] Aspect 14: The package of aspects 1 to 13, wherein the second bridge is configured to provide at least one second electrical path for input / output (I / O) signals between the first integrated device and the second integrated device.

[0107] Aspect 15: The package of aspects 1 to 2, wherein the first integrated device includes a first die and a second die coupled to the first die, the second integrated device includes a third die and a fourth die coupled to the third die, the first bridge configured to provide at least one first electrical path for input / output (I / O) signals between the first die and the third die, and the second bridge configured to provide at least one second electrical path for input / output (I / O) signals between the second die and the fourth die.

[0108] Embodiment 16: The package of embodiments 1 to 15, wherein the second bridge is located at least partially within the substrate.

[0109] Aspect 17: An apparatus including: a substrate; a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; means for a first bridge interconnect coupled to the first integrated device and the second integrated device, the first bridge interconnect configured to provide at least one first electrical path between the first integrated device and the second integrated device, the first bridge interconnect coupled to a top of the first integrated device and to a top of the second integrated device; and means for a second bridge interconnect coupled to the first integrated device and the second integrated device, the second bridge interconnect configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0110] Example 18: The apparatus of example 17, wherein the first integrated device includes a first die and a second die coupled to the first die.

[0111] Example 19: The apparatus of example 18, wherein the second integrated device includes a third die and a fourth die coupled to the third die.

[0112] Embodiment 20: The apparatus of embodiments 18 to 19, wherein a front surface of the first die faces a front surface of the second die.

[0113] Embodiment 21: The apparatus of embodiments 18 to 19, wherein a front surface of the first die faces a back surface of the second die.

[0114] Embodiment 22: The apparatus of embodiments 18 to 19, wherein a back surface of the first die faces a front surface of the second die.

[0115] Example 23: The apparatus of Examples 17-22, wherein the means for the first bridge interconnect comprises a bridge die including a die substrate and at least one bridge interconnect.

[0116] Example 24: An apparatus as described in Examples 17 to 22, wherein the means for the first bridge interconnection comprises a bridge structure including at least one dielectric layer and at least one bridge interconnection.

[0117] Aspect 25: The apparatus of aspects 17 to 24, wherein the apparatus comprises an electronic device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle.

[0118] Aspect 26: A method for manufacturing a package, the method comprising the steps of: preparing a substrate; bonding a first integrated device to the substrate; bonding a second integrated device to the substrate; bonding a first bridge to the first integrated device and the second integrated device, wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, the first bridge being bonded to a top of the first integrated device and to a top of the second integrated device; and bonding a second bridge to the first integrated device and the second integrated device, wherein the second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

[0119] Example 27: The method of Example 26, wherein the step of coupling the second bridge to the first integrated device and the second integrated device is performed when the first integrated device and the second integrated device are coupled to the substrate.

[0120] Example 28: The method of any one of Examples 26 to 27, wherein the at least one first electrical path comprises a back surface of the first integrated device and a back surface of the second integrated device.

[0121] Example 29: The method of any one of examples 26 to 28, wherein the first integrated device includes a first die, a second die coupled to the first die, a third die, and a fourth die coupled to the third die.

[0122] Example 30: The method of example 29, wherein the first die is configured to be electrically coupled to the third die through a first bridge.

[0123] Various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and is not intended to limit the scope of the claims. Thus, the present teachings can be easily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0124] 100 packages 102 Substrate 105 Integrated Devices 106 Board 107 Integrated Devices 110 Bridge 112 Bridge Interconnect 120 Dielectric layer 122 Interconnection 124 Solder Interconnects 125 Solder Interconnects 127 Solder Interconnects 130 Bridge 132 Bridge Interconnect 154 Solder Interconnects 154a Solder Interconnects 174 Solder Interconnects 174a Solder Interconnects 200 packages 225 Pillar Interconnect 227 Pillar Interconnect 254 Pillar Interconnect 254a Pillar Interconnect 274 Pillar Interconnect 274a Pillar Interconnect 300 packages 305 Integrated Devices 307 Integrated Devices 351 First Die 353 Second Die 354 Solder Interconnects 356 Encapsulation Layer 371 The Third Die 373 The Fourth Die 374 Solder Interconnects 376 Encapsulation Layer 451 Through-Substrate Via (TSV) 453 TSV 471 TSV 473 TSV 500 Bridge 510 Die Substrate 512 Bridge Interconnect 514 Under Bump Interconnect 514a Under Bump Interconnect 514b Under Bump Interconnect 520 Passivation layer 530 Solder Interconnects 600 Bridge 610 Dielectric layer 612 Bridge Interconnect 612a Bridge Interconnect 612b Bridge Interconnect 612c Bridge Interconnect 630 Solder Interconnects 700 graphs 710 Eye Opening 800 graphs 810 Eye Opening 930 Cavity 1100 Career 1102 Interconnection 1110 Cavity 1112 Interconnection 1114 Interconnection 1116 Interconnect 1120 Dielectric layer 1122 Dielectric layer 1124 Dielectric layer 1130 Cavity 1140 Cavity 1150 Dielectric layer 1160 First solder resist layer 1162 Second solder resist layer 1300 devices 1302 Mobile Phone Devices 1304 Laptop Computer Devices 1306 Fixed Location Terminal Device 1308 Wearable Devices 1310 Vehicles

Claims

1. A substrate; a first integrated device coupled to the substrate, the first integrated device including a first plurality of through-substrate vias; a second integrated device coupled to the substrate, the second integrated device including a second plurality of through-substrate vias; a first bridge coupled to the first integrated device and the second integrated device, the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device; the at least one first electrical path includes (i) the first plurality of through-substrate vias of the first integrated device, (ii) the first bridge, and (iii) the second plurality of through-substrate vias of the second integrated device; a first bridge coupled to a top of the first integrated device and a top of the second integrated device; a second bridge coupled to the first integrated device and the second integrated device, the second bridge configured to provide at least one second electrical path between the first integrated device and the second integrated device.

2. The package of claim 1 , wherein the at least one first electrical path includes a back surface of the first integrated device and a back surface of the second integrated device.

3. the first integrated device comprising: A first die; and 10. The package of claim 1, further comprising: a second die coupled to the first die.

4. the second integrated device comprising: A third die; and a fourth die coupled to the third die; the first die is disposed above the second die; the second die is coupled to the substrate; the third die is disposed above the fourth die; the fourth die is bonded to the substrate; or the first die is configured to be electrically coupled to the third die through the first bridge; or the first integrated device includes a first encapsulation layer; The package of claim 3 , wherein the second integrated device includes a second encapsulation layer.

5. a front surface of the first die faces a front surface of the second die; or a front surface of the first die faces a back surface of the second die; or The package of claim 3 , wherein a back surface of the first die faces a front surface of the second die.

6. The first bridge is A die substrate; at least one bridge interconnect; or The first bridge is at least one dielectric layer; at least one bridge interconnect; or the first bridge is configured to provide at least one first electrical path for input / output (I / O) signals between the first integrated device and the second integrated device; or 10. The package of claim 1, wherein the second bridge is configured to provide at least one second electrical path for input / output (I / O) signals between the first integrated device and the second integrated device.

7. the first integrated device comprising: A first die; and a second die coupled to the first die; the second integrated device comprising: A third die; and a fourth die coupled to the third die; the first bridge is configured to provide at least one first electrical path for input / output (I / O) signals between the first die and the third die; the second bridge is configured to provide at least one second electrical path for input / output (I / O) signals between the second die and the fourth die; or The package of claim 1 , wherein the second bridge is located at least partially within the substrate.

8. A substrate; a first integrated device coupled to the substrate, the first integrated device including a first plurality of through-substrate vias; a second integrated device coupled to the substrate, the second integrated device including a second plurality of through-substrate vias; a first bridge interconnection means coupled to the first integrated device and the second integrated device, the first bridge interconnection means comprising: the first bridge interconnection means configured to provide at least one first electrical path between the first integrated device and the second integrated device; the at least one first electrical path includes (i) the first plurality of through-substrate vias of the first integrated device, (ii) the first bridge interconnection means, and (iii) the second plurality of through-substrate vias of the second integrated device; the first bridge interconnection means is coupled to a top of the first integrated device and to a top of the second integrated device; the top portion of the first integrated device is a portion of a first back surface of the first integrated device; the first backside of the first integrated device includes the first plurality of through-substrate vias; the top of the second integrated device is a portion of a second back surface of the second integrated device; the second backside of the second integrated device includes the second plurality of through-substrate vias; and and a means for a second bridge interconnect coupled to the first integrated device and the second integrated device, the means for a second bridge interconnect configured to provide at least one second electrical path between the first integrated device and the second integrated device.

9. the first integrated device comprising: A first die; and and a second die coupled to the first die.

10. the second integrated device comprising: A third die; and a fourth die coupled to the third die; the second die is coupled to the substrate; a back surface of the second die facing the substrate; the fourth die is coupled to the substrate; a back surface of the fourth die facing the substrate; a front surface of the first die facing a front surface of the second die; a front surface of the third die facing a front surface of the fourth die; the first die includes the first plurality of through-substrate vias; the third die includes the second plurality of through-substrate vias; 10. The apparatus of claim 9, wherein the first bridge interconnect means is coupled to the first die and the third die.

11. a front surface of the first die faces a front surface of the second die; or a front surface of the first die faces a back surface of the second die; or The apparatus of claim 9 , wherein a back surface of the first die faces a front surface of the second die.

12. said first bridge interconnection means comprising: A die substrate; at least one bridge interconnect; or said first bridge interconnection means comprising: at least one dielectric layer; at least one bridge interconnect; or 9. The apparatus of claim 8, wherein the apparatus comprises an electronic device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

13. 1. A method for manufacturing a package, comprising: providing a substrate; coupling a first integrated device to the substrate, the first integrated device including a first plurality of through-substrate vias; coupling a second integrated device to the substrate, the second integrated device including a second plurality of through-substrate vias; coupling a first bridge to the first integrated device and the second integrated device, the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device; the at least one first electrical path includes (i) the first plurality of through-substrate vias of the first integrated device, (ii) the first bridge, and (iii) the second plurality of through-substrate vias of the second integrated device; the first bridge is coupled to a top of the first integrated device and to a top of the second integrated device; and coupling a second bridge to the first integrated device and the second integrated device, the second bridge configured to provide at least one second electrical path between the first integrated device and the second integrated device.

14. the step of coupling the second bridge to the first integrated device and the second integrated device is performed when the first integrated device and the second integrated device are coupled to the substrate; or The method of claim 13 , wherein the at least one first electrical path includes a back surface of the first integrated device and a back surface of the second integrated device.

15. the first integrated device comprising: A first die; and a second die coupled to the first die; the second integrated device comprising: A third die; and a fourth die coupled to the third die; The method of claim 13 , wherein the first die is configured to be electrically coupled to the third die through the first bridge.

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