3D Printed Interconnects and Resonators for Semiconductor Devices

Abstract

Techniques are provided for forming flip chip interconnects. For example, one or more embodiments described herein can have a three-dimensional printed flip chip interconnect that includes a conductive ink material that is compatible with three-dimensional printing technology. The three-dimensional printed flip chip interconnect can be located on a metal surface of a semiconductor chip.

Description

[Background technology]

[0001] (background) The present disclosure relates to three-dimensional ("3D") printed features of semiconductor devices, and more particularly to 3D printing techniques capable of forming interconnects and / or tune resonators for flip chip assembly of semiconductor devices. Summary of the Invention [Means for solving the problem]

[0002] (overview) The following presents a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to define the scope of particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, methods, apparatus, and / or devices are described that can use three-dimensional printing to achieve and / or modify one or more features of a semiconductor device.

[0003] According to one embodiment, a device is provided that can have a three-dimensional printed flip chip interconnect that can include a conductive ink material compatible with three-dimensional printing technology. The three-dimensional printed flip chip interconnect can be located on a metal surface of a semiconductor chip.

[0004] According to one embodiment, a method is provided that can include forming flip-chip interconnects by depositing a conductive ink material onto chip pads of a semiconductor device, the depositing can be performed by three-dimensional printing techniques.

[0005] According to one embodiment, a method is provided that can include tailoring a resonator of a semiconductor device by depositing an ink material on a surface of the resonator of the semiconductor device, the depositing can be performed by a three-dimensional printing technique. [Brief description of the drawings]

[0006] [Figure 1A] 1 illustrates an exemplary, non-limiting cross-sectional view of a three-dimensional printed interconnect that may be used in a flip chip assembly in accordance with one or more embodiments described herein. [Figure 1B] FIG. 1 illustrates an exemplary, non-limiting cross-sectional view of a flip chip assembly that can include one or more three dimensional printed interconnects in accordance with one or more embodiments described herein. [Diagram 2] FIG. 1 illustrates an exemplary, non-limiting overhead view of an exemplary geometry that may be embodied by one or more three dimensional printed interconnects that may be used in a flip chip assembly according to one or more embodiments described herein. [Diagram 3] 1 illustrates an exemplary, non-limiting cross-sectional view of a three dimensional printed interconnect during a first stage of fabrication in accordance with one or more embodiments described herein. [Figure 4A] FIG. 1 illustrates an exemplary and non-limiting diagram of a three dimensional printed interconnect during a second stage of fabrication in accordance with one or more embodiments described herein. [Figure 4B] FIG. 1 illustrates an exemplary and non-limiting diagram of a three dimensional printed interconnect during a second stage of fabrication in accordance with one or more embodiments described herein. [Figure 4C] FIG. 1 illustrates an exemplary and non-limiting diagram of a three dimensional printed interconnect during a second stage of fabrication in accordance with one or more embodiments described herein. [Figure 4D] FIG. 1 illustrates an exemplary and non-limiting diagram of a three dimensional printed interconnect during a second stage of fabrication in accordance with one or more embodiments described herein. [Figure 5A]FIG. 1 illustrates an exemplary and non-limiting diagram of a three dimensional printed interconnect during a third stage of fabrication in accordance with one or more embodiments described herein. [Figure 5B] FIG. 1 illustrates an exemplary and non-limiting diagram of a three dimensional printed interconnect during a third stage of fabrication in accordance with one or more embodiments described herein. [Figure 5C] FIG. 1 illustrates an exemplary and non-limiting diagram of a three dimensional printed interconnect during a third stage of fabrication in accordance with one or more embodiments described herein. [Figure 6A] FIG. 1 illustrates an exemplary, non-limiting top view of one or more three dimensional printed interconnects that may be used in a flip chip assembly according to one or more embodiments described herein. [Figure 6B] FIG. 1 illustrates an exemplary, non-limiting top view of one or more three dimensional printed interconnects that may be used in a flip chip assembly according to one or more embodiments described herein. [Figure 7] FIG. 1 illustrates an example, non-limiting, print map that can be generated to facilitate three-dimensional printing of one or more structures according to one or more embodiments described herein. [Figure 8] 1 illustrates an exemplary and non-limiting cross-sectional view of a resonator of a semiconductor device prepared by one or more three-dimensional printing techniques in accordance with one or more embodiments described herein. [Figure 9] 1 illustrates an exemplary and non-limiting cross-sectional view of a resonator of a semiconductor device during a first stage of tuning in accordance with one or more embodiments described herein. [Figure 10A] 1 illustrates an exemplary and non-limiting cross-sectional view of a resonator of a semiconductor device during a second stage of tuning in accordance with one or more embodiments described herein. [Figure 10B] 1 illustrates an exemplary and non-limiting cross-sectional view of a resonator of a semiconductor device during a second stage of tuning in accordance with one or more embodiments described herein. [Figure 10C]1 illustrates an exemplary and non-limiting cross-sectional view of a resonator of a semiconductor device during a second stage of tuning in accordance with one or more embodiments described herein. [Figure 10D] 1 illustrates an exemplary and non-limiting cross-sectional view of a resonator of a semiconductor device during a second stage of tuning in accordance with one or more embodiments described herein. [Figure 11A] FIG. 13 illustrates an exemplary and non-limiting diagram of a three dimensional printed interconnect during a third stage of preparation in accordance with one or more embodiments described herein. [Figure 11B] FIG. 13 illustrates an exemplary and non-limiting diagram of a three dimensional printed interconnect during a third stage of preparation in accordance with one or more embodiments described herein. [Figure 11C] FIG. 13 illustrates an exemplary and non-limiting diagram of a three dimensional printed interconnect during a third stage of preparation in accordance with one or more embodiments described herein. [Figure 12] FIG. 1 illustrates a flow diagram of an exemplary, non-limiting method that can facilitate manufacturing one or more three dimensional printed interconnects that can be used in flip chip assemblies in accordance with one or more embodiments described herein. [Figure 13] FIG. 1 illustrates a flow diagram of an example, non-limiting method that may facilitate tuning one or more resonators of a semiconductor device by one or more three-dimensional printing techniques in accordance with one or more embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] (Detailed Description) The following detailed description is merely illustrative and is not intended to limit the embodiments and / or the application or uses of the embodiments, and further, is not intended to be bound by any express or implied information presented in the preceding "Background" or "Summary" sections or in the "Detailed Description" section.

[0008] One or more embodiments will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that in various instances, one or more embodiments may be practiced without these specific details. Additionally, features depicted in the drawings using similar shading, cross-hatching, and / or coloring may have shared compositions and / or materials.

[0009] Flip chip assemblies can be used to connect one or more semiconductor devices (e.g., integrated circuit chips, integrated passive devices, microelectrochemical systems, and / or the like) with an external circuit (e.g., a package assembly). The one or more semiconductor devices can be disposed on one or more first chips, and the external circuit can be disposed on one or more second chips. The first chip can further have one or more chip pads, which can be aligned with one or more chip pads on the second chip. A conductive material can be deposited on the chip pads. When the first chip is disposed on the second chip, the conductive material can contact the aligned chip pads of the first and second chips to establish an interconnection.

[0010] Typically, conductive material is deposited on the chip pads as multi-layer pillars or stud bumps. However, the formation of multi-layer pillars requires full wafer processing and multiple processing steps that may harm, impair, and / or inhibit one or more features of the flip chip assembly. Furthermore, control over the dimensions and / or geometry of the stud bumps may be substantially limited. For example, the top surface of the stud bump includes a neck formed from disrupting the flow of the deposited material, and the dimensions and / or geometry of the neck may vary with each implementation.

[0011] Various embodiments described herein can be considered to be the use of three-dimensional printing techniques to form one or more flip-chip interconnects and / or tune one or more resonators of a semiconductor device. In one or more embodiments, the three-dimensional printing interconnects can be printed directly onto one or more chip pads. Furthermore, the three-dimensional printing techniques used to form the interconnects can allow for the formation of precisely defined sizes and / or geometries. In one or more embodiments, one or more resonators of a semiconductor device can be tuned by one or more three-dimensional printing techniques. For example, material can be added to a surface of one or more resonators to change the operating frequency exhibited by the one or more resonators.

[0012] As described herein, the terms "deposition process" and / or "deposition processes" can refer to any process that grows, coats, deposits, and / or otherwise transfers one or more first materials onto one or more second materials. Exemplary deposition processes may include, but are not limited to, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), atomic layer deposition ("ALD"), low pressure chemical vapor deposition ("LPCVD"), plasma enhanced chemical vapor deposition ("PECVD"), high density plasma chemical vapor deposition ("HDPCVD"), subatmospheric pressure chemical vapor deposition ("SACVD"), rapid thermal chemical vapor deposition ("RTCVD"), in-situ radical assisted deposition, high temperature oxide deposition ("HTO"), low temperature oxide deposition ("LTO"), limited reaction processing chemical vapor deposition ("LRPCVD"), ultra-high vacuum chemical vapor deposition ("UHVCVD"), metal organic chemical vapor deposition ("MOCVD"), physical vapor deposition ("PVD"), chemical oxidation, sputtering, plating, evaporation, spin-on coating, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, combinations thereof, and / or the like.

[0013] As described herein, the terms "lithography process" and / or "lithography processes" can refer to the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the semiconductor substrate. In semiconductor lithography, the pattern can be formed by a light-sensitive polymer called a photoresist. To build the complex structures that make up semiconductor devices and the numerous wirings that connect the various features of the circuits, the lithography process and / or etching pattern transfer steps can be repeated multiple times. Each pattern printed on the wafer is aligned to a previously formed pattern, and slowly thematic features (e.g., conductors, insulators, and / or selectively doped regions) can be built up to form the final device.

[0014] FIG. 1A illustrates an exemplary and non-limiting cross-sectional view of a chip structure 100 having one or more interconnects 102 that may be three-dimensionally printed and / or used in one or more flip chip assemblies according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. As shown in FIG. 1A, the one or more interconnects 102 may be located on one or more chip pads 104 of the chip structure 100. Furthermore, the one or more chip pads 104 may be located on one or more semiconductor substrates 106. Furthermore, the one or more interconnects 102 may be at least partially surrounded by one or more layers, such as one or more intermediate layers 108 and / or a protective layer 110.

[0015] The semiconductor substrate 106 may be crystalline, semi-crystalline, microcrystalline, or amorphous. The semiconductor substrate 106 may consist essentially of a single element (e.g., silicon or germanium) and / or compound (e.g., aluminum oxide, silicon dioxide, gallium arsenide, silicon carbide, silicon germanium, combinations thereof, and / or the like) (e.g., excluding contaminants). The semiconductor substrate 106 may also have multiple layers of materials, such as, but not limited to, a semiconductor-on-insulator substrate ("SeOI"), a silicon-on-insulator substrate ("SOI"), a germanium-on-insulator substrate ("GeOI"), a silicon germanium-on-insulator substrate ("SGOI"), combinations thereof, and / or the like. Additionally, the semiconductor substrate 106 may have other layers, such as oxides having a high dielectric constant ("High-K oxides") and / or nitrides. In one or more embodiments, the semiconductor substrate 106 may be a silicon wafer. In various embodiments, the semiconductor substrate 106 may comprise single crystal silicon (Si), silicon germanium (e.g., characterized by the chemical formula SiGe), a III-V semiconductor wafer or surface / active layer, combinations thereof, and / or the like.

[0016] The one or more chip pads 104 may be one or more metal surfaces. Exemplary metals that may comprise the one or more chip pads 104 may include, but are not limited to, gold, aluminum, copper, tungsten, tantalum, silver, palladium, combinations thereof, and / or the like. In one or more embodiments, the one or more chip pads 104 may have a circular or polygonal shape. For example, the one or more chip pads 104 may have a rectangular shape (e.g., as shown in FIG. 1A). The one or more chip pads 104 may have a total thickness (e.g., along the Y-axis shown in FIG. 1A) ranging from 0.1 micrometers (μm) to 6 μm. The one or more chip pads 104 may have a width (e.g., along the X-axis shown in FIG. 1) ranging from 30 μm to 300 μm. As shown in FIG. 1A, the one or more chip pads 104 may be positioned on a semiconductor substrate 106.

[0017] As shown in FIG. 1A, one or more intermediate layers 108 and / or protective layers 110 may also be positioned on the semiconductor substrate 106. Furthermore, one or more intermediate layers 108 and / or protective layers 110 may be positioned on at least a portion of one or more chip pads 104. In various embodiments, the one or more intermediate layers 108 may be metallic or dielectric. Exemplary materials that may comprise the one or more intermediate layers 108 may include, but are not limited to, silicon nitride (S3N4), aluminum nitride (AlN), benzocyclobutene (BCB), aluminum oxide (Al2O3), combinations thereof, and / or the like. Furthermore, the one or more intermediate layers 108 may have a thickness (e.g., along the Y-axis shown in FIG. 1A) ranging from 0.05 μm to 8 μm, for example. In various embodiments, the one or more protective layers 110 may protect one or more surfaces of the chip structure 100 from the surrounding environment. Exemplary materials that may comprise the one or more protective layers 110 may include, but are not limited to, silicon nitride (S3N4), aluminum nitride (AlN), benzocyclobutene (BCB), aluminum oxide (Al2O3), combinations thereof, and / or the like. Additionally, the one or more protective layers 110 may have a thickness (e.g., along the Y-axis shown in FIG. 1A) ranging from, for example, 0.05 μm to, for example, 8 μm. In various embodiments, the one or more intermediate layers 108 and / or protective layer 110 may be spaced apart from the one or more interconnects 102 by a distance "D" ranging from, for example, 0.05 μm to, for example, 8 μm.

[0018] In one or more embodiments, the one or more interconnects 102 may be printed on one or more chip pads 104 by one or more three-dimensional printing techniques. For example, the one or more interconnects 102 may have one or more conductive ink materials compatible with one or more three-dimensional printing techniques. For example, the conductive ink material may have one or more metals including, but not limited to, gold, aluminum, copper, tantalum, cobalt, ruthenium, titanium, tin-silver, solder, alloys thereof, combinations thereof, and / or the like. In one or more embodiments, the one or more interconnects 102 may have a substantially homogenous composition (e.g., as shown in FIG. 1A). In one or more embodiments, the one or more interconnects 102 may have multiple types of conductive ink materials (e.g., arranged in a stacking direction to form a multi-layer interconnect).

[0019] The one or more interconnects 102 can have a thickness (e.g., along the Y-axis shown in FIG. 1A) ranging from 20 μm to 150 μm, for example. Additionally, the one or more interconnects 102 can have a width (e.g., along the X-axis shown in FIG. 1A) ranging from 20 μm to 200 μm, for example. In various embodiments, the geometry of the one or more interconnects 102 can vary depending on the application and / or desired physical properties of the one or more interconnects 102. Although FIG. 1A illustrates the one or more interconnects 102 having a substantially cylindrical shape, the structure of the one or more interconnects 102 is not so limited. For example, the one or more interconnects 102 can have a spherical shape, a cubic shape, a pyramidal shape, a prism shape, a polyhedral shape, combinations thereof, and / or the like. In one or more embodiments, the top surface of one or more interconnects 102 can have a convex shape (eg, as shown in FIG. 1A), a concave shape, a flat shape, and / or combinations thereof.

[0020] 1B shows a diagram of an exemplary and non-limiting chip structure 100 used in an exemplary flip chip assembly 112 according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. As shown in FIG. 1B, one or more interconnects 102 can be disposed between aligned chip pads 104, each located on adjacent chips of the exemplary flip chip assembly 112.

[0021] The chip structure 100 shown in FIG. 1A can be included in one or more first and / or second semiconductor chips of the exemplary flip chip assembly 112. For example, the chip structure 100 can be configured in a chip further including one or more semiconductor devices of the exemplary flip chip assembly 112. The exemplary semiconductor devices can include, but are not limited to, bulk acoustic wave devices, monolithic microwave integrated circuits, integrated circuits, passive integrated circuits, microelectrochemical systems, magnetic material-based circuits, combinations thereof, and / or the like. For example, the chip structure 100 can be configured in a chip further including one or more semiconductor features including, but are not limited to, resonators, resistors, capacitors, inductors, combinations thereof, and / or the like. In another example, the chip structure 100 can be configured in a chip further including one or more external circuits of the exemplary flip chip assembly 112.

[0022] 1B illustrates an example embodiment in which chip structure 100 may be configured within a first chip (e.g., further comprising one or more semiconductor devices) of an example flip chip assembly 112. Additionally, a second chip of the example flip chip assembly may include a printed circuit board 114 and / or one or more additional chip pads 104. As shown in FIG. 1B, one or more interconnects 102 may be disposed between the respective chip pads 104 of the first and second chips when the chips are joined to form the example flip chip assembly 112.

[0023] FIG. 2 illustrates an exemplary, non-limiting top view of various geometries that may be embodied by one or more interconnects 102 according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. FIG. 2 illustrates a top surface 202 of one or more interconnects 102 illustrated in FIG. 1A. For example, an exemplary geometry of the distal end of one or more interconnects 102 shown in FIG. 1A is illustrated in FIG. 2.

[0024] As shown in FIG. 2, the top surface 202 of the one or more interconnects 102 can have various geometries depending on the desired application and / or characteristics of the one or more interconnects 102. For example, but not limited to, the top surface 202 can have a circular shape, a triangular shape, a pentagonal shape, a hexagonal shape, a cross shape, a star shape, a polygonal shape, combinations thereof, and / or the like. In various embodiments, the shape of the top surface 202 can affect the amount of surface area of ​​the one or more interconnects 102 that can contact one or more other chip pads 104. The shape of the top surface 202 can thereby affect the electrical connection between chips coupled by the one or more interconnects 102 (e.g., can affect the electrical connection between chips of the exemplary flip chip assembly 112 shown in FIG. 1B). For example, an interconnect 102 having a top surface 202 with a larger surface area can minimize electrical resistance and / or inductance to ground. However, special constraints on one or more chips of the chip assembly 112 may affect the possible size of the interconnects. Various embodiments described herein may allow for different shapes and / or geometries of the interconnects 102 to manage the relationship between increased surface area and the special constraints on one or more chips.

[0025] 3 shows a diagram of an exemplary and non-limiting chip structure 100 during a first stage of fabrication according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. During the first stage of fabrication, one or more chip pads 104 may be provided and / or prepared for subsequent printing of one or more interconnects 102.

[0026] In various embodiments, one or more chip pads 104 may be formed on one or more target locations of the semiconductor substrate 106 by one or more deposition processes. Additionally, one or more intermediate layers 108 and / or protective layers 110 may be formed on portions of the semiconductor substrate 106 and / or the chip pads 104. Additionally, one or more intermediate layers 108 and / or protective layers 110 may be patterned by one or more lithography processes to expose at portions of the one or more chip pads 104 for subsequent positioning of one or more interconnects 102. Thereby, one or more chip pads 104 may be provided for formation of one or more interconnects 102.

[0027] 4A-4D show diagrams of an exemplary and non-limiting chip structure 100 during a second stage of fabrication according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. During the second stage of fabrication, one or more interconnects 102 can be printed on one or more chip pads 104 by one or more three-dimensional printing techniques. As a result of the second stage of fabrication, at least a first portion 102a of the one or more interconnects 102 can be formed on the one or more chip pads 104.

[0028] In various embodiments, a three-dimensional printing technique can deposit the ink material (e.g., conductive ink material) of one or more interconnects 102 onto one or more chip pads 104. For example, one or more three-dimensional printing techniques can print one or more interconnects 102 by an additive process, where the ink material (e.g., conductive ink material) can be deposited by successive layers that are repeatedly placed on top of each other until a desired three-dimensional shape is achieved. Exemplary three-dimensional printing techniques that can be used to print one or more interconnects 102 can include, but are not limited to, direct-write printing techniques, inkjet printing techniques, aerosol jet printing techniques, combinations thereof, and / or the like.

[0029] For example, FIGS. 4A and 4C illustrate an exemplary nozzle 402 of a three-dimensional printing technique. A conductive ink material that constitutes one or more interconnects 102 can be ejected from the nozzle 402 when performing the three-dimensional printing technique. For example, FIGS. 4A and 4C illustrate that an ink material (e.g., a conductive ink material) is ejected from the exemplary nozzle 402 onto one or more chip pads 104. As shown in FIGS. 4A-4B, the exemplary nozzle 402 can move along a printing direction (e.g., represented by arrow "P" in FIGS. 4A-4B). As the exemplary nozzle 402 moves along the printing direction (e.g., represented by arrow "P"), the nozzle 402 can also deposit an ink material (e.g., a conductive ink material) onto one or more chip pads 104.

[0030] FIG. 4A illustrates a nozzle 402 in a first position above a chip pad 104 during a three-dimensional printing technique. From the first position, the nozzle 402 can move along a printing direction (e.g., represented by arrow "P") to a second position illustrated in FIG. 4C. As illustrated in FIG. 4B, the printing direction (e.g., represented by arrow "P") can traverse one or more chip pads 104 along an X-axis, a Z-axis, and / or combinations thereof. Furthermore, the printing direction can follow a straight line, a curved line, a wavy line, combinations thereof, and / or the like. Thereby, the printing direction (e.g., represented by arrow "P") can traverse an area on one or more chip pads 104 occupied by one or more interconnects 102. Furthermore, the path of the printing direction (e.g., represented by arrow "P") can be defined by the geometry of one or more interconnects 102. Thus, the location and / or path of the printing direction (e.g., represented by arrow "P") can be based on the desired geometry of one or more interconnects 102. For example, the path of the printing direction (e.g., represented by arrow "P") shown in FIG. 4B can be used to print rectangular prism and / or cubic geometries of one or more interconnects 102.

[0031] As the nozzle 402 traverses the printing direction (e.g., represented by arrow "P"), the ink material (e.g., conductive ink material) can be deposited on one or more chip pads 104. For example, FIGS. 4C-4D illustrate a first portion 102a of one or more interconnects 102 formed from an exemplary nozzle 402 traversing the exemplary printing direction (e.g., represented by arrow "P") shown in FIG. 4B. Additionally, although FIGS. 4C-4D illustrate continuous or near-continuous deposition of the ink material (e.g., conductive ink material) onto the chip pads 104 along the printing direction (e.g., represented by arrow "P"), the three-dimensional printing structures are not so limited. For example, embodiments are also envisioned in which the ink material (e.g., conductive ink material) is deposited periodically (e.g., according to one or more predetermined intervals).

[0032] In various embodiments, one or more exemplary nozzles 402 of one or more printing technologies can be controlled by one or more computing devices 404 via one or more communication connections 406 (e.g., direct electrical connections and / or wireless connections). The one or more communication connections 406 can include wired and wireless networks, including, but not limited to, cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs). For example, the one or more computing devices 404 can communicate with the apparatus of the three-dimensional printing technology using substantially any desired wired or wireless technology, including, but not limited to, cellular, WAN, Wireless Fidelity (Wi-Fi), Wi-Max, WLAN, Bluetooth technology, combinations thereof, and / or the like.

[0033] Exemplary computing devices 404 may include, but are not limited to, a personal computer, a desktop computer, a laptop computer, a mobile phone (e.g., a smartphone), a computing tablet (e.g., having a processor), a smartwatch, a keyboard, a touch screen, a mouse, combinations thereof, and / or the like. One or more computing devices 404 may be used to facilitate the execution of one or more printing techniques. For example, one or more computing devices 404 may transmit data and / or otherwise control one or more three-dimensional printing technology apparatus to define the type of ink material to be used and / or one or more printing directions traversed by the nozzle 402.

[0034] In various embodiments, the one or more computing devices 404 and / or communication connections 406 can be used to define the position, size, shape, and / or geometry of one or more three-dimensional structures to be printed by one or more three-dimensional printing techniques (e.g., define the position, size, shape, and / or geometry of one or more interconnects 102). For example, the one or more computing devices 404 can execute three-dimensional printing software to define one or more printing directions that may be used during a second and / or third stage of fabrication (e.g., described below with respect to at least FIGS. 5A-5C) to direct the operation of one or more nozzles 402 and thereby direct the deposition of an ink material (e.g., a conductive ink material).

[0035] 5A-5C show diagrams of an exemplary and non-limiting chip structure 100 during a third stage of fabrication according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. During the third stage of fabrication, one or more interconnects 102 can be further printed on one or more chip pads 104 by one or more three-dimensional printing techniques. As a result of the third stage of fabrication, one or more second portions 102b of one or more interconnects 102 can be formed on one or more chip pads 104.

[0036] As shown in Figures 5A-5C, one or more features of the second stage of fabrication can be repeated to further print one or more interconnects 102. For example, one or more three-dimensional printing techniques can be further performed to deposit an ink material (e.g., a conductive ink material) onto one or more previously formed portions of the one or more interconnects 102 (e.g., onto at least the first portion 102a of the one or more interconnects 102). By depositing additional ink material onto one or more previously formed portions of the interconnects 102 (e.g., onto the first portion 102a), a third stage of fabrication can further print one or more interconnects 102 to a desired height (e.g., can further print one or more interconnects 102 along the Y-axis shown in Figures 5A and / or 5C).

[0037] In various embodiments, the third stage of fabrication can be repeated multiple times to print one or more interconnects 102 in a desired geometry and / or height (e.g., along the Y-axis in FIG. 5A and / or FIG. 5C ). For example, with each performance of the third stage of fabrication, additional ink material (e.g., conductive ink material) can be deposited onto previously deposited ink material to further print one or more interconnects 102. Furthermore, each performance of the third stage of fabrication can deposit ink material in areas of the same size, smaller areas, and / or larger areas than one or more previous areas of ink material deposition. For example, each performance of the third stage of fabrication can follow the same one or more printing directions, or one or more different printing directions.

[0038] In one or more embodiments, the one or more three dimensional printing techniques can continuously deposit the ink material (e.g., conductive ink material) while transitioning from the second stage of manufacture to the third stage of manufacture. Similarly, in one or more embodiments, the one or more three dimensional printing techniques can continuously deposit the ink material (e.g., conductive ink material) while transitioning from one implementation of the third stage of manufacture to another implementation of the third stage of manufacture.

[0039] In various embodiments, the three-dimensional printing technique can follow one or more print directions (e.g., represented by a "P" arrow) used during the second stage of manufacture during one or more implementations of the third stage of manufacture. In one or more embodiments, the three-dimensional printing technique can follow one or more print directions (e.g., represented by a "P" arrow) that are different from the one or more print directions used during the second stage of manufacture during one or more implementations of the third stage of manufacture. For example, FIG. 5B illustrates an exemplary print direction (e.g., represented by a "P" arrow) used during the third stage of manufacture, which is opposite to the print direction (e.g., represented by a "P" arrow) used during the second stage of manufacture. In another example, the one or more print directions used during the third stage of manufacture can be parallel or perpendicular to the one or more print directions used during the second stage of manufacture.

[0040] As shown in FIG. 5B, the printing direction (e.g., represented by arrow "P") used during one or more implementations of the third stage of manufacturing can traverse the previously deposited ink material along the X-axis, the Z-axis, and / or combinations thereof. Furthermore, the printing direction can follow a straight line, a curved line, a wavy line, combinations thereof, and / or the like. Thereby, the printing direction (e.g., represented by arrow "P") can traverse an area occupied by an additional portion of one or more interconnects 102 (e.g., can traverse an area occupied by one or more second portions 102b). Furthermore, the path of the printing direction (e.g., represented by arrow "P") can be defined by the geometry of one or more interconnects 102. Thus, the location and / or path of the printing direction (e.g., represented by arrow "P") can be based on the desired geometry of one or more interconnects 102 at a given height to be printed during a given implementation of the third stage of manufacturing. For example, the printing direction path shown in FIG. 5B (e.g., represented by arrow "P") can be used to elevate the rectangular prism and / or cube geometries defined during the second stage of fabrication shown in FIGS. 5A-5C.

[0041] As the nozzle 402 traverses the printing direction (e.g., represented by arrow "P") during one or more of the third stages of fabrication, the ink material (e.g., conductive ink material) can be deposited onto previously deposited ink material. For example, FIG. 5C illustrates a second portion 102b of one or more interconnects 102 formed from an example nozzle 402 traversing the example printing direction (e.g., represented by arrow "P") shown in FIG. 5B. Additionally, although FIGS. 5A-5C depict continuous or near-continuous deposition of the ink material (e.g., conductive ink material) along the printing direction (e.g., represented by arrow "P") onto previously deposited ink material (e.g., conductive ink material), the three-dimensional printing structures are not so limited. For example, embodiments are also envisioned in which the ink material (e.g., conductive ink material) is deposited periodically (e.g., according to one or more predetermined intervals).

[0042] 6A-6B show exemplary and non-limiting top views of a chip undergoing three-dimensional printing according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. As shown in FIGS. 6A-6B, one or more three-dimensional printing techniques can be used on multiple locations of a chip and / or semiconductor device. For example, FIGS. 6A-6B can be considered as an exemplary chip structure 100 in which multiple interconnects 102 are three-dimensionally printed on multiple chip pads 104 (e.g., located around a periphery of a given chip).

[0043] FIG. 6A illustrates a top view of the chip structure 100 during a first stage of fabrication. Also, as shown in FIG. 6A, the first stage of fabrication can include identifying locations where one or more three-dimensional techniques can be used. For example, FIG. 6A illustrates printing locations 602 for one or more interconnects 102. In one or more embodiments, an entity using one or more three-dimensional techniques can identify printing locations 602 for depositing ink material by defining a center point of a three-dimensional structure formed by one or more three-dimensional printing techniques. For example, a manufacturer of one or more interconnects 102 can identify one or more printing locations 602 where a center of one or more interconnects 102 can be located as a result of a three-dimensional printing process (e.g., second and / or third stages of fabrication). In one or more embodiments, an entity using one or more three-dimensional techniques can identify printing locations 602 for depositing ink material by defining a surface area occupied by a three-dimensional printed structure. For example, a manufacturer of one or more interconnects 102 may specify the boundaries of one or more surface areas on one or more chip pads 104 onto which one or more interconnects 102 will be printed (e.g., by a second and / or third stage of manufacturing).

[0044] In various embodiments, the print locations 602 can be transmitted to one or more computing devices 404 that can be used to control one or more three-dimensional printing techniques. For example, three-dimensional printing software in the one or more computing devices 404 can be used to generate one or more print files that can define the size, shape, and / or geometry of one or more three-dimensional structures (e.g., one or more interconnects 102) to be printed by one or more three-dimensional printing techniques (e.g., by the second stage of manufacture and / or the third stage of manufacture described herein). For example, the one or more print files can define one or more print orientations to be used during the three-dimensional printing process. In another example, the one or more print files can further define the type of ink material to be deposited and / or one or more settings (e.g., pressure settings, flow rate settings, speed settings, combinations thereof, and / or the like) associated with the one or more three-dimensional printing techniques. Additionally, the one or more print files can be supplemented with position data that defines the print locations 602 for one or more three-dimensional printed structures. For example, a print location 602 on a given chip can be converted into position data (e.g., coordinate data relative to a virtual grid) related to one or more features defined by one or more print files generated and / or used by one or more computing devices 404.

[0045] In one or more embodiments, the one or more three-dimensional printing techniques used during the second and / or third stages of fabrication can print the interconnects 102 simultaneously, in parallel, and / or sequentially. For example, a first interconnect 102 (e.g., located on a first chip pad 104) can be printed simultaneously, in parallel, and / or sequentially with a second interconnect 102 (e.g., located on a second chip pad 104). For example, a respective nozzle 402 can be used in connection with printing a respective interconnect 102 to expedite fabrication of the chip structure 100. Additionally, as shown in FIG. 6B, one or more first interconnects 102 of a given chip can have a different size and / or geometry than one or more second interconnects 102 of a given chip. For example, FIG. 6B illustrates an exemplary chip structure 100 including one or more interconnects 102 having a circular top surface 202, one or more interconnects 102 having a rectangular top surface 202, and / or one or more interconnects 102 having a star-shaped top surface 202.

[0046] 7 illustrates an exemplary, non-limiting diagram of a print map 700 that may be generated to facilitate one or more three-dimensional printing operations according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. In various embodiments, one or more print maps 700 may be included in one or more print files executable by one or more computing devices 404 to facilitate the three-dimensional printing techniques described herein.

[0047] As shown in FIG. 7, one or more print maps 700 can delineate print locations 602 with respect to coordinates along a Z-axis and / or an X-axis. For example, the Z-axis and / or the X-axis can define a boundary of an area available for printing by one or more printing techniques, and the coordinates along the Z-axis and / or the X-axis can delineate print locations 602 within the available print area. For example, the print locations 602 illustrated in the exemplary print map 700 shown in FIG. 7 can correspond to the exemplary chip structures shown in FIGS. 6A-6B. Furthermore, as shown in FIG. 7, one or more print maps 700 can include one or more print directions associated with one or more print locations 602. For example, one or more print maps 700 can include a print direction used for each print location 602. For example, the print directions illustrated in the exemplary print map 700 shown in FIG. 7 (e.g., represented by P arrows) can correspond to the exemplary print directions shown in FIG. 4B. In various embodiments, each print location 602 can be associated with a respective print direction depending on the geometry of the three-dimensional structure (eg, interconnect 102) to be printed at the print location 602.

[0048] In one or more embodiments, multiple print maps 700 can be used by one or more computing devices 404 to print a three-dimensional structure (e.g., interconnects 102). For example, a first print map 700 can be used to depict print locations 602 and / or print directions during a second stage of manufacture described herein, a second print map 700 can be used to depict print locations 602 and / or print directions during a third stage of manufacture described herein, and one or more additional print maps 700 can be used to depict print locations 602 and / or print directions during additional iterations of the third stage of manufacture.

[0049] 8 shows a diagram of an exemplary and non-limiting resonator structure 800 that can include one or more tuning layers 808 printed by one or more printing techniques described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. In various embodiments, the resonator structure 800 can be included on one or more chips of a flip chip assembly (e.g., the exemplary flip chip assembly 112). For example, the resonator structure 800 can be configured in a bulk acoustic wave device.

[0050] As shown in FIG. 8, the resonator structure 800 can have one or more piezoelectric layers 802 disposed on the semiconductor substrate 106. Exemplary types of materials that can be included in the one or more piezoelectric layers 802 can include, but are not limited to, zinc oxide, cadmium sulfide, cadmium selenide, aluminum nitride, aluminum scandium nitride (e.g., with varying aluminum to scandium ratios), lithium niobate, lead titanate, combinations thereof, and / or the like. In various embodiments, the one or more piezoelectric layers 802 can have a thickness (e.g., along the “Y” axis shown in FIG. 8) ranging from 0.03 μm to 10 μm, for example. Additionally, the resonator structure 800 can have a first electrode 804 and / or a second electrode 806 disposed adjacent to the one or more piezoelectric layers 802. For example, the first electrode 804 can be disposed above the one or more piezoelectric layers 802 along the "Y" axis shown in FIG. 8, and the second electrode 806 can be disposed below the one or more piezoelectric layers 802 along the "Y" axis (e.g., as shown in FIG. 8). In various embodiments, the first electrode 804 can contact a first surface of the one or more piezoelectric layers 802, and the second electrode 806 can contact a second surface (e.g., opposite the first surface) of the one or more piezoelectric layers 802 (e.g., as shown in FIG. 8). Furthermore, the first electrode 804 and the second electrode 806 can have substantially the same composition or different compositions. Exemplary materials that may be comprised within the first electrode 804 and / or the second electrode 806 can include, but are not limited to, molybdenum, aluminum, tungsten, combinations thereof, and / or the like.

[0051] In one or more embodiments, the semiconductor substrate 106 can have a first semiconductor substrate portion 106a and a second semiconductor substrate portion 106b that can be spaced apart from one another. Furthermore, the second electrode 806 can be disposed between the first semiconductor substrate portion 106a and the second semiconductor substrate portion 106b (e.g., as shown in FIG. 8 ). In one or more embodiments, the one or more piezoelectric layers 802 can generate an internal charge from an applied mechanical stress and provide the charge to the first electrode 804 and / or the second electrode 806. For example, the resonator structure 800 can generate an oscillating signal of a defined frequency in response to a resonant mechanical vibration.

[0052] In various embodiments, the operating frequency of the resonator structure 800 can be tuned by one or more tuning layers 808, which can be printed on the first electrode 804 and / or the one or more piezoelectric layers 802 by one or more three-dimensional printing techniques in accordance with the printing techniques used to form the one or more interconnects 102 described herein. For example, the one or more tuning layers 808 can be composed of an ink material compatible with one or more three-dimensional printing techniques described herein. Exemplary ink materials that can be included in the one or more tuning layers 808 can include, but are not limited to, gold, aluminum, copper, tantalum, cobalt, ruthenium, titanium, tin, silver, solder materials, alloys thereof, combinations thereof, and / or the like. In various embodiments, the one or more tuning layers 808 can be printed on only the first electrode 804, only the one or more piezoelectric layers 802, or a combination of at least a portion of the first electrode 804 and at least a portion of the one or more piezoelectric layers 802 (e.g., as shown in FIG. 8 ).

[0053] The one or more tuning layers 808 can have a thickness (e.g., along the "Y" axis shown in FIG. 8) ranging from 0.01 μm to 20 μm, for example. In various embodiments, the one or more tuning layers 808 can have a substantially uniform thickness (e.g., as shown in FIG. 8). Alternatively, the one or more tuning layers 808 can have multiple portions having respective thicknesses (e.g., thicker portions or thinner portions). Furthermore, the top surface 810 of the one or more tuning layers 808 can have various geometries depending on the desired operating frequency of the resonator structure 800. For example, the top surface 810 of the one or more tuning layers 808 can have a circular and / or polygonal geometry (e.g., such as the geometry of the top surface 202 of the one or more interconnects 102 shown in FIG. 2). In various embodiments, the shape of the top surface 810 can affect the amount of ink material provided in the one or more tuning layers 808.

[0054] As the ink material is printed on the first electrode 804 and / or the one or more piezoelectric layers 802 to form the tuning layer(s) 808, the presence of the ink material can change the operating frequency of the resonator structure 800. The composition, location, dimensions, and / or geometry of the tuning layer(s) 808 can thereby affect the operating frequency of the resonator structure 800. Furthermore, the composition, location, dimensions, and / or geometry can be selected to achieve a target operating frequency of the resonator structure 800. For example, as more ink material is deposited on the one or more piezoelectric layers 802 and / or the first electrode 804 to form the tuning layer(s) 808, the operating frequency of the resonator structure 800 can increase. The various embodiments described herein can be used to individually tune each resonator structure 800 of a semiconductor device, whereby the combination of the resonator structures 800 can form a filter tuned to achieve a desired center frequency and / or bandwidth.

[0055] FIG. 8 illustrates an exemplary resonator structure 800 embodied as a film bulk acoustic wave resonator ("FBAR"), where one or more piezoelectric layers 802 may be suspended by an air bridge between the first semiconductor substrate portion 106a and the second semiconductor substrate portion 106b, although the structure of the resonator structure 800 is not so limited. For example, the resonator structure 800 may also be embodied as a solid-state mounted resonator ("SMR"), where one or more piezoelectric layers 802 may be disposed on one or more stacks of alternating layers of low impedance and high impedance materials that may be disposed on the semiconductor substrate 106. Furthermore, one or more stacks may be constructed based on a Bragg reflector and may exhibit an acoustic mirror effect. For example, one or more stacks of alternating layers may have a quarter-wave layer that acts as a reflector to confine acoustic waves in the vicinity of the one or more piezoelectric layers 802. The number of alternating layers in the stack or stacks can depend on the mechanical impedance between the layers and / or the semiconductor substrate 106, as well as an analysis of the resonant response as a function of the number of layers versus the resonator Q and coupling coefficient. If the resonator structure 800 embodies an SMR structure, then one or more tuning layers 808 can still be disposed on the one or more piezoelectric layers 802 and / or first electrode 804 according to various embodiments described herein.

[0056] FIG. 9 shows a diagram of an exemplary and non-limiting resonator structure 800 during a first stage of tuning according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. During the first stage of tuning, an untuned resonator structure 800 may be provided and / or prepared for subsequent printing of one or more tuning layers 808. For example, before tuning, the resonator structure 800 may have a semiconductor substrate 106, one or more piezoelectric layers 802, a first electrode 804, and / or a second electrode 806 without one or more tuning layers 808. In various embodiments, the resonator structure 800 may be operated during the first stage of tuning to determine an initial operating frequency. Based on the initial operating frequency, an amount of ink material to be added (e.g., by one or more second and / or third stages of tuning described herein) may be determined to achieve a target operating frequency.

[0057] 10A-10D show diagrams of an exemplary and non-limiting resonator structure 800 during a second stage of tuning according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. During the second stage of tuning, one or more tuning layers 808 can be printed on one or more piezoelectric layers 802 and / or first electrodes 804 by one or more three-dimensional printing techniques. As a result of the second stage of tuning, at least a first portion 808a of one or more tuning layers 808 can be formed on one or more piezoelectric layers 802 and / or first electrodes 804.

[0058] In various embodiments, a three-dimensional printing technique can deposit the ink material (e.g., a metallic material) of the one or more adjustment layers 808 onto the one or more piezoelectric layers 802 and / or the first electrode 804. For example, the one or more three-dimensional printing techniques can print the one or more adjustment layers 808 by an additive process, where the ink material (e.g., a conductive ink material) can be deposited by successive layers repeatedly placed on top of each other until a desired three-dimensional shape is achieved. Exemplary three-dimensional printing techniques that can be used to print the one or more interconnects 102 can include, but are not limited to, direct-write printing techniques, inkjet printing techniques, aerosol jet printing techniques, combinations thereof, and / or the like.

[0059] For example, FIGS. 10A and 10C illustrate an exemplary nozzle 402 of a three-dimensional printing technique. An ink material (e.g., a metal material) constituting one or more adjustment layers 808 can be ejected from the nozzle 402 when performing a three-dimensional printing technique. For example, FIGS. 10A and 10C illustrate that an ink material (e.g., a metal material) is ejected from the exemplary nozzle 402 onto one or more piezoelectric layers 802 and / or a first electrode 804. As shown in FIGS. 10A-10B, the exemplary nozzle 402 can move along a printing direction (e.g., represented by arrow "P" in FIGS. 10A-10B) according to various embodiments described herein. As the exemplary nozzle 402 moves along the printing direction (e.g., represented by arrow "P"), the nozzle 402 can also deposit an ink material (e.g., a metal ink material) onto one or more piezoelectric layers 802 and / or a first electrode 804.

[0060] FIG. 10A illustrates the nozzle 402 in a first position above one or more piezoelectric layers 802 during the three-dimensional printing technique. From the first position, the nozzle 402 can move along a printing direction (e.g., represented by arrow "P") to a second position illustrated in FIG. 10C. As illustrated in FIG. 10B, the printing direction (e.g., represented by arrow "P") can traverse the one or more piezoelectric layers 802 and / or the first electrode 804 along the X-axis, the Z-axis, and / or combinations thereof. Furthermore, the printing direction can follow a straight line, a curved line, a wavy line, combinations thereof, and / or the like. Thereby, the printing direction (e.g., represented by arrow "P") can traverse the area occupied by one or more adjustment layers 808. Furthermore, the path of the printing direction (e.g., represented by arrow "P") can be defined by the geometry of the one or more adjustment layers 808. Thus, the location and / or path of the printing direction (e.g., represented by arrow "P") can be based on the desired geometry of the one or more adjustment layers 808. For example, the path of the printing direction (e.g., represented by arrow "P") shown in FIG. 10B can be used to print rectangular prism and / or cube geometries of the one or more adjustment layers 808.

[0061] As the nozzle 402 traverses the printing direction (e.g., represented by arrow "P"), the ink material (e.g., metal ink material) can be deposited on the one or more piezoelectric layers 802 and / or the first electrodes 804. For example, FIGS. 10C-10D illustrate a first portion 808a of one or more tuning layers 808 formed from an example nozzle 402 traversing the example printing direction (e.g., represented by arrow "P") shown in FIG. 10B. Additionally, although FIGS. 10C-10D depict a continuous or near-continuous deposition of the ink material (e.g., conductive ink material) on the chip pad 104 along the printing direction (e.g., represented by arrow "P"), the three-dimensional printing structure is not so limited. For example, embodiments are also envisioned in which the ink material (e.g., metal ink material) is deposited periodically (e.g., according to one or more predetermined intervals).

[0062] In various embodiments, one or more exemplary nozzles 402 of one or more printing technologies can be controlled by one or more computing devices 404 by one or more communication connections 406 (e.g., direct electrical connections and / or wireless connections) according to various embodiments described herein. For example, the one or more computing devices 404 can transmit data and / or otherwise control the apparatus of one or more three-dimensional printing technologies to define the type of ink material to be used and / or one or more printing directions to be traversed by the nozzles 402. In various embodiments, the one or more computing devices 404 can execute three-dimensional printing software to direct the operation of the one or more nozzles 402 and thereby define one or more printing directions that may be used during tuning of the resonator structure 800 (e.g., as described below with respect to at least FIGS. 10A-10C ) to direct the deposition of the ink material (e.g., metal ink material).

[0063] 11A-11C show diagrams of an exemplary and non-limiting resonator structure 800 during a third stage of tuning according to one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. During the third stage of tuning, one or more tuning layers 808 can be further printed on one or more piezoelectric layers 802 and / or first electrodes 804 by one or more three-dimensional printing techniques. As a result of the third stage of tuning, one or more second portions 808b of one or more tuning layers 808 can be formed.

[0064] As shown in Figures 11A-11C, one or more features of the second stage of tuning can be repeated to further print one or more tuning layers 808. For example, one or more three-dimensional printing techniques can be further performed to deposit an ink material (e.g., a metal ink material) onto one or more previously formed portions of the one or more tuning layers 808 (e.g., onto at least the first portion 808a of the one or more tuning layers 808). By depositing additional ink material onto one or more previously formed portions of the tuning layer 808 (e.g., onto the first portion 808a of the tuning layer 808), the third stage of tuning can further print one or more tuning layers 808 to a desired height (e.g., can further print one or more tuning layers 808 along the Y-axis shown in Figures 11A and / or 11C).

[0065] In various embodiments, the third stage of adjustment can be repeated multiple times to print one or more adjustment layers 808 in a desired geometry and / or height (e.g., along the Y-axis in FIG. 11A and / or FIG. 11C ). For example, with each performance of the third stage of adjustment, additional ink material (e.g., metal ink material) can be deposited onto the previously deposited ink material to further print one or more adjustment layers 808. Furthermore, each performance of the third stage of adjustment can deposit ink material in the same sized area, smaller area, and / or larger area than one or more previous areas of ink material deposition. For example, each performance of the third stage of adjustment can follow the same one or more printing directions, or one or more different printing directions.

[0066] In one or more embodiments, the one or more three dimensional printing techniques can continuously deposit the ink material (e.g., metal ink material) while transitioning from the second stage of preparation to the third stage of preparation. Similarly, in one or more embodiments, the one or more three dimensional printing techniques can continuously deposit the ink material (e.g., metal ink material) while transitioning from one implementation of the third stage of preparation to another implementation of the third stage of preparation.

[0067] In various embodiments, the three-dimensional printing technique can follow one or more printing directions (e.g., represented by a "P" arrow) used during the second stage of adjustment during one or more of the third stages of adjustment. In one or more embodiments, the three-dimensional printing technique can follow one or more printing directions (e.g., represented by a "P" arrow) that are different from the one or more printing directions used during the second stage of adjustment during one or more of the third stages of adjustment. For example, FIG. 11B illustrates an exemplary printing direction (e.g., represented by a "P" arrow) used during the third stage of adjustment that is the opposite of the printing direction (e.g., represented by a "P" arrow) used during the second stage of adjustment. In another example, the one or more printing directions used during the third stage of manufacturing can be parallel or perpendicular to the one or more printing directions used during the second stage of adjustment.

[0068] As shown in FIG. 11B, the printing direction (e.g., represented by arrow "P") used during one or more implementations of the third stage of adjustment can traverse the previously deposited ink material along the X-axis, the Z-axis, and / or combinations thereof. Furthermore, the printing direction can follow a straight line, a curved line, a wavy line, combinations thereof, and / or the like. Thereby, the printing direction (e.g., represented by arrow "P") can traverse the area occupied by the additional portion of the one or more adjustment layers 808 (e.g., can traverse the area occupied by the one or more second portions 102b). Furthermore, the path of the printing direction (e.g., represented by arrow "P") can be defined by the geometry of the one or more adjustment layers 808. Thus, the position and / or path of the printing direction (e.g., represented by arrow "P") can be based on the desired geometry of the one or more adjustment layers 808 at a given height to be printed during a given implementation of the third stage of manufacturing. For example, the printing direction path shown in FIG. 11B (e.g., represented by arrow "P") can be used to elevate the rectangular prism and / or cube geometry defined during the second stage of adjustment shown in FIGS. 11A-11C.

[0069] As the nozzle 402 traverses the printing direction (e.g., represented by arrow "P") during one or more of the third stages of conditioning, the ink material (e.g., metal ink material) can be deposited onto the previously deposited ink material. For example, FIG. 11C illustrates a second portion 808b of the one or more conditioning layers 808 formed from the exemplary nozzle 402 traversing the exemplary printing direction (e.g., represented by arrow "P") shown in FIG. 11B. Furthermore, although FIGS. 11A-11C depict a continuous or near-continuous deposition of the ink material (e.g., metal ink material) onto the previously deposited ink material along the printing direction (e.g., represented by arrow "P"), the three-dimensional printing structure is not so limited. For example, embodiments are also envisioned in which the ink material (e.g., metal ink material) is deposited periodically (e.g., according to one or more predetermined intervals).

[0070] In various embodiments, the one or more print maps 700 can be used by the one or more computing devices 404 to facilitate tuning of the resonator structures 800. For example, a semiconductor device (e.g., a monolithic microwave integrated circuit ("MMIS") such as a bulk acoustic wave device) can have one or more resonator structures 800, and the one or more print maps 700 can depict print locations 602 corresponding to one or more of the resonator structures 800 to be tuned in the semiconductor device. Additionally, the one or more print maps 700 can depict one or more print directions used to form one or more tuning layers 808 during tuning (e.g., according to one or more iterations of a second and / or third stage of tuning described herein). According to various embodiments described herein, the multiple print maps 700 can be generated and / or used by the one or more computing devices 404 to facilitate the second and / or third stage of tuning.

[0071] 12 illustrates a flow diagram of an exemplary, non-limiting method 1200 that can facilitate fabrication of one or more three dimensional printed flip chip interconnects 102 in accordance with one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for the sake of brevity.

[0072] At 1202, the method 1200 can include forming one or more chip pads 104 by depositing metal on the semiconductor substrate 106. For example, the formation of the one or more chip pads 104 at 1202 can be performed according to a first stage of manufacturing described herein. At 1204, the method 1200 can include generating one or more print maps 700 that can define one or more locations (e.g., print locations) of the one or more chip pads 104 on the semiconductor chip. Additionally, the one or more print maps 700 can define one or more print directions utilized during the performance of one or more three-dimensional printing techniques. In various embodiments, one or more entities can use one or more computing devices 404 to facilitate the generation and / or use of the one or more print maps 700 generated at 1204. For example, generating 1204 one or more printed maps 700 may be performed during a first stage of manufacturing as described herein in preparation for a second and / or third stage of manufacturing as described herein. Additionally, generating 1204 one or more printed maps 700 may include one or more features described herein with respect to at least FIGS.

[0073] At 1206, the method 1200 may include forming one or more flip chip interconnects 102 by depositing a conductive ink material on one or more flip chip pads 104 by one or more three-dimensional printing techniques based on the one or more print maps 700. According to various embodiments described herein, one or more three-dimensional printing techniques may be used (e.g., by one or more computing devices 404) to print the conductive ink material onto one or more chip pads 104 to build the one or more interconnects 102 into a three-dimensional structure having a defined shape, geometry, and / or dimensions. For example, forming the one or more interconnects 102 at 1206 may be performed according to one or more iterations of the second and / or third stages of fabrication described herein.

[0074] 13 illustrates a flow diagram of an exemplary and non-limiting method 1300 that can facilitate tuning one or more resonator structures 800 by one or more three-dimensional printing techniques in accordance with one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for the sake of brevity.

[0075] At 1302, the method 1300 can include providing one or more resonators of a semiconductor device (e.g., resonator structure 800), where the one or more resonators can have one or more electrodes adjacent to one or more piezoelectric layers 802. For example, the one or more resonators provided at 1302 can embody the resonator structure 800 described herein. At 1304, the method 1300 can include determining an initial operating frequency of the one or more resonators (e.g., the resonator structure 800). For example, the one or more resonators can be operated during a first stage of tuning described herein to measure the initial operating frequency of the resonators.

[0076] At 1306, the method 1300 can include generating one or more print maps 700 that can define one or more locations of one or more resonators (e.g., resonator structures 800) on the semiconductor chip. Additionally, the one or more print maps 700 can define one or more print orientations utilized during the performance of one or more three-dimensional printing techniques. In various embodiments, one or more entities can use one or more computing devices 404 to facilitate the generation and / or use of the one or more print maps 700 generated at 1306. For example, generating the one or more print maps 700 at 1306 can be performed during a first stage of the tuning described herein in preparation for a second and / or third stage of the tuning described herein.

[0077] At 1308, the method 1300 can include tuning one or more resonators (e.g., resonator structure 800) by depositing an ink material (e.g., compatible with three-dimensional printing techniques) on a surface of one or more resonators based on one or more print maps 700, the depositing can be performed by one or more three-dimensional printing techniques. For example, the ink material can be printed on one or more piezoelectric layers 802 and / or electrodes (e.g., first electrode 804) of one or more resonators (e.g., resonator structure 800) by one or more three-dimensional printing techniques. For example, the depositing at 1308 can be performed according to one or more iterations of the second and / or third stages of tuning described herein. In various embodiments, depositing the ink material on one or more resonators can change the operating frequency of the resonators from an initial operating frequency to a target operating frequency. For example, the operating frequency of the one or more resonators can be increased as ink material is applied to the one or more resonators.

[0078] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X uses A or B" is intended to mean all natural inclusive permutations. That is, if X uses A, if X uses B, or if X uses both A and B, then "X uses A or B" is satisfied in any of the foregoing cases. Furthermore, the articles "a" and "an" as used in this specification and the accompanying drawings should generally be construed to mean "one or more" unless otherwise specified or clear from the context to be directed to the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not meant to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0079] Of course, it is not possible to describe every conceivable combination of components, products, and / or methods to describe the present disclosure, but one skilled in the art can recognize that many further combinations and modifications of the present disclosure are possible. Furthermore, to the extent that terms such as "includes," "has," "possesses," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when used as a transitional term in the claims. The description of various embodiments is presented for illustrative purposes, but is not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements over the art found in the marketplace of the embodiments, or to enable other skilled in the art to understand the embodiments disclosed herein.

Claims

1. A three-dimensional printed flip chip interconnect comprising a conductive ink material compatible with three-dimensional printing technology, the three-dimensional printed flip chip interconnect being located on a metal surface of a semiconductor chip. Semiconductor device.

2. The three-dimensional printing technique is a direct-write printing technique, an inkjet printing technique, or an aerosol jet printing technique; The semiconductor device of claim 1 .

3. the conductive ink material comprises at least one member selected from the group consisting of gold, aluminum, copper, tantalum, cobalt, ruthenium, titanium, tin, silver, solder, or an alloy thereof; The semiconductor device of claim 1 .

4. the three dimensional printed flip chip interconnect is cylindrical; The semiconductor device of claim 3 .

5. the metal surface is a chip pad having at least one metal selected from the group consisting of gold, aluminum, copper, tungsten, tantalum, silver, and palladium; The semiconductor device of claim 1 .

6. the three dimensional printed flip chip interconnect further comprises a second conductive ink material that is also compatible with the three dimensional printing technology; The semiconductor device of claim 1 .

7. a distal end of the three dimensional printed flip chip interconnect having a polygonal shaped surface; The semiconductor device of claim 1 .

8. 1. A method for manufacturing a semiconductor, comprising: forming flip chip interconnects by depositing a conductive ink material onto chip pads of a semiconductor device; The depositing is performed by a three-dimensional printing technique. method.

9. forming the chip pads by depositing metal on a semiconductor substrate; The metal comprises at least one member from the group consisting of gold, aluminum, copper, tungsten, tantalum, silver, and palladium; The method according to claim 8.

10. generating a printed map defining the locations of the chip pads on a semiconductor chip; the conductive ink material is deposited by the three-dimensional printing technique based on the printing map; 10. The method of claim 9.

11. the conductive ink material comprises at least one member selected from the group consisting of gold, aluminum, copper, tantalum, cobalt, ruthenium, titanium, tin, silver, or alloys thereof; The method according to claim 8.

12. The three-dimensional printing technique is a direct-write printing technique, an inkjet printing technique, or an aerosol jet printing technique; The method according to claim 8.

13. 1. A method for processing a semiconductor, comprising: tuning a resonator of the semiconductor device by depositing an ink material on a surface of the resonator of the semiconductor device; The depositing is performed by a three-dimensional printing technique. method.

14. providing a resonator having an electrode adjacent to the piezoelectric layer; the ink material is deposited on at least one of the electrodes and the piezoelectric layer; The method of claim 13.

15. generating a printed map defining the location of the resonator on the semiconductor chip; the ink material is deposited by the three-dimensional printing technique based on the printing map; The method of claim 13.

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