PACKAGE HAVING STACKED INTEGRATED DEVICES HAVING OVERHEAD - Patent application

Abstract

A package including a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the first integrated device. A portion of the second integrated device overhangs the first integrated device. The second integrated device is configured to be coupled to the substrate. The second integrated device includes a front surface and a back surface. The front surface of the second integrated device faces the substrate.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 375,931, filed in the United States Patent Office on July 14, 2021, the entire contents of which are incorporated by reference into this specification as if fully set forth below in its entirety, and for all applicable purposes.

[0002] Various aspects relate to a package having an integrated device. [Background technology]

[0003]

[0003] A package may include a substrate and an integrated device. These components are coupled together to provide a package capable of performing various electrical functions. How the integrated device and the substrate are coupled together affects how the package functions as a whole. There is a continuing need to provide better performing packages and reduce the overall size of the package. Summary of the Invention

[0004] Various features relate to packages having integrated devices.

[0005]

[0005] One embodiment provides a package including a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the first integrated device. A portion of the second integrated device overhangs the first integrated device. The second integrated device is configured to be coupled to the substrate. The second integrated device includes a front side and a back side. The front side of the second integrated device faces the substrate.

[0006] Another embodiment provides an apparatus including a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the first integrated device. A portion of the second integrated device overhangs the first integrated device. The second integrated device is configured to be coupled to the substrate. The second integrated device includes a front surface and a back surface. The front surface of the second integrated device faces the substrate.

[0007] Another embodiment provides a method for manufacturing a package. The method includes providing a substrate. The method includes bonding a first integrated device to the substrate. The method includes bonding a second integrated device to the first integrated device such that a portion of the second integrated device overhangs the first integrated device. The second integrated device is configured to be bonded to the substrate. The second integrated device includes a front surface and a back surface. The front surface of the second integrated device faces the substrate. [Brief description of the drawings]

[0008]

[0008] Various features, properties, and advantages may become apparent from reading the detailed description set forth below in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Figure 1]

[0009] FIG. 2 is a cross-sectional view of a package including a stacked integrated device having an overhang. [Diagram 2]

[0010] FIG. 2 is a cross-sectional view of a package including a stacked integrated device having an overhang. [Diagram 3]

[0011] FIG. 2 is a cross-sectional view of a package including a stacked integrated device having an overhang. [Figure 4]

[0012] FIG. 2 is a cross-sectional view of a package including a stacked integrated device having an overhang. [Diagram 5]

[0013] FIG. 2 is a cross-sectional view of a package including a stacked integrated device having an overhang. [Figure 6]

[0014] FIG. 2 is a cross-sectional view of a package including a stacked integrated device having an overhang. [Figure 7A]

[0015] 1A-1C illustrate an exemplary sequence for manufacturing a package including a stacked integrated device having an overhang. [Figure 7B] 1A-1C illustrate an exemplary sequence for manufacturing a package including a stacked integrated device having an overhang. [Figure 8A]

[0016] 1A-1C illustrate an exemplary sequence for manufacturing a package including a stacked integrated device having an overhang. [Figure 8B] 1A-1C illustrate an exemplary sequence for manufacturing a package including a stacked integrated device having an overhang. [Figure 9A]

[0017] 1A-1C illustrate an exemplary sequence for manufacturing a package including a stacked integrated device having an overhang. [Figure 9B] 1A-1C illustrate an exemplary sequence for manufacturing a package including a stacked integrated device having an overhang. [Figure 10]

[0018] FIG. 1 illustrates an exemplary flow diagram of a method for manufacturing a package including a stacked integrated device having an overhang. [Figure 11A]

[0019] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 11B] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 12]

[0020] 1 is an exemplary flow diagram of a method for manufacturing a substrate. [Figure 13]

[0021] Various electronic devices are illustrated that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0022] In the following description, specific details are described to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0010]

[0023] The present disclosure describes a package including a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the first integrated device. A portion of the second integrated device overhangs the first integrated device. The second integrated device is configured to be coupled to the substrate. The second integrated device includes a front surface and a back surface. The front surface of the second integrated device faces the substrate. The second integrated device is coupled to the substrate via at least one pillar interconnect, at least one solder interconnect, and / or an interposer. The package can avoid the use of wire bonds, which helps reduce the overall size of the package by reducing the interconnect length between the integrated devices, and helps improve the performance of the package. The package configuration, which includes placing one integrated device over another, can also reduce the size and / or footprint of the package while still providing improved package performance.

[0011] Exemplary Package Comprising Stacked Integrated Devices with Overhang

[0024] 1 shows a cross-sectional view of a package 100 including a stacked integrated device having an overhang. The package 100 includes a substrate 102, an integrated device 104, an integrated device 106, and an encapsulation layer 108. The integrated device 104 can be a first integrated device. The integrated device 106 can be a second integrated device. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder resist layer 126. A plurality of solder interconnects 130 can be coupled to the substrate 102.

[0012]

[0025] The integrated device 104 is coupled to the substrate 102 via a plurality of solder interconnects 140. The integrated device 106 is disposed on the integrated device 104. The integrated device 106 may be coupled to the integrated device 104 via an adhesive (not shown). A portion 180 of the integrated device 106 may overhang the integrated device 104. At least one pillar interconnect 160 may be coupled to the substrate 102 and a front surface of the portion 180 of the integrated device 106. The at least one pillar interconnect 160 may be coupled to the plurality of interconnects 122 via at least one solder interconnect (not shown). The integrated device 106 may be coupled to the substrate 102 via the at least one pillar interconnect 160. The at least one pillar interconnect 160 may be disposed between the substrate 102 and the portion 180 of the integrated device 106. The integrated device 106 can be configured to be electrically coupled to the integrated device 104 via at least one pillar interconnect 160, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between the integrated device 104 and the integrated device 106 can include at least one pillar interconnect 160, at least one interconnect from the plurality of interconnects 122, and / or at least one solder interconnect from the plurality of solder interconnects 140. In cases where a solder interconnect is present between the at least one pillar interconnect 160 and the plurality of interconnects 122, the electrical path can also include a solder interconnect between the at least one pillar interconnect 160 and the plurality of interconnects 122.

[0013]

[0026] The integrated device 104 may include a front side and a back side. Similarly, the integrated device 106 may include a front side and a back side. The front side of the integrated device 104 may face the substrate 102. The back side of the integrated device may include a die substrate (e.g., silicon) side of the integrated device. The front side of the integrated device 106 may face the back side of the integrated device 104 and / or the substrate 102. For example, the front side of the portion 180 of the integrated device 106 may face the substrate 102. The front side of the integrated device 106 may be bonded (e.g., mechanically bonded via an adhesive) to the back side of the integrated device 104.

[0014]

[0027] The encapsulation layer 108 can be disposed over the substrate 102, the integrated device 104, and the integrated device 106. The encapsulation layer 108 can at least partially encapsulate the integrated device 104, the integrated device 106, and the at least one pillar interconnect 160. The encapsulation layer 108 can include a mold, a resin, and / or an epoxy. The encapsulation layer 108 can be a means for encapsulation. The encapsulation layer 108 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0015]

[0028] The configuration of the package 100 may help to avoid the use of wire bonds. Avoiding the use of wire bonds helps to reduce the overall size of the package 100 by shortening the interconnection length between the integrated devices (e.g., 104, 106) and helps to improve the performance of the package 100. Because the front side of the integrated device 106 faces the substrate 102, there is a shorter and more direct electrical path between the substrate 102 and the integrated device 106, which helps to improve the signal speed between the integrated devices. Packages that use wire bonds may require more space between the integrated device and the edges of the package to accommodate the placement of the wire bonds. Because wire bonds are not required in the package 100, the edges of the package 100 can be placed closer to the edges of the integrated devices (e.g., 104, 106), which helps to reduce the overall form factor of the package 100. The same benefits and advantages may also be found with respect to other packages described in this disclosure.

[0016]

[0029] Different implementations may have packages with integrated devices of different configurations. FIG. 2 shows a package 200 including a stacked integrated device with an overhang. The package 200 is similar to the package 100 and may include similar components, the same components, and / or a similar configuration as the package 100. Therefore, the description of the package 100 may be applicable to the package 200. FIG. 2 shows that the package 200 includes at least one pillar interconnect 160 and at least one solder interconnect 260. The at least one solder interconnect 260 is coupled to the integrated device 106 and the at least one pillar interconnect 160. The at least one solder interconnect 260 may be coupled to a front surface of the portion 180 of the integrated device 106. The at least one pillar interconnect 160 may be coupled to the substrate 102. In some implementations, the at least one pillar interconnect 160 may be considered a part of the substrate 102. The integrated device 106 may be coupled to the substrate 102 via at least one solder interconnect 260 and at least one pillar interconnect 160. The at least one solder interconnect 260 and at least one pillar interconnect 160 may be disposed between the substrate 102 and a portion 180 of the integrated device 106. The integrated device 106 may be configured to be electrically coupled to the integrated device 104 via at least one solder interconnect 260, at least one pillar interconnect 160, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between the integrated device 104 and the integrated device 106 may include at least one solder interconnect 260, at least one pillar interconnect 160, at least one interconnect from the plurality of interconnects 122, and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0017]

[0030] FIG. 3 illustrates a package 300 including a stacked integrated device having an overhang. The package 300 is similar to the package 100 and may include similar components, the same components, and / or similar configurations as the package 100. Therefore, the description of the package 100 may be applicable to the package 300. FIG. 3 illustrates that the package 300 includes an interposer 302, at least one solder interconnect 260, and at least one solder interconnect 360. The at least one solder interconnect 260 is coupled to the integrated device 106 and the interposer 302. The at least one solder interconnect 260 may be coupled to a front surface of the portion 180 of the integrated device 106. The at least one solder interconnect 360 may be coupled to the substrate 102 and the interposer 302. The integrated device 106 may be coupled to the substrate 102 via at least one solder interconnect 260, an interposer 302, and at least one solder interconnect 360. The interposer 302 may be a substrate. The interposer 302 includes at least one dielectric layer 320 and at least one interconnect 322 (e.g., an interposer interconnect). The at least one solder interconnect 260, the interposer 302, and / or the at least one solder interconnect 360 may be disposed between the substrate 102 and the portion 180 of the integrated device 106.

[0018]

[0031] The integrated device 106 can be configured to be electrically coupled to the integrated device 104 via at least one solder interconnect 260, the interposer 302, at least one solder interconnect 360, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between the integrated device 104 and the integrated device 106 can include at least one solder interconnect 260, at least one interconnect 322, at least one solder interconnect 360, at least one interconnect from the plurality of interconnects 122, and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0019]

[0032] 1-3 illustrate that at least one pillar interconnect 160, at least one solder interconnect 260, interposer 302, and / or at least one solder interconnect 360 can be disposed between substrate 102 and portion 180 of integrated device 106 that overhangs integrated device 104.

[0020]

[0033] Different implementations may include different numbers of integrated devices, for example a package may include two or more integrated devices overhanging one or more integrated devices.

[0021]

[0034] FIG. 4 illustrates a package 400 including a stacked integrated device with an overhang. The package 400 is similar to the package 100 and may include similar components, the same components, and / or similar configurations as the package 100. Therefore, the description of the package 100 may be applicable to the package 400. FIG. 4 illustrates two integrated devices with an overhang above the integrated device. FIG. 4 illustrates that the package 400 includes a substrate 102, an integrated device 104 (e.g., a first integrated device), an integrated device 106 (e.g., a second integrated device), an integrated device 406 (e.g., a third integrated device), an encapsulation layer 108, at least one pillar interconnect 160 (e.g., at least one first pillar interconnect), and at least one pillar interconnect 460 (e.g., at least one second pillar interconnect).

[0022]

[0035] The integrated device 406 is disposed on the integrated device 104. The integrated device 406 may be coupled to the integrated device 104 via an adhesive (not shown). A portion 480 of the integrated device 406 may overhang the integrated device 104. A front surface of the integrated device 406 may face a rear surface of the integrated device 104 and / or the substrate 102. For example, a front surface of the portion 480 of the integrated device 406 may face the substrate 102. The front surface of the integrated device 406 may be coupled (e.g., mechanically coupled via an adhesive) to a rear surface of the integrated device 104.

[0023]

[0036] At least one pillar interconnect 460 may be coupled to the substrate 102 and a front surface of the portion 480 of the integrated device 406. At least one pillar interconnect 460 may be coupled to the plurality of interconnects 122 via at least one solder interconnect (not shown). The integrated device 406 may be coupled to the substrate 102 via at least one pillar interconnect 460. The integrated device 406 may be configured to be electrically coupled to the integrated device 104 via at least one pillar interconnect 460, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between the integrated device 104 and the integrated device 406 may include at least one pillar interconnect 460, at least one interconnect from the plurality of interconnects 122, and / or at least one solder interconnect from the plurality of solder interconnects 140. In cases where a solder interconnect is present between at least one pillar interconnect 460 and the plurality of interconnects 122, the electrical path may also include a solder interconnect between the at least one pillar interconnect 460 and the plurality of interconnects 122.

[0024]

[0037] The portion 480 of the integrated device 406 that overhangs the integrated device 104 may have a different size and / or length than the portion 180 of the integrated device 106 that overhangs the integrated device 104. Different implementations may have similar or different overhangs for different integrated devices. Note that at least one pillar interconnect 160 may be from a plurality of pillar interconnects (e.g., a row of pillar interconnects) coupled between the integrated device 106 and the substrate 102. Similarly, at least one pillar interconnect 460 may be from a plurality of pillar interconnects (e.g., a row of pillar interconnects) coupled between the integrated device 406 and the substrate 102.

[0025]

[0038] 5 illustrates a package 500 that includes a stacked integrated device having an overhang. Package 500 is similar to package 200 and / or package 400 and includes similar components, the same components, and / or similar configurations as package 200 and / or package 400. Thus, the descriptions of package 200 and package 400 may be applicable to package 500. FIG 5 illustrates two integrated devices overhanging another integrated device. FIG. 5 shows that package 500 includes substrate 102, integrated device 104, integrated device 106, integrated device 406, encapsulation layer 108, at least one pillar interconnect 160 (e.g., at least one first pillar interconnect), at least one pillar interconnect 460 (e.g., at least one second pillar interconnect), at least one solder interconnect 260 (e.g., at least one first solder interconnect), and at least one solder interconnect 560 (e.g., at least one second solder interconnect).

[0026]

[0039] The portion 480 of the integrated device 406 may overhang the integrated device 104. At least one solder interconnect 560 is coupled to the integrated device 406 and to the at least one pillar interconnect 460. The at least one solder interconnect 560 may be coupled to a front surface of the portion 480 of the integrated device 406. The at least one pillar interconnect 460 may be coupled to the substrate 102. In some implementations, the at least one pillar interconnect 460 may be considered as part of the substrate 102. The integrated device 406 may be coupled to the substrate 102 via the at least one solder interconnect 560 and the at least one pillar interconnect 460. The integrated device 406 may be configured to be electrically coupled to the integrated device 104 via the at least one solder interconnect 560, the at least one pillar interconnect 460, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between integrated device 104 and integrated device 406 may include at least one solder interconnect 560, at least one pillar interconnect 460, at least one interconnect from the plurality of interconnects 122, and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0027]

[0040] It should be noted that at least one pillar interconnect 160 and at least one solder interconnect 260 can be from a plurality of pillar interconnects (e.g., a row of pillar interconnects) and a plurality of solder interconnects (e.g., a row of solder interconnects) coupled between the integrated device 106 and the substrate 102. Similarly, at least one pillar interconnect 460 and at least one solder interconnect 560 can be from a plurality of pillar interconnects (e.g., a row of pillar interconnects) and a plurality of solder interconnects (e.g., a row of solder interconnects) coupled between the integrated device 406 and the substrate 102.

[0028]

[0041] FIG. 6 illustrates a package 600 including a stacked integrated device having an overhang. Package 600 is similar to package 300 and / or package 400 and includes similar components, the same components, and / or similar configurations as package 300 and / or package 400. Thus, the description of package 300 and package 400 may be applicable to package 600. FIG. 6 illustrates two integrated devices overhanging another integrated device. FIG. 6 illustrates that package 600 includes substrate 102, integrated device 104, integrated device 106, integrated device 406, encapsulation layer 108, interposer 302 (e.g., first interposer), interposer 602 (e.g., second interposer), at least one solder interconnect 260, at least one solder interconnect 360, at least one solder interconnect 660, and at least one solder interconnect 670.

[0029]

[0042] The portion 480 of the integrated device 406 may overhang the integrated device 104. At least one solder interconnect 670 is coupled to the integrated device 406 and the interposer 602. At least one solder interconnect 670 may be coupled to a front surface of the portion 480 of the integrated device 406. At least one solder interconnect 660 may be coupled to the substrate 102 and the interposer 602. The integrated device 406 may be coupled to the substrate 102 via the at least one solder interconnect 670, the interposer 602, and the at least one solder interconnect 660. The interposer 602 may be a substrate. The interposer 602 includes at least one dielectric layer 620 and at least one interconnect 622 (e.g., an interposer interconnect). The interposer 602 may be similar to the interposer 302.

[0030]

[0043] The integrated device 406 can be configured to be electrically coupled to the integrated device 104 via at least one solder interconnect 670, the interposer 602, at least one solder interconnect 660, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between the integrated device 104 and the integrated device 406 can include at least one solder interconnect 670, at least one interconnect 622, at least one solder interconnect 660, at least one interconnect from the plurality of interconnects 122, and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0031]

[0044] It should be noted that at least one interposer 302, at least one solder interconnect 260, and at least one solder interconnect 360 can be from a plurality of interposers (e.g., a row of interposers) and a plurality of solder interconnects (e.g., a row of solder interconnects) coupled between integrated device 106 and substrate 102. Similarly, at least one interposer 602, at least one solder interconnect 670, and at least one solder interconnect 660 can be from a plurality of interposers (e.g., a row of interposers) and a plurality of solder interconnects (e.g., a row of solder interconnects) coupled between integrated device 406 and substrate 102.

[0032]

[0045] It should be noted that the orientation of the interposer 302 and / or interposer 602 shown in this disclosure is exemplary. The interposer 302 and / or interposer 602 can also be oriented in different ways. The interposer 302 and / or interposer 602 can include a substrate. The interposer 302 and / or interposer 602 can be manufactured using the process described in Figures 11A, 11B. Figures 4-6 illustrate that at least one pillar interconnect 160, at least one solder interconnect 260, the interposer 302, and / or at least one solder interconnect 360 can be disposed between the substrate 102 and the portion 180 of the integrated device 106 that overhangs the integrated device 104. 4-6 also illustrate that at least one pillar interconnect 460, at least one solder interconnect 560, interposer 602, and / or at least one solder interconnect 660 may be disposed between the substrate 102 and the portion 480 of the integrated device 406 that overhangs the integrated device 104. Note that a package may include integrated devices coupled to a substrate using different combinations of pillar interconnects, solder interconnects, and / or interposers. For example, one integrated device may be coupled to a substrate via a pillar interconnect while another integrated device may be coupled to a substrate via an interposer. FIGS. 1-6 illustrate examples of integrated devices stacked on top of another, where one or more integrated devices (e.g., 106, 406) are coupled (e.g., mechanically coupled, electrically coupled) to a substrate (e.g., 102) via at least one non-wire bond. Examples of non-wire bonds include pillar interconnects, solder interconnects, and / or interposers. Non-wire bonds provide at least one electrical path between an integrated device and a substrate. Non-wire bonds may also provide structural support for portions of an integrated device that overhang another integrated device.

[0033]

[0046] The integrated device (e.g., 104, 106, 406) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 104, 106, 406) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0034]

[0047] In some implementations, the integrated device 104 (e.g., a first integrated device) may include a processor and / or a modem. In some implementations, the integrated device 106 (e.g., a second integrated device) and / or the integrated device 406 (e.g., a third integrated device) may include a memory. The integrated device 106 and the integrated device 406 may be planar with respect to each other. The integrated device 106 and the integrated device 406 may have similar or different thicknesses.

[0035]

[0048] Having described various packages, several methods for manufacturing the packages are now described below.

[0036] Exemplary Sequence for Fabricating a Package Comprising Stacked Integrated Devices with Overhang

[0049] In some implementations, manufacturing a package includes several processes. Figures 7A and 7B show an example sequence for providing or manufacturing a package. In some implementations, the sequence of Figures 7A and 7B can be used to provide or manufacture the package 100 of Figure 1. However, the process of Figures 7A and 7B can also be used to manufacture any of the packages (e.g., 400) described in this disclosure.

[0037]

[0050] It should be noted that the sequences of Figures 7A and 7B may be combined with one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0038]

[0051] As shown in FIG. 7A, stage 1 shows the state after the substrate 102 is prepared. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder resist layer 126. Different implementations can use different substrates with different numbers of metal layers. The substrate can include a coreless substrate, a core substrate, or an embedded trace substrate (ETS). FIG. 11A and FIG. 11B illustrate and describe one embodiment of manufacturing the substrate.

[0039]

[0052] Stage 2 illustrates the state after at least one pillar interconnect 160 has been formed on the substrate 102. A plating process may be used to form the at least one pillar interconnect 160. The at least one pillar interconnect 160 may be coupled to at least one interconnect from the plurality of interconnects 122. Note that in some implementations, the at least one pillar interconnect 160 may be provided with the substrate 102 when the substrate 102 is prepared in Stage 1. In some implementations, the at least one pillar interconnect 160 may be considered part of the substrate 102.

[0040]

[0053] Stage 3 shows the state after an integrated device 104 (e.g., a first integrated device) has been bonded to the substrate 102. The integrated device 104 may be bonded to the substrate 102 via a number of solder interconnects 140. A solder reflow process may be used to bond the integrated device 104 to the substrate 102.

[0041]

[0054] Stage 4 shows the state after the integrated device 106 (e.g., a second integrated device) is bonded to the integrated device 104 such that a portion (e.g., 180) of the integrated device 106 overhangs the integrated device 104. The integrated device 106 may be bonded to the integrated device 104 using an adhesive. For example, the front side of the integrated device 106 may be bonded to the back side of the integrated device 104 via an adhesive. The integrated device 106 may be bonded to the substrate 102 via at least one pillar interconnect 160. A solder reflow process may be used to bond the integrated device 106 to the at least one pillar interconnect 160, which may include using solder interconnects.

[0042]

[0055] In some implementations, the integrated device 106 may include at least one pillar interconnect 160. That is, in some implementations, the at least one pillar interconnect 160 may be formed and / or coupled to the integrated device 106 before it is coupled to the substrate 102. In such cases, it may not be necessary to form the at least one pillar interconnect 160 (in stage 2). A solder reflow process may be used to couple the at least one pillar interconnect 160 (e.g., of the integrated device 106) to the substrate 102. In such cases, at least one solder interconnect may be coupled to the at least one pillar interconnect 160 and to at least one interconnect from the plurality of interconnects 122. Different implementations may couple different integrated devices to the integrated device 104 and / or the substrate 102. For example, the integrated device 406 may be coupled to the integrated device 104.

[0043]

[0056] As shown in FIG. 7B, stage 5 shows the state after encapsulation layer 108 is provided over substrate 102 and integrated devices (e.g., 104, 106). Encapsulation layer 108 can encapsulate the integrated devices and / or components. Encapsulation layer 108 can include mold, resin, and / or epoxy. Compression molding, transfer molding, or liquid molding processes can be used to form encapsulation layer 108. Encapsulation layer 108 can be photoetchable. Encapsulation layer 108 can be a means for encapsulation.

[0044]

[0057] Stage 6 illustrates the state after the plurality of solder interconnects 130 have been bonded to the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 130 to the interconnects from the plurality of interconnects 122 of the substrate 102. Stage 6 may illustrate one embodiment of a package 100 that includes a stacked integrated device having an overhang.

[0045] Exemplary Sequence for Fabricating a Package Comprising Stacked Integrated Devices with Overhang

[0058] In some implementations, manufacturing a package includes several processes. Figures 8A and 8B show an example sequence for providing or manufacturing a package. In some implementations, the sequence of Figures 8A and 8B can be used to provide or manufacture package 200 of Figure 2. However, the process of Figures 8A and 8B can also be used to manufacture any of the packages described in this disclosure (e.g., 500).

[0046]

[0059] It should be noted that the sequences of Figures 8A and 8B may be combined with one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0047]

[0060] As shown in FIG. 8A, step 1 shows the state after the substrate 102 is prepared. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder resist layer 126. Different implementations can use different substrates with different numbers of metal layers. The substrate can include a coreless substrate, a core substrate, or an embedded trace substrate (ETS). FIG. 11A and FIG. 11B illustrate and describe an embodiment of manufacturing the substrate.

[0048]

[0061] Stage 2 illustrates the state after at least one pillar interconnect 160 has been formed on the substrate 102. A plating process may be used to form the at least one pillar interconnect 160. The at least one pillar interconnect 160 may be coupled to at least one interconnect from the plurality of interconnects 122. Note that in some implementations, the at least one pillar interconnect 160 may be provided with the substrate 102 when the substrate 102 is prepared in Stage 1. In some implementations, the at least one pillar interconnect 160 may be considered part of the substrate 102.

[0049]

[0062] Stage 3 shows the state after at least one solder interconnect 260 has been formed on the at least one pillar interconnect 160. A solder reflow process may be used to bond the at least one solder interconnect 260 to the at least one pillar interconnect 160.

[0050]

[0063] Stage 4 shows the state after an integrated device 104 (e.g., a first integrated device) is bonded to the substrate 102. The integrated device 104 may be bonded to the substrate 102 via a number of solder interconnects 140. A solder reflow process may be used to bond the integrated device 104 to the substrate 102.

[0051]

[0064] As shown in FIG. 8B, stage 5 shows a state after the integrated device 106 (e.g., a second integrated device) is bonded to the integrated device 104 such that a portion (e.g., 180) of the integrated device 106 overhangs the integrated device 104. The integrated device 106 can be bonded to the integrated device 104 using an adhesive. For example, the front side of the integrated device 106 can be bonded to the back side of the integrated device 104 via an adhesive. The integrated device 106 can be bonded to the substrate 102 via at least one solder interconnect 260 and at least one pillar interconnect 160. A solder reflow process can be used to bond the integrated device 106 to the at least one pillar interconnect 160 via the at least one solder interconnect 260. Different implementations can bond different integrated devices to the integrated device 104 and / or the substrate 102. For example, the integrated device 406 can be bonded to the integrated device 104.

[0052]

[0065] Stage 6 shows the state after an encapsulation layer 108 is provided (e.g., formed) over the substrate 102 and the integrated device. The encapsulation layer 108 can encapsulate the integrated device and / or components. The encapsulation layer 108 can include mold, resin, and / or epoxy. A compression molding process, a transfer molding process, or a liquid molding process can be used to form the encapsulation layer 108. The encapsulation layer 108 can be photoetchable. The encapsulation layer 108 can be a means for encapsulation.

[0053]

[0066] Stage 7 shows the state after the plurality of solder interconnects 130 have been bonded to the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 130 to the interconnects from the plurality of interconnects 122 of the substrate 102. Stage 7 may show one embodiment of a package 200 that includes a stacked integrated device having an overhang.

[0054] Exemplary Sequence for Fabricating a Package Comprising Stacked Integrated Devices with Overhang

[0067] In some implementations, manufacturing a package includes several processes. Figures 9A and 9B show an example sequence for providing or manufacturing a package. In some implementations, the sequence of Figures 9A and 9B can be used to provide or manufacture package 300 of Figure 3. However, the process of Figures 9A and 9B can also be used to manufacture any of the packages described in this disclosure (e.g., 600).

[0055]

[0068] It should be noted that the sequences of Figures 9A and 9B may be combined with one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0056]

[0069] As shown in FIG. 9A, step 1 shows the state after the substrate 102 is prepared. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder resist layer 126. Different implementations can use different substrates with different numbers of metal layers. The substrate can include a coreless substrate, a core substrate, or an embedded trace substrate (ETS). FIG. 11A and FIG. 11B illustrate and describe an embodiment of manufacturing the substrate.

[0057]

[0070] Stage 2 shows the state after an integrated device 104 (e.g., a first integrated device) has been bonded to the substrate 102. The integrated device 104 may be bonded to the substrate 102 via a number of solder interconnects 140. A solder reflow process may be used to bond the integrated device 104 to the substrate 102.

[0058]

[0071] Stage 3 shows the state after the interposer 302 has been bonded to the substrate 102. The interposer 302 may be bonded to the substrate 102 via at least one solder interconnect 360. The at least one solder interconnect 360 may be bonded to an interconnect from the plurality of interconnects 122. A solder reflow process may be used to bond the interposer 302 to the substrate 102.

[0059]

[0072] Stage 4 shows the condition after at least one solder interconnect 260 has been formed on the interposer 302. A solder reflow process can be used to bond the at least one solder interconnect 260 to the interposer 302.

[0060]

[0073] As shown in FIG. 9B, stage 5 shows a state after the integrated device 106 (e.g., a second integrated device) is bonded to the integrated device 104 such that a portion (e.g., 180) of the integrated device 106 overhangs the integrated device 104. The integrated device 106 can be bonded to the integrated device 104 using an adhesive. For example, the front side of the integrated device 106 can be bonded to the back side of the integrated device 104 via an adhesive. The integrated device 106 can be bonded to the substrate 102 via an interposer 302. The integrated device 106 can be bonded to the interposer 302 via at least one solder interconnect 260 using a solder reflow process. Different implementations can bond different integrated devices to the integrated device 104 and / or the substrate 102. For example, the integrated device 406 can be bonded to the integrated device 104.

[0061]

[0074] Stage 6 shows the state after an encapsulation layer 108 is provided (e.g., formed) over the substrate 102 and the integrated device. The encapsulation layer 108 can encapsulate the integrated device and / or components. The encapsulation layer 108 can include mold, resin, and / or epoxy. A compression molding process, a transfer molding process, or a liquid molding process can be used to form the encapsulation layer 108. The encapsulation layer 108 can be photoetchable. The encapsulation layer 108 can be a means for encapsulation.

[0062]

[0075] Stage 7 shows the state after the plurality of solder interconnects 130 have been bonded to the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 130 to the interconnects from the plurality of interconnects 122 of the substrate 102. Stage 7 may show one embodiment of a package 300 that includes a stacked integrated device having an overhang.

[0063] Exemplary Flow Diagram of a Method for Fabricating a Package that Includes Stacked Integrated Devices with Overhang

[0076] In some implementations, manufacturing a package including a substrate and a stacked integrated device having an overhang includes several processes. Figure 10 shows an example flow diagram of a method 1000 for providing or manufacturing a package. In some implementations, the method 1000 of Figure 10 can be used to provide or manufacture the package 100 of Figure 1 described in this disclosure. However, the method 1000 can also be used to provide or manufacture any of the packages described in this disclosure (e.g., 200, 300, 400, 500, 600).

[0064]

[0077] It should be noted that the method of Figure 10 may combine one or more processes to simplify and / or clarify the sequence for providing or manufacturing the package. In some implementations, the order of the processes may be changed or modified.

[0065]

[0078] The method provides (at 1005) a substrate (e.g., 102). The substrate 102 may be provided by a supplier or may be manufactured. The substrate 102 may be manufactured using a process similar to that shown in FIG. 11A-B. However, different implementations may use different processes to manufacture the substrate 102. Examples of processes that may be used to manufacture the substrate 612 include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder resist layer 126. The substrate 102 may include an embedded trace substrate (ETS). In some implementations, the at least one dielectric layer 120 may include a prepreg layer. In some implementations, the substrate 102 may include at least one pillar interconnect (e.g., 160). FIG. 7A, step 1, illustrates and describes one embodiment of preparing a substrate.

[0066]

[0079] The method includes (at 1010) bonding at least one integrated device (e.g., a first integrated device) to a substrate. For example, an integrated device 104 is bonded to a first surface (e.g., a top surface) of a substrate 102. The integrated device 104 may be bonded to the substrate 102 via a plurality of solder interconnects 140. In some implementations, the integrated device 104 may be bonded to the substrate 102 via a plurality of pillar interconnects (not shown) and a plurality of solder interconnects 140. A solder reflow process may be used to bond the integrated device 104 to the substrate 102 via the plurality of solder interconnects 140. Stage 2 of FIG. 7A illustrates and describes one embodiment of bonding at least one integrated device to a substrate.

[0067]

[0080] The method includes (at 1015) bonding another integrated device to the integrated device. For example, the integrated device 106 (e.g., a second integrated device) is bonded to the integrated device 104 such that a portion (e.g., 180) of the integrated device 106 overhangs the integrated device 104. The integrated device 106 can be bonded to the integrated device 104 using an adhesive. For example, a front side of the integrated device 106 can be bonded to a back side of the integrated device 104 via an adhesive. The integrated device 106 can include at least one pillar interconnect 160. The integrated device 106 can be bonded to the substrate 102 via the at least one pillar interconnect 160. A solder reflow process can be used to bond the at least one pillar interconnect 160 to the substrate 102. In such a case, at least one solder interconnect can be bonded to the at least one pillar interconnect 160 and to at least one interconnect from the plurality of interconnects 122. It should be noted that the at least one pillar interconnect 160 may be part of the substrate 102 prior to bonding the integrated device 106 to the substrate 102 and / or may be part of the integrated device 106. Step 4 of Figure 7A illustrates and describes one embodiment of bonding an integrated device via at least one pillar interconnect.

[0068]

[0081] In some implementations, the integrated device 106 may be coupled to the substrate 102 via at least one solder interconnect 260 and at least one pillar interconnect 160. In some implementations, the at least one pillar interconnect 160 may be considered part of the integrated device 106. In some implementations, the at least one pillar interconnect 160 may be considered part of the substrate 102. A solder reflow process may be used to couple the integrated device 106 to the at least one pillar interconnect 160 via the at least one solder interconnect 260. Step 5 of FIG. 8B illustrates and describes one example of coupling an integrated device via at least one pillar interconnect and at least one solder interconnect.

[0069]

[0082] In some implementations, the integrated device 106 may be coupled to the substrate 102 via an interposer 302. A solder reflow process may be used to couple the integrated device 106 to the interposer 302 via at least one solder interconnect 260. The interposer 302 may be coupled to the substrate 102 via a solder reflow process. Step 5 of Figure 9B illustrates and describes one example of coupling an integrated device at least via an interposer.

[0070]

[0083] The method forms (at 1020) an encapsulation layer (e.g., 108) over the substrate (e.g., 102). The encapsulation layer 108 can be provided and formed over the substrate 102 and the integrated devices (e.g., 104, 106). The encapsulation layer 108 can encapsulate the integrated devices and / or components. The encapsulation layer 108 can include molded materials, resins, and / or epoxies. The encapsulation layer 108 can be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation layer 108 can be photoetchable. The encapsulation layer 108 can be a means for encapsulation. Step 5 of FIG. 7B illustrates and describes one embodiment of forming an encapsulation layer.

[0071]

[0084] The method includes (at 1025) bonding a plurality of solder interconnects (e.g., 130) to a second surface of a substrate (e.g., 102). The plurality of solder interconnects 130 may be bonded to an interconnect (e.g., 122) disposed on the second surface of the at least one dielectric layer 120. A solder reflow process may be used to bond the plurality of solder interconnects 130 to the substrate 102. Step 6 of Figure 7B illustrates and describes one embodiment of bonding the solder interconnects to a substrate.

[0072]

[0085] The packages described in this disclosure (e.g., 100) can be manufactured one at a time, or can be manufactured integrally as part of one or more wafers and then singulated into individual packages.

[0073] Exemplary Sequence for Fabricating a Substrate

[0086] In some implementations, manufacturing a substrate includes several processes. FIGS. 11A and 11B show an exemplary sequence for providing or manufacturing a substrate. In some implementations, the sequence of FIGS. 11A and 11B can be used to provide or manufacture the substrate 102 of FIG. 1. However, the processes of FIGS. 11A and 11B can also be used to manufacture any of the substrates described in this disclosure.

[0074]

[0087] Note that the sequences of FIGS. 11A and 11B can combine one or more steps to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of this disclosure.

[0075]

[0088] As shown in FIG. 11A, step 1 shows the state after the carrier 1100 is prepared and a metal layer is formed on the carrier 1100. The metal layer can be patterned to form the interconnect 1102. A plating process and an etching process can be used to form the metal layer and the interconnect. In some implementations, the carrier 1100 can be provided with a metal layer patterned to form the interconnect 1102.

[0076]

[0089] Step 2 shows the state after the dielectric layer 1120 is formed on the carrier 1100 and the interconnect 1102. A deposition and / or lamination process can be used to form the dielectric layer 1120. The dielectric layer 1120 can include polyimide. However, different implementations can also use different materials for the dielectric layer.

[0077]

[0090] Stage 3 shows the state after the multiple cavities 1110 have been formed in the dielectric layer 1120. The multiple cavities 1110 can be formed using an etching process (e.g., a photoetching process) or a laser process.

[0078]

[0091] Stage 4 shows the state after interconnects 1112 have been formed in and on the dielectric layer 1120, including in and over the plurality of cavities 1110. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0079]

[0092] Stage 5 shows the state after another dielectric layer 1122 is formed on top of the dielectric layer 1120. A deposition and / or lamination process can be used to form the dielectric layer 1122. The dielectric layer 1122 can be the same material as the dielectric layer 1120. However, different implementations can use different materials for the dielectric layer.

[0080]

[0093] 11B, stage 6 shows the state after a number of cavities 1130 have been formed in the dielectric layer 1122. The cavities 1130 can be formed using an etching process or a laser process.

[0081]

[0094] Stage 7 shows the state after interconnects 1114 have been formed in and on dielectric layer 1122, including in and over multiple cavities 1130. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0082]

[0095] It should be noted that steps 5-7 may be repeated iteratively to form additional metal layers and additional dielectric layers. Some or all of the interconnects 1102, 1112, and / or 1114 may define a number of interconnects 122 in the substrate 102. The dielectric layers 1120 and 1122 may be represented by at least one dielectric layer 120.

[0083]

[0096] Stage 8 shows the state after the carrier 1100 has been detached (e.g., removed, ground away) from the dielectric layer 120, leaving behind a substrate 102 including at least one dielectric layer 120 and a number of interconnects 122.

[0084]

[0097] Stage 9 shows the state after solder resist layer 124 and solder resist layer 126 have been formed on substrate 102. A deposition process may be used to form solder resist layer 124 and solder resist layer 126. In some implementations, zero or one solder resist layer may be formed on at least one dielectric layer 120.

[0085]

[0098] Different implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0086] Exemplary Flow Diagram of a Method for Fabricating a Substrate

[0099] In some implementations, manufacturing a substrate includes several processes. Figure 12 shows an example flow diagram of a method 1200 for providing or manufacturing a substrate. In some implementations, the method 1200 of Figure 12 can be used to provide or manufacture the substrate of Figure 1. For example, the method of Figure 12 can be used to manufacture the substrate 102.

[0087]

[0100] It should be noted that the method 1200 of Figure 12 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate, and in some implementations, the order of the processes may be changed or modified.

[0088]

[0101] The method prepares (at 1205) a carrier 1100. Different implementations can use different materials for the carrier. The carrier can include a substrate, glass, quartz, and / or a carrier tape. Step 1 of Figure 11A illustrates and describes one example of a carrier being prepared.

[0089]

[0102] The method forms (at 1210) a metal layer on the carrier 1100. The metal layer can be patterned to form interconnects. A plating process can be used to form the metal layer and the interconnects. In some implementations, the carrier can include a metal layer. The metal layer on the carrier can be patterned to form the interconnects (e.g., 1102). Step 1 of FIG. 11A illustrates and describes one example of a metal layer and interconnects being formed on the carrier.

[0090]

[0103] The method forms (at 1215) a dielectric layer 1120 over the carrier 1100 and the interconnect 1102. A deposition and / or lamination process may be used to form the dielectric layer. The dielectric layer 1120 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1110) in the dielectric layer 1120. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 2 and 3 of FIG. 11A illustrate and describe one embodiment of forming the dielectric layer and the cavities in the dielectric layer.

[0091]

[0104] The method forms (at 1220) an interconnect in and over the dielectric layer. For example, interconnect 1112 may be formed in and over dielectric layer 1120. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity in the dielectric layer. Step 4 of FIG. 11A illustrates and describes one embodiment of forming an interconnect in and over the dielectric layer.

[0092]

[0105] The method forms (at 1225) a dielectric layer 1122 over the dielectric layer 1120 and the interconnect. A deposition and / or lamination process may be used to form the dielectric layer. The dielectric layer 1122 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1130) in the dielectric layer 1122. The plurality of cavities may be formed using an etching process or a laser process. Steps 5 and 6 of Figures 11A and 11B illustrate and describe one embodiment of forming the dielectric layer and the cavities in the dielectric layer.

[0093]

[0106] The method forms (at 1230) an interconnect in and / or on the dielectric layer. For example, interconnect 1114 may be formed. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer over and within the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity in the dielectric layer. Step 7 of FIG. 11B illustrates and describes one embodiment of forming an interconnect in and on the dielectric layer.

[0094]

[0107] The method may form additional dielectric layers and additional interconnects as described at 1225 and 1230 .

[0095]

[0108] Once all the dielectric layers and additional interconnects have been formed, the method may proceed to detach (e.g., remove, grind away) the carrier (e.g., 1100) from the dielectric layer 1120, leaving the substrate. In some implementations, the method may form one or more solder resist layers (e.g., 124, 126) over the substrate.

[0096]

[0109] Different implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0097] Exemplary Electronic Devices

[0110] FIG. 13 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1302, a laptop computer device 1304, a fixed location terminal device 1306, a wearable device 1308, or an automotive vehicle 1310 may include a device 1300 as described herein. The device 1300 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1302, 1304, 1306, and 1308 and the vehicle 1310 illustrated in FIG. 13 are merely examples. Other electronic devices may also feature device 1300, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, portable data units such as handheld personal communication system (PCS) units, personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous cars), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0098]

[0111] One or more of the components, processes, features, and / or functions shown in Figures 1-6, 7A, 7B, 8A, 8B, 9A, 9B, 10, 11A, 11B, and / or 12-13 may be rearranged and / or combined into a single component, process, feature, or function, or may be embodied as several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 1-6, 7A, 7B, 8A, 8B, 9A, 9B, 10, 11A, 11B, and / or 12-13 and the corresponding descriptions thereof in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 1-6, 7A, 7B, 8A, 8B, 9A, 9B, 10, 11A, 11B, and / or 12, 13 and corresponding descriptions thereof may be used to manufacture, fabricate, prepare, and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0099]

[0112] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0100]

[0113] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even though they are not in direct physical contact with each other. An object that is coupled to another object may be coupled to a portion of the object, or to the entire object. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two objects that are electrically coupled may or may not propagate a current between the two objects. The use of the terms "first," "second," "third," and "fourth" (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The term "encapsulate" means that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may also be considered a bottom component and vice versa.As described in this disclosure, a first component being disposed "over" a second component can mean that the first component is disposed above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be disposed above (e.g., above) a first surface of the second component, and a third component may be disposed above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being disposed above another component, the term "over" as used in this application can be used to mean a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but is not in direct contact with the second component, (2) that the first component is present on (e.g., on a surface of) the second component, and / or (3) that the first component is present within (e.g., embedded within) the second component. A first component that is disposed "in" a second component can be partially disposed within the second component or can be completely disposed within the second component. The term "about 'value X'" or "approximately value X" as used in this disclosure means within 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0101]

[0114] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, the interconnects may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process.

[0102]

[0115] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0103]

[0116] In the following, further examples are described to facilitate understanding of the invention.

[0104]

[0117] Aspect 1: A package comprising a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the first integrated device. A portion of the second integrated device overhangs the first integrated device. The second integrated device is configured to be coupled to the substrate. The second integrated device includes a front surface and a back surface. The front surface of the second integrated device faces the substrate.

[0105]

[0118] Embodiment 2: The package of embodiment 1, wherein a second integrated device is coupled to the substrate via at least one pillar interconnect.

[0106]

[0119] Aspect 3: The package of aspect 1, wherein a second integrated device is coupled to the substrate via the interposer and at least one solder interconnect.

[0107]

[0120] Aspect 4: The package of Aspect 3, wherein the interposer includes a dielectric layer and at least one interposer interconnect.

[0108]

[0121] Example 5: The package of Examples 3 and 4, wherein an interposer is disposed between the substrate and a portion of the second integrated device that overhangs the first integrated device.

[0109]

[0122] Embodiment 6: The package of embodiments 1-5, wherein the second integrated device is coupled to the first integrated device via an adhesive.

[0110]

[0123] Aspect 7: The package of aspects 1-6, wherein the first integrated device includes a first front side and a first back side, and the front side of the second integrated device faces the first back side of the first integrated device.

[0111]

[0124] Embodiment 8: The package of embodiments 1-7, wherein the first integrated device is coupled to the substrate via a plurality of solder interconnects.

[0112]

[0125] Example 9: The package of Examples 1-8, further comprising a third integrated device coupled to the first integrated device, a portion of the third integrated device overhanging the first integrated device, and the third integrated device configured to be coupled to the substrate.

[0113]

[0126] Example 10: The package of example 9, wherein the third integrated device is coupled to the substrate via at least one pillar interconnect, at least one solder interconnect, and / or an interposer.

[0114]

[0127] Aspect 11: An apparatus comprising a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the first integrated device. A portion of the second integrated device overhangs the first integrated device. The second integrated device is configured to be coupled to the substrate. The second integrated device includes a front surface and a back surface. The front surface of the second integrated device faces the substrate.

[0115]

[0128] Example 12: The apparatus of example 11, wherein the second integrated device is coupled to the substrate via at least one pillar interconnect, at least one solder interconnect, and / or an interposer.

[0116]

[0129] Example 13: The apparatus of Example 12, wherein the interposer comprises a dielectric layer and at least one interposer interconnect.

[0117]

[0130] Example 14: The apparatus of Examples 12 and 13, wherein an interposer is disposed between the substrate and a portion of the second integrated device that overhangs the first integrated device.

[0118]

[0131] Example 15: The apparatus of Examples 11-14, wherein the second integrated device is coupled to the first integrated device via an adhesive.

[0119]

[0132] Example 16: The apparatus of Examples 11-15, wherein the first integrated device includes a first front surface and a first back surface, and the front surface of the second integrated device faces the first back surface of the first integrated device.

[0120]

[0133] Example 17: The apparatus of Examples 11-16, wherein the first integrated device is coupled to the substrate via a plurality of solder interconnects.

[0121]

[0134] Example 18: The apparatus of Examples 11-17, further comprising a third integrated device coupled to the first integrated device, a portion of the third integrated device overhanging the first integrated device, and the third integrated device configured to be coupled to the substrate.

[0122]

[0135] Example 19: The apparatus of example 18, wherein the third integrated device is coupled to the substrate via at least one pillar interconnect, at least one solder interconnect, and / or an interposer.

[0123]

[0136] Aspect 20: The apparatus of aspects 11 to 19, wherein the apparatus comprises a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0124]

[0137] Aspect 21: A method for manufacturing a package. The method provides a substrate. The method bonds a first integrated device to the substrate. The method bonds a second integrated device to the first integrated device such that a portion of the second integrated device overhangs the first integrated device. The second integrated device is configured to be bonded to the substrate. The second integrated device includes a front surface and a back surface. The front surface of the second integrated device faces the substrate.

[0125]

[0138] Example 22: The method of example 21, wherein the second integrated device is coupled to the substrate via at least one pillar interconnect, at least one solder interconnect, and / or an interposer.

[0126]

[0139] Example 23: The method of Examples 21 and 22, wherein the second integrated device is coupled to the first integrated device via an adhesive.

[0127]

[0140] Example 24: The method of Examples 21-23, further comprising forming an encapsulation layer over the substrate.

[0128]

[0141] Example 25: The method of examples 21-24, further comprising bonding a third integrated device to the first integrated device, a portion of the third integrated device overhanging the first integrated device, and the third integrated device configured to be bonded to the substrate.

[0129]

[0142] Example 26: The method of example 25, wherein the third integrated device is coupled to the substrate via at least one pillar interconnect, at least one solder interconnect, and / or an interposer.

[0130]

[0143] Various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A substrate; a first integrated device coupled to the substrate; a second integrated device coupled to the first integrated device, a portion of the second integrated device overhangs the first integrated device; the second integrated device is configured to be coupled to the substrate; the second integrated device includes a front surface and a back surface; the front surface of the second integrated device faces the substrate; the second integrated device is coupled to the substrate via an interposer and at least one solder interconnect; the interposer includes a dielectric layer and at least one interposer interconnect; The package, wherein the interposer interconnect is formed in a cavity having a trapezoidal cross section in the dielectric layer.

2. The package of claim 1 , wherein the interposer is disposed between the substrate and the portion of the second integrated device that overhangs the first integrated device.

3. The package of claim 1 , wherein the second integrated device is coupled to the first integrated device via an adhesive.

4. the first integrated device includes a first front surface and a first back surface; the front surface of the second integrated device faces the first back surface of the first integrated device; The package of claim 1.

5. The package of claim 1 , wherein the first integrated device is coupled to the substrate via a plurality of solder interconnects.

6. a third integrated device coupled to the first integrated device; a portion of the third integrated device overhangs the first integrated device; The package of claim 1 , wherein the third integrated device is configured to be coupled to the substrate.

7. The package of claim 6 , wherein the third integrated device is coupled to the substrate via at least one pillar interconnect, at least one solder interconnect, and / or an interposer.

8. An apparatus comprising the package of any one of claims 1 to 7, the apparatus comprising a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

9. 1. A method for manufacturing a package, comprising: Preparing a substrate; Coupling a first integrated device to the substrate; coupling a second integrated device to the first integrated device such that a portion of the second integrated device overhangs the first integrated device; the second integrated device is configured to be coupled to the substrate; the second integrated device includes a front surface and a back surface; the front surface of the second integrated device faces the substrate; the second integrated device is coupled to the substrate via an interposer and at least one solder interconnect; the interposer includes a dielectric layer and at least one interposer interconnect; The method, wherein the interposer interconnect is formed in a cavity having a trapezoidal cross section in the dielectric layer.

10. The method of claim 9 , wherein the second integrated device is coupled to the first integrated device via an adhesive.

11. The method of claim 9 , further comprising forming an encapsulation layer over the substrate.

12. further comprising coupling a third integrated device to the first integrated device; a portion of the third integrated device overhangs the first integrated device; The method of claim 9 , wherein the third integrated device is configured to be bonded to the substrate.

13. The method of claim 12 , wherein the third integrated device is coupled to the substrate via at least one pillar interconnect, at least one solder interconnect, and / or an interposer.

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