Active Vias

Abstract

Active vias are taught, including at least one via and at least one transistor that functions as a switch element. The resulting active vias can be used with 1D, 2.5D, or 3D chips to control circuit elements, reduce EMI between vias, increase via density, improve chip power and thermal efficiency, simplify power, data, and other routing networks on the chip, and allow more sophisticated stacking of dies or layers within the chip while maintaining modularity. A control strategy system can be provided to remove power to one or more regions of the chip when the region is not in use, to provide power to the region when the region is in use, or to control input / output to the region of the chip. The active vias can be manufactured by back-end or front-end processes.

Description

[Technical field]

[0001] Priority This application claims the benefit of convention priority to U.S. Provisional Patent Application No. 63 / 221,292, filed July 13, 2021, which is incorporated by reference in its entirety into this specification.

[0002] The present invention relates to semiconductor integrated circuits, and more particularly to active vias used in semiconductor integrated circuits and chips.

[0003] Background technology The semiconductor industry is working hard to increase the capabilities of semiconductor integrated circuits and to increase their usefulness and functionality while correspondingly increasing their complexity and size. For example, the recent M1 Max integrated circuit designed by Apple Inc. has over 5.7 billion transistors and further includes multiple processor cores and specialized processors such as graphics processing units.

[0004] Due to the size and complexity of these integrated circuits (commonly referred to as "chips"), components within a "chip" are often electrically linked using interconnects (typically referred to as "vias"). Local interconnects provide connections within a local circuit (e.g., between layers within the die on which the integrated circuit is formed), while global interconnects allow connections between different dies (i.e., dies or circuits fabricated on different wafers or by different companies, etc.).

[0005] In particular, through-silicon vias (“TSVs”) enable the fabrication of integrated circuits, such as 2.5D integrated circuits or 3D integrated circuits (“3DICs”), by vertically connecting two or more otherwise discrete circuits into a single package.

[0006] Conventional vias, both locally and globally, are passive circuit elements, where the only control over the circuit elements connected by the conventional via resides in the selection of the via's intrinsic properties (size, resistivity, etc.), and such control cannot be further altered by the application of external forces (e.g., voltage bias, current bias, etc.).

[0007] However, as chip designs become more complex, controlling and managing the various portions of the chip becomes more difficult, and the required management circuitry includes what are often referred to as "Uncore" components, such as RAM, memory controllers, power networks, etc. As the complexity of the chip increases, there is a corresponding increase in the complexity and size of the Uncore components.

[0008] Furthermore, there is a limit to the number of conventional vias that can be used within a single chip: placing two or more vias in close proximity can lead to electromagnetic interference ("EMI") issues, such as crosstalk between two or more conventional vias.

[0009] As chip complexity increases, the probability of EMI, e.g., crosstalk between traditional vias, also increases as vias get closer to each other. Specifically, attempts to reduce the area required for Uncore components can result in electrically connected vias (inductive coupling between layers within the chip) or pseudo-electrically connected vias (due to a combination of inductive coupling and physical connections).

[0010] In an attempt to reduce EMI, in some cases, the size of the vias can be changed or more process layers can be added to the chip to build conventional vias (e.g., coaxial vias). The added insulating layers are intended to reduce electromagnetic coupling and therefore crosstalk between conventional vias, but such changes come with additional manufacturing costs and / or design compromises.

[0011] Similarly, the process steps to fabricate conventional vias require a "keep-out zone" (KoZ) around the via, further reducing the area available for the core components. In some cases, a KoZ as large as twice the diameter of the via is required. This is because conventional vias typically require process steps that are performed at significantly higher temperatures, and these temperatures can significantly change the properties of adjacent components, which can cause circuit elements to fail. For example, properties of adjacent components that may be affected in this way include timing deviations as a signal passes through a via.

[0012] Although traditional vias play a vital role in moving signals between circuit elements within a chip, whether related to data, power or other functions, challenges and drawbacks associated therewith remain.

[0013] A further limitation of conventional vias relates to chip power consumption. In particular, to reduce power consumption of the entire chip (e.g., System-on-Chip "SoC" or System-in-Package "SiP" and similar variations), "control strategies" such as "dark silicon" management or input / output management are typically implemented to reduce power draw in areas of the chip not used for a given function.

[0014] Additionally, conventional vias do not provide electrostatic protection or signal suppression between regions, sections, or levels within a chip.

[0015] Various implementations of the control strategies have in common the approach of sending a specific voltage at set frequency signal (Dynamic Voltage Scaling or DVS technique) or a specific frequency at set voltage signal (Dynamic Frequency Scaling or DFS technique) or a specific combination of voltage-frequency signals (Dynamic Voltage-Frequency Scaling or DVFS technique) from the management circuitry through conventional vias such as TSVs to one or more regions of the chip to put the chip in "idle mode" and thereby reduce its power draw. Via the same mechanism, a signal is sent from the management circuitry to take one or more regions of the chip out of idle mode when the functionality of each region is required.

[0016] However, while such control strategies can reduce the power requirements of a chip somewhat, areas of the chip that are always in idle mode still draw power, even at a reduced level.

[0017] It would therefore be desirable to have active vias that could reduce or avoid at least some of these problems.

[0018] Summary of the Invention It is an object of the present invention to provide a novel active via that avoids or reduces at least one of the disadvantages of the prior art.

[0019] According to a first aspect of the present invention, there is provided an active via for use in a chip, comprising: a via having a first end and a second end; and a switch element integrated with the via, the switch element comprising at least one transistor having a source contact, a drain contact and a gate contact, the source contact forming an electrical contact with a first circuit element of the chip, the drain contact forming an electrical contact with a second circuit element of the chip, and the gate contact forming an electrical contact with a third circuit element of the chip, wherein the source contact and the drain contact are electrically connected when one of the first circuit element, the second circuit element and the third circuit element applies a voltage to their respective connected contacts causing the at least one transistor to form a channel.

[0020] Preferably, at least one transistor is a thin film transistor. Also preferably, the thin film transistor has a vertical channel. Also preferably, the via may be a local via or a global via. Also preferably, the active via functions as a circuit element.

[0021] According to another aspect of the present invention, there is provided a chip comprising a plurality of regions each capable of performing at least one specific circuit function, the chip comprising a control strategy circuit and at least one active via connected to each corresponding region and operable to supply at least one signal to each corresponding region, wherein when the circuit function performed by a region is not required, the control strategy circuit turns off the at least one active via that supplies the at least one signal to the region, and when the circuit function performed by a region is required, the control strategy circuit turns on the at least one active via that supplies the at least one signal to the region.

[0022] Preferably, the at least one signal includes a supply of power to the respective region. Also preferably, the active vias are formed in a back-end process.

[0023] According to another aspect of the present invention, there is provided a chip comprising at least a first region and a second region of circuit elements, each region realizing a respective circuit function, at least one active via connecting the first region and the second region, and a control system for changing a state of the active via between an on state and an off state.

[0024] The present invention provides novel active vias that include one or more vias and thin film transistor switch elements. The active vias can be used in 1D, 2.5D and / or 3D chips to control circuit elements, reduce or eliminate EMI between vias, such as between adjacent TSVs, increase via density, improve power and thermal efficiency of semiconductor circuits, simplify the chip's power, data and other routing networks, and allow more advanced die or layer stacking while maintaining modularity. Furthermore, by using the thin film transistors of the present invention, the active vias of the present invention can be fabricated in back-end or front-end processes.

[0025] Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0026] [Figure 1] FIG. 2 is a schematic diagram showing an active via. [Diagram 2] 2 illustrates an example of a vertical thin film transistor for use with the active via of FIG. 1. [Diagram 3] 2 is a perspective view of one embodiment of the active via of FIG. 1. [Figure 4] 2 is a perspective view showing another embodiment of the active via of FIG. 1. [Diagram 5] 2 is a cross-sectional view of an example of a portion of the network of active vias of FIG. 1. [Figure 6]FIG. 6 is a top view illustrating an example network of active vias similar to those of FIG. 5. [Figure 7] 2 is a perspective view showing another embodiment of the active via of FIG. 1. [Figure 8] 8 is a cross-sectional view of the network of active vias of FIG. 7. [Figure 9] FIG. 13 shows a plot comparing the performance of active and passive vias.

[0027] Detailed Description of the Invention As will be appreciated by those skilled in the art, many semiconductor devices are fabricated in a series of steps, namely, forming substantially planar layers of materials and subsequently removing, processing and / or replacing portions of these layers with subsequent layers to obtain the desired semiconductor device. Thus, as used herein, the terms "horizontal" and "vertical" are used with respect to the planes of these layers, with horizontal referring to a direction approximately parallel to the planes of the layers and vertical referring to a direction approximately perpendicular to the planes of the layers. Similarly, terms such as "up," "down," "on," and "under" are also used with respect to these planar layers. In particular, as used herein, the term "vertical" with respect to channels formed in transistors is intended to include all orientations of the channels that are not substantially parallel to the planes of the layers.

[0028] Furthermore, as will be apparent to one of ordinary skill in the art, the fabrication of layers and / or features of the semiconductor devices described herein is referred to herein as "forming" those layers and / or features, which, as will be apparent to one of ordinary skill in the art, is intended to include all applicable semiconductor fabrication techniques suitable therefor, including, but not limited to, deposition (chemical, atomic layer, physical vapor deposition, etc.), sputtering, PECVD (plasma enhanced chemical vapor deposition), implantation and annealing, oxidation, etc.

[0029] Also, as used herein, the term "chip" is used broadly and is intended to include all 1D devices (traditional flat semiconductor die), 2.5D devices (separate circuit dies or chips that are joined in subsequent process steps), and 3D devices (where multiple semiconductor circuits are "stacked" on top of each other on top of the same die).

[0030] An active via in accordance with one embodiment of the present invention is generally indicated at 20 in Figure 1. The active via 20 is switchable between an on state in which it passes a signal and an off state in which it does not pass a signal. In the presently preferred embodiment, the active via 20 is formed by a BEOL compatible process, as described in more detail below.

[0031] Active via 20 includes a via 22, such as a local via, global via, or through-silicon via, and a switch 24, in this example a thin film FET transistor ("TFT"), described in more detail below, having a source terminal 28 connected to a signal source 32, a drain terminal 36 connected to a signal destination 40, and a gate terminal 44, which is used to turn on or off switch 24 and thus via 20. In the example shown in Figure 1, switch 24 is shown as a single transistor, although the invention is not so limited and may include two or more transistors combined in common drain, common source, cascode, and other desired configurations, as described further below, if desired.

[0032] As will be apparent to one skilled in the art, when a voltage is applied to the gate terminal 44 of the switch 24, the active via 20 is in an on state, allowing signals to pass from the signal source 32 to the signal destination 40. When there is no voltage applied to the gate terminal 44, the active via 20 is in an off state, preventing signals from passing from the signal source 32 to the signal destination 40. The signals controlled by the active via 20 may include power provided to the signal destination 40, data signals, etc.

[0033] The active vias 20 can be turned off when not in use, thus allowing control of circuit elements (including Uncore components) by turning on or off regions, sections or levels of the element. Such active vias provide, among many other advantages, increased via density, improved power and thermal efficiency of semiconductor circuits, simplification of power, data and other routing networks in semiconductor circuits, and greater sophistication of die or layer stacking while maintaining modularity.

[0034] Additionally, the use of active vias 20 can provide the advantage of significantly reducing or eliminating EMI issues, such as crosstalk and isolation issues between multiple vias. Similarly, the size of KoZ can be reduced by using active vias 20. Another advantage of active vias 20 can include improved thermal stability and improved predictability of circuit operation at or around the active vias 20.

[0035] Perhaps even more importantly, the use of active vias 20 can provide the advantage of significantly reducing power consumption of the chip by minimizing power consumption in unused chip areas when the active vias are off or when the active vias' gating of power to one or more particular areas of the chip is off.

[0036] Additionally, active vias constructed with high standoff voltage characteristics can provide electrostatic protection between regions of a packaged chip, especially when one region is more sensitive than an adjacent region isolated through a via, such as a TSV, that operates at a higher voltage.

[0037] 2 shows the general structure of a TFT 100 that can be used as a switch 24 according to one embodiment of the present invention. The TFT 100 features a vertical channel (i.e., a conductive region through the semiconductor layer when the TFT 100 is on) and is therefore preferably used here with an active via 20, although the invention is not so limited and any suitable transistor may be used as would occur to one skilled in the art.

[0038] The TFT 100 includes a gate 104, a source 108, and a drain 112. The gate 104 includes a gate contact 116 and a gate electrode 120, the source 108 includes a source contact 124 and a source electrode 128, and the drain 112 includes a drain contact 132 and a drain electrode 136. The TFT 100 also includes a dielectric layer 140 adjacent the gate 104 of the TFT 100, and includes a first insulating layer 144 formed over a substrate 148 (which may be any suitable substrate and includes an interlevel dielectric layer that may include an interlevel dielectric layer that includes vias) and over a second insulating layer 152. The TFT 100 further includes a semiconductor layer 156 and, optionally, a source-channel interface member 160. If desired, the TFT 100 may also include a gate tuning layer 164, as shown.

[0039] In TFT 100, the drain, source and gate contacts and electrodes may be formed of the same material or the materials may be selected separately as desired. For example, the source contact 124 may be formed of a material selected for a desired work function, while the source electrode 128 may be selected from a material better suited for connection to other circuit components, such as metallization layers.

[0040] Semiconductor layer 156 is preferably a semiconductor material selected so that it can be formed at temperatures less than 400° C. Examples of suitable materials include, but are not limited to, zinc oxide, tin oxide, indium gallium oxide, gallium oxide, germanium oxide, and the like.

[0041] Unlike conventional thin film transistors, the TFT 100 may include a source-channel interface member 160 formed between and electrically connecting the source contact 124 and the semiconductor layer 156. The source-channel interface member 160 is formed from a material selected to function as a charge carrier transport barrier such that substantially no current flows through the semiconductor layer 156 when the TFT 100 is in the off state.

[0042] The source-channel interface member 160 may be a semiconductor, an induced piezoelectric dipole, a controllable tunnel barrier, or other mechanism for modulating the injection current by an externally applied electric field. The method of forming the source-channel interface member 160 is not particularly limited. For example, the source-channel interface member 160 may be formed from germanium element, or may be formed by using an opposite polarity dopant in the relevant portion of the semiconductor layer 156. In other cases, the source-channel interface member 160 may be made of an oxide or sulfide, or other elements corresponding to group VI(A) of the periodic table, or chalcogens, such as oxygen, sulfur, selenium, tellurium, ruthenium, or polonium.

[0043] The source-channel interface material 160 may also be formed by catalytic growth of the material that forms the source contact 124. In other cases, the source-channel interface material 160 may be formed by depositing an opposite polarity dopant, such as a p-type metal oxide or an n-type semiconductor, by a deposition technique such as atomic layer deposition, sputtering physical vapor deposition, or chemical vapor deposition.

[0044] The dielectric layer 140 separates the gate contact 116 from the semiconductor layer 156. The dielectric layer 140 blocks the flow of electrons to the gate contact 116 and allows charge carriers to form a channel between the source contact 124 and the drain contact 132 that has a high concentration of electrons. The dielectric layer 140 may be made of a material such as, for example, hafnium oxide (HfO2), zirconium dioxide (ZrO2), silicon dioxide (SiO2), silicon nitride (Si3N4), or other suitable material as would occur to one skilled in the art.

[0045] The TFT 100 may also have an optional gate tuning layer 164. The gate tuning layer 164 may be an atomic layer of metal used to tune the effective barrier height and / or work function of the gate contact 116 as desired, as will be apparent to one of ordinary skill in the art.

[0046] In TFT 100, each of the gate electrode 120, source electrode 128 and drain electrode 136 are typically formed from a highly conductive metal, such as copper or aluminum, which is used to electrically connect the corresponding electrode to appropriate elements in the remainder of the integrated circuit in which TFT 100 is formed.

[0047] The TFT 100 also has an insulating layer 144 formed over a substrate 148 (which may itself be an interlevel dielectric layer). The substrate 148 serves as a foundation for building components and devices such as transistors and integrated circuits, and the insulating layer 144 is a dielectric isolation substrate 148 that provides dielectric isolation from the source contact 124. Examples of insulating layer 144 may include materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and the like.

[0048] As discussed above, the source-channel interface 160 is used to create an excess counter charge reservoir or barrier that functions to deplete the channel at least in the region of the semiconductor layer 156 adjacent the source contact 124. In a TFT fabricated according to an embodiment of the invention, such as TFT 100, the distance from the gate contact 116 through the gate dielectric layer 140, the semiconductor layer 156, and the source-channel interface 160 to the source contact 124 is selected such that the electric field induced by a voltage applied to the gate contact 116 reduces the complementary excess charge reservoir blocking potential introduced by the source-channel interface 160, transitioning the TFT, such as TFT 100, to an on state. In the absence of such gate voltage application, the blocking potential causes the TFT to be in an off state.

[0049] The TFT 100 can be fabricated with various elements formed within a range of thicknesses and / or lengths. As will be apparent to those skilled in the art, the first limiting factor is that the gate contact 116 must be sufficiently electrically close to the source contact 124 such that a minimum threshold voltage applied to the gate 104 helps to effectively reduce the barrier to charge carrier flow into the semiconductor layer 156 induced by the source-channel interface member 160. If a sufficient electric field is not induced, the ability to "turn on" the TFT 100 is reduced. This is very similar to well-known criteria for MOSFETs, such as those typically referred to as the Ada (η) coefficient.

[0050] As an example of a method for manufacturing the TFT 100, the source, drain and gate formation can be accomplished by sputtering and patterning, the semiconductor layer formation can be accomplished by atomic layer deposition, the dielectric or insulator formation can be accomplished by atomic layer deposition, and the source-channel interface member formation can be accomplished by oxidation of the source contact (if the material is an oxidizable metal) or by sputtering a layer of a modified doped monoatomic semiconductor such as germanium or silicon.

[0051] TFT 100 is merely one embodiment of a TFT in accordance with aspects of the present invention, and although gate 104 and drain 112 are shown on the top of TFT 100, it will be apparent to one skilled in the art that TFTs in accordance with aspects of the present invention can be fabricated in a variety of orientations or configurations, including source-and-gate-on-top and drain-on-bottom, etc.

[0052] 3 illustrates an active via 200 that can be fabricated using BEOL compatible processes, if desired, in accordance with an embodiment of the present invention, in which like components are designated with like reference numerals as in FIG. 2. Also, for clarity of illustration, the first insulating layer 144 and the second insulating layer 152 have been omitted from the figure.

[0053] The active vias 200 can be turned off when not in use, thus allowing control of circuit elements (including Uncore components) by turning on or off regions, sections or layers of such elements. The use of active vias 200 can provide various advantages such as increased via density, improved chip power and thermal efficiency, simplification of power, data and other routing networks on a chip, more advanced die or layer stacking, while maintaining modularity, among other advantages. The use of active vias 200 can also provide the advantage of significantly reducing or eliminating EMI issues, such as crosstalk and isolation issues between multiple vias. Additionally, the use of active vias 200 can reduce the size of KoZ, improve thermal stability, and improve predictability of circuit operation at or around the active vias.

[0054] The active via 200, or a circuit including multiple instances of the active via 200, is intended to be connected between circuit elements of two "chips" or regions within a chip, and in the embodiment shown in FIG. 3, the source 108 of the TFT 100 of the active via 200 is connected to a first chip (not shown) to receive a signal S, either directly or through a metal interconnect, and the drain of the TFT 100 is connected to a second chip 208 using two vias, in this example TSV 212 and TSV 216. TSV 212 is connected to a first drain electrode 136a of the TFT 100, and TSV 216 is connected to a second drain electrode 136b of the TFT 100. TSV 212 and TSV 216 are made of a via metal, such as copper.

[0055] To control the active via 200, the gate electrode 120 is connected by a wire 220 to a control mechanism, for example, an uncore control circuit 204. When it is desired to turn on the active via 200, the control circuit 204 supplies a gate voltage V g to the gate electrode 120 to pass a signal “S” from the first chip through the source 108, the source-channel interface member 160, the n-type semiconductor layer 156, the drain 112, and the TSVs 212 and 216 to the chip 208. Conversely, when it is desired to turn off the active via 200, the control circuit 204 applies a gate voltage V g to turn off the TFT 100, thereby preventing the transfer of the signal S. As mentioned above, the signal S may be a power source that provides energy to an associated region of the second chip 208, or it may be a data or control signal intended for an area of ​​the second chip 208.

[0056] 4 shows a perspective view of another embodiment of an active via 300 in accordance with another aspect of the present invention, again with the insulating layer omitted for clarity. The active via 300 connects a first chip (not shown) to respective regions of a second chip 308 in a dual switch network.

[0057] The active via 300 includes a first via, e.g., TSV 312, a second via, e.g., TSV 316, and a third via, e.g., TSV 320. The active via 300 includes two TFTs, e.g., the two TFTs 100 described above, that are disposed adjacent to each other and share a drain electrode 136b. As shown in this embodiment, the TSV 312 is connected to the drain electrode 136a of the first TFT, and the TSV 320 is connected to the drain electrode 136b of the second TFT. The drain electrode 136b is also connected to the TSV 316, and the TSV 312, TSV 316, and TSV 320 are formed from a suitable via metal, such as copper. The gate electrodes 120 of the TFTs are connected to the control circuit 304 by metal interconnects 324, and the sources 108 of each TFT are bonded and connected to receive a signal S by metal interconnects 328.

[0058] As will be appreciated by those skilled in the art, the control circuit 304 may be configured to supply V g1 and / or V g2 The TFTs can be individually controlled by applying a gate voltage V g1 When the control circuit 304 supplies a gate voltage V g2 , signal S will be sent to the respective regions of chip 308 through TSV 316 and TSV 320. If control circuit chip 304 supplies both gate voltages, signal S will be sent to the respective regions of chip 308 through all three of TSV 312, TSV 316, and TSV 320. If control circuit chip 304 does not supply any gate voltages, signal S will not be sent to the respective regions of chip 308.

[0059] As should be apparent by now, if signal S is in fact the power supply to each region of chip 308, then control circuit 304 can very effectively control the power consumption of chip 308 and the corresponding thermal effects.

[0060] The active via 300 can be repeated to form a larger network of vias as desired, and an example of such an arrangement is shown in cross section in Figure 5 and in top view in Figure 6. In Figure 5, three vias such as TFTs 100 are positioned adjacent to one another with an insulator 340 disposed between them, and the drain electrodes are interconnected by metal 400. Figure 6 shows a top view of a similar arrangement to Figure 5, but with the gate electrodes 120 and drain electrodes 136 extending through corresponding vias.

[0061] 7 shows an active via 400 with a different configuration of TFTs, in particular with a TFT configuration with a drain 112 at the bottom and a source (108a, 108b) and gate 120 at the top of the TFT, according to an embodiment of the present invention. The active via 400 connects a first electronic chip 404 to a second electronic chip 408 using a number of through silicon vias 412. In the illustrated embodiment, the source contact 108a and the source contact 108b are connected to the electronic chip 404 via metal interconnects 416, and the drain electrode 136 is connected to the electronic chip via a TSV 412. The gate electrode 120 is connected to the electronic chip 404 by a metal interconnect 420. A cross-sectional view of the active via 400 is shown in FIG. 8.

[0062] A method of forming an active via in a chip, such as active via 200 of Figure 3, in accordance with one embodiment of the present invention, begins after a via is formed in the chip. A source 108 is formed at the bottom of the via, and a source-channel interface member 160 (if present) is formed at the top of the source 108.

[0063] For example, the source 108 can be formed from copper, tungsten, or any other material that would occur to one skilled in the art that can be used to fabricate a vertical transistor, and in particular, the material of the source 108 is selected based on its work function to provide the desired effect of electron injection into the accumulation layer during operation of the active via in combination with the source-channel interface member 160. The source-channel interface member 160 can also be formed in a variety of manners, and in one embodiment is deposited using atomic layer deposition techniques.

[0064] Next, a semiconductor layer 156 is formed over the source-channel interface member 160. The semiconductor layer 156 can be formed in a variety of ways, but in one embodiment is deposited using atomic layer deposition techniques.

[0065] A portion of the semiconductor layer 156 is then patterned to form a void within which the gate dielectric 140 is formed. The choice of material for the dielectric layer 140 is not particularly limited, and the dielectric layer 140 may be any suitable material having a high dielectric constant, as would be apparent to one skilled in the art.

[0066] A portion of the dielectric layer 140 is then patterned to form a void in which the gate 116 is formed. A drain contact 132 is then formed to contact the semiconductor layer 156, and a gate electrode 120 is formed on top of the gate 116.

[0067] Finally, in this example, drain electrodes 136a and 136b are formed on drain contact 132 in alignment with vias 212 and 216.

[0068] 9 shows a graph illustrating the performance of active vias according to an embodiment of the present invention. Plot 500 shows that when the active vias are turned off, the gain in isolation and crosstalk suppression is about 50 dB. In contrast, plot 504 shows that the prior art passive vias provide 0 dB of gain in isolation and crosstalk. The isolation and crosstalk suppression properties of the active vias tend to improve the power efficiency and thermal performance of the circuit when the active via network is off. Plot 508 shows that when the active vias are turned on, the signal throughput gain is about 10 dB at low frequency levels, while the passive vias provide 0 dB of gain.

[0069] Therefore, the active vias of the present invention can also be used as a means to suppress crosstalk between adjacent circuits, which allows for a significantly denser arrangement of circuits on a chip. For example, two adjacent circuits (or circuit elements) can be designed such that their input sensitivity requires an input level that can only be achieved if the input signal is amplified (by approximately 10 dB) by the active via that supplies the signal. Thus, if a first circuit receives an input signal through an active via that amplifies the input signal, any crosstalk received by a second circuit adjacent to the first circuit will be below the input sensitivity level of the second circuit, and the second circuit will not be affected by the crosstalk.

[0070] As should be apparent by now, the active vias of the present invention provide many advantages and / or additional features compared to conventional vias: For example, active vias can be used to provide electrostatic protection to regions of a chip by enabling power to be delivered to the regions to be controlled by one or more active vias, while data for or from those regions can be controlled by one or more other active vias.

[0071] Similarly, the transistor used as the switch 20 in the active via of the present invention can provide gain as shown in FIG. 9, so that the signal provided through the active via can be amplified as desired.

[0072] In the above examples, the active via is switched between an on state and an off state by application of a voltage to the gate, however, as will be apparent to one of ordinary skill in the art, one or more transistors in the active via can be configured to operate in a variety of other arrangements, such as common drain, common source, cascade or other configurations, thereby, for example, changing the state of the active via by applying a state-changing voltage to the source or drain instead, as will be apparent to one of ordinary skill in the art.

[0073] Moreover, because the active vias of the present invention are truly active, they can function as circuit elements of their own and within themselves, either individually or networked together to effectively form "mini-circuits" that enable desired additional functionality within the chip.

[0074] As will be apparent to those skilled in the art, the active vias of the present invention provide many advantages over conventional vias, and in particular can be used to achieve significant power savings (and corresponding increases in thermal efficiency or reductions in cooling requirements) by essentially powering off one or more regions of a chip when the active vias are off, rather than having them in an idle mode that still consumes significant amounts of power. As chip complexity and circuit density continue to increase, this ability to turn off regions of a chip will become increasingly important.

[0075] Furthermore, because the active vias of the present invention are active elements, they can be circuit elements themselves, either individually or networked together to form circuits on a chip. If the active vias of the present invention are fabricated in a back-end process, it becomes possible to add circuit elements built with active vias to a chip during the back-end process, providing greater flexibility for chip designers.

[0076] The present invention provides novel active vias that include one or more vias and transistor switch elements. The active vias are used to control circuit elements on 1D, 2.5D and / or 3D chips to reduce or eliminate EMI between vias including TSVs, increase via density, improve power and thermal efficiency of semiconductor circuits, simplify power, data and other routing networks on chips, and enable more advanced die or layer stacking while maintaining modularity. Furthermore, the active vias of the present invention can be fabricated in back-end or front-end processes by using the thin film transistors of the present invention.

[0077] The above-described embodiments of the invention are intended to be examples of the invention, and changes and modifications may be made by those of ordinary skill in the art without departing from the scope of the invention, which is defined solely by the appended claims.

Claims

1. A method for forming an active via in a semiconductor die, comprising: forming a via that penetrates the die and has a first end and a second end; forming a source contact at the first end of the via; forming a source-channel interface member above the source contact within the via, the source-channel interface member including a semiconductor material and being formed by oxidizing the source contact; forming a semiconductor layer above the source-channel interface member within the via; forming a gate dielectric above the semiconductor layer within the via; forming a gate contact above the gate dielectric within the via; forming a gate electrode in contact with the gate contact at the second end of the via and electrically connecting the gate contact to a control circuit; forming a drain contact in contact with the semiconductor layer at the second end of the via.

2. The method of claim 1, wherein the source contact is formed by sputtering.

3. The method of claim 1, wherein the semiconductor layer is formed by atomic layer deposition.

4. The method of claim 3, wherein the semiconductor layer includes tin oxide.

5. The method of claim 1, wherein the active via is formed in a back-end-of-line manufacturing process.

6. The method of claim 1, wherein the via is one of a local via, a global via, or a silicon through-via.

7. The method of claim 1, wherein the semiconductor layer does not surround the gate contact at the second end of the via, thereby exposing the surface of the gate contact for connection of the gate electrode.

8. The method of claim 7, wherein in the completed active via, the semiconductor layer does not surround the gate contact at the second end of the via.

9. The method of claim 1, further comprising forming a drain electrode in contact with the drain contact at the second end of the via, wherein the drain electrode and the gate electrode are formed in the same plane.

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