Page access frequency tracking

Abstract

An apparatus includes a memory access circuit (11) for processing memory access requests requesting access to a memory system (10, 32) and an access frequency tracking circuit (40). In response to a given memory access request requesting access to a given page of a memory address space, the access frequency tracking circuit (40) determines an outcome of a chance-dependent test, the outcome of the chance-dependent test being chance-dependent. If the outcome of the chance-dependent test is a first outcome, an access frequency tracking indicator corresponding to the given page is updated in an access frequency tracking structure. If the chance-dependent test has an outcome other than the first outcome, the access frequency tracking circuit 40 omits updating the access frequency tracking indicator corresponding to the given page.

Description

[Technical field]

[0001] The present technique relates to the field of data processing.

[0002] In a data processing system, it may be useful to provide a mechanism for tracking the relative frequency with which each page of a memory address space is accessed. This may be useful, for example, in determining how virtual addresses should be mapped to physical addresses, because the access frequency tracking information may be used to identify more frequently accessed pages of the address space that can be mapped to portions of the memory system that can be accessed more quickly, and less frequently accessed pages are allocated to portions of the memory system that have slower access.

[0003] At least some examples provide an apparatus that includes a memory access circuit that processes memory access requests requesting access to a memory system; and an access frequency tracking circuit responsive to a given memory access request requesting access to a given page of a memory address space, the access frequency tracking circuit for determining a result of a chance-dependent test that is chance-dependent when a result of the chance-dependent test is determined for the given memory access request, updating an access frequency tracking indicator corresponding to the given page in an access frequency tracking structure if the result of the chance-dependent test is a first result, and omitting updating the access frequency tracking indicator corresponding to the given page if the result of the chance-dependent test is a result other than the first result.

[0004] At least some examples provide a method for tracking a frequency of access to one or more pages of a memory address space, the method including: in response to a given memory access request requesting access to a given page of the memory address space, determining a result of a chance-dependent test that is chance-dependent when a result of the chance-dependent test is evaluated for the given memory access request; if the result of the chance-dependent test is a first result, updating an access frequency tracking indicator corresponding to the given page in an access frequency tracking structure; and omitting updating the access frequency tracking indicator corresponding to the given page if the result of the chance-dependent test is a result other than the first result. [Brief description of the drawings]

[0005] Further aspects, features, and advantages of the present technology will become apparent from the following description of examples, read in conjunction with the accompanying drawings. [Figure 1] 1 illustrates a schematic diagram of an example data processing system. [Diagram 2] FIG. 2 illustrates an example of an access frequency tracking circuit. [Diagram 3] FIG. 2 is a flow diagram illustrating a method for tracking access frequency to a given page of a memory address space. [Figure 4] Here are some examples of implementing chance dependency tests. [Diagram 5] Here are some examples of implementing chance dependency tests. [Figure 6] Here are some examples of implementing chance dependency tests. [Figure 7] Here are some examples of implementing chance dependency tests. [Figure 8] Here are some examples of implementing chance dependency tests. [Figure 9] Several examples of implementing the access frequency tracking structure are given below. [Figure 10] Several examples of implementing the access frequency tracking structure are given below. [Figure 11] Several examples of implementing the access frequency tracking structure are given below. [Figure 12] 1 illustrates an example in which an access frequency tracking indicator for a given page is stored in an access frequency tracking hardware structure (e.g., a translation lookaside buffer); and [Figure 13] Schematically illustrates reducing the probability that a chance-dependent test will provide a first result when an access frequency tracking indicator for a given page indicates that an estimated frequency of access to the given page has reached or exceeded a certain threshold.

[0006] One approach to tracking the frequency of access to pages of an address space may be to set a flag in a page table entry associated with a given page when the page is accessed or modified. However, this only distinguishes pages that have never been accessed from pages that have been accessed at least once. The flag may be expanded to be a counter, but typically there is not much room for bits in a page table entry. The inventors have recognized that for some purposes it may be useful to be able to distinguish pages that have been accessed a very large number of times from pages that have been accessed less often (e.g., distinguishing pages that are accessed on the order of 100-1000 times per second from pages that are accessed on the order of 1 million times per second). However, maintaining a counter with a sufficient number of bits to track this number of accesses per page may be costly in terms of performance, memory overhead and / or circuit area.

[0007] In the example described below, the apparatus has a memory access circuit for processing a memory access request requesting access to a memory system, and an access frequency tracking circuit for determining an outcome of a contingency-dependent test in response to a given memory access request requesting access to a given page of a memory address space. The outcome of the contingency-dependent test is contingency-dependent when determined for the given memory access request. If the outcome of the contingency-dependent test is a first outcome, an access frequency tracking indicator corresponding to the given page is updated in an access frequency tracking structure. However, when the contingency-dependent test provides an outcome other than the first outcome, updating of the access frequency tracking indicator corresponding to the given page is omitted.

[0008] Thus, rather than updating the access frequency tracking indicator every time there is an access to the corresponding page, the updates to the access frequency tracking indicator are updated at a time depending on whether the chance-dependent test provides a first result or another result. The chance-dependent test may be similar to a roll of a dice or a lottery, providing a certain probability of having a first result when it is a matter of chance whether the first result occurs for any given instance of a memory access request. Even if two memory access requests are controlled based on identical memory access control parameters (e.g., the same target address, the same type of memory access, the same permissions set in the page table entry, the same execution mode or operating state of the processor when issuing the memory access request, and the same control settings set in any control register for configuring how the memory access request is processed, etc.), the chance-dependent test may nevertheless provide a first result for one of the requests and a different result for another of the requests.

[0009] Thus, whether the chance-dependent test provides a first result, and therefore whether the access frequency tracking indicator corresponding to a given page is updated, depends on chance. This may be considered counterintuitive since the chance-dependent test will provide a first result for the very first access to a given page that has not been accessed before, but it is possible that a more frequently accessed page will provide a different result each time it is accessed, which may lead to increased inaccuracies in the access frequency tracking, and therefore may mean that the access frequency tracking structure may identify some pages as being accessed more frequently than they actually are. However, the inventors have recognized that, statistically, more frequently accessed pages are more likely to encounter instances where the chance-dependent test provides a first result than less frequently accessed pages. In effect, more frequently accessed pages are given a greater number of "rolls of the dice" compared to less frequently accessed pages, and therefore ultimately, more frequently accessed pages have a higher probability of having their access frequency tracking indicator updated. Thus, occasional false positives are unlikely to distort the tracking information provided by the access frequency tracking structure by a significant amount.

[0010] The advantage of using a chance-dependent test to control whether an access frequency tracking indicator is updated for an accessed page is that this can reduce circuit area, power and performance costs, even when the objective is to track page access frequency over a wide range of access numbers. By implementing a chance-dependent test such that the probability that the tracking indicator is updated is reduced for any particular memory access to a given page, this means that a smaller counter or other tracking indicator can be employed while simulating counts over a larger absolute range of access frequencies. This allows useful information about the approximate relative frequency of access to different pages to be tracked at much less cost in terms of circuit area, power and performance.

[0011] The chance-dependent test may have a software-configurable probability of providing a first result. Thus, the software may set the probability that the access frequency tracking indicator is updated for a memory access request to a corresponding page. For example, the probability that the test provides a first result may be defined as 1 / N, where the value of N is variable depending on a configuration value selected by the software.

[0012] In some cases, the right to configure the probability of the chance-dependent test providing the first result may be restricted to software with a certain level of privilege or above. Software operating with privileges below a threshold level of privilege may not be permitted to configure the probability.

[0013] In one example, the software configurable probability of providing the first outcome may be specified in a software configurable register, such that software can adjust the probability by updating the software configurable register.

[0014] Another example may provide a control state in a page table or another memory-based structure that can be updated by software to control the probability that the chance-dependent test provides the first result.

[0015] In some examples, the software configurable probability of providing a first result in a chance-dependent test may depend on a software configured global parameter shared among all memory access requests.

[0016] It is also possible to provide at least one software-configured local parameter that is specific to a particular subset of memory access requests that includes a given memory access request and controls the probability of the chance-dependent test providing a first result for that particular subset of memory access requests. For example, the local parameter may be specific to a particular type of access (e.g., whether the access is a privileged or non-privileged access, or whether the access is a load or a store), or may be specific to a memory access request issued in a particular execution mode or state. It is also possible to provide software-configured local parameters that are specific to a particular region of the address space. Thus, the probability of the chance-dependent test providing a first result can be independently adjusted for different subsets of memory accesses. If local parameters are defined to control the probability, they may be set in software-configurable registers or data structures in memory.

[0017] Setting independent probabilities for different subsets of memory access requests can be useful because it allows some subsets of memory access requests to be prioritized over other subsets when the tracking information is used by the software (e.g., to determine address mapping). For example, the software may wish to set a higher probability of a first outcome occurring for a first subset of accesses (e.g., secure / privileged accesses) compared to a second subset (e.g., less secure / privileged accesses) such that the apparent number of accesses represented by the access frequency tracking structure is skewed in favor of the first subset compared to the actual number of accesses for the first / second subset of accesses. When the access frequency tracking structure is later used by the software to control the memory map such that more frequently accessed pages can be allocated to faster parts of the memory system, this can increase the likelihood that the first subset of accesses can be performed with higher performance to take into account the software's preferred prioritization scheme. This can simplify software analysis of the access frequency tracking information, as if the prioritization was already taken into account when the access frequency tracking structures were updated, and there is less need for the analysis software algorithms to combine the access frequency tracking information with other information about the type of memory access. Thus, by supporting in hardware the ability for software to set independent probabilities for different subsets of memory accesses, this can provide a practical benefit to software developers in simplifying their code for analyzing the access frequency tracking information.

[0018] Some examples may use a combination of a software configured global parameter and one or more software configured local parameters to control the probability of a chance-dependent test providing a first result. For example, a global parameter may set a default probability, while one or more software configured local parameters may specify a different probability for a particular subset of memory access requests or specify an adjustment to the default probability used for that subset of access requests.

[0019] In some examples, the probability of a chance-dependent test providing a first result for a unique subset of memory access requests may remain constant regardless of the number of accesses previously encountered since tracing began.

[0020] However, in other approaches, the probability of the chance-dependent test providing a first result may be variable over time depending on the number of accesses to a given page. For example, the access frequency tracking circuit may set the probability of the chance-dependent test providing a first result separately for different pages of the memory address space, and in response to determining that the frequency of accesses to the given page has reached or exceeded a predetermined threshold, the access frequency tracking circuit may reduce the probability of the chance-dependent test providing a first result for a subsequent instance of a memory access request that requires access to the given page. It should be noted that since the access frequency tracking information may be statistically set based on chance-dependent tests as described above, the determination that the access frequency has reached / exceeded the threshold may not be accurate, but may be an estimated access frequency has reached / exceeded the threshold, and the estimate may provide an approximate indication of the relative frequency that may be a reasonable estimate on average, but the estimate may not be accurate in each particular instance.

[0021] In general, reducing the probability of a test giving a first result with increasing number of accesses to a given page may be useful to implement a non-linear scaling between the estimated number of accesses represented by the access frequency tracking indicator and the actual value of the access frequency tracking indicator used to represent that number of accesses. This may also help to reduce the overall size of the counters needed to track accesses over a wider range of magnitudes. For example, in some use cases, it may be useful to be able to distinguish pages that have never been accessed from pages that have been accessed at least once, but once a page has been accessed at least once, it may not be useful to be able to distinguish whether it has been accessed once, twice, three times, etc., until the number of accesses reaches a much larger value. Similarly, once a page has been accessed a certain number of times (e.g., 100 or 1000 times), the next boundary where it is interesting to identify pages that have been accessed beyond that number may not exist until the page access count reaches hundreds of thousands or millions. Thus, there may be several threshold interest points, but they may not be evenly distributed. As the number of accesses to a given page increases, this can be useful in allowing smaller counters to track a wider range so that the limited granularity of the frequency tracking indicator can be used more efficiently, by reducing the probability of a chance-dependent test providing a first result for an access to that page.

[0022] Chance-dependent tests can be implemented in a variety of ways. A chance-dependent test may have a probability of providing a first result that is less than one. A chance-dependent test may depend on information or signals that are not controllable by the software that causes a given memory access request to be issued. In some cases, issuing the exact same memory access request on different occasions may lead to different results of the chance-dependent test, even if all properties of the memory access request and software-defined parameters for controlling whether the memory access request may be granted are identical.

[0023] In one specific example (but not the only example), the contingency-dependent test includes determining whether a test evaluation counter provided for counting memory access requests satisfies a predetermined condition. The test evaluation counter may be any information that has a number of states and is advanced to a next state in response to each memory access request that satisfies at least one criterion for advancing the counter, and that may be determined to satisfy the predetermined condition if the state is advanced a certain number of times after the test evaluation counter is reset to an initial state. For example, the test evaluation counter may be a binary integer that is incremented or decremented each time an associated memory access request is encountered, and that may be considered to satisfy the predetermined condition when the test evaluation counter reaches a predetermined value or passes a given threshold. However, it is not required that the counter be represented as a binary integer, and another example may provide a shift register that is shifted to a next state in response to each memory access request that satisfies at least one criterion for advancing the counter, such that the shift register cycles through a certain series of states and satisfies the predetermined condition when it reaches a predetermined state within the cycle. For example, a shift register may comprise a certain number of bits having a first value (0 or 1) and one bit having a second value (the other of 0 and 1), and a single bit having a value distinct from all other bits may be considered to satisfy a predetermined condition when shifted into a particular location in the shift register, and the shift register is shifted by one location each time a memory access request that satisfies the advancement criteria is encountered. Of course, these are just some particular ways of implementing a test evaluation counter and other options may be used.

[0024] In general, by providing a test evaluation counter for evaluating chance-dependent tests, this can provide a simple method of implementing the evaluation of chance-dependent tests. Whether the test evaluation counter satisfies a predetermined condition when a given memory access request is processed can be considered a matter of chance since it depends not only on the characteristics of that particular memory access request, but also on apparently random occurrences such as the number of previously encountered requests and the relative order of memory access requests, which are usually outside the control of the software issuing the memory access request, and as a result, from the software's point of view, whether the test evaluation counter satisfies the predetermined condition can be considered an essentially random event that provides a 1 / N chance of providing a first result, where N is the number of states the counter traverses between initialization and reaching a state where the condition is satisfied.

[0025] In some examples, the test evaluation counter may be a global counter shared among all memory access requests regardless of which page is accessed by the memory access request, which may result in a lower implementation cost in terms of circuit area and power.

[0026] Alternatively, the test evaluation counter can be one of several local counters, each for counting a unique subset of memory access requests, and the contingency-dependent test performed when a given memory access request is processed can be based on the local counter corresponding to the unique subset of memory access requests that includes the given memory access request. For example, different local counters can correspond to unique subsets of memory access requests associated with different operating modes or execution states (e.g., distinguishing privileged access from less privileged access, or secure access from less secure access). Also, it is possible to provide different local counters corresponding to loads and stores, respectively, such that load requests (requiring data transfer from memory to registers) and store requests (requiring data transfer from registers to memory) have contingency-dependent tests evaluated based on different counters. In another option, local counters corresponding to unique regions or pages of the memory address space can be provided, such that a memory access request to one region or page can have contingency-dependent tests evaluated based on different counters for memory access requests targeting different regions or pages. In the case of page-specific local counters, a convenient structure for tracking local counters may be in a translation lookaside buffer (TLB) that stores address translation entries corresponding to respective pages, and the address translation entries for a given page may include the local counters corresponding to the given page. This may help reduce circuit area and power consumption by avoiding the need for an additional lookup to a separate structure, since an existing TLB lookup may be used to identify the local test evaluation counter for the currently accessed page. Nevertheless, it is also possible to implement a structure separate from the TLB to provide region / page-specific local test evaluation counters.

[0027] Providing separate local test evaluation counters specific to individual regions / pages of the memory address space can increase the accuracy of access frequency tracking, such that the estimated access frequency represented by the access frequency tracking indicator for a given page can be more closely correlated with the actual number of accesses to that page, since it reduces the likelihood that a false positive caused by an access to a previously unaccessed region / page will accidentally cause the first result of a dependent test.

[0028] Test evaluation counters are not the only way to implement chance-dependent tests. In another example, chance-dependent tests may include determining whether some of the bits have a predetermined value, the some of the bits including bits sampled from a serial pulse train derived from one or more items of internal control information of the device or from one or more analog or digital signals of the device. In some cases, it may not be necessary to maintain any special state (such as a counter) for the implementation of chance-dependent tests, especially since there may be existing signals or information within the data processing device (having other purposes than access frequency tracking) that can be sampled or reused to provide values ​​that can vary approximately randomly according to a certain probability, and thus can be sampled and compared to a predetermined value to determine whether the test is satisfied. For example, the processing device may have internal counters for counting events such as elapsed clock cycles, cache misses, or other events for performance monitoring, and some bits of those counters may be interpreted as a pulse train of equally spaced events with a certain probability. In another example, the serial pulse train can be derived from multiple internal states or physical signals that may be substantially independent of each other, but may be combined such that the resulting pulse train (a sequence of sampled bits based on successive values ​​of states / signals over time) can be considered effectively random, and the access frequency tracking circuitry can then evaluate whether those bits meet a certain condition (such as containing a certain number of 1's in a row). It is not essential that a digital signal is used as the source of the pulse train. Analog signals such as a random bit stream from a diode or an interference pattern between unrelated signals can also be used. For example, the mixing (XOR) of two clock signals can give a beat frequency with a common factor of the respective clock frequencies, and multiple such sources can be mixed to give a pulse train that is approximately random. Thus, there can be many options by which the sampled bits used to evaluate the chance-dependent test can be obtained, for example, using existing analog or digital signals or information available in the processing device.

[0029] In another example, the chance-dependent test may include determining whether a random or pseudorandom number has a predetermined value. Some systems may already have random or pseudorandom number generators for other purposes (such as encryption), so an existing source of randomness may be utilized to provide some bits that can be compared to some predetermined value to determine whether the chance-dependent test provides a first result or a different result.

[0030] The access frequency tracking structure that is updated when the chance dependent test is determined to have a first result for a given memory access request may be implemented in a number of different ways.

[0031] In some examples, the access frequency tracking indicator may include a tracking flag (e.g., a single-bit flag) that may have one of a first value or a second value. When the result of the chance-dependent test is a first result and the tracking flag corresponding to the given page has the first value, the access frequency tracking circuit may update the tracking flag corresponding to the given page to specify the second value. Thus, in this case, a one-bit flag may be sufficient to represent the access frequency tracking indicator, which may reduce the cost of implementing the access frequency tracking structure. Since the chance-dependent test provides a certain probability 1 / p of providing the first result, a tracking flag set to a second value may indicate, for example, that the probability that more than a certain number p of accesses have been made to the page is greater than 1 / 2.

[0032] In another example, the access frequency tracking indicator may include a multi-bit access frequency tracking counter. It should be noted that this is a different counter than the aforementioned test evaluation counter used to determine whether the chance-dependent test provided a first result. The access frequency tracking counter is an indicator in the access frequency tracking structure that is updated if the result of the chance-dependent test is a first result. Thus, if the result of the chance-dependent test is a first result, the access frequency tracking circuit may increment a multi-bit access frequency tracking counter corresponding to a given page. It will be appreciated that the counter may saturate at a given value, so once the counter reaches a saturation value, no further increments may be performed even if the page is accessed again when the chance-dependent test provides a first result. By providing a multi-bit counter as the access frequency tracking indicator, this may allow a wider range of access frequencies to be tracked. Nevertheless, because updating the counter depends on the chance-dependent test result, the size of the counter may be much smaller than in an implementation in which the counter is incremented every time the page is accessed.

[0033] The access frequency tracking structure can be implemented in different ways.

[0034] In some implementations, the access frequency tracking structure may provide access frequency tracking indicators at the granularity of an individual page, such that different access frequency tracking indicators are provided for different pages of the address space. It is not required that the access frequency tracking structure have a corresponding access frequency tracking indicator for each page. For example, currently unmapped pages of the address space need not have corresponding tracking indicators, depending on the implementation of the structure. By providing access frequency tracking indicators for each page, this may allow for more fine-grained tracking of access frequency and enable more informed decisions regarding page mapping.

[0035] However, in other examples, the access frequency tracking indicators may be defined at a coarser granularity than an individual page. For example, each access frequency tracking indicator may correspond to a block of multiple pages, and thus an access frequency tracking indicator corresponding to a given page may be an access frequency tracking indicator corresponding to the block of pages that includes the given page. Managing access frequency tracking indicators on a region or block basis, rather than at the granularity of individual pages, may reduce the size of the access frequency tracking structure, while still providing useful information regarding the relative frequency of access to different blocks / regions of memory.

[0036] In one example, the access frequency tracking structure may include an access frequency tracking hardware structure that includes a plurality of entries, each of which stores an access frequency tracking indicator for a corresponding page of the memory address space. Thus, the access frequency tracking indicators may be maintained in a hardware storage structure separate from the memory that may be looked up (similar to a cache) based on the address of the memory access to identify the corresponding access frequency tracking indicator.

[0037] A mechanism can be provided that allows software to read the access frequency tracking indicator corresponding to a given address from the access frequency tracking hardware structure.

[0038] Similarly, or instead of allowing direct software access to the access frequency tracking indicators in the access frequency tracking hardware structure, the access frequency tracking hardware structure can act as a cache for a memory-based backing data structure that provides access frequency tracking indicators corresponding to respective pages of an address space. The memory-based backing data structure can store tracking indicators for a larger number of pages than the access frequency tracking hardware structure. In response to a given memory access to a given page, the access frequency tracking circuit can perform a chance-dependent test and, if the result is a first result, update the access frequency tracking indicator in a corresponding entry of the access frequency tracking hardware structure for the given page. If an entry corresponding to the given page does not already exist, a new entry can be allocated in the access frequency tracking hardware structure. Upon a write-back event associated with a given access frequency tracking indicator, the value of that tracking indicator can be used to update the corresponding indicator in the backing data structure in memory. For example, the write-back event can be a counter overflow of a given access frequency tracking indicator, or a given access frequency tracking indicator reaching a given threshold. A writeback event may also be the eviction of an entry from the access frequency tracking hardware structure (e.g., due to capacity contention when a new entry is allocated to a page that did not previously have a corresponding entry in the access frequency tracking hardware structure). Thus, in implementations in which the access frequency tracking hardware structure acts as a cache for a backing data structure in memory, there may be no need for direct software access to the access frequency tracking hardware structure, as software may be able to access the underlying backing data structure in memory to read the access frequency tracking indicator associated with a particular page.

[0039] The access frequency tracking hardware structure may be a dedicated hardware storage structure specifically provided for storing the access frequency tracking indicators.

[0040] Alternatively, the entries of the access frequency tracking hardware structure may be used for purposes other than tracking access frequency. For example, the access frequency tracking hardware structure may be a translation lookaside buffer (TLB), and the multiple entries may be translation lookaside buffer entries for storing access frequency tracking information and address translation information associated with the corresponding pages, respectively. This may be an efficient approach in terms of power and circuit area, since the TLB may already be provided to speed up access translation and already provides a lookup mechanism for looking up information of the accessed page in memory, and thus by extending the TLB entry to also include the access frequency tracking indicator of a given page, this avoids the cost of providing a second set of cache lookup logic for looking up a dedicated structure.

[0041] In another example, the access frequency tracking structure (updated in response to the chance-dependent test that provides a first result for a particular memory access) may be a memory-based data structure stored in a memory system. In this case, there may be no specific hardware storage for the access frequency tracking indicators (other than the general-purpose memory system already provided for general-purpose data storage, and any data caches that cache general-purpose data from the memory system). This approach reduces the circuit area cost of implementing access frequency tracking. Since the chance-dependent test means that the access frequency tracking indicators for a given page are updated only on a portion of accesses, the performance cost of additional accesses to memory may be limited compared to alternative approaches that do not use statistical approaches that use chance-dependent tests. In an embodiment in which the access frequency tracking structure itself is a memory-based structure, this differs from the memory-based backing data structure described above, which is a backing structure for a hardware cache of the access frequency tracking indicators. Because when the memory-based structure serves as a backing data structure for a hardware cache, the memory-based backing data structure is updated in response to other flush events that trigger evictions from the cache or cache write-backs to the memory, rather than updating the memory-based backing data structure every time the chance-dependent test provides a first result. In contrast, if the access frequency tracking structure is itself a data structure stored in memory, the structure may be updated each time a chance dependent test provides a first result.

[0042] Thus, when a memory-based structure is used as the access frequency tracking structure, the access frequency tracking structure may be assigned a certain address in memory space, and updates to the access frequency tracking structure may be performed by the access frequency tracking circuitry by controlling the issuance of one or more memory access requests that request that an access frequency tracking indicator corresponding to a given page be incremented or updated in memory. All or a portion of the access frequency tracking structure may be cached in at least one cache of the memory system, and thus, it may not necessarily be necessary to update the location corresponding to the access frequency tracking structure in a backing store in main memory if a memory access request to update the access frequency tracking structure hits in a cache earlier in the memory hierarchy.

[0043] In one example, the memory-based access frequency tracking structure may be implemented as a linear data structure including a number of entries having addresses within a contiguous block of the memory address space, and the access frequency tracking circuitry may identify an entry of the linear data structure that provides an access frequency tracking indicator corresponding to a given page based on an offset determined based on the address of the given page. Such a linear data structure may be easier to analyze when software traverses the data structure to identify which pages have been accessed more frequently than other pages.

[0044] Alternatively, the memory-based access frequency tracking structure may be implemented as a tree structure, and accessing the access frequency tracking indicator for a given page may depend on traversing multiple levels of the tree structure to follow pointers from a root node of the tree through various branches of the tree to identify the access frequency tracking indicator at a leaf node of the tree. In some cases, the tree structure may be independent of any tree structure used to track page table entries for specifying address translation information for corresponding pages of the memory address space.

[0045] However, in many cases, a page table structure may already be available, and there may be a certain number of bits available in a page table entry that can be reused to provide an access frequency tracking indicator, so that in some cases, the memory-based access frequency tracking structure may include the page table structure itself, such that a page table entry corresponding to a given page includes the access frequency tracking indicator corresponding to that page. This avoids the need to define a separate structure, and allows existing mechanisms for traversing the page table structure to be reused for access frequency tracking. By supporting a probabilistic approach that relies on chance-dependent tests to update the access frequency tracking indicator, this allows a wider range of access frequencies to be tracked using page table entries, even when only a relatively small number of bits are available to specify the access frequency tracking indicator.

[0046] Whether the memory-based access frequency tracking structure is implemented as a linear data structure or a tree structure, indexing of the access frequency tracking structure may be performed based on the address corresponding to a given page. This differs from a sequential log of events, in which a number of records are sequentially allocated to the log data store as various events occur, in which the records are ordered by the time the respective event occurred, with each event record providing information about a particular event. By providing a structure that may be indexed based on the address of a given page, this makes it more efficient for software to identify the access frequency tracking indicators that correspond to a particular page.

[0047] The access frequency tracking circuitry can be implemented in different locations within a data processing system. In some cases, the access frequency tracking circuitry and the memory access circuitry may be provided within a processing element that also comprises processing circuitry for performing data processing in response to instructions defined according to an instruction set architecture (ISA). For example, the processing element may be a central processing unit (CPU) or a graphics processing unit (GPU), which may comprise the access frequency tracking circuitry.

[0048] In another example, the apparatus may include an input / output memory management unit (IOMMU) that may perform memory management operations on behalf of devices that have direct memory access to the memory system. The IOMMU may be referred to as a "system memory management unit" (SMMU). The IOMMU may perform operations that correspond to those performed by a memory management unit (MMU) in a processing element, but may do so on behalf of devices that have direct memory access to the memory system, which devices may not themselves have processing circuitry capable of executing ISA-defined program instructions. The IOMMU may include memory access circuitry and access frequency tracking circuitry as described above, such that the frequency of accesses of memory access requests made from such devices may also be tracked.

[0049] In some cases, a data processing system may include multiple sources of memory access requests (e.g., multiple processing elements, or at least one processing element and at least one IOMMU), each with an access frequency tracking circuit. In that case, the respective access frequency tracking circuits in the processing elements and the IOMMU may be configured to update the same access frequency tracking structure (or may update different local access frequency tracking structures that are backed up to a shared access frequency tracking data structure stored in memory). Alternatively, the different sources of memory accesses may each update their own dedicated access frequency tracking structure, such that the frequency of accesses made by the device is tracked separately from the frequency of accesses made by the processing elements.

[0050] It will be understood that some systems may not have an IOMMU at all, or that some systems, even if they have both a processing element and an IOMMU, may only implement the access frequency tracking circuitry in one of the processing element or the IOMMU, and thus it is not required that both include access frequency tracking circuitry.

[0051] FIG. 1 illustrates generally an example of a data processing system 2 having at least one processing element (PE) 4, e.g., a CPU (Central Processing Unit) or GPU (Graphics Processing Unit), having an instruction decoder 6 for decoding program instructions and processing circuitry 8 controlled to perform processing operations in response to instructions decoded by the instruction decoder 6. Registers 9 are provided for storing data that may be used as operands by instructions executed by the processing circuitry 8. Results of operations performed by the processing circuitry 8 may be written back to the registers 9. The PE 4 has at least one cache 10 that caches data from memory for faster access by the CPU, memory access circuitry 11 that issues memory access requests to access a memory system (including the cache(s) 10 and main memory 32) in response to memory access instructions executed by the processing circuitry 8, and a memory management unit (MMU) 12 that functions as an address translation circuit to translate virtual addresses specified by instructions executed by the PE 4 into physical addresses identifying locations in the memory system. The MMU 12 may have at least one translation lookaside buffer (TLB) 14 for storing translation entries that depend on page table data from a page table structure stored in the memory system. The page table structure defines address mappings between virtual addresses and physical addresses, and may also define memory access permissions that may define whether a particular software process running on the PE 4 is permitted to access a particular address. The MMU 12 may support two-stage address translation, in which the mapping of a virtual address to a physical address depends on both stage 1 address translation data that maps a virtual address (VA) to an intermediate physical address (IPA) and stage 2 translation data that maps an IPA to a physical address (PA). The stage 1 address translation data may be set by the operating system or the virtual machine. The stage 2 translation data may be set by the hypervisor.

[0052] The PE 4 is an example of a requesting device capable of executing program instructions. FIG. 1 shows an example of a system with two such PEs 4, although obviously the number of PEs may vary. Some systems may have only a single PE, while other systems may have more than two PEs. For simplicity, the internal components of the second PE 4 are not shown in FIG. 1, but it will be understood that the second PE 4 may also include an instruction decoder 6, processing circuitry 8, registers 9, cache(s) 10, memory access circuitry 11, and MMU 12. In some cases, the PEs 4 may be symmetrical and have the same design. It is also possible to include heterogeneous or asymmetric PEs 4 that have different components or where components such as the processing circuitry 8, cache(s) 10, etc. may have different micro-architectural implementations.

[0053] In addition to PE4, the system may also include requesting devices 20 that may not have an internal MMU, and thus, to access memory and provide address translation functions, such devices may communicate with the rest of the system through an input / output memory management unit (IOMMU), also known as a system memory management unit (SMMU) 22. The IOMMU 22 comprises address translation circuitry that controls address translation and memory permissions based on translation data defined in a page table structure in memory. The IOMMU 22 may have one or more TLBs 24 with similar functionality to the TLB 14 in the MMU 12 of the CPU 4. For example, the device 20 may include a display controller for controlling the display of image frames on a display, a network controller for controlling the input or output of data over a network, hardware accelerators for performing certain specialized processing functions in a more efficient manner than can be achieved using software running on a general purpose processor such as the CPU 4, and the like. The device 20 has direct memory access to the memory 32, meaning that it can issue access requests that directly request access to stored data without having to be explicitly programmed to do so by the PE 4.

[0054] The requesting devices 4, 20 communicate with each other via an interconnect 30, which is responsible for routing transactions between the requesting devices and memory 32, and between the respective requesting devices. The interconnect 30 may also be responsible for managing coherency between data cached in the system's respective caches 10. It will be understood that Figure 1 is a simplified diagram and that the system 2 may have many other components that are not shown in Figure 1 for the sake of brevity.

[0055] As shown in FIG. 1, processing element 4 and / or IOMMU 22 may include access frequency tracking circuitry 40 for monitoring memory access requests made by memory access circuitry 11 and updating an access frequency tracking structure that provides an indication of the relative frequency of accesses to each page of the memory address space.

[0056] One approach for tracking page access frequency is for the PE 4 or IOMMU 22 to maintain an accessed / dirty flag for each page and set the flag in the translation descriptor (page table entry) when the page is accessed or modified. The accessed flag can be used by the operating system to classify pages as "cold" or "hot" pages. For example, when memory is tight and a victim page needs to be selected for swap-out, the operating system (OS) may prefer to target a page that will not be used again soon, and can predict whether the page will be used again based on whether it has been used recently.

[0057] This area is of particular interest due to the emerging heterogeneity in memory systems: some parts of memory may be faster (higher bandwidth or lower latency) than others due to memory technology or physical proximity to the processing elements or accessing agents. NUMA (non-uniform memory access) migration or multi-stage page migration is being actively researched, for example by monitoring access patterns so that frequently accessed data can be copied to pages closer to the accessing agents. Detecting that a page is frequently accessed is part of this (copying / moving data is a separate issue).

[0058] Two possible approaches to detect frequently accessed pages are page protection and per-page access flags. As a general procedure, a periodic software process samples whether pages have been accessed and consolidates this information into a long-term data structure (stored in memory and maintained by software) that keeps a count over several sampling periods. This data then gives a view of which pages have been accessed more frequently than other pages (e.g., a histogram / per-page counter maintained by software shows the relative number of samples between pages). This software procedure can be used with page access flags or page protection as follows:

[0059] Option 1 - The access flag is cleared for all pages at the beginning of the sampling period. After a delay (either a periodic time or some interesting OS event), the page table is traversed and the access flag for each page is observed. If the access flag is set, a software procedure updates a long-term data structure (e.g., increments a counter corresponding to the page address) and clears the access flag. This process is repeated.

[0060] Option 2 - Or the page's permissions are modified to make the page inaccessible at the start of the sampling period. If the page is accessed, a page fault occurs. The page fault handler updates long-term data structures to make the page accessible for some period of time. (This event can be used to trigger different pages to be protected / sampled.)

[0061] Option 1 has the disadvantage that it is unspecified and requires the software to traverse the entire page table in case there is no possibility of finding that the page is marked as accessed; this task can be performed on a different CPU than the application, but it can take a very long time to traverse a large page table, wasting background CPU time.

[0062] Option 2 has the drawback of being high overhead for the application if the application is frequently interrupted by page faults, or inaccurate if the application is only rarely interrupted; this method wastes CPU time "inline".

[0063] Thus, not only is capturing the access state of a page costly (depending on the mechanism), but the access state is a poor proxy for the ongoing page access frequency unless sampled at an infeasibly high rate. Without maintaining per-page counters, it becomes difficult to distinguish pages that are accessed "occasionally" from very hot pages, which is also space-costly. As an example, a page accessed 100-1000 times / sec may be considered "cold" compared to a page accessed 1 million times / sec.

[0064] In the example described below, an access frequency tracking structure is provided (e.g., in memory or in a hardware storage structure) with an entry corresponding to each page in the address space. The tracking structure can be approximated to have a large per-page counter that is updated with every load or store, but without the astronomical cost of that approach. It is observed that a threshold may be adopted for the determination of "a page is hot" such that a page is considered hot if it is accessed more frequently than the threshold (but after that point the relative value is less important). In the technique described in this application, the access frequency tracking circuit 40 gives the execution of a load or store instruction a configurable probability of updating a bit or access frequency tracking counter in the tracking structure corresponding to the accessed address of that load / store. The probability is configured in a register and can be adjusted depending on the page migration algorithm being used. In one specific example, this can be implemented by incrementing a test evaluation counter upon execution of each load / store instruction. Once the test evaluation counter reaches a configured value, execution of the load / store instruction causes both an update of the tracking structure and a reset of the test evaluation counter value. Other examples are also described for implementing chance-dependent tests with configurable probabilities. This technique can also be applied to IO (input / output) accesses, whereby the IOMMU 22 updates the secondary data structure in response to read / write transactions from the client device 20.

[0065] When this feature is implemented in the hardware circuitry of the device, it allows software profiling the address space of "hot" pages to set appropriate probability registers (to define a probability 1 / P) for what it considers to be "hot" pages. In one particular example, the information in the secondary data structure can mean: 1-The corresponding page is likely to have been accessed more than P / 2 times 0 - The corresponding page is unlikely to have been accessed more than P / 2 times

[0066] Variations on this idea include the following: Instead of a secondary data structure, probabilistic updates can be made to fields in the corresponding PTE. - Using different probability values ​​for loads instead of stores. - Updating different secondary structures based on load vs. store. -has different probability values ​​for different areas of the address space. -Instead of one bit per page in the data structures (meaning "page is hot"), update a small (e.g. 2-3 bits) saturating counter. This allows us to distinguish between "page is hot" and "page is very hot" and allows the migration algorithm to prioritize between them. This also allows us to filter out some of the noise of false positives.

[0067] False positives will occur (e.g., a load accessing an address that has not been accessed before will trigger an update and correctly "roll the dice") and the software algorithm may filter out updates for a period of time.

[0068] Variations that may provide improved correlation between the actual frequency of access and the recorded tracking information (reducing the chance of false positives) may be the following. -Extend the TLB entry with a counter that is incremented for any TLB lookup that hits that entry if the dice roll probability test is passed for that lookup. On overflow, the structural bits corresponding to the address of the TLB entry are updated.

[0069] (This could be implemented similarly to an LRU counter in a cache.)

[0070] FIG. 2 illustrates generally one example of an access frequency tracking circuit 40 that may be included in either a processing element 4 or an IOMMU 22. The access frequency tracking circuit 40 has a chance dependent test evaluation circuit 42 for determining whether a chance dependent test performed for a given memory access request has a first result or has another result other than the first result. Several different examples of chance dependent tests are described below with respect to FIGS. 4-8. The access frequency tracking circuit 40 has at least one software configurable probability register 44 that defines one or more configurable values ​​that may control the probability that the chance dependent test evaluation circuit will provide the first result. For example, the probability register may store a value that configures the number of bits in a counter or other input value 54 that is used to evaluate whether the chance dependent test provides the first result.

[0071] As shown in FIG. 2, in some examples, the software configurable probability register 44 may include two or more separate probability configuration values ​​46 corresponding to different subsets of memory access requests, such that the probability of a chance-dependent test providing a first result may be set independently for different subsets of memory access requests. For example, the different subsets may each include loads and stores, or may include requests issued from different operating states or execution modes of the processing element 4, or may include requests targeting different regions of the memory address space, or may correspond to different combinations of two or more of these properties. The ability to update the probability control value 46 in the software configurable probability register 44 may be restricted to instructions executed by processing elements with a certain level of privilege, such as instructions executed at or above a certain exception level. Instructions executed at a lower exception level, or instructions that are not privileged, may not be permitted to change the value in the software configurable probability register 44. In some cases, the software configurable probability register may be implemented as a control register within an instruction set architecture supported by the instruction decoder 6 and processing circuitry 8, while in other examples the software configurable probability register 44 may be a memory mapped register accessed by the processing circuitry 8 executing load / store instructions that specify a target memory address mapped to the software configurable probability register 44.

[0072] The access frequency tracking circuit 40 also has an access frequency tracking structure update circuit 48 for triggering an update to the access frequency tracking structure 50 when the contingency-dependent test evaluation circuit 42 determines that the test provides a first result. If the contingency-dependent test provides a result other than the first result, no update to the access frequency tracking structure 50 is required. In some cases, the access frequency tracking structure may be stored in a dedicated hardware data structure, such as an access frequency tracking hardware structure, or a set of registers dedicated to storing the access frequency tracking structure. For example, the access frequency tracking hardware structure may be the TLB 14.

[0073] However, in other examples, the access frequency tracking structure that is updated when the chance-dependent test provides a first result may be implemented as a data structure in memory 32, some portions of which may be cached in general-purpose data cache 10. The memory-based structure may be updated by access frequency tracking structure update circuitry 48 issuing one or more memory access requests that specify as a target address an address corresponding to a location in access frequency tracking structure 50. This may reduce circuit area costs within the PE 4 or IOMMU 22, as no additional storage logic is required within the PE 4 or IOMMU 22 to hold the access frequency tracking indicators.

[0074] The access frequency tracking structure may include several access frequency tracking indicators 52, each corresponding to a block of one or more pages of the address space and providing an indication of the relative frequency of access to that block of pages. In some cases, the access frequency tracking indicators 52 may be provided per page, but this is not required and some pages need not have corresponding indicators in their tracking structure (e.g., it may not be necessary to include indicators corresponding to currently unmapped pages for which no virtual to physical address mapping is defined). Also, in some examples, each access frequency tracking indicator may correspond to a single page such that each page has a different tracking indicator, but in other cases, the tracking may be less granular and a single indicator 52 may be shared between blocks of adjacent pages. The associated indicator 52 corresponding to a particular page may be identified based on the address of that page, e.g., the address may be used to derive an offset relative to a base address of the structure 50, or various sets of index bits of the page address may be used to control traversal through the tree structure. If address translation is used, it may be the virtual address of the page that is used to index into the data structure 50, such that the corresponding physical address does not need to be obtained and software may parse the structure 50 based on the virtual address.

[0075] Although the access frequency tracking structure update circuitry 48 may comprise hardware circuit logic that automatically initiates any necessary updates to the access frequency tracking structure without the need for explicit software store instructions to control the updates to be performed, the access frequency tracking structure 50 may also be accessible by software issuing a load instruction specifying an address within the data structure, which may be useful if the operating system or other software wishes to later analyze the access frequency tracking structure 50 to identify pages that may have been frequently accessed.

[0076] 3 is a flow diagram illustrating a method for monitoring the relative frequency of accesses to respective pages of an address space. In step S100, the access frequency tracking circuit 40 detects that the memory access circuit 11 has received or is processing a memory access request requesting access to a given page. In response to the memory access request being received or processed, in step S102, the chance-dependent test evaluation circuit 42 determines the result of a chance-dependent test evaluated for the memory access request. A chance-dependent test may be any test that produces an uncertain result that may depend at least in part on chance, such that the result of the chance-dependent test cannot be derived deterministically based solely on the characteristics of the memory access request or on any control parameters used to govern whether the memory access request is granted or on any control parameters that control the location in the memory system that is accessed in response to the memory access request. For example, the chance-dependent test may rely on random or pseudo-random numbers, randomly sampled bits from a pulse train, or other internal states sampled within the system that are not correlated with the memory access request itself, or on a counter provided to count the number of memory access requests that may have a certain 1 / N probability of having a particular value when the memory access request is received. Regardless of how the chance-dependent test is performed, the test may be such that even if the exact same memory access request with the same characteristics is issued many times, the chance-dependent test may have different results for those repeated instances of the same memory access request. This means that the access frequency tracking structure 50 is not updated in response to every occurrence of a memory access to a given page, but rather sometimes the chance-dependent test may succeed, and therefore the access frequency tracking structure is updated, and sometimes the chance-dependent test may fail, and no update is performed, and the outcome of each individual memory access request may have a configurable probability that is arbitrary in nature, but controlled by the software configurable probability register 44.

[0077] Thus, in step S104, the chance-dependent test evaluation circuit 42 or the access frequency tracking structure update circuit 48 determines whether the result of the chance-dependent test is the first result, and if so, in step S106, the access frequency tracking structure update circuit 48 updates the access frequency tracking indicator 52 corresponding to the given page accessed by the memory access request in the access frequency tracking structure 50. If the result of the chance-dependent test was not the first result, in step S108, this update of the access frequency tracking indicator 52 corresponding to the given page is omitted.

[0078] Thus, by controlling whether the access frequency tracking structure 50 is updated for a given memory access request based on a chance-dependent test 42 that has a probability of providing a first result less than one, such that the access frequency tracking structure 50 is not updated every time the corresponding page is accessed, this means that even if the purpose of the access frequency tracking structure 50 is to count memory accesses over a relatively large range, the size of any counter required for the access frequency tracking indicator 52 does not need to scale with the same range as the number of accesses that are intended to be tracked, because the lower probability of increment means that a smaller counter can be employed while still measuring a large absolute range, thus saving many state bits and therefore reducing the area, power and performance cost of implementing the access frequency tracking structure.

[0079] As shown in FIG. 2, the chance-dependent test may depend on certain input information 54 provided to the chance-dependent test evaluation circuit. This information may have a range of forms, depending on the nature of the chance-dependent test implemented. In general, the chance-dependent test may use input information that may vary substantially randomly in a manner that is not particularly correlated with the nature of the memory access request itself. From a software perspective, whether a particular memory access request passes the chance-dependent test may be viewed as a dice roll event, such that the outcome for a particular memory access request is uncertain, but generally, the more frequently a given page is accessed, the more dice rolls it will get, and therefore the more likely it is that it will have its access frequency tracking indicator 52 set to distinguish it from other, less frequently accessed pages. Nevertheless, there may be occasional false positives where the first accessed page happens to hit the dice roll and the chance-dependent test provides a first result even though it has never been accessed before, while the more frequently accessed pages continue to lose dice rolls and their access frequency tracking indicators are never updated. Nonetheless, on average, more frequently accessed pages are more likely to be identified using this mechanism, and therefore this can still be beneficial for performance by allowing some placement decisions for placing certain data within the memory system to be optimized in favor of more frequently accessed pages.

[0080] 4-8 show several different examples for implementing the coincidence-dependent test. As shown in FIG. 4, in one example, a global counter 60 may be maintained by the access frequency tracking circuit 40, the global counter being shared among all memory access requests. As a memory access request is processed, the global counter 60 is incremented or otherwise advanced to the next state. One implementation of the counter may be a binary value that is incremented by adding or subtracting one in response to each memory access request, but it will be appreciated that in other approaches the counter may be represented as a shift register that transitions between a certain sequence of states such that it does not necessarily need to be incremented or decremented (e.g., the shift register may be shifted one bit location to the right or left). The current value of the global counter 60 is compared to a predetermined value or threshold by a comparator 62, and in response to the comparison, a signal is issued to the access frequency tracking structure update circuit 48 to control whether a corresponding access frequency tracking indicator 52 is set or updated for the corresponding page accessed by the current memory access request. Thus, in this approach, whether a chance-dependent test results in a first result is based on whether a global counter reaches a threshold or matches a predetermined value, which may be effectively random for each individual memory access request, because which particular memory access request happens to be processed when the counter passes or reaches its threshold may be effectively arbitrary and may depend on the timing of the processing of that memory access request relative to other memory access requests, which may depend on microarchitectural implementation details such as whether out-of-order execution is supported and the size of any operation queues that may reorder operations, as well as events that may vary from execution run to execution run, such as the timing of a particular interrupt that is triggered, and therefore the counter value may be viewed as uncorrelated to the characteristics of a given memory access request, such that whether the counter meets the conditions necessary to determine a first result may be viewed as a matter of chance.After counter 60 is determined to have reached a state in which the predetermined condition is satisfied, it is reset to its initial state and resumes another period of counting memory access requests.

[0081] FIG. 5 illustrates a similar approach to FIG. 4, except that the global counter 60 is replaced by several local counters 64, each corresponding to a particular subset of memory access requests. When a memory access request in the first subset is encountered, the state of a first local counter 64-1 is incremented or advanced, and similarly, when a memory access request in the second subset is encountered, the state of a second local counter 64-2 is incremented or advanced. The local counter used to evaluate the contingency-dependent test for the current memory access request is selected based on which subset the memory access request belongs to, and a comparator 62 compares the state of the selected counter 64 to a predetermined value or threshold value similar to FIG. 4. When a counter reaches the predetermined value or threshold, the access frequency tracking structure update circuit 48 triggers an update of the associated tracking indicator 52 in the access frequency tracking structure 50. Also, the selected associated counter 64 may be reset to its initial state to resume counting for another period. Again, there may be different ways of classifying memory access requests into different subsets; for example, the subsets may be distinguished by the type of memory access request (e.g., load vs. store), the particular region of address space targeted by the memory access request, and / or the execution mode or state or privilege level associated with the memory access request (or any combination of these factors).

[0082] 4 and 5, the software configurable probability register 44 may store a value that controls the number of transitions required to advance the counter 60, 64 between an initial state (where the counter is reset immediately after an update event occurs) and a state where the next update event is detected (when the counter is deemed to meet a predetermined threshold or condition). For example, the value in the software configurable probability register 44 may cause the chance-dependent test evaluation circuit 42 to adjust the value to which the counter 60, 64 is reset immediately after an update event occurs, or to adjust the value or threshold to which the counter is compared to provide similar results.

[0083] FIG. 6 shows another example of implementing a contingency-dependent test. In this example, the input 54 for the contingency-dependent test may include a serial pulse train or a number of bits sampled from within an item of internal state 68 sampled at the time of the relevant memory access request for which the contingency-dependent test is being evaluated. The serial pulse train may be a sequence of bits derived from values ​​sampled from a particular signal or group of signals at respective instances over time. For example, the value of a particular signal may be digitally sampled over several clock cycles, and if the sampled values ​​provide a certain pattern of 1s and 0s that match a predefined value, the update condition may be considered satisfied (a first outcome occurs in the contingency-dependent test), while other patterns of 1s and 0s may correspond to the first outcome not occurring. Alternatively, an item of internal state having other functional purposes may be used to provide the internal state 68, such as an event counter for counting events such as the passage of clock cycles, the number of cache misses, address faults or other errors in the cache 10, and the like, from which a certain number of bits 54 may be extracted and compared to a predefined value to determine whether the first outcome occurs. The selection of which particular item of internal state is sampled or which particular analog or digital signal is sampled as a serial pulse train may depend on the particular processor implementation. In some cases, multiple items of internal state may be combined (e.g., based on an exclusive-or (XOR) operation) to provide a pulse train or data value 68 that may have sampled bits 54 with less bias toward a particular set of values. Thus, in the example of Figure 6, it is not necessary to provide dedicated counters 60, 64 for tracking memory accesses, but instead some items of internal state or existing analog or digital signals within the processing system 2 may be used or combined with others to provide a contingency-dependent test.

[0084] 7 shows another example in which a random or pseudorandom number 70 is obtained and compared to a predetermined value, and depending on whether the random or pseudorandom number matches the predetermined value, it is determined whether to update the access frequency tracking structure 50. This can take advantage of the fact that the processing system 2 may already have a random or pseudorandom number generator for other purposes, such as encryption, and thus can use an already available source of randomness to provide a random or pseudorandom number having a certain number of bits, such that an N-bit random or pseudorandom number can provide a 1 / N chance of having a certain value representing a first result, and when it does not match the predetermined value, provide a result other than the first result. The random or pseudorandom number can be regenerated for each memory access request for which the chance-dependent test is evaluated.

[0085] In both the examples of Figures 6 and 7, the software configurable probability register 44 can control the number of bits in a sample that are compared between predetermined values ​​in Figure 6, or the number of bits in a random / pseudo-random number 70 that are compared to predetermined values ​​in Figure 7, to adjust the probability that the access frequency tracking indicator 52 of the currently accessed page will be updated.

[0086] Figure 8 illustrates another approach for implementing coincidence-dependent tests, which, similar to Figures 4 and 5, uses a local counter 64 that serves as a test evaluation counter for determining whether the coincidence-dependent test provides a first result for a given memory access request. However, in the example of Figure 8, TLB 14 has each TLB entry 80 extended such that, in addition to a valid bit 84 indicating TLB entry validity and any page table data 82 cached in the associated TLB entry associated with a given page of address space, the TLB entry also stores a test evaluation counter 64 that serves as a local counter corresponding to memory access requests targeted to that particular page. Thus, in this approach, each page for which page table data 82 is cached in a valid TLB entry 80 has a corresponding local counter 64 maintained for that page by MMU 12, so that when a given memory access request is issued, if the access request hits in TLB 14, its page table data 82 is read and used to control the evaluation of address translation or access permissions, and counter 64 is read and compared to a predetermined value or threshold by comparator 62 to determine whether to update access frequency tracking structure 50. Also, if there is a TLB hit, test evaluation counter 64 in the corresponding TLB entry 80 is updated (e.g., incremented) to advance to the next state in its transition sequence. By maintaining different test evaluation counters 64 for different pages within the TLB 14, this can increase the likelihood that the access frequency tracking indicators 52 in the access frequency tracking structure 50 will be more closely correlated with the actual relative frequency of accesses to the corresponding pages, reducing the probability that less frequently accessed pages will be erroneously identified as more frequently accessed and less frequently accessed pages due to the effect of chance on the respective chance-dependent tests that are performed when those pages are accessed.

[0087] 9-11 show different ways of implementing a memory-based access frequency tracking structure 50. These techniques can also be used with memory-based backing structures where access frequency tracking indicators from a hardware caching structure such as a TLB are written back or flushed.

[0088] In the example of FIG. 9, the structure is implemented as an access frequency bitmap providing a linear data structure stored as a block of memory addresses starting from a base address 90, with each access frequency tracking indicator 52 being a single bit flag having a first value (0 in this example) where all flags are reset at the beginning of the period for tracking access frequency, and set to a second value (1 in this example) when a coincidence dependent test has a first result for a particular memory access request targeted to the associated page corresponding to that tracking indicator 52. Thus, an indicator 52 having a second value represents a page that has been accessed at least once when the coincidence dependent test has a first result. A flag having a second value can be seen as indicating that the probability is greater than half of a page that has been accessed at least P times, where 1 / P is the probability that the coincidence dependent test has a first result. Indexing into the access frequency bitmap 50 can be performed based on the base address 90 and an offset 92 that can be derived from the address of the corresponding page. Because this is a linear data structure, all access frequency tracking indicators 52 may be stored in a contiguous block of virtual address space (which may or may not be contiguous in physical address space depending on the address mapping used).

[0089] FIG. 10 shows a second example where the access frequency tracking structure is also a linear data structure stored at addresses starting from a base address and indexed based on an offset 92 derived from the (virtual) page address of the page corresponding to a particular tracking indicator 52. However, in this example, each tracking indicator is a multi-bit access frequency tracking counter that counts the number of times the corresponding page was accessed when a coincidence-dependent test provided a first result. Note that these counters differ from the test evaluation counters 60, 64 described with respect to FIGS. 4, 5 and 8 in that these counters are for evaluating whether a coincidence-dependent test is satisfied for an individual memory access request, but do not provide an indication of the relative frequency of access of a particular page. By using the coincidence-dependent update method described above, the counters 52 can be made much smaller than would be required if the access frequency tracking structure was updated for every memory access request, while still simulating counts over a larger range. In both the examples of FIGS. 9 and 10, some implementations can provide an access frequency tracking indicator 52 for each page in at least a portion of the address space, so that the granularity of setting the tracking indicators is per page. Another approach may share the tracking indicator 52 between blocks of two or more adjacent pages.

[0090] FIG. 11 shows another approach for maintaining a memory-based access frequency tracking structure or a backing structure in memory to back up the access frequency tracking indicators from a hardware caching structure, where a tree structure is used instead of the linear data structure shown in FIG. 9 and FIG. 10. Although it is possible to maintain the tree structure separately from the page tables used by MMU 12 or IOMMU 22 to provide the address translation data, in practice the address translation data may be defined in a set of page tables managed as a tree structure, and may have some spare bits in each page table entry that may be used to provide the access frequency tracking indicators 52 (or back up the access frequency tracking indicators 52 from a caching structure provided in hardware), and thus in some cases the tree structure may be the page table structure itself. As shown in the bottom right of FIG. 11, the tree structure may include several tree nodes 100, where the nodes at higher levels of the tree contain several pointers to respective nodes at lower levels of the tree, and some of the bits from the address used to query the tree structure are used to select a subsequent alternative pointer to obtain the location of the node at the next level of the tree, and different parts of the query address are used to select between these pointers at different levels of the tree. Eventually, a final leaf entry in the tree is reached (e.g., level 3 in this example, although a tree node at an earlier level in the tree could be encoded to indicate that it has completed the tree traversal and that it itself provides the relevant information sort for the query address). The leaf entry provides the data sought for the query address, e.g., a page table entry for a page table and / or an access frequency tracking indicator 52 for an access frequency tracking data structure 50.

[0091] For example, to obtain address translation data corresponding to a particular virtual page address, the MMU 12 or IOMMU 22 may use a level 0 (L0) base address 120 and an offset 122 derived from the L0 index bits 124 of the virtual page address to select an entry in a level 0 page table 126 that provides a pointer 128 to a base address 130 of a level 1 (L1) page table 132 that corresponds to the virtual page address. Different entries in the level 0 page table 126 may provide different pointers that allow the tree to branch to different level 1 nodes at the next level of the tree after level 0. Similarly, at each subsequent level of the tree, further portions of the index bits 134, 136, 138 are used to provide offsets to the base addresses 130, 140, 142 of the level 1, 2, and 3 page tables, respectively. At the branch nodes of the tree (nodes other than the leaf nodes that provide the actual page table entries themselves), the selected entry provides a pointer to the next level. Eventually, a leaf entry is found (at level 3, or at an earlier level if the tree traversal terminates earlier) that provides the page table entry 150 of interest (e.g., encoding the address translation mapping and / or access permissions for the corresponding page). This page table entry can be extended to provide an access frequency tracking indicator 52, which can be a single-bit flag or a multi-bit counter as in the examples of Figures 9 and 10. Thus, in this example, the access frequency tracking circuit 40 can reuse the mechanism provided in the MMU 12 or SMMU 22 to traverse the page table to determine the address for which the associated access frequency tracking indicator 52 should be updated when the coincidence-dependent test for a given memory access provides a first result. Thus, multiple memory accesses may be required to find the access frequency tracking indicator 52 to be updated.In other examples, a tree structure may be used that may be independent of the page table, in which case a separate tree traversal mechanism may be implemented within the access frequency tracking circuit 40. It will be appreciated that the number of tree levels shown in FIG. 11 is just one example and need not be four levels.

[0092] 12 shows another example in which an access frequency tracking hardware structure 158 is provided in a PE 4 or IOMMU 22 that includes a number of storage entries 159 that can be looked up based on the address of a given page for a given memory access to obtain the access frequency tracking indicator 52 for that given page. The access frequency tracking hardware structure 158 can be a dedicated hardware structure for access frequency tracking, but in this example the access frequency caching hardware structure 158 is a TLB 14, and thus each entry 159 also points to the page table data 82 for the corresponding page. Again, each entry can have a valid bit 84 that indicates whether the entry is valid.

[0093] The access frequency tracking indicator 52 may be an access frequency tracking counter that is incremented upon access to a corresponding page for which the chance-dependent test yielded a first result.

[0094] Thus, in this example, when access to a target page is requested, if the address hits in hardware structure 158 and the chance dependency test gives a first result, the access frequency tracking indicator 52 in the corresponding entry in tracking structure 158 is incremented, and if the chance dependency test gives a different result, this increment is omitted.

[0095] If the address is not in the tracking structure, a new entry may be allocated with the address of the target page and the access frequency tracking indicator 52 set to an initial value (e.g., 0 or 1). If the tracking structure 158 is the TLB itself 14, a new entry may be allocated on a TLB miss whether or not the coincidentally dependent test gives a first result (because a new entry may be needed anyway to cache the page table data 82 of the target page in the TLB whether or not the counter is also incremented, in which case the initial value of the newly allocated entry may be 0 if the coincidentally dependent test did not give a first result and 1 if the coincidentally dependent test did give a first result). If the tracking structure 158 is a dedicated structure other than the TLB 14, a new entry may be allocated if the coincidentally dependent test gives a first result for a miss in the structure, but may not require allocation if the coincidentally dependent test gives a different result.

[0096] In the example of Figure 12, the coincidence-dependent testing is implemented using a global test evaluation counter 60 as in the example of Figure 4, but the example of Figure 12 may also use any of the other techniques for implementing coincidence-dependent testing, such as those shown in Figures 5-8. If the example of Figure 8 is used for coincidence-dependent testing, each entry 159 of the tracking structure may include a local test evaluation counter 64 for the corresponding page in addition to the access frequency tracking indicator 52, so that both types of counters 64, 52 may be provided, but in practice the option shown in Figures 4-7 may be cheaper in terms of circuit area to avoid the need to provide two separate counters per TLB entry 80.

[0097] In some examples, there may be no underlying memory-based structure backing up the access frequency tracking indicators 52 from the hardware structure 158 (14), but there may be a mechanism for software to read the value of the access frequency tracking indicators 52 for a given page from the hardware structure 158, and the software may control the writing of such tracking indicators 52 to memory locations selected by the software. In this case, there may be no hardware management means backing up the access frequency tracking indicators 52 from the tracking structure 14. In this approach, if an entry 159 of the structure 158 is invalidated or evicted (e.g., due to capacity contention), the corresponding access frequency tracking indicator 52 may simply be discarded. For example, if the TLB 14 serves as the access frequency tracking hardware structure 158, it may be assumed that a page accessed infrequently enough that does not have a resident TLB entry may not be of interest for tracking access frequency. For software, knowing access frequency tracking information about more frequently accessed pages that have been allocated TLB entries may be sufficient. Thus, the additional cost of hardware management writeback of the access frequency tracking indicators to memory may not be justified.

[0098] Optionally, however, in some implementations, hardware circuitry within the access frequency tracking circuitry 40 may manage the write-back of the access frequency tracking indicators to the in-memory backing data structure 180. The access frequency tracking circuitry 40 may have a register that software may configure with the base address of the backing data structure 180. In this case, as shown by the dotted lines in FIG. 12, when a write-back event occurs for an entry 159 of a given page from the tracking hardware structure 158, the access frequency tracking circuitry 40 may cause one or more memory access requests to be issued to update the corresponding access frequency tracking indicators 182 of the given page in the memory-based backing data structure 180. A writeback event may be, for example, the eviction or invalidation of an entry 159 for a given page; an overflow of the access frequency tracking indicators 52 at that entry 159; the occurrence of a periodic flush event to trigger a writeback of all or a subset of the access frequency tracking indicators 52 in the hardware structure 158, and / or the execution of a "flush" instruction to request that the access frequency tracking indicators 52 be written back to memory for all entries 159 of the hardware structure 158 or only for those entries 159 that satisfy a filter condition specified by the instruction (e.g., the entry 159 corresponds to a specified address or address range).

[0099] Writeback can be performed in different ways. In some examples, access frequency tracking indicator 182 can be a single-bit flag such that upon a writeback event, if the previous value of flag 182 was 0, it is updated to 1, but if flag 182 was already 1 before the writeback event, it remains 1. In this case, memory-based structure 182 indicates whether an overflow of access frequency tracking indicator 52 has occurred for the respective page to indicate that the number of accesses to the corresponding page is likely to be relatively large (e.g., more likely than P / 2 if the probability of the chance-dependent test giving the first result is 1 / P).

[0100] Alternatively, the tracking indicator 182 in the memory-based structure 180 may be a multi-bit counter. In this case, upon a writeback of a given tracking indicator 52, the value of that counter may be written to the corresponding indicator 182 in memory. Alternatively, the writeback may include adding a value derived from the writeback counter 52 to a previous value of the indicator 182 in memory to generate an updated value that is written to the location of the indicator 182. This may be useful to allow multiple sources of memory accesses to share the same backing structure 180, such that the indicator 182 tracks the total number of accesses to the page initiated by any of those sources. The increment added to the indicator value in the memory 182 may not be the exact value of the counter. For example, the increment may be a scaled version of the value of the counter 52, with the scaling factor being variable depending on the probability 1 / P of the chance-dependent test that provided the first result, e.g., the scaling factor may be P. This may allow multiple sources using chance-dependent tests with different values ​​of probability to maintain a shared indicator 182 in memory that tracks the estimated number of accesses. Also, as described below with respect to FIG. 13, in an implementation using a variation in probability 1 / P with the number of accesses, the value of the estimated number of accesses may be scaled non-linearly with the value of the access frequency tracking counter 52; thus, in this case, each possible value of the access frequency tracking counter 52 may be associated with a corresponding increment value representing the estimated number of accesses represented by that value of the counter 52, such that upon counter write-back, an appropriate increment value may be selected based on the current value of the counter 52 for adding to the corresponding indicator 182 in memory.

[0101] As shown in Figure 13, in some implementations, the probability of a first outcome occurring in a chance-dependent test may be reduced from time to time as the frequency of access to a given page increases. The reduction in probability may be accomplished, for example, by increasing a reset value for resetting a test evaluation counter, increasing a threshold value that is compared against the test evaluation counter to determine if the first outcome occurred, or increasing the number of bits in the test evaluation counter, the internal state, the pulse train, or the sampled portion of the random / pseudorandom number that is used to evaluate if the first outcome occurred.

[0102] 12, in which TLB 14 or other access frequency tracking hardware structure 158 provides an access frequency tracking indicator 52 for each page, the probability of a chance-dependent test providing a first result for a given page may depend on the access frequency tracking indicator 52 for the given page. For example, as shown in FIG 13, when the current value of the access frequency tracking counter 52 for a given page x reaches a first threshold 160, the probability may be reduced from a first value A to a second value B, and then, if the access frequency tracking counter for that page continues to increment and reaches a second threshold 162, the probability may be reduced again from the second value B to a third value C.

[0103] For example, in an embodiment in which the test evaluation counter 60 is compared to an access frequency tracking indicator to evaluate chance-dependent tests, one way to implement a gradual reduction in the probability of the test giving a first result is to vary the number of bits of the counter 60 that are compared to a predetermined value (such as 0), with the number of counter bits used for the comparison increasing as the value of the access frequency tracking indicator 52 increases. For example, in a specific embodiment, a 16-bit test evaluation counter 60 is provided and the number of bits used for the comparison can be varied with the value of the access frequency tracking indicator 52 to give different probabilities as follows:

[0104] [Table 1]

[0105] It will be appreciated that this is just one example and other implementations may select different thresholds that reduce the probability.

[0106] In general, by decreasing the probability, a greater number of accesses to a given page is required on average to cause further increments of the counter 52, so that the counter value can scale nonlinearly with the actual number of accesses to the corresponding page. This can be useful to allow a counter with a relatively small number of bits to track the frequency of accesses over several orders of magnitude, so that the threshold number of accesses at which the counter is more likely to be incremented does not need to be uniformly distributed. For example, by setting the probabilities A, B, C and the threshold points 160, 162 at which the probabilities are appropriately switched, the software can configure the counter so that a first value of the counter indicates that a relatively small number of accesses have occurred, a second level of the counter can indicate that the number of accesses is likely to be at least 10 or 100 times the first number, and a next value of the counter can indicate that there may have been several orders of magnitude more accesses, even if the counter value itself is incremented linearly. Again, this helps to reduce the size of the counter required to determine tracking information for a certain range of access numbers.

[0107] Thus, the probability configuration register 44 may also contain configuration data that allows one to select either: whether the probability is gradually decreased as the count value of the access frequency tracking counter 52 increases, or whether the probability is maintained constant regardless of the value of the access frequency tracking counter 52; · Threshold points 160, 162 that define the values ​​of the counter 52 at which the probability should be reduced; Probability levels A, B, C set for different ranges of counter values. The number of transition points at which the probabilities should be switched (FIG. 13 shows two transitions at thresholds 160, 162, but the software may be able to select a different number).

[0108] In this application, the term "configured to..." is used to mean that an element of an apparatus has a configuration capable of performing a defined operation. In this context, "configuration" refers to a method of arrangement or interconnection of hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that an apparatus element needs to be modified in any way to provide the defined operation.

[0109] Although exemplary embodiments of the present invention are described in detail herein with reference to the accompanying drawings, it will be understood that the invention is not limited to these precise embodiments, and that various changes and modifications can be made to the embodiments by those skilled in the art without departing from the scope of the present invention as defined by the appended claims.

Claims

1. An apparatus comprising: a memory access circuit that processes a memory access request for requesting access to a memory system; an access frequency tracking circuit that responds to a given memory access request for requesting access to a given page of a memory address space, determining a result of a contingency-dependent test that contingently depends when the result of the contingency-dependent test is determined for the given memory access request, when the result of the contingency-dependent test is a first result, updating an access frequency tracking indicator corresponding to the given page in an access frequency tracking structure, when the result of the contingency-dependent test is a result other than the first result, omitting updating of the access frequency tracking indicator corresponding to the given page for the access frequency tracking circuit; and the apparatus.

2. The apparatus according to claim 1, wherein the contingency-dependent test has a software-configurable probability of providing the first result.

3. The software-configurable probability of providing the first result depends on a software-configured global parameter shared among all memory access requests, and a software-configured local parameter specific to a particular subset of memory access requests including the given memory access request at least one of. The apparatus according to claim 2.

4. The apparatus according to claim 2, wherein the software-configurable probability is specified in a software-configurable register.

5. The access frequency tracking circuit is configured to set a probability of the contingency-dependent test that provides the first result separately for different pages of the memory address space, in response to a determination that the frequency of access to the given page has reached or exceeded a predetermined threshold, the access frequency tracking circuit is configured to reduce the probability that the contingency-dependent test provides the first result for subsequent instances of a memory access request for requesting access to the given page. The apparatus according to any one of claims 1 to 4.

6. The apparatus according to any one of claims 1 to 4, wherein the contingency-dependent test includes determining whether a test evaluation counter for counting memory access requests satisfies a predetermined condition.

7. The apparatus according to claim 6, wherein the test evaluation counter is a global counter shared among all memory access requests.

8. The apparatus according to claim 6, wherein the test evaluation counter is one of a plurality of local counters each counting a specific subset of memory access requests, and the contingency-dependent test is based on the local counter corresponding to the specific subset of memory access requests including the given memory access request.

9. The apparatus according to claim 8, wherein the plurality of local counters correspond to specific subsets of memory access requests associated with different operation modes or execution states.

10. The apparatus according to claim 8, wherein the plurality of local counters include a load counter for counting load memory access requests and a store counter for counting store memory access requests.

11. The apparatus according to claim 8, wherein the plurality of local counters correspond to specific subsets of memory access requests requesting access to different regions or pages of the memory address space.

12. The apparatus according to claim 8, wherein the plurality of local counters correspond to specific subsets of memory access requests requesting access to different pages of the memory address space.

13. The apparatus according to any one of claims 1 to 4, wherein the contingency-dependent test includes determining whether a part of bits has a predetermined value, and the part of bits includes bits sampled from one or more items of internal control information of the apparatus or a serial pulse train derived from one or more analog or digital signals of the apparatus.

14. The apparatus according to any one of claims 1 to 4, wherein the contingency-dependent test includes determining whether a random number or a pseudo-random number has a predetermined value.

15. The access frequency tracking indicator includes a tracking flag, The apparatus according to any one of claims 1 to 4, wherein when the result of the contingency-dependent test is the first result and the tracking flag corresponding to the given page has a first value, the access frequency tracking circuit is configured to set the tracking flag corresponding to the given page to specify a second value.

16. The access frequency tracking indicator includes a multi-bit access frequency tracking counter, The apparatus according to any one of claims 1 to 4, wherein when the result of the contingency-dependent test is the first result, the access frequency tracking circuit is configured to increment the multi-bit access frequency tracking counter corresponding to the given page.

17. The apparatus according to any one of claims 1 to 4, wherein the access frequency tracking structure includes an access frequency tracking hardware structure including a plurality of entries, and each entry stores the access frequency tracking indicator for the corresponding page of the memory address space.

18. The apparatus according to claim 17, wherein the access frequency tracking hardware structure is a translation lookaside buffer, and the plurality of entries are translation lookaside buffer entries for storing the access frequency tracking information and address translation information respectively associated with the corresponding page.

19. The apparatus according to any one of claims 1 to 4, wherein the access frequency tracking structure includes a memory-based data structure stored in the memory system.

20. The apparatus according to claim 19, wherein the access frequency tracking structure includes a linear data structure including a plurality of entries having addresses within a contiguous block of the memory address space, and the access frequency tracking circuit is configured to identify the entry of the linear data structure that provides the access frequency tracking indicator corresponding to the given page based on an offset determined based on the address of the given page.

21. The apparatus according to any one of claims 1 to 4, wherein the access frequency tracking structure includes a tree structure.

22. The apparatus according to claim 21, wherein the tree structure is a page table structure including a plurality of page table entries for specifying address translation information for the corresponding page of the memory address space, and the page table entry corresponding to the given page includes the access frequency tracking indicator corresponding to the given page.

23. A processing circuit that executes data processing in response to an instruction defined according to an instruction set architecture, the memory access circuit, and the access frequency tracking circuit A processing element comprising the apparatus according to any one of claims 1 to 4.

24. An input / output memory management unit for performing memory management operations instead of at least one device having direct memory access to the memory system, The apparatus according to any one of claims 1 to 4, wherein the input / output memory management unit includes the memory access circuit and the access frequency tracking circuit.

25. A method for tracking access frequencies to one or more pages of a memory address space, comprising: In response to a given memory access request that requests access to a given page of the memory address space, Determining a result of the contingency-dependent test that contingently depends when the result of the contingency-dependent test is determined for the given memory access request; Updating an access frequency tracking indicator corresponding to the given page in the access frequency tracking structure when the result of the contingency-dependent test is a first result; Omitting updating of the access frequency tracking indicator corresponding to the given page when the result of the contingency-dependent test is a result other than the first result A method comprising.

Images