Gamma voltage conversion circuit, display device, and gamma voltage conversion method

Abstract

The present disclosure provides a gamma voltage conversion circuit having a plurality of first input terminals and a plurality of first voltage dividing output terminals, where one first input terminal is arranged to receive a first gamma voltage signal inputted by one first gamma channel, the first voltage dividing circuit is arranged to generate a multiple first analog voltage signal based on the first gamma voltage signal, the one first voltage dividing output terminal is arranged to output one first analog voltage signal, the gray code control circuit is used to generate and output a corresponding gray code control signal based on a gray scale value to be displayed, the first encoding circuit is used to generate and output a multiple second analog voltage signal based on one of the gray code control signal and the multiple first analog voltage signal, and the first output control circuit is used to generate and output an analog gray scale voltage signal based on the multiple second analog voltage signal. The present disclosure further provides a display device and a gamma voltage conversion method.

Description

[Technical field]

[0001] The present disclosure relates to the field of display technology, and in particular to a gamma voltage conversion circuit, a display device, and a gamma voltage conversion method. [Background technology]

[0002] Organic Light-Emitting Device (OLED) display substrate is a display substrate different from conventional Liquid Crystal Display (LCD). It has advantages such as active light emission, good temperature characteristics, low power consumption, fast response, bendability, ultra-lightweight, and low cost, and has already become one of the important development discoveries of next-generation display devices. In addition, active matrix organic light-emitting diode (AMOLED) display substrate is also beginning to stand out in the small size field. Meanwhile, the corresponding display system needs to convert the corresponding gamma voltage into analog gray scale voltage before displaying, and in this case, a corresponding gamma voltage conversion circuit needs to be used. At the current stage, the conventional conversion circuit has problems such as large noise, slow response speed, gray scale display brightness jitter during gamma voltage conversion, and poor uniformity of the display substrate. Summary of the Invention [Problem to be solved by the invention]

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a gamma voltage conversion circuit, a display device, and a gamma voltage conversion method. [Means for solving the problem]

[0004] In order to achieve the above object, in a first aspect, an embodiment of the present disclosure comprises: a first voltage dividing circuit having a plurality of first input terminals and a plurality of first voltage dividing output terminals, one of the first input terminals being arranged to receive a first gamma voltage signal inputted by one first gamma channel, the first voltage dividing circuit being arranged to generate multiple first analog voltage signals based on the first gamma voltage signal, and one of the first voltage dividing output terminals being arranged to output one of the first analog voltage signals; A gray code control circuit is used for generating and outputting a corresponding gray code control signal according to the gray scale value to be displayed; a first encoding circuit for generating and outputting a multiplexed second analog voltage signal according to one of the Gray code control signal and the multiplexed first analog voltage signal; a first output control circuit for generating and outputting an analog gray scale voltage signal based on the multiplexed second analog voltage signal.

[0005] In some embodiments, the first voltage divider circuit includes a plurality of series-connected resistors, a connection node between any two series-connected resistors is a series connection node, and one of the series connection nodes corresponds to one of the first voltage divider output terminals.

[0006] In some embodiments, the Gray code control signal includes a first Gray code signal and a second Gray code signal, and each bit of the first Gray code signal and the second Gray code signal are inverted; The first encoding circuit is specifically used for generating and outputting the multiplexed second analog voltage signal based on either the first Gray code signal, the second Gray code signal, or the multiplexed first analog voltage signal.

[0007] In some embodiments, the first encoding circuit includes a plurality of switching sub-circuits and a plurality of output sub-circuits; Each of the switching sub-circuits includes a plurality of branches, each of the branches having a second input terminal and a plurality of third input terminals, the second input terminal being arranged to receive the first analog voltage signal outputted by the first voltage dividing output terminal, and the third input terminal being arranged to receive a first preset bit of the Gray code control signal, each of the branches being arranged to control its own on / off state according to the first preset bits of the Gray code control signal, and being arranged to generate a voltage signal to be outputted according to the received first analog voltage signal when in an on state; Each of the output sub-circuits has a plurality of fourth input terminals and a plurality of fifth input terminals, one of the fourth input terminals being arranged to receive the voltage signal waiting to be outputted by one of the switching sub-circuits and one of the fifth input terminals being arranged to receive one second preset bit of the Gray code control signal, and each of the output sub-circuits is arranged to control the on-state of itself and one of the switching sub-circuits based on the plurality of second preset bits of the Gray code control signal, and to generate and output the second analog voltage signal based on the received voltage signal waiting to be outputted.

[0008] In some embodiments, the first analog voltage signal and the first voltage dividing output terminal correspond to the gray scale value in a one-to-one manner, and the second analog gray scale voltage corresponds to the gray scale value in a one-to-one manner, m m is a positive integer, the plurality of switching subcircuits includes a plurality of first switching subcircuits and a plurality of second switching subcircuits, each of the first switching subcircuits includes 2n branches, each of the second switching subcircuits includes 2n branches, n is a positive integer; The first voltage dividing output terminals are arranged in order from small to large according to the corresponding gradation values, and every n adjacent first voltage dividing output terminals form one set, and for N sets of the first voltage dividing output terminals whose corresponding gradation values ​​are equal to or smaller than a predetermined first threshold, every two adjacent sets of the first voltage dividing output terminals are connected to the second input terminals in one of the first switching sub-circuits, N is a positive integer, and for M sets of the first voltage dividing output terminals whose corresponding gradation values ​​are equal to or larger than a predetermined second threshold, every two adjacent sets of the first voltage dividing output terminals are connected to the second input terminals in one of the second switching sub-circuits, the second threshold is larger than the first threshold, and M is a positive integer.

[0009] In some embodiments, the plurality of switching subcircuits includes a third switching subcircuit and a plurality of fourth switching subcircuits, the third switching subcircuit including k branches and each of the fourth switching subcircuits including n branches, where k=(2 m -N*nM*n) / n, where k is a positive integer, For a plurality of sets of first voltage dividing output terminals whose corresponding gradation values ​​are greater than the first threshold value and smaller than the second threshold value, the gradation values ​​corresponding to the first voltage dividing output terminals of each set include the smallest first gradation value and n-1 second gradation values ​​thereamong, and the first voltage dividing output terminals corresponding to each of the n adjacent first gradation values ​​are sequentially and alternately connected to the n second input terminals of the third switching sub-circuit and each of the second input terminals of one of the fourth switching sub-circuits.

[0010] In some embodiments, m=8 and n=4, the corresponding gray scale values ​​are arranged in order from smallest to largest and include stages 0 to 255, the Gray code control signal includes bits 0 to 7 in order from least to largest, the first threshold is equal to the gray scale value of the 31st stage, and the second threshold is equal to the gray scale value of the 224th stage.

[0011] In some embodiments, the first preset bits corresponding to the first switching sub-circuit and the second switching sub-circuit both include bits 0 to 4, the first preset bits corresponding to the third switching sub-circuit include bits 2 to 7, and the first preset bits corresponding to the fourth switching sub-circuit include bits 3 to 7.

[0012] In some embodiments, the first encoding circuit has a plurality of switching transistors, the switching transistors including first to eighth transistors, the control poles of which are respectively used to receive the opposite 0th bit to the opposite 7th bit, and the control poles of 9th to 16th transistors are respectively used to receive the 0th bit to the 7th bit; Each of the first switching sub-circuit and the second switching sub-circuit includes a first branch to an eighth branch, the first branch includes a first transistor, a second transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to a gradation value of 5+8i stages, and the second branch includes a ninth transistor, a second transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to a gradation value of 4+8i stages. the third branch includes a first transistor, a tenth transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to a gradation value of 6+8i stages; the fourth branch includes a ninth transistor, a tenth transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to a gradation value of 7+8i stages. the fifth branch includes a first transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to a gradation value of 1+8i stages; the sixth branch includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to a gradation value of 0+8i stages. the seventh branch includes a first transistor, a second transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output by the first voltage dividing output terminal corresponding to a 2+8i stage grayscale value; the eighth branch includes a ninth transistor, a second transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output by the first voltage dividing output terminal corresponding to a 3+8i stage grayscale value; Here, for the first switching sub-circuit, the value of i is one of 0, 1, 2, and 3, and for the second switching sub-circuit, the value of i is one of 28, 29, 30, and 31.

[0013] In some embodiments, the first through eighth branches multiplex the twelfth and thirteenth transistors, the first through fourth branches multiplex the third transistor, the fifth through eighth branches multiplex the eleventh transistor, the first and second branches multiplex one second transistor, the third and fourth branches multiplex one tenth transistor, the fifth and sixth branches multiplex another tenth transistor, and the seventh and eighth branches multiplex another second transistor.

[0014] In some embodiments, one of the fourth switching sub-circuits includes a ninth branch to a twelfth branch, the ninth branch includes a fourth transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output by the first voltage dividing output terminal corresponding to a first gradation value of a 60+32j stage, and the tenth branch includes a twelfth transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output by the first voltage dividing output terminal corresponding to a first gradation value of a 52+32j stage. the 11th branch includes a 4th transistor, a 5th transistor, a 6th transistor, a 15th transistor, and a 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to a first gray scale value of a 44+32j stage; the 12th branch includes a 12th transistor, a 5th transistor, a 6th transistor, a 15th transistor, and a 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to a first gray scale value of a 36+32j stage, where the value of j is any of 0, 1, 2, 3, 4, and 5; The third switching subcircuit includes a plurality of basic cells, and each of the basic cells includes a thirteenth branch to a sixteenth branch. The thirteenth branch includes a third transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to a first gradation value of a 56+32j stage. The fourteenth branch includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to a first gradation value of a 48+32j stage. The fifteenth branch includes a third transistor, a fifth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence. the 16th branch includes an 11th transistor, a 12th transistor, a 5th transistor, a 6th transistor, a 15th transistor, and a 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output by the first voltage dividing output terminal corresponding to a first gradation value of a 32+32j stage; with respect to one of the basic cells, a fourth transistor is further connected between the 11th transistor of the 14th branch and the 5th transistor of the 15th branch; with respect to two adjacently disposed basic cells, a fourth transistor is further connected between the 11th transistor of the 16th branch of one of the basic cells and the 13th transistor of the 13th branch of the other basic cell.

[0015] In some embodiments, the ninth branch through the twelfth branch multiplex the sixth transistor, the fifteenth transistor, and the sixteenth transistor; the ninth branch and the tenth branch multiplex the thirteenth transistor; the eleventh branch and the twelfth branch multiplex the fifth transistor; For one basic cell, the 13th to 16th branches multiplex the 6th transistor, the 15th transistor and the 16th transistor, the 13th and 14th branches multiplex the 13th transistor, and the 15th and 16th branches multiplex the 5th transistor.

[0016] In some embodiments, the plurality of output subcircuits include a first output subcircuit, a second output subcircuit, and a third output subcircuit, each of the output subcircuits having four of the fourth inputs and configured to receive the voltage signals output by a corresponding one of the first plurality of switching subcircuits, the second plurality of switching subcircuits, the third switching subcircuit, and the fourth plurality of switching subcircuits, respectively; The first output sub-circuit and the second output sub-circuit are both arranged to output one of the second analog voltage signals based on the voltage signal waiting to be output, and the third output sub-circuit is arranged to output two identical second analog voltage signals based on the voltage signal waiting to be output.

[0017] In some embodiments, the first output sub-circuit is arranged to control turning on itself and one of the first switching sub-circuits or one of the second switching sub-circuits based on a fifth bit, a sixth bit and a seventh bit of the Gray code control signal, or to control turning on itself and the third switching sub-circuit or one of the fourth switching sub-circuits based on a second bit and a third bit of the Gray code control signal; the second output sub-circuit is arranged to control turning on itself and one of the first switching sub-circuits or one of the second switching sub-circuits based on a fifth bit, a sixth bit, and a seventh bit of the Gray code control signal, or to control turning on itself and the third switching sub-circuit or one of the fourth switching sub-circuits based on a zeroth bit and a first bit of the Gray code control signal; The third output sub-circuit is configured to control the on-state of itself and one of the first switching sub-circuits or one of the second switching sub-circuits based on the fifth bit, sixth bit and seventh bit of the Gray code control signal, or to control the on-state of itself and the third switching sub-circuit or one of the fourth switching sub-circuits based on the first bit of the Gray code control signal.

[0018] In some embodiments, each of the output subcircuits includes a plurality of switching transistors, the switching transistors including first through eighth transistors whose control poles are adapted to receive the opposite 0th bit through the opposite 7th bit, respectively, and ninth through sixteenth transistors whose control poles are adapted to receive the 0th bit through the 7th bit, respectively; the first output sub-circuit is connected to the outputs of the plurality of fourth switching sub-circuits via a third transistor and a twelfth transistor and to the outputs of the plurality of fourth switching sub-circuits via a fourth transistor and an eleventh transistor; the first output sub-circuit is connected to the third switching sub-circuit via an eleventh transistor and a twelfth transistor and to the third switching sub-circuit via a fourth transistor and a third transistor; the first output sub-circuit is connected to the outputs of the plurality of first switching sub-circuits via a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor; and the first output sub-circuit is connected to the outputs of the plurality of second switching sub-circuits via a fourteenth transistor, a fifteenth transistor, and an eighth transistor; the second output sub-circuit is connected to the outputs of the plurality of fourth switching sub-circuits via a second transistor and a ninth transistor and to the outputs of the plurality of fourth switching sub-circuits via a first transistor and a tenth transistor; the second output sub-circuit is connected to the third switching sub-circuit via a ninth transistor and a tenth transistor and to the third switching sub-circuit via a first transistor and a second transistor; the second output sub-circuit is connected to the outputs of the plurality of first switching sub-circuits via a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor; and the second output sub-circuit is connected to the outputs of the plurality of second switching sub-circuits via a fourteenth transistor, a fifteenth transistor, and an eighth transistor; The third output sub-circuit is connected to the output ends of the plurality of fourth switching sub-circuits via a second transistor, the third output sub-circuit is connected to the third switching sub-circuit via a tenth transistor, the third output sub-circuit is connected to the output ends of the plurality of first switching sub-circuits via a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, and the third output sub-circuit is connected to the output ends of the plurality of second switching sub-circuits via a fourteenth transistor, a fifteenth transistor, and an eighth transistor.

[0019] In some embodiments, the first output control circuit includes an operational amplifier, an input terminal of the first output control circuit is arranged to receive the four second analog voltage signals output by the multiple output sub-circuits, and the operational amplifier is arranged to perform weighted summation based on the four second analog voltage signals to generate the analog grayscale voltage signal.

[0020] In some embodiments, the Gamma voltage conversion circuit comprises: a second voltage dividing circuit having a plurality of sixth input terminals and a plurality of second voltage dividing output terminals, wherein one of the sixth input terminals is arranged to receive a second gamma voltage signal inputted by one second gamma channel, the second voltage dividing circuit is arranged to generate a plurality of third analog voltage signals based on the second gamma voltage signal, and one of the second voltage dividing output terminals is arranged to output one of the third analog voltage signals; a second encoding circuit for generating and outputting a multiplexed fourth analog voltage signal according to the Gray code control signal and one of the plurality of third analog voltage signals; The display further includes a second output control circuit, which is used for generating and outputting an analog gray scale voltage signal according to the multiplexed fourth analog voltage signal.

[0021] In some embodiments, The first encoding circuit and the second encoding circuit each include a plurality of switching transistors, the switching transistors in the first encoding circuit are either P-type transistors or N-type transistors, and the switching transistors in the second encoding circuit are either P-type transistors or N-type transistors, and a control pole signal corresponding to the switching transistors in the first encoding circuit and a control pole signal corresponding to the switching transistors in the second encoding circuit are each bit reversed.

[0022] In a second aspect, an embodiment of the present disclosure provides a display device including a gamma voltage conversion circuit, The gamma voltage conversion circuit employs any of the gamma voltage conversion circuits described in the above embodiments.

[0023] In a third aspect, an embodiment of the present disclosure comprises: A gamma voltage conversion method applied to the gamma voltage conversion circuit according to any one of the above embodiments, generating a multiplexed first analog voltage signal based on a first gamma voltage signal inputted by a first gamma channel; generating a corresponding gray code control signal based on the gray scale value to be displayed; generating a multiplexed second analog voltage signal based on one of the Gray code control signal and the multiplexed first analog voltage signal; generating and outputting an analog gray scale voltage signal based on the multiplexed second analog voltage signal.

[0024] In some embodiments, the step of generating multiple second analog voltage signals based on one of the Gray code control signal and the multiple first analog voltage signals comprises: controlling an on / off state of one branch of one of its switching sub-circuits according to the first preset bits of the Gray code control signal, and generating a voltage signal ready to be output according to the first analog voltage signal received by the branch in an on state; and turning on its output sub-circuit and the switching sub-circuit based on the second preset bits of the Gray code control signal, and generating and outputting the second analog voltage signal based on the voltage signal waiting to be output.

[0025] In some embodiments, the step of generating and outputting an analog grayscale voltage signal based on the multiplexed second analog voltage signal includes: The method includes performing weighted addition based on the multiplexed second analog voltage signal to generate the analog gray scale voltage signal.

[0026] In some embodiments, the method further comprises: generating a multiplexed third analog voltage signal according to a second gamma voltage signal inputted by a second gamma channel; generating a multiplexed fourth analog voltage signal based on one of the Gray code control signal and the multiplexed third analog voltage signal; generating and outputting an analog gray scale voltage signal based on the multiplexed fourth analog voltage signal. [Brief description of the drawings]

[0027] The drawings are intended to provide a further understanding of the present disclosure, constitute a part of the specification, and are intended to explain the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the drawings.

[0028] [Figure 1] 1 is a structural conceptual diagram of a gamma voltage conversion circuit according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a structural conceptual diagram of a first encoding circuit according to an embodiment of the present disclosure. [Diagram 3] FIG. 13 is a conceptual diagram of another first encoding circuit according to an embodiment of the present disclosure. [Figure 3a] FIG. 2 is a structural conceptual diagram of a first switching sub-circuit or a second switching sub-circuit according to an embodiment of the present disclosure. [Figure 3b] FIG. 13 is a structural schematic diagram of a fourth switching sub-circuit according to an embodiment of the present disclosure. [Figure 3c] FIG. 13 is a structural conceptual diagram of a plurality of basic cells of a third switching sub-circuit according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a conceptual diagram of an output subcircuit according to an embodiment of the present disclosure. [Figure 4a] FIG. 2 is a structural schematic diagram of a first output sub-circuit according to an embodiment of the present disclosure. [Figure 4b] FIG. 13 is a structural schematic diagram of a second output sub-circuit according to an embodiment of the present disclosure. [Figure 4c] FIG. 13 is a structural schematic diagram of a third output sub-circuit according to an embodiment of the present disclosure. [Diagram 5] FIG. 13 is a structural conceptual diagram of another Gamma voltage conversion circuit according to an embodiment of the present disclosure. [Figure 6] 4 is a flow chart of a gamma voltage conversion method according to an embodiment of the present disclosure. [Figure 7] 11 is a flowchart of a specific implementation method of step S3 in an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] In order to make the technical solution of the present disclosure more easily understandable to those skilled in the art, the following detailed description of the gamma voltage conversion circuit, display device and gamma voltage conversion method provided by the present disclosure will be given in combination with the accompanying drawings.

[0030] Exemplary embodiments are described more fully below with reference to the drawings, which should not be construed as being limited to the embodiments described herein, as they may be embodied in different forms, and on the contrary, the purpose of providing these embodiments is to make this disclosure thorough and complete, and to fully convey the scope of the disclosure to those skilled in the art.

[0031] The terms used herein are used only to describe specific embodiments and are not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly indicates otherwise. It will also be understood that the use of the terms "comprising" and / or "comprising" herein refers to the presence of such features, wholes, steps, operations, components, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, components, and / or groups thereof.

[0032] In the present specification, terms such as first, second, etc. may be used to describe various parts, but it should be understood that these parts should not be limited by these terms. These terms are used only to distinguish one part from another. Thus, a first part, first component, or first module discussed below may be referred to as a second part, second component, or second module without departing from the teachings of the present disclosure.

[0033] Unless otherwise specified, the meaning of all terms (including technical and scientific terms) used in the present specification is the same as that commonly understood by those skilled in the art. It will also be understood that terms defined in general dictionaries, unless expressly limited in this specification, are interpreted as having a meaning consistent with the meaning in the context of the relevant technology and this disclosure, and are not interpreted as having an ideal or excessively formal meaning.

[0034] 1 is a structural conceptual diagram of a gamma voltage conversion circuit according to an embodiment of the present disclosure. As shown in FIG. 1, the gamma voltage conversion circuit includes a first voltage dividing circuit 1, a gray code control circuit 2, a first encoding circuit 3, and a first output control circuit 4.

[0035] Here, the first voltage dividing circuit 1 has a plurality of first input terminals 101 and a plurality of first voltage dividing output terminals 102, one first input terminal 101 is arranged to receive a first Gamma voltage signal inputted by one first Gamma channel, the first voltage dividing circuit 1 is arranged to generate a multiplexed first analog voltage signal based on the first Gamma voltage signal, and the one first voltage dividing output terminal 102 is arranged to output one first analog voltage signal.

[0036] The gray code control circuit 2 is used for generating and outputting a corresponding gray code (Gray) control signal based on the gray scale value to be displayed.

[0037] The first encoding circuit 3 is used for generating and outputting a multiplexed second analog voltage signal according to one of the Gray code control signal and the multiplexed first analog voltage signal.

[0038] The first output control circuit 4 is used for generating and outputting an analog gray scale voltage signal according to the multiplexed second analog voltage signal.

[0039] In some embodiments, the first voltage divider circuit 1 includes a plurality of series-connected resistors, a connection node between any two series-connected resistors is a series-connected node, and one series-connected node corresponds to one first voltage-divided output terminal. In some embodiments, the first voltage divider circuit 1 is also called a resistor string.

[0040] In some embodiments, the Gray code control signal includes a first Gray code signal and a second Gray code signal, and each bit of the first Gray code signal and the second Gray code signal are inverse. The first encoding circuit 3 is specifically used for generating and outputting a multiple second analog voltage signal according to either the first Gray code signal, the second Gray code signal, or the multiple first analog voltage signal.

[0041] In some embodiments, the binary code and the Gray code can be mutually converted based on the following method: The conversion from the binary code to the Gray code includes: retaining the most significant bit of the binary code, and taking the exclusive OR result of the most significant bit of the binary code and the second most significant bit as the second most significant bit of the Gray code; and then taking the exclusive OR result of the previous bit of the binary code and the current bit as the current bit of the Gray code to obtain the Gray code corresponding to the binary code; The conversion from the Gray code to the binary code includes: taking 0 and the most significant bit of the Gray code as the most significant bit of the binary code, and taking the exclusive OR result of the most significant bit of the binary code and the second most significant bit of the Gray code as the second most significant bit of the binary code; and then taking the exclusive OR result of the previous bit of the binary code and the current bit of the Gray code as the current bit of the binary code to obtain the binary code corresponding to the Gray code.

[0042] As for the conventional technical solution of gamma voltage conversion based on binary code, it will cause problems such as jitter of display brightness, uneven brightness and power supply fluctuation when switching between gray levels, because there may be a situation where multiple bits are inverted at the same time when converting between gray levels based on binary code. For example, from the 127th gray level to the 128th gray level, the corresponding binary code is from 01111111 to 10000000, and 8 bits are inverted at the same time, which will generate large burrs and noise. In addition, because the length of the scanning lines and the magnitude of the load are different, the switches controlled by each of the eight bits cannot work simultaneously, and there is a possibility that an intermediate state will be formed during reversal, such as from 01111111 to 00011111, and even to 10000000, the intermediate state 00011111, that is, the 31st stage gray scale is not desired to appear, so that the voltage corresponding to the 31st stage gray scale is temporarily turned on during the switching process, which causes the output voltage to fluctuate, and the required gray scale cannot be output quickly and accurately, that is, the voltage corresponding to the 128th stage gray scale affects the response speed and the time to reach a steady state. In addition, the charging time of each row is short, which is even more likely to cause insufficient charging at the far end and reduced brightness, resulting in poor uniformity of the panel and device. Multiple bits are switched at the same time, which increases the instantaneous suction load of the digital circuit and analog circuit, causing the power supply to fluctuate. On the other hand, when using the Gray code, from the 127th to 128th gray levels, the corresponding Gray code is from 01001000 to 11000000, and only the 7th and 3rd bits change, and from the 199th to 200th gray levels, the corresponding Gray code is from 10100100 to 10101100, and only the 3rd bit changes, and in most Gray code applications, only one bit changes. Therefore, by using the Gray code to participate in the conversion, the unstable state in the conversion process is greatly reduced, and the output voltage fluctuation caused by the simultaneous switching of multiple bits in the switching process of each gray level is avoided, so that the output reaches the target voltage more quickly and accurately, and the response speed is improved.

[0043] In the embodiments of the present disclosure, a coding circuit based on a Gray code or the like is adopted to perform gamma voltage conversion, and the adjacent gray scale switching process corresponding to the Gray code brings about a change of at most 2 bits, avoiding switching of multiple bits and the unstable and intermediate states in the process, thereby improving the response speed, reducing circuit burrs and noise, and making the change in gray scale display brightness when switching between gray scales smoother, thereby solving problems such as display jitter and power supply fluctuations caused by switching between gray scales, and furthermore, the output reaches the target potential more accurately, so that the voltages at the far and near ends of the panel are consistent, thereby making the brightness consistent and making the panel more uniform.

[0044] 2 is a structural conceptual diagram of a first encoding circuit according to an embodiment of the present disclosure. Specifically, the structure is an optional implementation based on the Gamma voltage conversion circuit shown in FIG. 1. As shown in FIG. 2, the first encoding circuit includes a plurality of switching sub-circuits 301 and a plurality of output sub-circuits 302.

[0045] Here, each switching sub-circuit 301 includes multiple branches, each branch has a second input terminal 3011 and multiple third input terminals 3012, the second input terminal 3011 is arranged to receive a first analog voltage signal output by a first voltage dividing output terminal, the third input terminal 3012 is arranged to receive a first preset bit of a Gray code control signal, each branch is arranged to control its own on / off state according to the multiple first preset bits of the Gray code control signal, and when in an on state, is arranged to generate a voltage signal waiting to be output based on the received first analog voltage signal.

[0046] Here, each output sub-circuit 302 has a plurality of fourth input terminals 3021 and a plurality of fifth input terminals 3022, one fourth input terminal 3021 is arranged to receive a voltage signal to be outputted from one switching sub-circuit 301, one fifth input terminal 3022 is arranged to receive one second preset bit of the Gray code control signal, and each output sub-circuit 302 is arranged to control the on-state of itself and one switching sub-circuit 301 based on the plurality of second preset bits of the Gray code control signal, and generate and output a second analog voltage signal based on the received voltage signal to be outputted. Note that in each embodiment of the present disclosure, a circuit connected between one second input terminal and an output terminal of the switching sub-circuit is regarded as one branch of the switching sub-circuit.

[0047] 3 is a conceptual diagram of another first encoding circuit according to an embodiment of the present disclosure. Specifically, this structure is an optional implementation based on the first encoding circuit shown in FIG. 2. Here, the first analog voltage signal and the first voltage dividing output terminal correspond one-to-one with the gray scale value, and the second analog gray scale voltage signal corresponds one-to-one with the gray scale value, resulting in a total of two m It has tone values ​​in steps, where m is a positive integer.

[0048] Here, as shown in FIG. 3, the multiple switching subcircuits include multiple first switching subcircuits 501 and multiple second switching subcircuits 502, each first switching subcircuit 501 includes 2n branches, each second switching subcircuit 502 includes 2n branches, n is a positive integer, arranged in order from small to large according to the corresponding gradation values, every n adjacent first voltage dividing output terminals form a set, for N sets of first voltage dividing output terminals whose corresponding gradation values ​​are equal to or smaller than a predetermined first threshold, every two adjacent sets of first voltage dividing output terminals are connected to each second input terminal 3011 in one first switching subcircuit 501, N is a positive integer, for M sets of first voltage dividing output terminals whose corresponding gradation values ​​are equal to or larger than a predetermined second threshold, every two adjacent sets of first voltage dividing output terminals are connected to each second input terminal 3011 of one second switching subcircuit 502, the second threshold is greater than the first threshold, and M is a positive integer. Here, as shown in the drawing, the first switching sub-circuit 501 corresponds to the output D terminal, and the second switching sub-circuit 502 corresponds to the output E terminal.

[0049] In some embodiments, m=8 and n=4, the corresponding gray scale values ​​are arranged in order from smallest to largest and include stages 0 to 255, the Gray code control signal is arranged in order from least to largest and includes bits 0 to 7, the first threshold is equal to the gray scale value of the 31st stage, and the second threshold is equal to the gray scale value of the 224th stage.

[0050] Specifically, since the output of the first voltage divider circuit is nonlinear, the degree of nonlinearity is particularly large when outputting the corresponding low gradations (e.g., steps 0 to 31 in this embodiment) and high gradations (e.g., steps 224 to 255 in this embodiment), so the low and high gradations need to be output for each gradation.

[0051] In some embodiments, the first encoding circuit has a plurality of switching transistors, including a first transistor 601 to an eighth transistor 608, whose control poles are respectively used to receive the opposite 0th bit to the opposite 7th bit, and in the drawings, Sn <0> The control electrodes of the ninth transistor 609 to the sixteenth transistor 616 are respectively used to receive the 0th bit to the 7th bit. In the figure, S <0> represents the 0th bit, and the other codes can be inferred similarly.

[0052] 3a is a structural conceptual diagram of the first switching sub-circuit or the second switching sub-circuit according to an embodiment of the present disclosure. As shown in FIG. 3a, this corresponds to the situation where m=8 and n=4, and the structures of the first switching sub-circuit 501 and the second switching sub-circuit 502 are exemplarily shown. Note that these values ​​do not limit the technical solutions in this embodiment and the following embodiments, but are described only as examples, and other values ​​of m and n can also be applied to the technical solutions of the present application.

[0053] Here, the first preset bits corresponding to the first switching sub-circuit 501 and the second switching sub-circuit 502 each include the 0th bit to the 4th bit.

[0054] Here, there are a total of four first switching sub-circuits 501 and four second switching sub-circuits 502, and each of the first switching sub-circuits 501 and the second switching sub-circuits 502 includes a first branch to an eighth branch, where the first branch includes a first transistor 601, a second transistor 602, a third transistor 603, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, and is arranged to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to a gradation value of the 5+8i stage, and in the drawings, the object that the branch is arranged to receive is represented by INH<5+8i>, and the other symbols may be inferred therefrom.The second branch includes a ninth transistor 609, a second transistor 602, a third transistor 603, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, and is arranged to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to a gradation value of a 4+8i stage; the third branch includes a first transistor 601, a tenth transistor 610, a third transistor 603, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, and is arranged to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to a gradation value of a 6+8i stage. The fourth branch includes a ninth transistor 609, a tenth transistor 610, a third transistor 603, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, and is arranged to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to a gradation value of the 7+8ith stage. The fifth branch includes a first transistor 601, a tenth transistor 610, an eleventh transistor 611, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence. The sixth branch includes a ninth transistor 609, a tenth transistor 610, an eleventh transistor 611, a twelfth transistor 612, and a thirteenth transistor 613, which are connected in sequence, and are arranged to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to a gradation value of a 0+8i stage; the seventh branch includes a first transistor 601, a second transistor 613, which are connected in sequence, and are arranged to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to a gradation value of a 0+8i stage; The eighth branch includes a ninth transistor 609, a second transistor 602, an eleventh transistor 611, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, and is arranged to receive the first analog voltage signal output by the first voltage dividing output terminal corresponding to the 3+8i stage gradation value, and the eighth branch includes a ninth transistor 609, a second transistor 602, an eleventh transistor 611, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, and is arranged to receive the first analog voltage signal output by the first voltage dividing output terminal corresponding to the 3+8i stage gradation value.

[0055] Here, for the first switching subcircuit 501, the value of i is 0, 1, 2, or 3, and for the second switching subcircuit 502, the value of i is 28, 29, 30, or 31, and the first switching subcircuit 501 corresponds to the output D terminal and the second switching subcircuit 502 corresponds to the output E terminal, as shown in FIG. 3a.

[0056] In some embodiments, as shown in FIG. 3a, the first through eighth branches multiplex the twelfth transistor 612 and the thirteenth transistor 613, the first through fourth branches multiplex the third transistor 603, the fifth through eighth branches multiplex the eleventh transistor 611, the first and second branches multiplex one second transistor 602, the third and fourth branches multiplex one tenth transistor 610, the fifth and sixth branches multiplex another tenth transistor 610, and the seventh and eighth branches multiplex another second transistor 602.

[0057] In some embodiments, as shown in FIG. 3, the multiple switching subcircuits include a third switching subcircuit 503 and multiple fourth switching subcircuits 504, where the third switching subcircuit 503 includes k branches and each fourth switching subcircuit 504 includes n branches, where k=(2m-N*nM*n) / n, where k is a positive integer.

[0058] For a plurality of sets of first voltage dividing output terminals whose corresponding gradation values ​​are greater than the first threshold value and less than the second threshold value, the gradation values ​​corresponding to the first voltage dividing output terminals of each set include the smallest first gradation value and n-1 second gradation values ​​thereamong, and the first voltage dividing output terminals corresponding to each of four adjacent first gradation values ​​are sequentially and alternately connected to n second input terminals 3011 of the third switching sub-circuit 503 and each second input terminal 3011 of one fourth switching sub-circuit 504. Here, as shown in the drawing, the first switching sub-circuit 501 corresponds to the output B terminal, and the second switching sub-circuit 502 corresponds to the output A terminal.

[0059] Specifically, since the output of the first voltage divider circuit is nonlinear, especially since the degree of nonlinearity is large when outputting the corresponding low and high gradations, the low and high gradation parts need to be output for each gradation based on the first switching subcircuit 501 and the second switching subcircuit 502, and the gradations located in the intermediate part can be output using the third switching subcircuit and the fourth switching subcircuit described below based on the principle of reducing the occupied area.

[0060] 3b is a structural conceptual diagram of the fourth switching sub-circuit according to an embodiment of the present disclosure. As shown in FIG. 3b, this corresponds to the situation where m=8 and n=4, and exemplarily illustrates the structure of the fourth switching sub-circuit 504. Here, the first preset bits corresponding to the fourth switching sub-circuit 504 include the third bit to the seventh bit.

[0061] Here, there are six fourth switching sub-circuits 504 in total, and one fourth switching sub-circuit 504 includes ninth to twelfth branches, where the ninth branch includes a fourth transistor 604, a thirteenth transistor 613, a sixth transistor 606, a fifteenth transistor 615, and a sixteenth transistor 616 connected in sequence, and is arranged to receive a first analog voltage signal output from the first voltage dividing output terminal 102 corresponding to a first gradation value of the 60+32j stage; the tenth branch includes a twelfth transistor 612, a thirteenth transistor 613, a sixth transistor 606, a fifteenth transistor 615, and a sixteenth transistor 616 connected in sequence, and is arranged to receive a first analog voltage signal output from the first voltage dividing output terminal 102 corresponding to a first gradation value of the 52+32j stage. the eleventh branch includes a fourth transistor 604, a fifth transistor 605, a sixth transistor 606, a fifteenth transistor 615, and a sixteenth transistor 616 connected in sequence, and is arranged to receive a first analog voltage signal output by the first voltage dividing output terminal 102 corresponding to a first gray scale value of the 44+32j stage; the twelfth branch includes a twelfth transistor 612, a fifth transistor 605, a sixth transistor 606, a fifteenth transistor 615, and a sixteenth transistor 616 connected in sequence, and is arranged to receive a first analog voltage signal output by the first voltage dividing output terminal 102 corresponding to a first gray scale value of the 36+32j stage, where the value of j is any of 0, 1, 2, 3, 4, and 5.

[0062] In some embodiments, as shown in FIG. 3b, the ninth through twelfth branches multiplex the sixth transistor 606, the fifteenth transistor 615 and the sixteenth transistor 616, the ninth and tenth branches multiplex the thirteenth transistor 613, and the eleventh and twelfth branches multiplex the fifth transistor 605.

[0063] 3c is a structural conceptual diagram of a plurality of basic cells of the third switching sub-circuit according to an embodiment of the present disclosure. As shown in FIG. 3c, this corresponds to the situation where m=8 and n=4, and exemplarily illustrates the structure of the third switching sub-circuit 503. Here, the first preset bits corresponding to the third switching sub-circuit 503 include the second bit to the seventh bit.

[0064] Specifically, the third switching sub-circuit 503 includes six basic cells in total, two of which are shown in the drawing as an example. Here, one basic cell includes a thirteenth branch to a sixteenth branch, and the thirteenth branch includes a third transistor 603, a thirteenth transistor 613, a sixth transistor 606, a fifteenth transistor 615, and a sixteenth transistor 616 connected in sequence, and receives a first analog voltage signal outputted from the first voltage dividing output terminal 102 corresponding to a first gray scale value of the 56+32jth stage. the 14th branch includes an 11th transistor 611, a 12th transistor 612, a 13th transistor 613, a 6th transistor 606, a 15th transistor 615, and a 16th transistor 616 connected in sequence, and is arranged to receive a first analog voltage signal output from the first voltage dividing output terminal 100 corresponding to a first grayscale value of the 48+32jth stage; the 15th branch includes a third transistor 603, a fifth transistor 605, a sixth transistor 606, and a sixteenth transistor 616 connected in sequence. the 16th branch includes an 11th transistor 611, a 12th transistor 612, a 5th transistor 605, a 6th transistor 606, a 15th transistor 615, and a 16th transistor 616, and is arranged to receive a first analog voltage signal output by the first voltage dividing output terminal 102 corresponding to a first gradation value of the 32+32j stage; the 16th branch includes an 11th transistor 611, a 12th transistor 612, a 5th transistor 605, a 6th transistor 606, a 15th transistor 615, and a 16th transistor 616, which are connected in sequence, and is arranged to receive a first analog voltage signal output by the first voltage dividing output terminal 102 corresponding to a first gradation value of the 32+32j stage; with respect to one basic cell, a fourth transistor 604 is further connected between the 11th transistor 611 of the 14th branch and the 5th transistor 605 of the 15th branch; with respect to two adjacent basic cells, a fourth transistor 604 is further connected between the 11th transistor 611 of the 16th branch of one of the basic cells and the 13th transistor 613 of the 13th branch of the other basic cell.

[0065] In some embodiments, as shown in FIG. 3c, for one basic cell, the 13th branch through the 16th branch multiplex the 6th transistor 606, the 15th transistor 615 and the 16th transistor 616, the 13th branch and the 14th branch multiplex the 13th transistor 613, and the 15th branch and the 16th branch multiplex the 5th transistor 605.

[0066] 4 is a schematic diagram of an output sub-circuit according to an embodiment of the present disclosure. Specifically, the structure is an optional implementation based on the first encoding circuit shown in FIG. 3. Here, the output sub-circuits include a first output sub-circuit 701, a second output sub-circuit 702, and a third output sub-circuit 703, and each output sub-circuit 302 has four fourth input terminals 3021, which are respectively arranged to receive the voltage signals outputted by the corresponding first switching sub-circuits, second switching sub-circuits, third switching sub-circuits, and fourth switching sub-circuits, that is, connected to the output terminals A, B, D, and E of each switching sub-circuit.

[0067] The first output sub-circuit 701 and the second output sub-circuit 702 are both arranged to output one second analog voltage signal based on the voltage signal awaiting output, and the third output sub-circuit 703 is arranged to output two identical second analog voltage signals based on the voltage awaiting output.

[0068] In some embodiments, each output subcircuit includes a plurality of switching transistors including a first transistor 601 through an eighth transistor 608 whose control poles are used to receive the opposite 0th bit through the opposite 7th bit, respectively, and a ninth transistor 609 through a sixteenth transistor 616 whose control poles are used to receive the 0th bit through the 7th bit, respectively.

[0069] 4a is a structural conceptual diagram of a first output sub-circuit according to an embodiment of the present disclosure. Connected correspondingly to each switching sub-circuit in the above-mentioned FIGS. 3a-3c, the first output sub-circuit 701 is arranged to control the on-state of itself and one first switching sub-circuit or one second switching sub-circuit according to the fifth, sixth and seventh bits of the Gray code control signal, or control the on-state of itself and one third switching sub-circuit or one fourth switching sub-circuit according to the second and third bits of the Gray code control signal, i.e., turn on the output D or E terminal according to the fifth, sixth and seventh bits of the Gray code control signal, or turn on the output A or B terminal according to the second and third bits of the Gray code control signal.

[0070] As shown in FIG. 4a, the first output sub-circuit 701 is connected to the output ends of the plurality of fourth switching sub-circuits via the third transistor 603 and the twelfth transistor 612, and connected to the output ends of the plurality of fourth switching sub-circuits via the fourth transistor 604 and the eleventh transistor 611; the first output sub-circuit is connected to the third switching sub-circuit via the eleventh transistor 611 and the twelfth transistor+612, and connected to the third switching sub-circuit via the fourth transistor 604 and the third transistor 603; the first output sub-circuit is connected to the output ends of the plurality of first switching sub-circuits via the fourteenth transistor 614, the fifteenth transistor 615, and the sixteenth transistor 616; and the first output sub-circuit is connected to the output ends of the plurality of second switching sub-circuits via the fourteenth transistor 614, the fifteenth transistor 615, and the eighth transistor 608.

[0071] 4b is a structural schematic diagram of a second output sub-circuit according to an embodiment of the present disclosure, where the second output sub-circuit 702 is configured to control turning on itself and one first switching sub-circuit or one second switching sub-circuit according to the 5th, 6th and 7th bits of the Gray code control signal, or to control turning on itself and one third switching sub-circuit or one fourth switching sub-circuit according to the 0th and 1st bits of the Gray code control signal.

[0072] As shown in FIG. 4b, the second output sub-circuit 702 is connected to the output ends of the plurality of fourth switching sub-circuits via the second transistor 602 and the ninth transistor 609 and to the output ends of the plurality of fourth switching sub-circuits via the first transistor 601 and the tenth transistor 610; the second output sub-circuit is connected to the third switching sub-circuit via the ninth transistor 609 and the tenth transistor 610 and to the third switching sub-circuit via the first transistor 601 and the second transistor 602; the second output sub-circuit 702 is connected to the output ends of the plurality of first switching sub-circuits via the fourteenth transistor 614, the fifteenth transistor 615, and the sixteenth transistor 616; and the second output sub-circuit 702 is connected to the output ends of the plurality of second switching sub-circuits via the fourteenth transistor 614, the fifteenth transistor 615, and the eighth transistor 608.

[0073] 4c is a structural schematic diagram of a third output sub-circuit according to an embodiment of the present disclosure, in which the third output sub-circuit 703 is configured to control turning on itself and one first switching sub-circuit or one second switching sub-circuit according to the fifth bit, the sixth bit and the seventh bit of the Gray code control signal, or to control turning on itself and one third switching sub-circuit or one fourth switching sub-circuit according to the first bit of the Gray code control signal.

[0074] As shown in FIG. 4c, the third output sub-circuit 703 is connected to the output terminals of the plurality of fourth switching sub-circuits via the second transistor 602, the third output sub-circuit is connected to the third switching sub-circuit via the tenth transistor 610, the third output sub-circuit is connected to the output terminals of the plurality of first switching sub-circuits via the fourteenth transistor 614, the fifteenth transistor 615, and the sixteenth transistor 616, and the third output sub-circuit is connected to the output terminals of the plurality of second switching sub-circuits via the fourteenth transistor 614, the fifteenth transistor 615, and the eighth transistor 608.

[0075] In some embodiments, the first output control circuit includes an operational amplifier, an input terminal of the first output control circuit is arranged to receive four second analog voltage signals output by the multiple output sub-circuits, and the operational amplifier is arranged to perform weighted summation based on the four second analog voltage signals to generate an analog grayscale voltage signal.

[0076] Specifically, the above-mentioned gamma voltage conversion circuit will be described in detail below in combination with practical application examples. Take a set of first voltage dividing output terminals as an example, the gray scale values ​​corresponding to the set include a first gray scale value and three second gray scale values, the first gray scale value is the 48th gray scale value, and the second gray scale values ​​include the 49th, 50th and 51st gray scale values.When the analog gray scale voltage signal output by the gamma voltage conversion circuit corresponds to the 48th gray scale value, the corresponding gray code is 00100000, the first output circuit outputs an analog voltage corresponding to the 48th gray scale value, the second output circuit outputs an analog voltage corresponding to the 48th gray scale value, and the third output circuit outputs two analog voltages corresponding to the 48th gray scale values, so that the first output control circuit generates and outputs an analog gray scale voltage signal corresponding to the 48th gray scale value, and the gamma voltage conversion circuit outputs When the analog gray scale voltage corresponds to the 49th gray scale value, the corresponding gray code is 00100001, the first output circuit outputs an analog voltage corresponding to the 48th gray scale value, the second output circuit outputs an analog voltage corresponding to the 52nd gray scale value, and the third output circuit outputs two analog voltages corresponding to the 48th gray scale value, so that the first output control circuit generates and outputs an analog gray scale voltage signal corresponding to the 49th gray scale value according to the four analog voltages, and the gamma voltage conversion circuit When the analog gray scale voltage output by the first output circuit corresponds to the gray scale value of the 51st step, the corresponding gray code is 00100010, the first output circuit outputs an analog voltage corresponding to the gray scale value of the 48th step, the second output circuit outputs an analog voltage corresponding to the gray scale value of the 52nd step, and the third output circuit outputs two analog voltages corresponding to the gray scale values ​​of the 52nd step, so that the first output control circuit generates and outputs an analog gray scale voltage signal corresponding to the gray scale value of the 51st step according to the four analog voltages, and the gamma current is When the analog gray scale voltage output by the voltage conversion circuit corresponds to the 50th gray scale value, the corresponding gray code is 00100011, the first output circuit outputs an analog voltage corresponding to the 48th gray scale value, the second output circuit outputs an analog voltage corresponding to the 48th gray scale value, and the third output circuit outputs two analog voltages corresponding to the 52nd gray scale value, so that the first output control circuit generates and outputs an analog gray scale voltage signal corresponding to the 50th gray scale value according to the four analog voltages.

[0077] An embodiment of the present disclosure provides a gamma voltage conversion circuit, which can perform gamma voltage conversion by adopting an encoding circuit based on Gray code, etc., thereby improving response speed, reducing circuit burrs and noise, and making the change in gray scale display luminance smoother when switching between gray scales, thereby solving problems such as display jitter and power supply fluctuation caused by switching between gray scales, and furthermore, the output reaches the target potential more accurately, so that the voltages at the far and near ends of the panel are consistent, thereby making the luminance consistent and making the panel more uniform. In view of this, an embodiment of the present disclosure provides a first encoding circuit of a segment encoding type, which adopts a method of outputting encoding for each gradation for low and high gradations such as the above-mentioned 0th to 31st gradations and 254th to 255th gradations, uses a first switching sub-circuit and a second switching sub-circuit for encoding and output, and uses a third switching sub-circuit and a fourth switching sub-circuit for encoding and output for intermediate gradations, outputs a first gradation value corresponding to the first voltage dividing output terminal of each set of analog voltages, and generates an analog gradation voltage based on the multiple analog voltage using a first output control circuit, thereby realizing the reduction in the area occupied by the gamma voltage conversion circuit to half while ensuring the gradation accuracy output by the gamma voltage conversion circuit.

[0078] Specifically, taking 8-bit digital mode conversion as an example, the conventional switching tree structure digital mode conversion circuit requires 29, i.e., 512 switching transistors to achieve 8-bit digital mode conversion, whereas the present disclosure realizes 8-bit digital mode conversion based on 6-bit digital mode conversion and a 2-bit interpolation operational amplifier, and based on the above-mentioned multiplexed structure of the switching transistor, only 297 switching transistors are installed, thereby reducing the occupied area by half.

[0079] 5 is a structural conceptual diagram of another Gamma voltage conversion circuit according to an embodiment of the present disclosure. Specifically, the structure is an alternative embodiment based on the Gamma voltage conversion circuit shown in FIG. 1. Wherein, the circuit further includes:

[0080] The second voltage dividing circuit 10 has a plurality of sixth input terminals 103 and a plurality of second voltage dividing output terminals 104, one sixth input terminal 103 is arranged to receive a second gamma voltage signal inputted by one second gamma channel, the second voltage dividing circuit is arranged to generate a multiplexed third analog voltage signal based on the second gamma voltage signal, and one second voltage dividing output terminal 104 is arranged to output one third analog voltage signal.

[0081] The second encoding circuit 30 is used for generating and outputting a multiplexed fourth analog voltage signal according to one of the Gray code control signal and the multiplexed third analog voltage signal.

[0082] The second output control circuit 40 is used for generating and outputting an analog gray scale voltage signal according to the multiplexed fourth analog voltage signal.

[0083] In some embodiments, in the circuit, the first encoding circuit 3 and the second encoding circuit 30 each include a plurality of switching transistors, the switching transistor in the first encoding circuit 3 adopts one of P-type transistors and N-type transistors, the switching transistor in the second encoding circuit 30 adopts the other of P-type transistors and N-type transistors, and the control pole signal corresponding to the switching transistor in the first encoding circuit 3 and the control pole signal corresponding to the switching transistor in the second encoding circuit 30 are inverse in each bit. Specifically, the signal adopts a full positive half-voltage format, so that the high voltage and the low voltage are transferred by the P-type transistor and the N-type transistor, respectively.

[0084] In some embodiments, the first encoding circuit 3 and the second encoding circuit 30 are connected to the same Gray code control circuit 2, or the Gray code control circuits 2 corresponding to the first encoding circuit 3 and the second encoding circuit 30 are provided independently.

[0085] An embodiment of the present disclosure further provides a display device including any of the gamma voltage conversion circuits in the above embodiments.

[0086] 6 is a flow chart of a gamma voltage conversion method according to an embodiment of the present disclosure. Specifically, the method is applied to any of the gamma voltage conversion circuits in the above embodiments, and as shown in FIG. 6, the method includes the following steps:

[0087] Step S1: generating a multiplexed first analog voltage signal according to a first gamma voltage signal inputted by a first gamma channel.

[0088] Step S2: generating a corresponding gray code control signal based on the gray scale value to be displayed.

[0089] Step S3, generating a multiplexed second analog voltage signal based on one of the Gray code control signal and the multiplexed first analog voltage signal.

[0090] Step S4: generating and outputting an analog gray scale voltage signal based on the multiplexed second analog voltage signal.

[0091] In some embodiments, the step S4 of generating and outputting an analog gray scale voltage signal based on the multiple second analog voltage signals includes performing weighted addition based on the multiple analog voltages to generate an analog gray scale voltage.

[0092] In some embodiments, the method further includes the steps of generating a multiplexed third analog voltage signal based on a second gamma voltage signal input to the second gamma channel, generating a multiplexed fourth analog voltage signal based on one of the Gray code control signal and the multiplexed third analog voltage signal, and generating and outputting an analog grayscale voltage signal based on the multiplexed fourth analog voltage signal.

[0093] 7 is a flow chart of a specific implementation method of step S3 in the embodiment of the present disclosure. Specifically, as shown in FIG. 7, step S3 of generating multiple analog voltages according to a first analog voltage signal and a corresponding Gray code control signal includes the following steps:

[0094] Step S301: control the on / off state of one branch of one of its switching sub-circuits according to a plurality of first preset bits of a Gray code control signal, and generate a voltage signal waiting to be output according to a first analog voltage signal received by the branch in the on state.

[0095] In step S302, turn on its output sub-circuit and the switching sub-circuit according to the second preset bits of the Gray code control signal, and generate and output a second analog voltage signal according to the voltage signal waiting to be output.

[0096] In an embodiment of the present disclosure, a gamma voltage conversion method is provided for a corresponding gamma voltage conversion circuit, which can perform gamma voltage conversion according to a gray code, and the adjacent gray scale switching process corresponding to the gray code brings about a change of at most 2 bits, avoiding switching of multiple bits and the uncertain and intermediate states in the process, improving the response speed, reducing circuit burrs and noise, and making the change in gray scale display luminance during switching of each gray scale smoother, thereby solving problems such as display jitter and power supply fluctuation caused by switching of each gray scale, and furthermore, the output reaches the target potential more accurately, so that the voltages at the far end and near end of the panel are consistent, thereby making the luminance consistent, and the uniformity of the panel is better.

[0097] Those skilled in the art will understand that all or some steps of the methods disclosed above, functional modules / units in the apparatuses can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware embodiments, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components, for example, one physical component may have multiple functions, and one function or step may be performed by multiple physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processor, digital signal processor, or microprocessor, or can be implemented as hardware or as an integrated circuit, such as a dedicated integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and accessed by a computer. Additionally, communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery media, as known to those skilled in the art.

[0098] In the present specification, exemplary embodiments are disclosed and specific terms are used, but they are used and should be interpreted as being generally illustrative only and not for limiting purposes. It is obvious to those skilled in the art that in some embodiments, unless expressly indicated otherwise, the features, characteristics, and / or elements described in combination with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in combination with other embodiments. Thus, those skilled in the art will appreciate that various modifications in form and detail are possible without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. It has a plurality of first input terminals and a plurality of first voltage-dividing output terminals. One of the first input terminals is arranged to receive a first gamma voltage signal input by one first gamma channel. The first voltage-dividing circuit is arranged to generate a multiplexed first analog voltage signal based on the first gamma voltage signal. One of the first voltage-dividing output terminals is arranged to output one of the first analog voltage signals, and the first voltage-dividing circuit; A Gray code control circuit used to generate and output a corresponding Gray code control signal based on the tone value waiting for display; A first encoding circuit used to generate and output a multiplexed second analog voltage signal based on one of the Gray code control signal and the multiplexed first analog voltage signal; A first output control circuit used to generate and output an analog tone voltage signal based on the multiplexed second analog voltage signal, and includes A gamma voltage conversion circuit.

2. The first voltage-dividing circuit includes a plurality of resistors connected in series. The connection node between any two resistors connected in series is a series connection node, and one of the series connection nodes corresponds to one of the first voltage-dividing output terminals. The gamma voltage conversion circuit according to Claim 1.

3. The Gray code control signal includes a first Gray code signal and a second Gray code signal. Each bit of the first Gray code signal and the second Gray code signal is inverted. Specifically, the first encoding circuit is used to generate and output the multiplexed second analog voltage signal based on any one of the first Gray code signal, the second Gray code signal, and the multiplexed first analog voltage signal. The gamma voltage conversion circuit according to Claim 1.

4. The first encoding circuit includes a plurality of switching sub-circuits and a plurality of output sub-circuits. Each of the switching sub - circuits includes a plurality of branches. Each branch has one second input terminal and a plurality of third input terminals. One of the second input terminals is arranged to receive one of the first analog voltage signals output by one of the first voltage - dividing output terminals. One of the third input terminals is arranged to receive one of the first preset bits of the Gray - code control signal. Each branch is arranged to control its own on - off state based on the plurality of the first preset bits of the Gray - code control signal. When in the on - state, it is arranged to generate a voltage signal waiting for output based on the received first analog voltage signal. Each of the output sub - circuits has a plurality of fourth input terminals and a plurality of fifth input terminals. One of the fourth input terminals is arranged to receive the voltage signal waiting for output output by one of the switching sub - circuits. One of the fifth input terminals is arranged to receive one of the second preset bits of the Gray - code control signal. Each of the output sub - circuits is arranged to control the on - state of itself and one of the switching sub - circuits based on the plurality of the second preset bits of the Gray - code control signal, and is arranged to generate and output the second analog voltage signal based on the received voltage signal waiting for output. The gamma voltage conversion circuit according to claim 1.

5. The first analog voltage signal and the first voltage - dividing output terminal correspond one - to - one with the gradation values. The second analog gradation voltage corresponds one - to - one with the gradation values, and has a total of 2m gradation values, where m is a positive integer. The plurality of switching sub - circuits include a plurality of first switching sub - circuits and a plurality of second switching sub - circuits. Each of the first switching sub - circuits includes 2n branches. Each of the second switching sub - circuits includes 2n branches, where n is a positive integer. They are arranged in ascending order along the corresponding gradation values, and every n adjacent ones of the first voltage-dividing output terminals form a set. For N sets of the first voltage-dividing output terminals whose corresponding gradation values are less than or equal to a preset first threshold value, every two adjacent ones of the first voltage-dividing output terminals are connected to each second input terminal in one of the first switching sub-circuits. N is a positive integer. For M sets of the first voltage-dividing output terminals whose corresponding gradation values are greater than or equal to a preset second threshold value, every two adjacent ones of the first voltage-dividing output terminals are connected to each second input terminal of one of the second switching sub-circuits. The second threshold value is greater than the first threshold value, and M is a positive integer. The gamma voltage conversion circuit according to claim 4.

6. The plurality of switching sub-circuits include a third switching sub-circuit and a plurality of fourth switching sub-circuits. The third switching sub-circuit includes k branches, and each fourth switching sub-circuit includes n branches, where k = (2m - N*n - M*n) / n, and k is a positive integer. For a plurality of sets of the first voltage-dividing output terminals whose corresponding gradation values are greater than the first threshold value and less than the second threshold value, the gradation value corresponding to each set of the first voltage-dividing output terminals includes the smallest first gradation value and n - 1 second gradation values. The first voltage-dividing output terminals corresponding to every n adjacent first gradation values are sequentially and alternately connected to the n second input terminals of the third switching sub-circuit and each second input terminal of one of the fourth switching sub-circuits. The gamma voltage conversion circuit according to claim 5.

7. m = 8, n = 4. The corresponding gradation values are arranged in ascending order and include from stage 0 to stage 255. The gray code control signal includes bits from bit 0 to bit 7 in ascending order from the lower bit to the upper bit. The first threshold value is equal to the gradation value of stage 31, and the second threshold value is equal to the gradation value of stage 224. The gamma voltage conversion circuit according to claim 6.

8. The first preset bits corresponding to the first switching sub-circuit and the second switching sub-circuit both include bits from bit 0 to bit 4. The first preset bit corresponding to the third switching sub-circuit includes bits from bit 2 to bit 7. The first preset bit corresponding to the fourth switching sub-circuit includes bits from bit 3 to bit 7. The gamma voltage conversion circuit according to claim 7.

9. The first encoding circuit has a plurality of switching transistors. The switching transistors include the first transistor to the eighth transistor, and their control electrodes are respectively used to receive the opposite 0th bit to the opposite 7th bit. The control electrodes of the ninth transistor to the sixteenth transistor are respectively used to receive the 0th bit to the 7th bit. Each of the one first switching sub-circuit and the one second switching sub-circuit includes a first branch to an eighth branch. The first branch includes a first transistor, a second transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage-dividing output terminal corresponding to the gradation value of the 5 + 8i-th step. The second branch includes a ninth transistor, a second transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage-dividing output terminal corresponding to the gradation value of the 4 + 8i-th step. The third branch includes a first transistor, a tenth transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage-dividing output terminal corresponding to the gradation value of the 6 + 8i-th step. The fourth branch includes a ninth transistor, a tenth transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage-dividing output terminal corresponding to the gradation value of the 7 + 8i-th step. The fifth branch includes a first transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage-dividing output terminal corresponding to the gradation value of the 1 + 8i-th step. The sixth branch includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage-dividing output terminal corresponding to the gradation value of the 0 + 8i-th step. The seventh branch includes a first transistor, a second transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage-dividing output terminal corresponding to the gradation value of the 2 + 8i-th step. The eighth branch includes a ninth transistor, a second transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage-dividing output terminal corresponding to the gradation value of the 3 + 8i-th step. Regarding the first switching sub-circuit, the value of i is any one of 0, 1, 2, 3, and regarding the second switching sub-circuit, the value of i is any one of 28, 29, 30, 31. The gamma voltage conversion circuit according to claim 8.

10. The first to eighth branches multiplex the 12th transistor and the 13th transistor, the first to fourth branches multiplex the 3rd transistor, the fifth to eighth branches multiplex the 11th transistor, the first and second branches multiplex one 2nd transistor, the third and fourth branches multiplex one 10th transistor, the fifth and sixth branches multiplex another 10th transistor, and the seventh and eighth branches multiplex another 2nd transistor. The gamma voltage conversion circuit according to claim 9.

11. One of the fourth switching sub-circuits includes the ninth to twelfth branches. The ninth branch includes the fourth transistor, the 13th transistor, the 6th transistor, the 15th transistor, and the 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to the first gradation value of the 60 + 32j stage. The tenth branch includes the 12th transistor, the 13th transistor, the 6th transistor, the 15th transistor, and the 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to the first gradation value of the 52 + 32j stage. The eleventh branch includes the fourth transistor, the fifth transistor, the 6th transistor, the 15th transistor, and the 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to the first gradation value of the 44 + 32j stage. The twelfth branch includes the 12th transistor, the fifth transistor, the 6th transistor, the 15th transistor, and the 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to the first gradation value of the 36 + 32j stage. The value of j is any one of 0, 1, 2, 3, 4, 5. The third switching sub-circuit includes a plurality of basic cells. One of the basic cells includes a 13th branch to a 16th branch. The 13th branch includes a third transistor, a 13th transistor, a sixth transistor, a 15th transistor, and a 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage division output terminal corresponding to the first gradation value of the 56 + 32j stage. The 14th branch includes an 11th transistor, a 12th transistor, a 13th transistor, a sixth transistor, a 15th transistor, and a 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage division output terminal corresponding to the first gradation value of the 48 + 32j stage. The 15th branch includes a third transistor, a fifth transistor, a sixth transistor, a 15th transistor, and a 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage division output terminal corresponding to the first gradation value of the 40 + 32j stage. The 16th branch includes an 11th transistor, a 12th transistor, a fifth transistor, a sixth transistor, a 15th transistor, and a 16th transistor connected in sequence, and is arranged to receive the first analog voltage signal output from the first voltage division output terminal corresponding to the first gradation value of the 32 + 32j stage. For one of the basic cells, one fourth transistor is further connected between the 11th transistor of the 14th branch and the fifth transistor of the 15th branch. For two adjacent basic cells, one fourth transistor is further connected between the 11th transistor of the 16th branch of one of the basic cells and the 13th transistor of the 13th branch of the other basic cell. The gamma voltage conversion circuit according to claim 9.

12. The 9th branch to the 12th branch multiplex the sixth transistor, the 15th transistor, and the 16th transistor. The 9th branch and the 10th branch multiplex the 13th transistor. The 11th branch and the 12th branch multiplex the fifth transistor. For one of the basic cells, the 13th branch to the 16th branch multiplex the sixth transistor, the 15th transistor, and the 16th transistor. The 13th branch and the 14th branch multiplex the 13th transistor. The 15th branch and the 16th branch multiplex the fifth transistor. The gamma voltage conversion circuit according to claim 11.

13. The plurality of output sub - circuits include a first output sub - circuit, a second output sub - circuit, and a third output sub - circuit. Each of the output sub - circuits has four of the fourth input terminals, and is arranged to receive the voltage signals waiting to be output by the corresponding plurality of first switching sub - circuits, the plurality of second switching sub - circuits, the third switching sub - circuit, and the plurality of fourth switching sub - circuits respectively. Both the first output sub - circuit and the second output sub - circuit are arranged to output one of the second analog voltage signals based on the voltage signals waiting to be output. The third output sub - circuit is arranged to output the same two second analog voltage signals based on the voltage waiting to be output. The gamma voltage conversion circuit according to claim 7.

14. The first output sub - circuit is arranged to control the turning - on of itself and one of the first switching sub - circuits or one of the second switching sub - circuits based on the fifth, sixth, and seventh bits of the Gray - code control signal, or to control the turning - on of itself and the third switching sub - circuit or one of the fourth switching sub - circuits based on the second and third bits of the Gray - code control signal. The second output sub - circuit is arranged to control the turning - on of itself and one of the first switching sub - circuits or one of the second switching sub - circuits based on the fifth, sixth, and seventh bits of the Gray - code control signal, or to control the turning - on of itself and the third switching sub - circuit or one of the fourth switching sub - circuits based on the zero - th and first bits of the Gray - code control signal. The third output sub - circuit is arranged to control the turning - on of itself and one of the first switching sub - circuits or one of the second switching sub - circuits based on the fifth, sixth, and seventh bits of the Gray - code control signal, or to control the turning - on of itself and the third switching sub - circuit or one of the fourth switching sub - circuits based on the first bit of the Gray - code control signal. The gamma voltage conversion circuit according to claim 13.

15. Each of the output sub - circuits has a plurality of switching transistors. The switching transistors include the first transistor to the eighth transistor, and their control electrodes are respectively used to receive the opposite 0 - th bit to the opposite 7 - th bit. The control electrodes of the ninth transistor to the sixteenth transistor are respectively used to receive the 0 - th bit to the 7 - th bit. The first output sub - circuit is connected to the output ends of the plurality of fourth switching sub - circuits via the third transistor and the twelfth transistor, and is connected to the output ends of the plurality of fourth switching sub - circuits via the fourth transistor and the eleventh transistor. The first output sub - circuit is connected to the third switching sub - circuit via the eleventh transistor and the twelfth transistor, and is connected to the third switching sub - circuit via the fourth transistor and the third transistor. The first output sub - circuit is connected to the output ends of the plurality of first switching sub - circuits via the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor. The first output sub - circuit is connected to the output ends of the plurality of second switching sub - circuits via the fourteenth transistor, the fifteenth transistor, and the eighth transistor. The second output sub - circuit is connected to the output ends of the plurality of fourth switching sub - circuits via the second transistor and the ninth transistor, and is connected to the output ends of the plurality of fourth switching sub - circuits via the first transistor and the tenth transistor. The second output sub - circuit is connected to the third switching sub - circuit via the ninth transistor and the tenth transistor, and is connected to the third switching sub - circuit via the first transistor and the second transistor. The second output sub - circuit is connected to the output ends of the plurality of first switching sub - circuits via the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor. The second output sub - circuit is connected to the output ends of the plurality of second switching sub - circuits via the fourteenth transistor, the fifteenth transistor, and the eighth transistor. The third output sub-circuit is connected to the output ends of the plurality of fourth switching sub-circuits via a second transistor, the third output sub-circuit is connected to the third switching sub-circuit via a tenth transistor, the third output sub-circuit is connected to the output ends of the plurality of first switching sub-circuits via a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, and the third output sub-circuit is connected to the output ends of the plurality of second switching sub-circuits via a fourteenth transistor, a fifteenth transistor, and an eighth transistor. The gamma voltage conversion circuit according to claim 14.

16. The first output control circuit includes an operational amplifier. The input end of the first output control circuit is arranged to receive the four second analog voltage signals output by the plurality of output sub-circuits. The operational amplifier is arranged to perform weighted addition based on the four second analog voltage signals to generate the analog gradation voltage signal. The gamma voltage conversion circuit according to claim 13.

17. It has a plurality of sixth input ends and a plurality of second voltage division output ends. One of the sixth input ends is arranged to receive the second gamma voltage signal input by one second gamma channel. The second voltage division circuit is arranged to generate a multiplexed third analog voltage signal based on the second gamma voltage signal. One of the second voltage division output ends is arranged to output one of the third analog voltage signals, the second voltage division circuit; A second encoding circuit used to generate and output a multiplexed fourth analog voltage signal based on one of the Gray code control signal and the plurality of third analog voltage signals; And a second output control circuit used to generate and output an analog gradation voltage signal based on the multiplexed fourth analog voltage signal. The gamma voltage conversion circuit according to any one of claims 1 to 16.

18. Both the first encoding circuit and the second encoding circuit include a plurality of switching transistors. The switching transistor in the first encoding circuit employs one of a P-type transistor and an N-type transistor, and the switching transistor in the second encoding circuit employs the other of the P-type transistor and the N-type transistor. The control electrode signal corresponding to the switching transistor in the first encoding circuit and the control electrode signal corresponding to the switching transistor in the second encoding circuit further include that each bit is reversed. The gamma voltage conversion circuit according to claim 17.

19. Including a gamma voltage conversion circuit employing the gamma voltage conversion circuit according to any one of claims 1 to 16 Display device.

20. A gamma voltage conversion method applied to the gamma voltage conversion circuit according to any one of claims 1 to 16, comprising: generating a multiplexed first analog voltage signal based on a first gamma voltage signal input by a first gamma channel; generating a corresponding Gray code control signal based on a tone value waiting for display; generating a multiplexed second analog voltage signal based on one of the Gray code control signal and the multiplexed first analog voltage signal; generating and outputting an analog tone voltage signal based on the multiplexed second analog voltage signal. Gamma voltage conversion method.

21. The step of generating a multiplexed second analog voltage signal based on one of the Gray code control signal and the multiplexed first analog voltage signal includes: controlling the on / off state of one branch of one switching sub-circuit of itself based on a plurality of first preset bits of the Gray code control signal, and generating a voltage signal waiting for output based on the first analog voltage signal received by the branch in the on state; turning on its output sub-circuit and the switching sub-circuit based on a plurality of second preset bits of the Gray code control signal, and generating and outputting the second analog voltage signal based on the voltage signal waiting for output. The gamma voltage conversion method according to claim 20.

22. The step of generating and outputting an analog tone voltage signal based on the multiplexed second analog voltage signal includes: performing weighted addition based on the multiplexed second analog voltage signal to generate the analog gradation voltage signal The gamma voltage conversion method according to claim 20.

23. generating a multiplexed third analog voltage signal based on a second gamma voltage signal input by a second gamma channel; generating a multiplexed fourth analog voltage signal based on one of the gray code control signal and the multiplexed third analog voltage signal; generating and outputting an analog gradation voltage signal based on the multiplexed fourth analog voltage signal The gamma voltage conversion method according to claim 20.

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