Address translation circuit and method for performing address translation

Abstract

An address translation circuit and method for performing address translation. The address translation circuit performs an address translation between a first address and a second address by performing a predetermined maximum number of sequential lookups in response to receiving a first address. The address translation circuit is configured to support a normal page table including 2N entries and a big page table including 2N*M entries. The address translation circuit is configured to perform intermediate lookups to retrieve information indicative of a sequentially next lookup address and page table size information, and if the page table size information indicates that the sequentially next lookup corresponds to one of the big page tables, suppress a subsequent lookup if performing the sequentially next lookup exceeds the predetermined maximum number of sequential lookups, and generate a second address based on the information indicative of the sequentially next lookup address.

Description

[Technical field]

[0001] The present invention relates to an address translation circuit and method for performing address translation.

[0002] The address translation circuitry is used to translate from a first address to a second address using a predetermined number of sequential lookups in multiple page table levels, where performing each of the predetermined number of lookups can take time and introduce latency into the address translation.

[0003] In some configurations, an address translation circuit is provided that, in response to receiving a first address, performs an address translation between the first address and the second address by performing a predetermined maximum number of sequential lookups in a plurality of page table levels; The address translation circuit is 2 N A normal page table level containing 2 entries, N*M a large page table level containing entries, each sequential lookup in the normal page table level being considered to be a single-level lookup of a predetermined maximum number of sequential lookups, and each sequential lookup in the large page table level being considered to be an M-level lookup of a predetermined maximum number of sequential lookups; extracting information indicating a sequentially next lookup address of the sequentially next page table level from a current intermediate page table level of the plurality of page table levels, and page table level size information indicating a size of the sequentially next page table level; When the page table level size information indicates that the sequentially next lookup corresponds to one of the large page table levels and performing the sequentially next lookup would exceed a predetermined maximum number of sequential lookups, the sequentially next lookup address is suppressed based on the information indicating the sequentially next lookup address, and an intermediate lookup is performed to generate a second address.

[0004] In some configurations, in response to receiving the first address, N A normal page table level containing 2 entries, N*M a large page table level including M entries, each sequential lookup in the large page table level being considered as a single lookup of the predetermined maximum number of sequential lookups, and each sequential lookup in the large page table level being considered as M lookups of the predetermined maximum number of sequential lookups; The method is: retrieving information from a current intermediate page table level of the plurality of page table levels indicating a sequentially next lookup address of the sequentially next page table level and page table level size information indicating a size of the sequentially next page table level; When the page table level size information indicates that the sequentially next lookup corresponds to one of the large page table levels and performing the sequentially next lookup would exceed a predetermined maximum number of sequential lookups, performing the intermediate lookup by suppressing a subsequent lookup of the predetermined maximum number of sequential lookups based on information indicating the sequentially next lookup address and generating a second address. [Brief description of the drawings]

[0005] The present technology will now be further described, by way of example only, with reference to embodiments thereof illustrated in the accompanying drawings, in which: [Figure 1] 1A-1D are schematic diagrams illustrating data processing apparatus according to various configurations of the present technology; [Diagram 2] 1A-1D are schematic diagrams illustrating address translation circuits according to various configurations of the present technology; [Diagram 3]1A-1C are schematic diagrams illustrating further details of address translation circuitry in accordance with various configurations of the present technology; [Figure 4] 1A-1D are schematic diagrams illustrating address translation according to various configurations of the present technology; [Diagram 5] 1A-1C are schematic diagrams illustrating address translation using large page tables according to various configurations of the present technology; [Figure 6] 1A-1D are schematic diagrams illustrating address translation according to various configurations of the present technology; [Figure 7] 1A-1D are schematic diagrams illustrating address translation using recursion in accordance with various configurations of the present technology; [Figure 8a] 1A-1D are schematic diagrams illustrating address translation using recursion in accordance with various configurations of the present technology; [Figure 8b] 1A-1D are schematic diagrams illustrating address translation using recursion in accordance with various configurations of the present technology; [Figure 9a] 1A-1C are schematic diagrams illustrating details of address translation using recursion in accordance with various configurations of the present technology; [Figure 9b] 1A-1C are schematic diagrams illustrating details of address translation using recursion in accordance with various configurations of the present technology; [Figure 9c] 1A-1C are schematic diagrams illustrating details of address translation using recursion in accordance with various configurations of the present technology; [Figure 10a] 1A-1D are schematic diagrams illustrating address translation according to various configurations of the present technology; [Figure 10b] 1A-1D are schematic diagrams illustrating address translation according to various configurations of the present technology; [Figure 10c] 1A-1D are schematic diagrams illustrating address translation according to various configurations of the present technology; [Figure 10d] 1A-1D are schematic diagrams illustrating address translation according to various configurations of the present technology; [Figure 11] 1A-1D are schematic diagrams illustrating address translation using recursion in accordance with various configurations of the present technology; [Figure 12] 1A-1C are schematic diagrams illustrating the use of a page walker cache in address translation according to various configurations of the present technology; [Figure 13]1A-1D are schematic diagrams illustrating address translation according to various configurations of the present technology; [Figure 14] 1A-1D are schematic diagrams illustrating address translation according to various configurations of the present technology; [Figure 15a] 1A-1D are schematic diagrams illustrating address translation according to various configurations of the present technology; [Figure 15b] 1A-1D are schematic diagrams illustrating address translation according to various configurations of the present technology; [Figure 16] 1A-1C illustrate generally the sequence of steps performed to perform an intermediate lookup according to various configurations of the present technology; [Figure 17] 1A-1C illustrate generally the sequence of steps performed to perform an intermediate lookup according to various configurations of the present technology;

[0006] According to some configurations, an address translation circuit is provided that, in response to receiving a first address, performs an address translation between a first address and a second address by performing a predetermined maximum number of sequential lookups in a plurality of page table levels. N A normal page table level containing 2 entries, N*MThe address conversion circuit is further configured to support a large page table level including a plurality of sequential lookups, each sequential lookup in the normal page table level being considered as a single-level lookup of the predetermined maximum number of sequential lookups, and each sequential lookup in the large page table level being considered as an M-level lookup of the predetermined maximum number of sequential lookups. The address conversion circuit is further configured to perform an intermediate lookup to retrieve, from a current intermediate page table level of the plurality of page table levels, information indicating a sequentially next lookup address of the sequentially next page table level and page table level size information indicating a size of the sequentially next page table level. The address conversion circuit is further configured to suppress a subsequent lookup of the predetermined maximum number of sequential lookups based on the information indicating the sequentially next lookup address and perform an intermediate lookup to generate a second address when the page table level size information indicates that the sequentially next lookup corresponds to one of the large page table levels and performing the sequentially next lookup exceeds the predetermined maximum number of sequential lookups.

[0007] The address translation circuit performs address translation between the first address and the second address using a predetermined maximum number of sequential lookups. The predetermined number can be set in any manner and in some configurations can be flexibly defined. However, in some configurations, the predetermined number is set in hardware and correlates with a number of bits or subsections of bits in the first address. Each lookup of the predetermined number of lookups is performed using some indexing bits of the first address and information obtained from a sequentially preceding lookup. The predetermined number of lookups is divided into intermediate lookups that generate intermediate addresses used in the sequentially next lookups and a final lookup that is used to generate the second address. Each of the multiple page tables includes a set number of entries that are indexed by one of the indexing parts of the first address. The sequential lookups form a page table walk. The predetermined number of lookups results in a certain latency in the page table walk that depends on the number of lookups that need to be performed. The inventors of the present technique recognized that the number of lookups performed can be reduced through the definition of a normal page table and a large page table. Each regular page table has 2 pages, where N is a positive (non-zero) integer. N Each large page table contains 2 entries, where M is a positive integer greater than 1. N*M The regular page table includes M entries (2 to the power of N*M). The address translation circuit is configured to consider each lookup in the regular page table as a single lookup of a predetermined number of lookups (i.e., count or otherwise treat each lookup in the regular page table as a single lookup) and consider each lookup in the big page table as M lookups. Thus, it is possible to perform a single lookup in the big page table that is equivalent to M lookups in the regular page table, resulting in a reduced number of lookups being performed.

[0008] The address conversion circuit is configured to determine whether the next sequential lookup corresponds to the big page table based on the size information in the current intermediate page table when performing the intermediate lookup. If the size information indicates that the next sequential lookup is a lookup in the big page table, the address conversion circuit can determine that the next entry will be equivalent to M lookups, and can therefore perform the next lookup using an appropriate number of bits (corresponding to an appropriate number of indexing portions) of the first address. The address conversion circuit is further configured to suppress subsequent lookups of a predetermined maximum number of sequential lookups when the size information indicates that the next sequential lookup corresponds to one of the big tables, and when performing the next lookup exceeds the predetermined number of sequential lookups. In particular, if the predetermined number of lookups is equal to an integer K and the current number of lookups is J, the size information indicates that the next lookup is in the big page table, and when J+M>K, the remaining KJ lookups of the predetermined number of lookups are suppressed. In this situation, the address translation circuitry does not perform a final lookup, but instead uses information indicating the sequentially next lookup address obtained from the current intermediate page table level to generate information from the second address and the first address. In such configurations, the second address is generated directly from the next lookup address. In some such configurations, the upper portion of the next lookup address forms the upper portion of the second address, and the remaining lower portion of the second address is generated by offsetting the lower portion of the next lookup address by an amount indicated in the least significant portion of the first address.

[0009] The number of bits used to index the page table can be defined in various ways and in some configurations is different for each lookup in the predetermined number of lookups. However, in some configurations, the first address comprises a series of N-bit indexing portions, and the address conversion circuit is configured to index each sequential lookup in one of the regular page table levels using a single N-bit indexing portion of the series of N-bit indexing portions, and to index each sequential lookup in one of the large page table levels using M sequential N-bit indexing portions of the series of N-bit indexing portions. The series of N-bit indexing portions is also a subsection of the first address, and in some configurations includes information for specifying a final portion of the second address or information for specifying a particular starting address of the first intermediate lookup. Each of the regular page tables comprises two N-bit indexing portions. N It contains a contiguous area of ​​memory containing entries, of size 2 N The page table addresses are aligned to the boundary between the regions of 2 entries, so that each regular page table address is N The address specifies a range of entries, and a particular entry may be indexed using an N-bit indexing portion from the first address. In some configurations, the address specifies the last N+D (where 2 D where D corresponds to the size of the page table entry in bytes) are zero, and the address of a particular entry is generated by replacing the last N+D bits of the regular page table base address with an N+D bit indexing portion generated using the N-bit indexing portion from the first address with D trailing zeros appended as the least significant portion. Similarly, each of the large page tables has 2 N*M It contains a contiguous area of ​​memory (of size 2 N entries), size 2 N*M The page table addresses are aligned to the boundary between the two entry regions, so that each large page table address is N*MThe regular page table address specifies a range of entries, and a particular entry may be indexed using M sequential N-bit indexing portions from the first address. In some configurations, the last M*N+D bits of the regular page table address are zero, and the address of a particular entry is generated by replacing the last M*N+D bits of the regular page table address with an (M*N+D)-bit indexing portion generated using the N*M-bit indexing portion from the first address with D trailing zeros appended as the least significant portion.

[0010] It is desirable to provide a mechanism for mapping a first address to a lookup address of one of the normal or large page table levels, i.e., such that the memory space in which the normal or large page table level is stored can be accessed via the first address. This can be achieved by performing a recursive lookup in which the next lookup address in sequence corresponds to the address of the current intermediate page table, for one or more of a predetermined maximum number of lookups. However, the inventors have recognized that, when a large page table is present, this mechanism cannot always be used to map the lookup addresses of all page table levels to the first address. For example, it may be desirable to map the lookup address of the first page table level in sequence. When a large page table is not present, the lookup address of the first page table level in sequence can be mapped by repeatedly self-referencing the first page table level in sequence. The first page table level in sequence can then be indexed using the final indexing portion of the first address. However, if the first page table level is a large page table level that is treated as M lookups of the predetermined number of lookups, each lookup in the large page table requires M sequential N-bit portions of the first address. In such a case, there may not always be a sufficient number of bits in the final indexing portion to sequentially index into the first page table level, and a failure occurs. Thus, in some configurations, when the page table level size information indicates that the execution of the sequentially next lookup is within the predetermined maximum number of lookups, and when the sequentially next lookup address corresponds to the address of the current intermediate page table, the intermediate lookup is considered to be a single-level lookup of the predetermined maximum number of sequential lookups, regardless of the current size of the current intermediate page table level.The address conversion circuit is configured to either perform the next sequential intermediate lookup when the execution of the next sequential lookup is within (i.e., does not exceed) the predetermined maximum number of lookups, or perform the final lookup when the execution of the next sequential lookup results in a number of lookups equal to the predetermined maximum number of lookups. In such a situation, when the current lookup is a self-referential (recursive) lookup, i.e., a lookup that results in a next sequential lookup address that is the address of the current intermediate lookup, the current lookup is treated as a single lookup regardless of the size of the current lookup. In other words, if the current lookup is a lookup at the current large page table level and it is determined that the next sequential lookup address is the address of the current large page table level, the current lookup is determined to be a single lookup rather than M lookups associated with a non-self-referential large page table lookup. On the other hand, if the current lookup is a lookup at the current big page table level and it is determined that the sequentially next lookup address is different from the address of the current big page table level, then the current lookup is determined to be M lookups. By treating a self-referencing lookup as a single lookup, it is always possible to index into the page table level resulting from a predetermined number of lookups, and the big page table lookup address can be mapped as the first address.

[0011] In some configurations, the address translation circuitry is configured to, in response to a control bit indicating that the intermediate lookup is to be treated as a single-level lookup, treat the intermediate lookup as a single-level lookup of a predetermined maximum number of sequential lookups, regardless of the current size of the current intermediate page table level. In some configurations, the control bit is provided as a control bit in a preceding page table level read in the previous lookup. Alternatively, in some configurations, the control bit is encoded in the first address. In some alternative configurations, the address translation circuitry includes a storage circuit for storing a lookup table indicating a page table level that is a large page table level, and the address translation circuitry is configured to perform a lookup in the lookup table to determine a value of the control bit based on the address of the current intermediate page. The control bit provides an alternative mechanism that avoids the need for the address translation circuitry to determine whether a page table level is self-referential, which requires a comparison of an address of the current page table level with an address of the next page table level in sequence. Thus, by using a control bit to indicate whether a page table level is self-referential, this comparison can be avoided and a more compact implementation can be provided.

[0012] In some configurations, when the sequentially next lookup address corresponds to an address of the current intermediate page table and the current lookup corresponds to one of the large page table levels, the current lookup is indexed using the current M sequential portions of the series of N-bit indexing portions, and the lowest M-1 sequential N-bit indexing portions of the current M sequential indexing portions are the most significant M-1 sequential N-bit indexing portions of the sequentially next M sequential indexing portions used to index the sequentially next lookup. Since each large lookup requires M sequential portions of the series of N-bit indexing portions, if the lookup in the large page table is a self-referential lookup, a total of two lots of M sequential portions of the series of N-bit indexing portions are required to perform these two lookups (the lookup that was self-referential and the next lookup that must also be a large lookup because the current lookup is self-referential). The inventors have noticed that if the first lookup is treated as a single lookup, the total number of bits required to index a certain number of sequential lookups exceeds the total number of bits available in the first address. Therefore, if the lookup is self-referential, some bits used to index the self-referential lookup are sequentially reused in the next lookup. For example, if M=2, the lookup at the large page table level requires two sequential N-bit indexing parts. In this example, the first address includes three sequential N-bit indexing parts, namely N-bit indexing part 1, N-bit indexing part 2, and N-bit indexing part 3 (N-bit indexing part 1 is the most significant indexing part, followed by N-bit indexing part 2, followed by N-bit indexing part 3). If the lookup is self-referential, the lookup at the large page table level is treated as a single-level lookup.As a result, the least significant portion of the M=2 sequential indexing portions (the M-1 portions where M=2) is reused in the sequentially next lookup. In this case, N-bit indexing portion 2 is used a second time in combination with N-bit indexing portion 3 to index the sequentially next lookup into the large lookup level. Using this mechanism, and by selecting the placement of recursive (self-referencing) entries in the large page table level, an appropriate number of lookups can be performed without having to add an additional N-bit portion to the first address.

[0013] In some implementations, the address translation circuitry needs to access the same set of page table levels as legacy configurations that do not support large page table levels. To support such legacy configurations, in some configurations, the address translation circuitry recognizes a legacy configuration area in one of the large page table levels, and the legacy configuration area identifies a sequentially next lookup address that corresponds to the address of the current intermediate page table level. N entries, with M sequential N-bit indexing parts N The system is further configured to generate a legacy configuration table fault when the system points to the legacy configuration area of ​​the entry. In such a configuration, the large pages corresponding to M of the predetermined maximum number of sequential lookups are each 2 N Contains 2 entries M The regular page table is one of two contiguous regions in the large page table that can be treated as a regular page table by legacy configurations. NThe M bit indexing portions of the first address are reserved as legacy configuration areas, containing entries pointing to the M regions. In this way, legacy configurations can interpret the page table levels as if each of the page table levels were a normal page table level. However, the address translation circuitry can still achieve the benefits of using the large page table level as long as it does not index into the legacy configuration areas. Thus, if the M sequential N-bit indexing portions of the first address cause the address translation circuitry to index into the legacy configuration areas, a fault occurs. The address translation circuitry can recognize the legacy configuration in various ways. In some configurations, additional bits are provided in the page table levels to indicate the legacy areas. In other alternative configurations, the location of the legacy configuration areas in the large table is fixed, and any attempt to index into the fixed regions of the large page table results in a legacy configuration fault.

[0014] In some configurations, the first address specifies a number of indexing portions equal to the predetermined number of lookups and a final portion that is used in combination with the address of the sequentially next page table level to generate the second address. If the intermediate lookup is a lookup in a large page table containing M entries and the size information indicates that performing the sequentially next lookup would exceed the predetermined maximum number of lookups by one, there are still M-1 (M minus 1) unused indexing portions. Thus, the final portion of the first address is used in combination with the M-1 unused indexing portions and the address of the sequentially next page table level to form the second address. In some configurations, the address translation circuit is configured to output an invalid translation fault when the page table level size information indicates that performing the sequentially next lookup would exceed the predetermined maximum number of sequential lookups by an amount greater than one. This is because if performing the sequentially next lookup would result in the predetermined number of lookups being exceeded by an amount greater than one, there is insufficient information in the first address to generate the second address. Thus, an invalid translation fault is output.

[0015] In some configurations, the address translation circuit further comprises a storage circuit for storing information indicating a sequentially first page table level address corresponding to a first intermediate lookup of the predetermined maximum number of sequential lookups and first size information indicating a size of the first page table level. In some configurations, the storage circuit is a specific memory location. In other configurations, the storage circuit is one or more registers used to store the sequentially first page table level addresses. The one or more registers also store the size information such that the sequentially first intermediate lookup can be set to correspond to one of the large page tables.

[0016] In some configurations, the storage circuit stores information indicative of a plurality of page table level addresses, and the address conversion circuit is configured to sequentially select a first page table level address from the plurality of page table level addresses based on one or more selection bits of the first address. In some configurations, the one or more selection bits are a single bit used to select between two first page table level addresses. In other configurations, the selection bits include a plurality of bits that enable a plurality of first page table level addresses to be selected. In some configurations, the address conversion circuit is configured to recognize the one or more selection bits as one or more most significant bits of the first address. In other configurations, the address conversion circuit is configured to recognize the one or more selection bits as information encoded in a plurality of control bits of the first address. In some configurations, each of the first page table level addresses stored in the storage circuit includes its own size information such that for each of the first page table level addresses, it is possible to uniquely define whether that first page table level is a large page table level or a normal page table level. In another configuration, a single set of size information is provided that is used to determine whether all of the first page table level addresses are big page table level addresses or small page table level addresses.

[0017] In some configurations, the address translation circuitry is configured to sequentially select a first page table level address from the plurality of page table level addresses further based on a current privilege level, the privilege level being a privilege level of a processing circuit providing the first address for translation by the address translation circuitry. In this manner, different first page table level addresses can be provided for higher and lower privilege levels. Using this technique, it is possible to maintain separation between page table levels accessed by processors operating at higher and lower privilege levels.

[0018] In some configurations, the address translation circuit further comprises a partial translation storage circuit that associates intermediate lookup information retrieved during the intermediate lookup with a corresponding subset of bits of the first address already used in the address translation, the intermediate lookup information further comprising information indicative of a sequentially next lookup address and information indicative of a size of the sequentially next page table level. The partial translation storage circuit allows the first subset to be skipped in the sequence of a predetermined maximum number of sequential lookups, the first subset of the sequence of the predetermined maximum number of sequential lookups having been performed sufficiently recently that the translation has already been stored in the partial translation cache. Each translation is defined entirely based on the bits provided in the first address. In some configurations, the first address comprises a series of indexing portions associated with sequential lookup levels of the predetermined maximum number of sequential lookups. The partial transform storage circuit is configured to store information indicative of each of these transforms, so that if a subsequent first address includes some indexing portions that are the same as corresponding indexing portions of the conflicting transforms, the results of these transforms can be determined from lookups in the partial transform storage circuit rather than repeating these lookups.

[0019] In some configurations, the address translation circuit is further configured to perform a partial translation lookup in the partial translation storage circuit based on the first address, and when the partial translation lookup hits in the partial translation storage circuit, retrieve information indicative of the sequentially next lookup address and information indicative of the size of the sequentially next page table level from the partial translation storage circuit, and suppress lookups associated with corresponding subsets of bits of the first address already used in the address translation. As an example, when a first address including four indexing portions is translated, information indicative of each of the lookups is stored in the partial translation storage circuit. If a subsequent lookup shares all four indexing portions, all four lookups can be skipped, and a second address can be determined based on the lookups in the partial translation storage circuit. However, if a subsequent lookup shares only the two most significant indexing portions with the first address, the lookups associated with the two most significant indexing portions can be skipped, and the required information can be extracted from the partial address translation storage circuit. To support lookups corresponding to the large page table and the normal page table, the partial translation storage circuit is configured to store size information indicating the size of the next page table level in sequence. Thus, the partial address translation storage circuit can provide an additional way in which the total number of lookups required can be reduced. When used in combination with the large page table level, the total number of lookups can be further reduced.

[0020] The first address and the second address may be defined within the same address space. However, in some configurations, the first address is defined in a first address space and the second address is defined in a second address space. In such configurations, the second address space is a different address space than the first address space. In some configurations, each of the first address space and the second address space is one of a virtual address space, an intermediate physical address space, and a physical address space. In this manner, the address translation circuitry may be configured to support a virtualization system in which a virtual address is translated to an intermediate physical address and then to a physical address.

[0021] In some configurations, M is one of a fixed value and the size information is a single bit, and the value of M is variable and indicated by the size information. In some configurations where M is fixed, the value of M is defined as a center value stored in a register. In other configurations where M is fixed, the value of M is set by hardware and cannot be changed. In some configurations, M is equal to 2. Such a configuration results in a simpler implementation. In an alternative configuration where the value of M is variable, the value of M is defined by the size information. For example, the size information may include 2 bits allowing for four values. The four values ​​may be used to indicate whether the next lookup in sequence corresponds to a normal lookup or to a large lookup of size M=2, M=3, or M=4. This configuration may provide a particularly flexible arrangement of page table levels.

[0022] A specific example will now be described with reference to the figures.

[0023] 1 shows a schematic diagram of an example of a data processing apparatus 2 utilizing address translation circuitry according to various configurations of the present technology. The data processing apparatus 2 includes a number of stages including a fetch stage 6, a decode stage 10, a rename stage 12, an issue stage 16, an execute stage 18, and a writeback stage 20. Instructions move from stage to stage through a pipeline, with some instructions being in one stage of the pipeline and other instructions pending in another stage. It will be appreciated that this is merely an example of a possible pipeline configuration, and other examples may have different stages or combinations of stages as desired.

[0024] The fetch stage 6 fetches instructions, for example from an instruction cache. A branch predictor 4 may be provided to predict the outcome of branch instructions. The fetched instructions are passed to a decode stage 10, which decodes the instructions to generate decoded instructions that may provide control signals to trigger an execution stage 18 to perform corresponding processing operations. For some instructions fetched by the fetch stage 6, the decode stage 10 may map the instruction to two or more decoded instructions, such that the "instruction" seen by later stages of the pipeline may be in a different form than the instruction fetched from the cache 8. The decoded instructions are passed to a register renaming stage 12 for mapping architectural register specifiers specified by the instruction to physical register specifiers that identify corresponding physical registers 14 to be accessed in response to the instruction. The issue stage 16 queues instructions awaiting issue for execution. The execution stage 18 executes the instructions issued by the issue stage 16 and, in response to the instructions, performs various data processing operations such as arithmetic or logical operations or load / store operations to a data cache 30 or a further level cache 32 or a memory 34. The execution units 18 may have several execution units 22, 24, 21, 25 including a load store unit 26 for queuing any pending load / store operations. The execution units may be capable of speculative execution of one or more instructions and a speculation control unit 35 may be provided to track the execution of speculatively executed instructions. The writeback stage 20 writes the results of instructions executed by the execution stage 18 to the physical register file 14, which includes a predicate register 44 and a condition status register 42.

[0025] The pipeline also includes an address translation circuit 40 for performing a translation between a first address and a second address. The address translation circuit 40 performs a translation of a first address received from the load / store unit 26 and the fetch stage 6 and returns a second address to the load / store unit 26 or the fetch stage 6 from which the first address was received. The address translation circuit 40 performs the address translation by performing a predetermined maximum number of sequential lookups in a page table level stored in the L2 cache 32 or memory 34.

[0026] 2 illustrates in schematic detail an address translation circuit 40 in some exemplary configurations. The address translation circuit receives a first address 42, performs a translation, and outputs a second address 44. The address translation circuit 40 performs the translation by performing a predetermined maximum number of sequential lookups in a number of page tables. The page tables may be divided into two parts. N A normal page table level 48 containing 2 entries, N*Mand a large page table level containing entries. Each lookup in one of the regular page table levels 48 is considered to be (i.e., counted as) a single lookup of the predetermined maximum number of sequential lookups. Each lookup in one of the large page table levels 46 is considered to be M lookups of the predetermined maximum number of sequential lookups. Each lookup of the predetermined maximum number of lookups uses information from a preceding lookup and information from the first address. The predetermined maximum number of lookups includes an intermediate lookup that generates an address of a sequentially next lookup in a sequentially next page table level and page table level size information indicating the size of the sequentially next page table level. If during the intermediate lookup it is determined that the sequentially next lookup of the predetermined maximum number of lookups corresponds to the large lookup and performing the sequentially next lookup would exceed the predetermined maximum number of sequential lookups, then the subsequent lookup is suppressed and a second address 44 is output based on the sequentially next lookup address determined from the current intermediate lookup and information from the first address 42.

[0027] The address conversion circuit 40 outputs a second address generated from the final lookup in sequence in the series of lookups. As explained, this may be the output address obtained from an intermediate lookup (if it is determined that performing the next lookup in sequence would exceed a predetermined maximum number of lookups), or otherwise the output address obtained from the final lookup. Unlike the address from the preceding lookup that points to a page table (large or normal) in memory, the output address is directly used to obtain the second address such that the number of bits of the second address is the same as the number of bits of the output address. In particular, the output address includes some bits, e.g., a 32-bit output address used in a 32-bit address space (it is readily apparent to those skilled in the art that other address space sizes, e.g., a 64-bit address space, can also be used). At this stage, the output address indicates a region of the address space and does not indicate a specific second address. The specific second address output by the address conversion circuit 40 is generated by offsetting the output address by the number of least significant bits from the first address. This is accomplished by taking the most significant portion of the output address and appending the least significant bit of the first address to the most significant portion of the output address. For example, if the second address is a 32-bit address and the output address denotes a normal sized region of memory, the second address is generated by taking the most significant 20 bits of the output address and appending the 12 bits of the first address to the most significant 20 bits. As an alternative, if the second address is a 32-bit address and the output address denotes a large sized region of memory, the second address is generated by taking the most significant 11 bits of the output address and appending the 21 bits of the first address to the most significant 11 bits. Alternatively, the second address can be generated by performing an arithmetic operation that combines the output address and the least significant portion of the first address.

[0028] FIG. 3 illustrates in schematic form further details of the address translation circuit 40 in some exemplary configurations. The address translation circuit includes a partial translation storage circuit 50 that caches information related to previous address translations. The address translation circuit 40 also includes a privileged base register 52 and a non-privileged base register 54. The privileged base register 52 and the non-privileged base register 54 each include an address of a first page table level in a sequential manner and size information indicating a size of the first page table level in a sequential manner. The address translation circuit 40 selects between the privileged base register 52 and the non-privileged base register 54 based on information stored in the selection bits of the first address 42. In this manner, the address translation circuit 40 maintains a distinction between translations associated with addresses provided by processing circuits operating in privileged mode and translations associated with addresses provided by processing circuits operating in non-privileged mode. The address translation circuit 40 is further provided with a fault output indication 56. The fault output indication 56 provides an indication of a fault occurring during operation of the address translation circuit 40. The fault indication 56 is used to indicate address translation faults and privilege level faults.

[0029] 4 shows in schematic form details of the address conversion performed by the address conversion circuit 40 according to various configurations. The address conversion circuit 40 receives a first address. The first address includes 48 bits including a series of indexing portions (bits 47 to 39, bits 38 to 30, bits 29 to 21, and bits 20 to 12). Each indexing portion of the series of indexing portions corresponds to (is used for) a lookup level of the predetermined maximum number of sequential lookups. In the illustrated configuration, the predetermined maximum number of lookups is four, and the first address includes one indexing portion for each of the predetermined maximum number of lookups.

[0030] Bits 47 through 39 of the first address are L0 indexing bits, which are used to index into the page table level accessed during the L0 lookup (the sequentially first intermediate lookup of the predetermined number of lookups). The L0 lookup is performed at the page table level at a page table address (L0 base address) stored in a storage circuit of the address translation circuit. The storage circuit further includes size information indicating that the L0 lookup is a lookup at the normal page table level (next large:0). The lookup performed based on the L0 base address and the L0 indexing bits returns a base address used for the sequentially next lookup, the L1 lookup, and size information indicating that the L1 lookup is a lookup at the normal page table level.

[0031] Bits 38 through 30 of the first address are L1 indexing bits used to index into the page table level accessed during an L1 lookup (the sequentially second intermediate lookup of the predetermined number of lookups). The L1 lookup is performed at the page table level at a base address (L1 base address) obtained during the L0 lookup. The lookup performed based on the L1 base address and the L1 indexing bits returns a base address used for the sequentially next lookup, the L2 lookup, and size information indicating that the L2 lookup is generally a lookup at the page table level.

[0032] Bits 29 through 21 of the first address are L2 indexing bits, which are used to index into the page table level accessed during the L2 lookup (the sequentially third intermediate lookup of the predetermined number of lookups). The L2 lookup is performed at the page table level at a base address (L2 base address) obtained during the L1 lookup. The lookup performed based on the L2 base address and the L2 indexing bits returns a base address used for the sequentially next lookup, the L3 lookup, and size information indicating that the L3 lookup is typically a lookup at the page table level.

[0033] Bits 20 through 12 of the first address are L3 indexing bits used to index into the page table level accessed during the L3 lookup (the final lookup of a predetermined number of lookups). The L3 lookup is performed at the page table level at the base address (L3 base address) obtained during the L2 lookup. The lookup performed based on the L3 base address and the L3 indexing bits returns an address that is combined with the addressing portion of the first address (bits 11 through 0) to obtain the second address.

[0034] FIG. 5 shows in schematic form details of the address conversion performed by the address conversion circuit 40 according to various configurations. As in FIG. 4, the address conversion circuit 40 receives a first address. The first address includes a 48-bit first address including a series of indexing portions (bits 47 to 39, bits 38 to 21, and bits 20 to 12). Each indexing portion of the series of indexing portions corresponds to (is used for) a lookup level of a predetermined maximum number of sequential lookups. In the illustrated configuration, the predetermined maximum number of lookups is four. However, the first address includes only three indexing portions. The second indexing portion (bits 38 to 21) corresponds to a big lookup indexed using M=2 sequential indexing portions (i.e., a combination of bits 38 to 30 and bits 29 to 21). To ensure that the indexing portions of the first address are correctly interpreted by the address conversion circuit, the corresponding page table level stores size information indicating when the next page table level is a big page table level. Note that the size information is indicated in the figure by the "next large" indicator, or "NL" indicator, being set to 1; if the "next large" indicator, or "NL" indicator, is not present in the figure, it implies that the "next large" indicator, or "NL" indicator, is set to 0, indicating that the next page table level is a normal page table level. Comparing to Figure 4, it can be seen that the indexing portions associated with L1 and L2 lookups have been merged.

[0035] Bits 47 through 39 of the first address are L0 indexing bits, which are used to index into the page table level accessed during the L0 lookup (the first intermediate lookup in the sequence of the predetermined number of lookups). The L0 lookup is performed at the page table level at a page table address (L0 base address) stored in a storage circuit of the address translation circuit. The storage circuit further includes size information indicating that the L0 lookup is a lookup at the normal page table level. The lookup performed based on the L0 base address and the L0 indexing bits returns a base address used for the next lookup in the sequence, the merged L1 / L2 lookup, and size information (next large:1) indicating that the L1 / L2 lookup is a lookup at the large page table level.

[0036] Bits 38 through 21 of the first address are L1 / L2 indexing bits, which are used to index into the big page table level accessed during an L1 / L2 lookup (a single lookup in the big page table, the second lookup in sequence equivalent to the L1 and L2 lookups of FIG. 4). The L1 / L2 lookup is performed at the big page table level at the base address (L1 / L2 base address) obtained during the L0 lookup. The lookup performed based on the L1 / L2 base address and the L1 / L2 indexing bits returns the base address used for the next lookup in sequence, the L3 lookup, and size information indicating that the L3 lookup is a lookup at the normal page table level.

[0037] Bits 20 through 12 of the first address are L3 indexing bits used to index into the page table level accessed during the L3 lookup (the final lookup of a predetermined number of lookups). The L3 lookup is performed at the page table level at the base address (L3 base address) obtained during the L1 / L2 lookup. The lookup performed based on the L3 base address and the L3 indexing bits returns an address that is combined with the addressing portion of the first address (bits 11 through 0) to obtain the second address.

[0038] In the illustrated configuration, the L1 and L2 lookups have been combined to form a single lookup in the large page table. It will be readily apparent to one of ordinary skill in the art that any sequential page table level lookups may be combined based on the techniques disclosed herein. Additionally, the illustrated configuration shows that 9 bits are used for each of the N-bit portions. However, alternative configurations may provide a different number of bits and may provide different lookup levels, each using a different number of bits.

[0039] FIG. 6 illustrates a schematic of the definition of a first page table level address based on information stored in the storage circuit 60 of the address conversion circuit 40. A sequential first page table level address (L0 base address) is determined using one or more selection bits from the first address. The address conversion circuit 40 performs a lookup in the storage circuit 60 based on the one or more selection bits. The one or more selection bits define the sequential first page table level address from a plurality of sequential first page table addresses stored in the storage circuit. In the illustrated configuration, the address conversion from the first address to the second address continues as described in connection with FIG. 4.

[0040] FIG. 7 shows the concept of a recursive (self-referencing) lookup. The recursive lookup is used to map a first address to a page table level address. In the illustrated embodiment, the address translation circuit is configured to perform four sequential lookups (the predetermined maximum number of sequential lookups is four). If no large page table exists, a predetermined number of lookups are performed in sequential page table levels L0, L1, L2, and L3 (as described with reference to FIG. 4). When a recursive lookup occurs, the same page table level is referenced twice. As a result, one or more of the page table lookups may be looked up more than once.

[0041] In the top lookup sequence of FIG. 7, the first page table level in sequence defines the address of the first intermediate lookup 70 in sequence. This is the L0 lookup 70 in the (L0) page table. The notation "L0" is used to indicate that the lookup is the L0 level, and the notation "(L0)", i.e., the lookup level in parentheses, is used to indicate that the page table being looked up is the page table from the L0 lookup 70. In the L0 lookup 70, the (L0) page table is indexed using the L0 indexing portion of the first address. In this case, the L0 lookup returns an entry in the (L0) page table level that points to the (L0) page table. Then, an L1 lookup 72 is performed using the L1 indexing portion in the (L0) page table, i.e., the same page table used in the L0 lookup 70. In the L1 lookup 72, the (L0) page table indexed using the L1 indexing portion returns the address of the (L1) page table level, i.e., the page table level that would have been referenced in the L1 lookup 72, but for the self-referential lookup. Thus, an L2 lookup 74 is performed in the (L1) page table using the L2 indexing portion of the first address, which returns the address of the (L2) page table level, i.e., the page table level that would have been referenced in the L2 lookup 74, but for the self-referential lookup. Thus, an L3 lookup 76 is performed in the (L2) page table using the L3 indexing portion of the first address, which returns the address of the (L3) page table. Now that four lookups have been performed, the address of the (L3) page table is output and used to generate the second address.

[0042] In the lookup sequence at the bottom of FIG. 7, the first page table level in sequence defines the address of the first intermediate lookup 78 in sequence. This is the L0 lookup 78 in the (L0) page table. In the L0 lookup 78, the (L0) page table is indexed using the L0 indexing portion of the first address. In this case, the L0 lookup returns an entry in the (L0) page table level that points to the (L0) page table. Then, an L1 lookup 80 is performed using the L1 indexing portion in the (L0) page table, i.e., the same page table used in the L0 lookup 78. In the L1 lookup 80, the (L0) page table indexed using the L1 indexing portion again returns the address of the (L0) page table level, i.e., the page table level that would have been referenced in the L0 lookup 78 if there had been no self-referential lookup. Thus, an L2 lookup 82 is performed in the (L0) page table using the L2 indexing portion of the first address, which returns an address of the (L1) page table level, i.e., the page table level that would have been referenced in L1 lookup 80, but for the self-referential lookup. Thus, an L3 lookup 84 is performed in the (L1) page table using the L3 indexing portion of the first address, which returns an address of the (L2) page table. Now that four lookups have been performed, the address of the (L2) page table is output and used to generate the second address.

[0043] The same technique can be used to generate a second address based on the (L1) page table address using a further self-referential lookup as L2 lookup 82. Moreover, the same technique can be used to generate a second address based on the (L0) page table address using two further self-referential lookups as L2 lookup 82 and L3 lookup 84. In this manner, addresses at each page table level can be mapped using self-referential lookups.

[0044] 8a-8b show a schematic representation of the use of recursion for address translation by the address translation circuit 40 when a large page table is used. FIG. 8a shows a schematic representation of the use of recursion to map addresses in the large page table. Similar to FIGS. 4-7, the address translation circuit 40 is configured to perform a four-level lookup in the page table as a predetermined maximum number of sequential lookups. The first address includes 48 address bits including three 9-bit portions. Bits 47 through 39 define an index used during the L0 level lookup. Bits 38 through 30 define an index used during the L1 level lookup. Bits 29 through 21 define an index used during the L2 level lookup. The least significant 21 bits, bits 20 through 0, are used in combination with the output from the L2 level lookup to form a second address.

[0045] In response to receiving the first address, the address translation circuit sequentially determines a first page table level address, which is determined from additional bits (not shown) of the first address or from a register that sequentially stores the first page table level address. An L0 level lookup is then performed using the first page table level address sequentially to determine a (L0) page table indexed using bits 47 to 39 from the first address. The L0 lookup is a lookup in a normal page table and therefore counts as a single lookup of the predetermined number of lookups. In this case, the entry in the (L0) page table is a self-referential entry that points to the (L0) page table. Thus, an L1 lookup is performed in the (L0) page table using the L1 indexing bits (bits 38 to 30 from the first address). The L1 lookup is a lookup in a normal page table and therefore counts as a single lookup of the predetermined number of lookups. The L1 lookup is also a self-referential entry that points to the (L0) page table. Thus, the L2 lookup is performed in the (L0) page table using the L2 indexing bits (bits 29 to 21 of the first address). The L2 lookup is a lookup in a normal page table and is therefore counted as one lookup of the predetermined number of lookups. Unlike the L0 level lookup and the L1 level lookup, the L2 level lookup is not a self-referential entry. Instead, the L2 level lookup results in an entry that points to the L1 / L2 large page table. The size information determined from the L2 level lookup indicates to the address translation circuit that the next lookup is a large lookup (NL:1, i.e., next large set to 1), which counts as M=2 lookups of the predetermined number of lookups.At this point, the address conversion circuit 40 has performed three lookups (L0 level lookup, L1 level lookup, and L2 level lookup), each of which is considered to be a single-level lookup. Thus, the address conversion circuit has performed three of the four maximum sequential lookups. Since the L2 level lookup indicates that the next level lookup is a large lookup, when the next lookup is performed sequentially, the number of lookups performed is greater than the four maximum sequential lookups. Thus, the address conversion circuit 40 suppresses the remaining lookups of the four maximum sequential lookups, and generates a second address using the base address of the (L1 / L2) large page table (determined during the L2 level lookup) and the least significant 21 bits of the first address for generating the second address, thus providing the address of an entry in the (L1 / L2) large page table.

[0046] FIG. 8b illustrates generally an alternative address translation performed by the address translation circuit 40 in response to receiving a first address. Similar to FIGS. 4-7 and 8a, the address translation circuit 40 is configured to perform a four-level lookup in the page table as a predetermined maximum number of sequential lookups. The first address includes 48 address bits including two 9-bit portions. Bits 47 through 39 define an index used during the L0 level lookup. Bits 38 through 30 define an index used during the L1 level lookup. The first address further includes a single 18-bit portion. Bits 29 through 12 define an index used during the L2 / L3 level lookup. The least significant 12 bits of the first address, bits 11 through 0, are used in combination with the output from the L2 / L3 level lookup to form the second address.

[0047] In response to receiving the first address, the address translation circuit sequentially determines a first page table level address, which is determined from additional bits (not shown) of the first address or from a register that sequentially stores the first page table level address. An L0 level lookup is then performed using the first page table level address sequentially to determine a (L0) page table indexed using bits 47 to 39 from the first address. The L0 lookup is a lookup in a normal page table and therefore counts as a single lookup of the predetermined number of lookups. In this case, the entry in the (L0) page table is a self-referential entry that points to the (L0) page table. Thus, an L1 lookup is performed in the (L0) page table using the L1 indexing bits (bits 38 to 30 from the first address). The L1 lookup is a lookup in a normal page table and therefore counts as a single lookup of the predetermined number of lookups. Unlike the L0 level lookup, the L1 level lookup is not a self-referential entry. Instead, the L1 level lookup results in an entry that points to the (L1 / L2) large page table. The size information determined from the L1 level lookup indicates to the address translation circuit that the next lookup is a large lookup (next large set to NL:1-1) that counts as M=2 lookups out of the predetermined number of lookups. At this point, the address translation circuit 40 has performed two lookups (the L0 level lookup and the L1 level lookup), each of which is considered to be a single-level lookup. Thus, the address translation circuit has performed two of the four maximum sequential lookups. Because the L1 level lookup indicates that the next level lookup is a large lookup, when the sequential next lookup is performed, the number of lookups performed is equal to the four maximum sequential lookups.Thus, the address translation circuit 40 performs the L2 level lookup and the L3 level lookup as a single L2 / L3 level lookup in the (L1 / L2) large page table indexed by the L2 / L3 indexing bits (bits 29 through 12 of the first address). This is the final lookup of the four largest lookups. Thus, the output from the L2 / L3 lookup in the (L1 / L2) page table is used in combination with the least significant 12 bits of the first address to generate a second address used to access an entry in the (L3) page table.

[0048] 9a-9c show schematic diagrams of the use of different N-bit portions of a first address to index different level lookups of an address translation when the current level lookup is a lookup in a big page table. In FIG. 9a, a first address 90 is provided that includes four N-bit portions 90(A), 90(B), 90(C), and 90(D). The first address 90 also has a least significant H-bit portion 90(E) that is used to generate a second address based on the output from the series of level lookups. As in FIGS. 4-8, the predetermined maximum number of sequential lookups is four. The first lookup in sequence is an L0 / L1 lookup in a big page table (M=2). The L0 / L1 lookup in the big page table is indexed using M=2 of the N-bit portions of the first address 90. In this case, the L0 / L1 lookup is indexed using N-bit portion 90(A) and N-bit portion 90(B). In Fig. 9a, based on the L0 / L1 lookup, it is determined that the next level lookup is a lookup in a regular page table. Therefore, the next level lookup is an L2 level lookup that is indexed using a single N-bit portion 90(C) of the first address 90. From the L2 lookup, it is determined that the next lookup in sequence is also a lookup in a regular page table. Therefore, the next level lookup is an L3 level lookup that is indexed using a single N-bit portion 90(D) of the first address 90. The output from the L3 level lookup is combined with the H-bit portion 90(E) of the first address 90 to generate a second address.

[0049] In FIG. 9b, a first address 92 is provided that includes four N-bit portions 92(A), 92(B), 92(C), and 92(D). The first address 92 also has a least significant H-bit portion 92(E) that is used to generate a second address based on the output from a series of level lookups. As in FIG. 4-8, the predetermined maximum number of sequential lookups is four. The first lookup in sequence is an L0 / L1 lookup in a large page table (M=2). The L0 / L1 lookup in the large page table is indexed using M=2 of the N-bit portions of the first address 92. In this case, the L0 / L1 lookup is indexed using N-bit portion 92(A) and N-bit portion 92(B). In FIG. 9b, based on the L0 / L1 lookup, it is determined that the next level lookup is a lookup in a large page table that is different from the large page table referenced in the L0 / L1 lookup. Thus, the next level lookup is an L2 / L3 level lookup in a large page table (M=2) that is indexed using M=2 sequential N-bit portions 92(C) and 92(D) of the first address 92. The output from the L2 / L3 level lookup is combined with the H-bit portion 92(E) of the first address 92 to generate a second address.

[0050] In FIG. 9c, a first address 94 is provided that includes four N-bit portions 94(A), 94(B), 94(C), and 94(D). The first address 94 also has a least significant H-bit portion 94(E) that is used to generate a second address based on the output from a series of level lookups. As in FIGS. 4-8, the predetermined maximum number of sequential lookups is four. The first lookup in sequence is an L0 / L1 lookup in a large page table (M=2). The L0 / L1 lookup in the large page table is indexed using M=2 of the N-bit portions of the first address 94. In this case, the L0 / L1 lookup is indexed using N-bit portion 94(A) and N-bit portion 94(B). In FIG. 9c, based on the L0 / L1 lookup, it is determined that the next level lookup is a lookup in the large page table, and the L0 / L1 lookup is a self-referential lookup that references the (L0 / L1) page table. Since the L0 / L1 lookup is a self-referential lookup, the L0 / L1 lookup is considered to be a single-level lookup. Therefore, the next level lookup is an L1 / L2 level lookup in the (L0 / L1) large page table. The L1 / L2 level lookup is indexed using M=2 of the N-bit portion of the first address 94. The address conversion circuit 40 reuses the least significant M-1=1 of the N-bit portion 94(A), 94(B) used to index the L0 / L1 level lookup as the most significant M-1=1 of the N-bit portion to index the L1 / L2 level lookup in (L0 / L1). Thus, an L1 / L2 lookup is performed using N-bit portion 94(B) and N-bit portion 94(C). Based on the L1 / L2 lookup, it is determined that the next lookup is a lookup in a regular page table. Thus, the next level lookup is an L3 level lookup in the (L2) page table that is indexed using the single N-bit portion 94(D) of the first address 90.The output from the L3 level lookup in the (L2) level page table is combined with the H bit portion 90(E) of the first address 90 to generate a second address in the (L3) level page table.

[0051] 10a-10d show a schematic of an address conversion based on the principle shown in FIG. 9a-9c. In FIG. 10a, a first address is converted to a second address by an address conversion circuit 40. The predetermined maximum number of sequential lookups is 4. The address conversion circuit sequentially determines a first page table level address based on the most significant bit (not shown) of the first address. The first address sequentially points to a large page table (M=2) indexed using M=2 of the N-bit portion of the first address. Thus, the first lookup is an L0 / L1 level lookup in the (L0 / L1) page table indexed by bits 47 to 30 of the first address. The sequentially next page table address output by the L0 / L1 lookup is the address of the (L0 / L1) page table. The size information output from the L0 / L1 level lookup indicates that the next level page table is a large page table (NL set to 1). Therefore, the next lookup is determined to be an L1 / L2 level lookup in the (L0 / L1) page table, which is indexed by using M-1=1 of the N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table as the most significant M-1=1 N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table. In this case, bits 38 through 21 of the first address are used to index the L1 / L2 lookup. The L1 / L2 lookup returns an address of the sequentially next page table, which is different from the (L0 / L1) page table level. The size information returned by the L1 / L2 lookup indicates that the next page table is a normal page table (NL set to 0). Therefore, the next lookup is an L3 lookup in the (L2) page table, which is indexed by the sequentially next N-bit portion of the first address. In this case, the L3 lookup in the (L2) page table is indexed using bits 20 through 12 of the first address.The L3 lookup returns the address of the next page table in sequence, i.e., the (L3) page table. Once a predetermined maximum number of lookups have been performed (one lookup for the L0 / L1 self-referencing level lookup, M=2 lookups for the L1 / L2 level lookups, and one lookup for the L3 level lookup), the L3 page table is combined with the least significant 12 bits (bits 11 through 0) of the first address to generate a second address.

[0052] In FIG. 10b, the first address is translated to a second address by the address translation circuit 40. The predetermined maximum number of sequential lookups is 4. The address translation circuit sequentially determines a first page table level address based on the most significant bit (not shown) of the first address. The first address sequentially points to a large page table (M=2) indexed using M=2 of the N-bit portion of the first address. Thus, the first lookup is an L0 / L1 level lookup in the (L0 / L1) page table indexed by bits 47 to 30 of the first address. The sequentially next page table address output by the L0 / L1 lookup is the address of the (L0 / L1) page table. The size information output from the L0 / L1 level lookup indicates that the next level page table is a large page table (NL set to 1). Therefore, the next lookup is determined to be an L1 / L2 level lookup in the (L0 / L1) page table, which is indexed by using M-1=1 of the N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table as the most significant M-1=1 N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table. In this case, bits 38 to 21 of the first address are used to index the L1 / L2 lookup. The L1 / L2 lookup returns the address of the sequentially next page table, which is different from the (L0 / L1) page table level. The size information returned by the L1 / L2 lookup indicates that the next page table is a large page table (NL is set to 1). Up to now, the address translation circuit has performed three level lookups (one lookup for L0 / L1 self-referencing level lookups and M=2 for L1 / L2 level lookups). Since the next level lookup is in the large page table, performing this lookup would cause the number of lookups to exceed the predetermined maximum number of lookups.Therefore, further lookups are suppressed and the (L2 / L3) level page table address output from the (L0 / L1) page table during the L1 / L2 lookup is used to generate the second address. Since the output page table level is the big page table, the remaining 21 bits of the first address are needed to generate the second address.

[0053] In FIG. 10c, the first address is translated to a second address by the address translation circuit 40. In the address translation of FIG. 10c, the predetermined maximum number of sequential lookups is 5. The address translation circuit sequentially determines a first page table level address based on the most significant bit (not shown) of the first address. The sequential first address points to a large page table (M=2) indexed using M=2 of the N-bit portion of the first address. Thus, the first lookup is an L0 / L1 level lookup in the (L0 / L1) page table indexed from bits 56 to 39 of the first address. The sequential next page table address output by the L0 / L1 lookup is the address of the (L0 / L1) page table. The size information output from the L0 / L1 level lookup indicates that the next level page table is a large page table (NL set to 1). Therefore, the next lookup is determined to be an L1 / L2 level lookup in the (L0 / L1) page table, which is indexed by using M-1=1 of the N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table as the most significant M-1=1 N-bit portion used to index the L1 / L2 level lookup in the (L0 / L1) page table. In this case, bits 47 to 30 of the first address are used to index the L1 / L2 lookup. The L1 / L2 lookup returns the address of the sequentially next page table, which is different from the (L0 / L1) page table level. The size information returned by the L1 / L2 lookup indicates that the next page table is a large page table (NL is set to 1). Up until now, the address translation circuit has performed three level lookups (one lookup for the L0 / L1 self-referencing level lookup, and M=2 for the L1 / L2 level lookups). Since the next level lookup is in the big page table, performing this lookup will make the number of lookups equal to a predetermined maximum number of lookups (5 for this address translation).Therefore, the next lookup is determined to be an L3 / L4 level lookup in the (L2 / L3) page table indexed from bit 29 to bit 12 of the first address. The L3 / L4 level lookup in the (L2 / L3) page table returns an address of the (L4) page table, which is combined with the least significant 12 bits of the first address to generate a second address in the (L4) level page table.

[0054] FIG. 10d shows an alternative configuration in which a control bit stored in the current page table level is used to indicate whether the lookup is a self-referential lookup. In FIG. 10d, the first address is translated by the address translation circuit 40 to a second address. In the address translation of FIG. 10d, the predetermined maximum number of sequential lookups is 5. Furthermore, the address translation circuit 40 is configured to determine whether to count a page table level as a single lookup level based on the control bit, rather than by directly determining whether the page table level is a self-referential page table level. The address translation circuit sequentially determines a first page table level address based on the most significant bit (not shown) of the first address. The sequential first address points to a large page table (M=2) that is indexed using M=2 of the N-bit portion of the first address. Thus, the first lookup is an L0 / L1 level lookup in the (L0 / L1) page table indexed by bits 56 through 39 of the first address. The sequentially next page table address output by the L0 / L1 lookup is the address of the (L0 / L1) page table. However, rather than determining whether the L0 / L1 lookup is a self-referential lookup through a comparison of the address used for the L0 / L1 lookup with the address output from the L0 / L1 lookup, the address translation circuit 40 determines that the L0 / L1 lookup is a self-referential lookup because a control bit is set. The size information output from the L0 / L1 level lookup indicates that the next level page table is a large page table (NL set to 1). Thus, the next lookup is determined to be an L1 / L2 level lookup in the (L0 / L1) page table, which is indexed by using M-1=1 of the N-bit portions used to index the L1 / L2 level lookup in the (L0 / L1) page table as the most significant M-1=1 N-bit portions used to index the L1 / L2 level lookup in the (L0 / L1) page table.In this case, bits 47 through 30 of the first address are used to index the L1 / L2 lookup. The L1 / L2 lookup returns an address of the sequentially next page table that is different from the (L0 / L1) page table level. However, instead of determining that the address of the sequentially next lookup does not correspond to the address of the L1 / L2 level lookup, the address translation circuit determines that the L1 / L2 level lookup is not a self-referential lookup based on the control bit, which is set to 0 in this case. The size information returned by the L1 / L2 lookup indicates that the next page table is a big page table (NL is set to 1). Up until now, the address translation circuit has performed three level lookups (one lookup for the L0 / L1 self-referential level lookup and M=2 for the L1 / L2 level lookup). Because the next level lookup is in the big page table, performing this lookup will result in the number of lookups being equal to a predetermined maximum number of lookups (5 in this address translation). Therefore, the next lookup is determined to be an L3 / L4 level lookup in the (L2 / L3) page table indexed from bit 29 to bit 12 of the first address. The L3 / L4 level lookup in the (L2 / L3) page table returns an address of the (L4) page table, which is combined with the least significant 12 bits of the first address to generate a second address in the (L4) level page table.

[0055] FIG. 11 illustrates the effect of address translation in which the final lookup of a predetermined number of lookups indicates that the next level lookup is a large page table (M>1). The address translation circuit 40 performs translation of the first address with a predetermined maximum number of sequential lookups equal to 4. The first to third sequential level lookups (L0 level lookup, L1 level lookup, L2 level lookup) are not self-referential lookups but lookups in normal page tables. Thus, the L3 lookup is the fourth level lookup in sequence. In the L3 lookup, it is determined that the size information (NL set to 1) indicates that the address output corresponds to an address in the large page table (M=2). Since there have already been four level lookups (each of L0 through L3 counts as a single level lookup), the address translation circuit determines that it is not possible to continue because there are not enough bits remaining in the first address to generate an address for the large page table, which requires either two N-bit segments for byte addressing, or two N-bit segments + 3 bits for bit addressing. Because there are an insufficient number of bits remaining in the first address, the address translation circuit outputs a fault.

[0056] FIG. 12 illustrates the use of storage circuits (Page Walker Cache 100) in the address translation circuit when translating from a virtual address (VA) as a first address to a physical address (PA) as a second address. The address translation circuit receives a virtual address and performs an initial lookup in Page Walker Cache 100. The lookup in Page Walker Cache 100 determines whether the virtual address or a portion thereof has already been recently translated by the address translation circuit. The lookup in Page Walker Cache 100 results in a hit if any sequentially most significant portion of the first address is hit in the cache. Thus, a cache hit occurs if the most significant N-bit portion of the virtual address hits in Page Walker Cache 100. A hit also occurs if two most significant N-bit portions of the virtual address hit in Page Walker Cache 100. A hit also occurs if three most significant N-bit portions of the virtual address hit in Page Walker Cache. Finally, a hit also occurs if four most significant N-bit portions of the virtual address hit in Page Walker Cache. In this manner, the Page Walker Cache can determine multiple hits to a single virtual address. If there are multiple hits in the Page Walker Cache 100, the address translation circuitry is configured to use the most specific match, ie, the hit that matches the most N-bit portion of the virtual address.

[0057] If the lookup in the Page Walker cache 100 misses, the address translation circuitry performs the address translation by performing up to a predetermined number of sequential lookups at the page table level, in which case the Page Walker cache 100 performs an L0 level lookup 102, an L1 level lookup 104, an L2 level lookup 106, and an L3 level lookup 108 to determine the physical address.

[0058] If the best hit in the Page Walker cache 100 matches only the most significant N-bit portion of the virtual address, then the address translation circuitry does not need to perform an L0 lookup because the results of this lookup can be retrieved from the Page Walker cache. Thus, the address translation circuitry performs an L1 lookup 104, an L2 lookup 106, and an L3 lookup 108 to determine the physical address.

[0059] If the best hit in the Page Walker cache 100 matches the two most significant N-bit portions of the virtual address, then the address translation circuitry does not need to perform an L0 lookup or an L1 lookup because the results of these can be retrieved from the Page Walker cache. Thus, the address translation circuitry performs an L2 lookup 106 and an L3 lookup 108 to determine the physical address.

[0060] If the best hit in the Page Walker cache 100 matches the three most significant N-bit portions of the virtual address, then the address translation circuitry does not need to perform an L0 lookup, an L1 lookup, or an L2 lookup, and the results of these lookups can be retrieved from the Page Walker cache. Thus, the address translation circuitry only performs an L3 lookup 108 to determine the physical address.

[0061] FIG. 13 illustrates the use of the Page Walker cache 100 to perform address translation. The address translation circuit 40 receives a first address to be translated to a second address. The address translation circuit performs an initial lookup of the first address in the Page Walker cache 100. The lookup in the Page Walker cache 100 determines whether any most significant portion of the first address matches an entry in the Page Walker cache 100. The most significant 9 bits of the first address 102 are determined to be a hit in the Page Walker cache 100, and the Page Walker cache entry 104 is returned. Thus, the address translation circuit 40 can suppress the L0 lookup and proceed directly to the next level lookup based on the returned Page Walker cache entry 104. The Page Walker cache entry 104 provides a base address for the next level lookup and size information (NL set to 1) indicating that the next level lookup is a lookup in one of the large page tables. Therefore, the address translation circuit 40 determines that the next level lookup is an L1 / L2 lookup at the (L1 / L2) page table level. The address translation circuit performs this lookup and determines an entry in the (L1 / L2) page table level based on 18 bits (bits 38 to 21) of the first address. The result of the L1 / L2 level lookup is an address for the L3 lookup and size information indicating that the L3 level lookup is a lookup in a normal page table. The address translation circuit 40 performs an L3 lookup in the (L3) page table using 9 bits (bits 20 to 12) of the first address. The result of the L3 level lookup is used in combination with the last 12 bits of the first address to generate a second address.

[0062] FIG. 14 shows a schematic of the interpretation of the large page table 106 by a legacy configuration. MLarge page table 106 is an area of ​​memory occupied by two contiguous regular page tables. Thus, a legacy translation circuit can be used to perform a page table walk to translate a first address to a second address by performing a page table walk in which each page table is treated as a regular page table. Large page table 106 is an area of ​​memory occupied by two contiguous regular page tables. N*M The big page table is aligned on the boundary between the two regular page table entries. NThe entry is aligned to the boundary between the regions of the entry. As a result, the entry of the preceding page table level 108 can be used to determine the particular region of the big page table 106. Thus, the legacy address translation performs an initial L0 lookup based on the most significant portion of the first address and determines that the next lookup, an L1 lookup, is the regular page table 108. The legacy address translation circuit performs a lookup in the regular page table 108 using index bits 38 through 30 of the first address to determine a particular regular page table from the contiguous regular page tables that form the big page table 106. The legacy address translation circuit then performs an L2 level lookup based on bits 29 through 21 of the first address using the particular regular page table of the big page table 106. The page table walk then continues to perform an L3 lookup and output a second address based on this information. The same translation can be performed by the address translation circuit 40 according to the present technique by combining the L1 level lookup and the L2 level lookup into a single L1 / L2 level lookup, in which bits 38 to 21 of the first address are used to index into the large page table 106, thereby performing a single L1 / L2 level lookup instead of two lookups (one L1 level lookup and one L2 level lookup). In such a configuration, a different (L0) level page table entry is cached from the (L0) level page table entry used by the legacy configuration. The legacy (L0) level page table entry points to the legacy L1 page table. In contrast, the (L0) level page table entry used by the address translation circuit 40 points to the combined L1 / L2 page table. Thus, the legacy configuration is provided with a different (L0) level page table entry to the address translation circuit 40.

[0063] 15a and 15b show schematic diagrams of a translation of a first address to a second address by an address translation circuit according to a legacy configuration (FIG. 15a) and according to the present technique (FIG. 15b) when a big page table level 112 is provided with a preceding legacy configuration area 110 embedded within the big page table. In FIG. 15a, the legacy address translation circuit receives a first address and performs an L0 level lookup based on the L0 index portion (bits 47 to 39) of the first address. The L0 level lookup returns a base address for an L1 level lookup that points to the legacy configuration area 110 embedded within the big page table 112. The legacy address translation circuit is unaware of the big page table and uses the L1 indexing bits (bits 38 to 30) of the first address to access the legacy configuration area as if it were a normal page table, as part of the L1 level lookup. An L1 level lookup in the legacy configuration area 110 returns an address of a particular normal page table size area of ​​the big page table 112 that is used for an L2 level lookup. The L2 level lookup is performed in a particular area of ​​the normal page table size area of ​​the big page table 112 using the L2 indexing bits (bits 29 through 21) of the first address. The L2 level lookup returns an address of the normal page table that is used in combination with the L3 indexing bits (bits 20 through 12) of the first address to perform an L3 lookup. The result of the L3 level lookup is combined with the least significant bits (bits 11 through 0) of the first address to generate a second address.

[0064] FIG. 15b shows a schematic of the performance of the address translation circuit 40 according to the present technology. The address translation circuit 40 receives a first address and performs an L0 level lookup based on the L0 index portion (bits 47 through 39) of the first address. The first address in this case is the same as the first address used in the legacy configuration. The result of the L0 level lookup is the base address of the legacy configuration area 110 of the big page table 112 and size information (NL set to 1) indicating that the next level lookup is a lookup in the big page table. The big page table is of size 2 N*M The page table is usually aligned to the boundary between the N Since the L1 / L2 indexing portion of the first address is aligned to the boundary between the legacy configuration area 110 and the big page table 112, the most significant portion of the base address for the legacy configuration area 110 is also the base address of the big page table 112. Thus, by using the L1 / L2 indexing portion of the first address in combination with the base address determined from the (L0) level lookup, the address translation circuit 40 can directly index into the big page table 112. Thus, the address translation circuit performs a next level lookup, an L1 / L2 level lookup, in the big page table 112 using the L1 / L2 indexing bits (bits 38 through 21) of the first address, which point to a particular entry at the (L1 / L2) page table level. The address translation circuit 40 checks that the L1 / L2 indexing bits do not point to the legacy configuration area 110 of the big page table 112 before proceeding to perform the lookup. The result of the L1 / L2 level lookup returns an address of a normal page table that is used in combination with the L3 indexing bits (bits 20 through 12) of the first address to perform an L3 lookup, and size information that indicates that the L3 level lookup is a normal level lookup. The result of the L3 level lookup is combined with the least significant bits (bits 11 through 0) of the first address to generate a second address.

[0065] FIG. 16 shows a schematic sequence of steps performed by the address translation circuit when performing an intermediate lookup. The flow starts at step S100, where the address translation circuit starts an intermediate lookup in a current intermediate page table. The flow then proceeds to step S102, where the address translation circuit retrieves information from the current intermediate page table indicating the sequentially next lookup address of the sequentially next page table. The flow then proceeds to step S104, where the address translation circuit retrieves page table size information from the current intermediate page table indicating the size of the sequentially next page table. The flow then proceeds to step S106, where it is determined whether performing the sequentially next lookup would exceed a predetermined maximum number of lookups. If it is determined in step S106 that performing the next lookup would not exceed a predetermined maximum number of lookups, the flow proceeds to step S108, where the current intermediate lookup is terminated, and then the next lookup (either another intermediate level lookup or a final level lookup) is initiated. If in step S106 it is determined that performing the next sequential lookup would exceed a predetermined maximum number of lookups, flow proceeds to step S110, where the subsequent lookup is suppressed, and the address conversion circuit generates a second address based on information indicating the next sequential lookup address.

[0066] FIG. 17 shows a schematic of a set of steps performed by the address translation circuit in response to receiving a first address to generate a second address. The flow begins at step S200, where the address translation circuit receives a first address and an indication of first size information. At step S200, the address translation circuit also sets a counter j equal to 1. Next, the flow proceeds to step S202, where it is determined whether the jth page table is a big page table. If it is determined at step S202 that the jth page table is not a big page table, the flow proceeds to step S212, where the address translation circuit uses a single N-bit portion of the first address to identify an entry in the jth page table. Then, the flow proceeds to step S206. If it is determined at step S202 that the jth page table is a big page table, the flow proceeds to step S204. At step S204, the address translation circuit uses M sequential N-bit portions of the first address to identify an entry in the jth page table. Then, the flow proceeds to step S206. In step S206, the address conversion circuit extracts information indicating the j+1th lookup address of the j+1th page table and the j+1th page table size information indicating the size of the j+1th page table from the entry in the jth page table.

[0067] Next, the flow proceeds to step S208, where it is determined whether the j+1th size information indicates that the next lookup will cause the total number of lookups to exceed the predetermined number of lookups. In particular, the size of the current lookup is known from steps S202, S204, and S212. Thus, the total number of lookups required to perform the next lookup in sequence can be determined from information about the size of the current (jth) lookup and information returned from the jth lookup as size information. If it is determined in step S208 that performing the (j+1)th lookup will exceed the predetermined number of lookups, the flow proceeds to step S210. In step S210, the address conversion circuit suppresses the subsequent lookup and generates a second address based on the information indicating the (j+1)th lookup address. If it is determined in step S208 that performing the (j+1)th lookup will not exceed the predetermined number of lookups, the flow proceeds to step S214.

[0068] In step S214, it is determined whether the jth page table is a large page table. If it is determined in step S214 that the jth page table is not a large page table, the flow proceeds to step S222, where the current lookup is counted (considered to be a single lookup). The flow then proceeds to step S224, where j is incremented by 1, and then the flow returns to step S202. If it is determined in step S214 that the jth page table is a large page table, the flow proceeds to step S216. In step S216, the address conversion circuit determines whether the (j+1)th lookup address corresponds to the address of the jth page table. If it is determined in step S216 that the (j+1)th lookup address corresponds to the address of the jth page table, the flow proceeds to step S222, where the current lookup is counted (considered to be a single lookup). Flow then proceeds to step S224 where j is incremented by 1, after which flow returns to step S202. If in step S216 it is determined that the (j+1)th lookup address does not correspond to the jth page table address, flow proceeds to step S218 where the current lookup is counted (considered) as M lookups. Flow then proceeds to step S220. In step S220, j is incremented by M before flow returns to step S202.

[0069] In summary, the present invention relates to an address translation circuit and method for performing address translation. The address translation circuit performs an address translation between a first address and a second address by performing a predetermined maximum number of sequential lookups in response to receiving a first address. The address translation circuit performs an address translation between a first address and a second address by performing a predetermined maximum number of sequential lookups in response to receiving a first address. N A regular page table containing 2 entries, N*Mand a large page table including the number of entries. The address translation circuitry is configured to perform an intermediate lookup to retrieve information indicative of a sequentially next lookup address and page table size information, inhibit a subsequent lookup if the page table size information indicates that the sequentially next lookup corresponds to one of the large page tables and performing the sequentially next lookup exceeds a predetermined maximum number of sequential lookups, and generate a second address based on the information indicative of the sequentially next lookup address.

[0070] In this application, the term "configured to..." is used to mean that elements of an apparatus have a configuration that is capable of performing a defined operation. In this context, "configuration" refers to a manner of arrangement or interconnection of hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that the apparatus elements need to be modified in any way to provide the defined operation.

[0071] Although illustrative embodiments have been described in detail herein with reference to the accompanying drawings, it will be understood that the invention is not limited to exact embodiments thereof, and that various changes, additions and modifications may be made by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims. For example, various combinations of the features of the following dependent claims may be made with the features of the independent claims without departing from the scope of the invention.

Claims

1. An address translation circuit that performs address translation between a first address and a second address by performing a predetermined maximum number of sequential lookups at a plurality of page table levels in response to reception of the first address, wherein the address translation circuit, 2 Ｎ Supports a normal page table level containing 2 Ｎ＊Ｍ entries and a large page table level containing 2 entries, and each sequential lookup at the normal page table level is regarded as a single-level lookup of the predetermined maximum number of sequential lookups, and each sequential lookup at the large page table level is regarded as an M-level lookup of the predetermined maximum number of sequential lookups. retrieves information indicating a next sequential lookup address at a next page table level and page table level size information indicating a size of the next page table level, in sequence, from a current intermediate page table level among the plurality of page table levels, and when the page table level size information indicates that the next sequential lookup corresponds to one of the large page table levels and that performing the next sequential lookup exceeds the predetermined maximum number of sequential lookups, suppresses a subsequent lookup after the predetermined maximum number of sequential lookups and performs an intermediate lookup to generate the second address, the address translation circuit being configured as such.

2. The first address includes a series of N-bit indexing portions, and the address translation circuit, indexes each sequential lookup at one of the normal page table levels using a single N-bit indexing portion among the series of N-bit indexing portions, and indexes each sequential lookup at one of the large page table levels using M sequential N-bit indexing portions among the series of N-bit indexing portions, the address translation circuit according to claim 1 being configured as such.

3. When the page table level size information indicates that execution of the next sequential lookup is within the predetermined maximum number of lookups and that the next sequential lookup address corresponds to an address of the current intermediate page table, the intermediate lookup is regarded as a single-level lookup of the predetermined maximum number of sequential lookups, regardless of a current size of the current intermediate page table level, the address translation circuit according to claim 2.

4. The address translation circuit is configured to regard the intermediate lookup as the single-level lookup of the predetermined maximum number of sequential lookups, regardless of the current size of the current intermediate page table level, in response to a control bit indicating that the intermediate entry is treated as a single-level lookup. The address translation circuit according to claim 2.

5. When the next sequential lookup address corresponds to the address of the current intermediate page table and the current lookup corresponds to one of the large page table levels, the current lookup is indexed using the current M sequential indexing portions of the series of N-bit indexing portions, the lowermost M - 1 sequential N-bit indexing portions of the current M sequential indexing portions are the uppermost M - 1 sequential N-bit indexing portions of the next M sequential indexing portions used to index the next sequential lookup. The address translation circuit according to claim 3 or 4.

6. Recognize a legacy configuration area within one of the large page table levels, the legacy configuration area identifying two Ｎ entries that sequentially identify the next lookup address corresponding to the address of the current intermediate page table level, When the M sequential N-bit indexing portions point to the legacy configuration area of 2N entries, it is further configured to generate a legacy configuration table fault. The address translation circuit according to any one of claims 2 to 4.

7. The address translation circuit is configured to output an invalid translation fault when the page table level size information indicates that executing the next sequential lookup exceeds the predetermined maximum number of sequential lookups by an amount greater than 1. The address translation circuit according to any one of claims 1 to 4.

8. The address translation circuit according to any one of claims 1 to 4 further comprises a storage circuit for storing information indicating the first page table level address corresponding to the first intermediate lookup of the predetermined maximum number of sequential lookups and first size information indicating the size of the first page table level.

9. The storage circuit stores information indicating a plurality of page table level addresses, and the address translation circuit is configured to select the first page table level address in sequence from the plurality of page table level addresses based on one or more selection bits of the first address. The address conversion circuit according to claim 8.

10. The address conversion circuit is configured to sequentially select the first page table level address from the plurality of page table level addresses based on a current privilege level. The address conversion circuit according to claim 9.

11. The address conversion circuit further comprises a partial conversion storage circuit that associates intermediate lookup information retrieved during the intermediate lookup with a corresponding subset of bits of the first address already used in the address conversion, the intermediate lookup information further comprising information indicating the next lookup address in sequence and information indicating the size of the next page table level in sequence. The address conversion circuit according to any one of claims 1 to 4.

12. Based on the first address, perform a partial conversion lookup in the partial conversion storage circuit. When the partial conversion lookup hits in the partial conversion storage circuit, retrieve the information indicating the next lookup address in sequence and the information indicating the size of the next page table level in sequence from the partial conversion storage circuit, and suppress the lookup associated with the corresponding subset of bits of the first address already used in the address conversion. The address conversion circuit according to claim 11, further configured as such.

13. The first address is defined in a first address space, and the second address is defined in a second address space. The address conversion circuit according to any one of claims 1 to 4.

14. Each of the first address space and the second address space is a virtual address space, an intermediate physical address space, a physical address space, and is one of them. The address conversion circuit according to claim 13.

15. In response to receiving the first address, 2 Ｎ A normal page table level including entries and a large page table level including 2 Ｎ＊Ｍ entries, and performing a predetermined maximum number of sequential lookups at a plurality of page table levels, a method for performing address translation between the first address and the second address, wherein each sequential lookup at the normal page table level is regarded as a single lookup of the predetermined maximum number of sequential lookups, and each sequential lookup at the large page table level is regarded as M lookups of the predetermined maximum number of sequential lookups. The method includes retrieving, from a current intermediate page table level among the plurality of page table levels, information indicating the next lookup address in sequence and page table level size information indicating the size of the next page table level in sequence. When the page table level size information indicates that the next sequential lookup in sequence corresponds to one of the large page table levels and that performing the next sequential lookup in sequence exceeds the predetermined maximum number of sequential lookups, suppressing subsequent lookups after the predetermined maximum number of sequential lookups and generating the second address based on the information indicating the next sequential lookup address, thereby including performing an intermediate lookup, a method.

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