PACKAGE COMPRISING INTEGRATED DEVICE HAVING BACK METAL LAYER - Patent application

Abstract

A device comprising a package and a board. The package includes a substrate including a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a backside metal layer coupled to a backside of the integrated device, a first solder interconnect coupled to the backside metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The board is coupled to the package via the plurality of solder interconnects. The first solder interconnect is coupled to the board.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of non-provisional application Ser. No. 17 / 482,294, filed in the United States Patent Office on September 22, 2021, the entire contents of which are incorporated by reference herein as if fully set forth in its entirety below, and for all applicable purposes.

[0002] Various features relate to a package having an integrated device. [Background technology]

[0003] The package may include a substrate and an integrated device. The integrated device may generate a large amount of heat during operation, which may affect the performance of the integrated device and / or the package. There is a continuing need to provide integrated devices and packages with improved heat dissipation performance. Summary of the Invention [Means for solving the problem]

[0004] Various features relate to a package having an integrated device.

[0005] One embodiment provides a device comprising a package and a board. The package includes a substrate having a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a backside metal layer coupled to a backside of the integrated device, a first solder interconnect coupled to the backside metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The board is coupled to the package via the plurality of solder interconnects. The first solder interconnect is coupled to the board.

[0006] Another embodiment provides a package including a substrate including a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a backside metal layer coupled to a backside of the integrated device, a first solder interconnect coupled to the backside metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate.

[0007] Another embodiment provides a method of providing a package including a substrate having a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a backside metal layer coupled to a backside of the integrated device, a first solder interconnect coupled to the backside metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The method couples the package to a board coupled via the plurality of solder interconnects. The first solder interconnect is coupled to the board.

[0008] Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] 1 is an exemplary cross-sectional view of a package including an integrated device having a backside metal layer. [Diagram 2] 1 is an exemplary expanded view of a package including an integrated device having a backside metal layer. [Diagram 3] 1 is an exemplary expanded view of a package including an integrated device having a backside metal layer. [Figure 4] 1 is an exemplary cross-sectional view of a package including an integrated device having a backside metal layer. [Figure 5A] 1A-1C illustrate an exemplary sequence for manufacturing a package with an integrated device having a back metal layer and assembling the package to a board. [Figure 5B] 1A-1C illustrate an exemplary sequence for manufacturing a package with an integrated device having a back metal layer and assembling the package to a board. [Figure 5C] 1A-1C illustrate an exemplary sequence for manufacturing a package with an integrated device having a back metal layer and assembling the package to a board. [Figure 5D] 1A-1C illustrate an exemplary sequence for manufacturing a package with an integrated device having a back metal layer and assembling the package to a board. [Figure 5E] 1A-1C illustrate an exemplary sequence for manufacturing a package with an integrated device having a back metal layer and assembling the package to a board. [Figure 6A] 1A-1C illustrate an exemplary sequence for manufacturing a package with an integrated device having a back metal layer and assembling the package to a board. [Figure 6B] 1A-1C illustrate an exemplary sequence for manufacturing a package with an integrated device having a back metal layer and assembling the package to a board. [Figure 7] 4 is an exemplary flow chart of a method for manufacturing a package with an integrated device having a backside metal layer and assembling the package to a board. [Figure 8A] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 8B] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 9] 1 is an exemplary flow chart of a method for manufacturing a substrate. [Figure 10] FIG. 1 illustrates various electronic devices that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are described to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011] The present disclosure describes a device including a package and a board. The package includes a substrate including a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a back metal layer coupled to a back surface of the integrated device, a first solder interconnect coupled to the back metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The board is coupled to the package via the plurality of solder interconnects. The first solder interconnect is coupled to the board. The package and the board are configured to dissipate heat from the integrated device via the back metal layer, the first solder interconnect, and the board. The back metal layer can be configured as an electromagnetic interference (EMI) shield for the integrated device and / or package. Thus, the back metal layer can provide multiple functions for the package. The back metal layer helps to improve the performance of the integrated device and / or package by efficiently dissipating heat from the integrated device and by helping to shield the integrated device from other signals and / or currents.

[0012] Exemplary Package with Integrated Device Having Back Metal Layer 1 shows a cross-sectional view of a package 100 including an integrated device having a back metal layer that may be configured to dissipate heat from the integrated device and / or as an electromagnetic interference (EMI) shield for the integrated device and / or the package.

[0013] The package 100 includes a substrate 102, an integrated device 104, a passive component 105, a passive component 107, a passive component 109, an encapsulation layer 106, and an encapsulation layer 108. The package 100 may also include a number of solder interconnects 130.

[0014] The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122. The substrate 102 can be a coreless substrate (e.g., an embedded trace substrate (ETS)). The substrate 102 can include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). Different implementations can use different substrates. In some implementations, the package 100 can include a core substrate.

[0015] Passive component 105 is coupled to the first surface of substrate 102 via a plurality of solder interconnects 150. Passive component 107 is coupled to the first surface of substrate 102 via a plurality of solder interconnects 170. Passive component 109 is coupled to the first surface of substrate 102 via a plurality of solder interconnects 190. The passive components (e.g., 105, 107, 109) may include capacitors and / or inductors.

[0016] The encapsulation layer 106 is provided (e.g., formed) on the first surface of the substrate 102. The encapsulation layer 106 can encapsulate the passive components (e.g., 105, 107, 109). The encapsulation layer 106 can include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid molding process can be used to form the encapsulation layer 106. The encapsulation layer 106 can be photoetchable. The encapsulation layer 106 can be a first encapsulation layer. The encapsulation layer 106 can be a first encapsulation means.

[0017] The integrated device 104 is coupled to a second surface (e.g., a bottom surface) of the substrate 102 via a plurality of solder interconnects 140. For example, the integrated device 104 is coupled to a plurality of interconnects 122 of the substrate 102 via a plurality of solder interconnects 140. The integrated device 104 may include a front surface and a back surface. The front surface of the integrated device 104 may face the substrate 102, while the back surface of the integrated device 104 may face away from the substrate 102. The back surface of the integrated device 104 may face the board 110. The plurality of solder interconnects 130 are coupled to a second surface of the substrate 102. The plurality of solder interconnects 130 may be coupled to a plurality of interconnects 122 of the substrate 102.

[0018] The encapsulation layer 108 is provided (e.g., formed) on a second surface (e.g., bottom surface) of the substrate 102. The encapsulation layer 108 can at least partially encapsulate the integrated device 104 and the plurality of solder interconnects 130. The encapsulation layer 108 can include a mold, a resin, and / or an epoxy. The encapsulation layer 108 can be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation layer 108 can be photo-etchable. The encapsulation layer 108 can be a second encapsulation layer. The encapsulation layer 108 can be a second encapsulation means.

[0019] The back metal layer 142 is coupled to the back surface of the integrated device 104. At least in FIG. 2, the back metal layer 142 may be disposed on and coupled to a die substrate of the integrated device 104, as described further below. In some implementations, the back metal layer 142 may be considered part of the integrated device 104. In some implementations, the back metal layer 142 may be considered part of the back surface of the integrated device 104. Different implementations may use different materials for the back metal layer 142. For example, the back metal layer 142 may include stainless steel (SUS), copper (Cu), palladium (Pd), and / or gold (Au). A first solder interconnect 144 is coupled to the back metal layer 142.

[0020] The package 100 may be coupled to a board 110 via a plurality of solder interconnects 130 and a first solder interconnect 144. The board 110 may include a printed circuit board (PCB). The board 110 includes at least one dielectric layer 111 and a plurality of board interconnects 112. The package 100 may be coupled to the plurality of board interconnects 112 via the plurality of solder interconnects 130 and the first solder interconnect 144. The package 100 and the board 110 may be part of an assembly and / or a device.

[0021] The package 100 is coupled to the board 110 such that the back side of the integrated device 104 faces the board 110. The back side of the integrated device 104 and the backside metal layer 142 may be coupled to the board 110 via a first solder interconnect 144. The backside metal layer 142 may not have an electrical connection to the active devices (e.g., transistors) of the integrated device 104. The backside metal layer 142 and the first solder interconnect 144 may be configured to be coupled to ground. The backside metal layer 142 may be configured as an electromagnetic interference (EMI) shield for the integrated device 104 and / or the package 100. The backside metal layer 142 may be configured as a bottom EMI shield for the package 100.

[0022] The package 100 and the board 110 are coupled together such that the package 100 and the board 110 can be configured to dissipate heat from the integrated device 104 through the back metal layer 142, the first solder interconnects 144, and the board 110. For example, the package 100 and the board 110 are coupled together such that the package 100 and the board 110 can be configured to dissipate heat from the integrated device 104 through the back metal layer 142, the first solder interconnects 144, and at least one board interconnect from the plurality of board interconnects 112. Heat dissipating through the back metal layer 142, the first solder interconnects 144, and at least one board interconnect from the plurality of board interconnects 112 dissipates heat through thermal conduction, which is much more efficient and effective than heat dissipated through convection. Because the board 110 and the plurality of board interconnects 112 are relatively large components, they can be effective heat sinks for heat that may be generated and / or located at or near the integrated device 104 .

[0023] This ability of the back metal layer 142 to be configured as both an EMI shield and a heat sink allows the back metal layer 142 to help improve the performance of the integrated device 104 and / or package 100.

[0024] FIG. 2 shows an expanded view of FIG. 1. In particular, FIG. 2 shows one embodiment of how the backside of the integrated device 104 can be coupled to the board 110. As shown in FIG. 2, the integrated device 104 includes a die substrate 204, a circuit layer 206, and a die interconnect portion 208. The circuit layer 206 can be disposed on the die substrate 204. The circuit layer 206 can include transistors formed in and / or on the die substrate 204. The die interconnect portion 208 is coupled to the die substrate 204 and the circuit layer 206. The die interconnect portion 208 can be disposed on the die substrate 204 and the circuit layer 206. The die interconnect portion 208 includes at least one die dielectric layer and a plurality of die interconnects (both not shown). The plurality of die interconnects can be coupled to the circuit layer 206. For example, the plurality of die interconnects can be coupled to transistors of the circuit layer 206. The die substrate 204 may include silicon (Si). The portion of the integrated device 104 that includes the die substrate 204 may be considered the backside of the integrated device 104. The backside metal layer 142 is coupled to the die substrate 204 of the integrated device 104. As described above, the backside metal layer 142 may be considered part of the integrated device 104. The first solder interconnects 144 are coupled to the backside metal layer 142 and to the board interconnects 112a of the board 110. The integrated device 104 and the board 110 are coupled to one another such that the integrated device 104 and the board 110 may be configured to dissipate heat from the integrated device 104 via the backside metal layer 142, the first solder interconnects 144, and the board interconnects 112a.

[0025] FIG. 3 shows an expanded view of FIG. 1. In particular, FIG. 3 shows another example of how the backside of the integrated device 104 can be coupled to the board 110. As shown in FIG. 3, the integrated device 104 includes a die substrate 204 and a plurality of die substrate vias 242. The plurality of die substrate vias 242 can extend partially and / or completely through the thickness of the die substrate 204. The plurality of die substrate vias 242 can be configured not to be electrically coupled to any transistors of the integrated device 104. The plurality of die substrate vias 242 are coupled to the backside metal layer 142. The plurality of die substrate vias 242 can include a thermally conductive material (e.g., metal). The plurality of die substrate vias 242 can be a better thermal conductor than the die substrate 204, and thus the plurality of die substrate vias 242 can help provide better heat dissipation. The integrated device 104 and the board 110 are coupled together such that the integrated device 104 and the board 110 can be configured to dissipate heat from the integrated device 104 through the die substrate vias 242, the back metal layer 142, the first solder interconnects 144, and the board interconnects 112a. The die substrate vias 242, the back metal layer 142, the first solder interconnects 144, and the board interconnects 112a can be configured to be coupled to ground. The die substrate vias 242, the back metal layer 142, the first solder interconnects 144, and the board interconnects 112a can be configured as an EMI shield for the integrated device 104 and / or the package 100.

[0026] In some implementations, the package may include additional components to add improved performance. FIG. 4 shows a package 400 coupled to a board 110. The package 400 is similar to the package 100 and may include similar components and / or similar configurations as the package 100. Thus, the description of the package 100 may be applicable to the package 400. The package 400 may improve the package 100 by adding EMI shielding for the package 400 and / or the integrated device 104. The package 400 includes a metal layer 408 formed and disposed on a surface of the encapsulation layer 106, a side of the substrate 102, and / or a surface of the encapsulation layer 108. The metal layer 408 may be configured to be coupled to a ground. The metal layer 408 may be configured as an EMI shield for the passive devices (e.g., 105, 107, 109), the integrated device 104, and / or the package 400. The metal layer 408 may be coupled to an interconnect from the plurality of interconnects 122. A metal layer 408 may be formed and disposed on an outer surface of the package 400 .

[0027] In this disclosure, package 100 and package 400 are described as being coupled to a board. However, package 100 and package 400 may also be coupled to a substrate and / or interposer in a similar manner. In some implementations, package 100 and / or package 400 may be implemented in a package on package (PoP).

[0028] The integrated device (e.g., 104) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 104) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device.

[0029] The package (e.g., 100, 400) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 100, 400) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100, 400) may be configured to support Global System for Mobile (GSM) communications, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 100, 400) may be configured to transmit and receive signals having different frequencies and / or different communication protocols.

[0030] Having described the various packages, the sequence for manufacturing the packages will now be described below.

[0031] Exemplary sequence for manufacturing a package with an integrated device having a back metal layer In some implementations, manufacturing the package includes several processes. Figures 5A-5E show an example sequence for providing or manufacturing a package including an integrated device having a back metal layer. In some implementations, the sequence of Figures 5A-5E can be used to provide or manufacture package 400. However, the process of Figures 5A-5E can also be used to manufacture any of the packages described in this disclosure (e.g., 100).

[0032] 5A-5E may be combined with one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0033] As shown in FIG. 5A, stage 1 illustrates a state after a substrate 102 is prepared. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 102 may be manufactured using a method such as that described in FIG. 7A and FIG. 7B. In some implementations, a core substrate (e.g., a substrate including a core layer) is prepared.

[0034] Stage 2 shows the state after a number of passive components (e.g., 105, 107, 109) have been coupled to a first surface (e.g., top surface) of the substrate 102. A pick-and-place process may be used to couple the passive components (e.g., 105, 107, 109) to the substrate 102. Passive component 105 may be coupled to the substrate 102 via a number of solder interconnects 150. Passive component 107 may be coupled to the substrate 102 via a number of solder interconnects 170. Passive component 109 may be coupled to the substrate 102 via a number of solder interconnects 190.

[0035] Stage 3 shows the state after encapsulation layer 106 has been provided (e.g., formed) on the first surface of substrate 102. Encapsulation layer 106 can encapsulate the passive components (e.g., 105, 107, 109). Encapsulation layer 106 can include mold, resin, and / or epoxy. Compression molding, transfer molding, or liquid molding processes can be used to form encapsulation layer 106. Encapsulation layer 106 can be photoetchable. Encapsulation layer 106 can be a means for encapsulation.

[0036] As shown in FIG. 5B, stage 4 shows the state after the integrated device 104 is coupled to a second surface (e.g., bottom side) of the substrate 102 via a plurality of solder interconnects 140. A solder reflow process can be used to couple the integrated device 104 to the substrate 102. FIG. 2 shows one example of how the integrated device 104 can be coupled to the substrate 102. Different implementations can couple different components and / or devices to the substrate 102. Stage 4 also shows a plurality of solder interconnects 130 coupled to the second surface of the substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 130 to the substrate 102.

[0037] Stage 5 illustrates the state after an encapsulation layer 108 is provided (e.g., formed) on a second surface (e.g., bottom surface) of the substrate 102. The encapsulation layer 108 can encapsulate the integrated device 104 and the plurality of solder interconnects 130. The encapsulation layer 108 can include a mold, a resin, and / or an epoxy. The encapsulation layer 108 can be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation layer 108 can be photo-etchable. The encapsulation layer 108 can be a means for encapsulation.

[0038] As shown in FIG. 5C, stage 6 shows the state after the back surface of the package has been removed. For example, portions of the encapsulation layer 108 can be removed by a grinding process, and portions of the solder interconnects 130 can be removed by a grinding process. Removing portions of the encapsulation layer 108 can expose the back surface of the integrated device 104. In some implementations, portions of the back surface of the integrated device 104 can be removed as well. For example, portions of the die substrate 204 of the integrated device 104 can be removed. The surface of the encapsulation layer 108 can be flush with the surface of the back surface of the integrated device 104 after the grinding process.

[0039] Stage 7 shows the state after metal layer 408 is formed on the surface of encapsulation layer 106, the side of substrate 102, and the side of encapsulation layer 108. A sputtering process or a plating process may be used to form metal layer 408. Metal layer 408 may include stainless steel (SUS) and / or copper (Cu). However, metal layer 408 may include any type of conductive material. Metal layer 408 may be configured as an EMI shield.

[0040] Stage 8 shows the state after the back metal layer 142 is formed on the back side of the integrated device 104. A sputtering process and / or a plating process can be used to form the back metal layer 142. In some implementations, a mask can be used to form the back metal layer 142, as further described below in FIG. 6A, FIG. 6B. The back metal layer 142 can also be formed on the encapsulation layer 108. The back metal layer 142 can include stainless steel (SUS), copper (Cu), palladium (Pd), and / or gold (Au). However, the back metal layer 142 can include any type of electrically conductive and / or thermally conductive material. In some implementations, the back metal layer 142 can be formed by selective plating, such as electroless plating.

[0041] As shown in FIG. 5D, stage 9 shows the state after portions of the back metal layer 142 have been removed. In some implementations, portions of the back metal layer 142 may be removed to ensure that the back metal layer 142 does not contact interconnects that are part of the circuitry of the package and / or integrated device. In some implementations, portions of the back metal layer 142 may sputter onto nearby solder interconnects during the sputtering process, resulting in unintended connections. A laser process may be used to separate the back metal layer 142 from any unintended connections. A laser process (e.g., laser ablation) may also be used to form cavities in the plurality of solder interconnects 130.

[0042] Stage 10 shows the state after additional solder interconnects may be added to re-form the plurality of solder interconnects 130. Portions of the additional solder interconnects may be formed within the cavities of the solder interconnect formed in stage 9. A solder reflow process may be used to form the additional solder interconnects.

[0043] 5E, stage 11 shows a first solder interconnect 144 being bonded to the back metal layer 142. A solder reflow process can be used to form and bond the first solder interconnect 144 to the back metal layer 142. Stage 11 may show a package 400 including an integrated device 104, a back metal layer 142 bonded to a back side of the integrated device 104, and the first solder interconnect 144 bonded to the back metal layer 142.

[0044] Once package 400 is manufactured, package 400 may be combined with other components. For example, package 400 may be coupled to board 110. The coupling of package 400 to board 110 may occur separate from the manufacture of package 400. The assembly of package 400 to board 110 may occur by the same entity that manufactured package 400 or by a different entity than the entity that manufactured package 400.

[0045] Stage 12 shows the state after the package 400 has been coupled to the board 110 via the plurality of solder interconnects 130 and the first solder interconnects 144. The plurality of solder interconnects 130 and the first solder interconnects 144 are coupled to the plurality of board interconnects 112 of the board 110. The package 400 and the board 110 are coupled together such that the package 400 and the board 110 are configured to dissipate heat from the integrated device 104 via the backside metal layer 142, the first solder interconnects 144, and at least one board interconnect from the plurality of board interconnects 112. As shown and described in FIG. 3, when the integrated device 104 includes the die substrate vias 242, the package 400 and the board 110 are configured to dissipate heat from the integrated device 104 through the die substrate vias 242, the back metal layer 142, the first solder interconnects 144, and at least one board interconnect from the plurality of board interconnects 112.

[0046] The packages described in this disclosure (eg, 100, 400) can be manufactured one by one, or can be manufactured together as part of one or more wafers and then singulated into individual packages.

[0047] In some implementations, the back metal layer 142 can be formed in a different manner than described in Figures 5A-5E. Figures 6A-6B show part of an exemplary sequence for providing or manufacturing a package including an integrated device having a back metal layer. The sequence shown in Figures 6A-6B can replace the sequence of steps 7-10 in Figures 5C-5D.

[0048] Stage 1 of FIG. 6A shows the state after metal layer 408 is formed on the surface of encapsulation layer 106, the side of substrate 102, and the side of encapsulation layer 108. A sputtering process or a plating process can be used to form metal layer 408. Metal layer 408 can include stainless steel (SUS) and / or copper (Cu). However, metal layer 408 can include any type of conductive material. Metal layer 408 can be configured as an EMI shield. Stage 1 of FIG. 6A can be similar to stage 7 of FIG. 5C.

[0049] Stage 2 shows the state after a mask 640 is formed on the backside of the integrated device 104. A deposition process may be used to form the mask 640. The mask 640 may be etched and / or patterned. The mask 640 may be formed on the encapsulation layer 108.

[0050] Stage 3 shows the state after a back metal layer 142 is formed on the back side of the integrated device 104. A sputtering process and / or a plating process may be used to form the back metal layer 142. The back metal layer 142 may be formed through one or more openings in the mask 640. The back metal layer 142 may include stainless steel (SUS), copper (Cu), palladium (Pd), and / or gold (Au). However, the back metal layer 142 may include any type of electrically conductive and / or thermally conductive material.

[0051] Step 4 in Figure 6B shows the state after the mask 640 has been removed. A cleaning process can be used to remove the mask 640. Steps 2-4 in Figures 6A and 6B can replace steps 8 and 9 in Figures 5C and 5D.

[0052] Stage 5 shows the state after additional solder interconnects may be added to reform the plurality of solder interconnects 130. Portions of the additional solder interconnects may be formed within the cavities of the solder interconnects formed in stage 9. A solder reflow process may be used to form the additional solder interconnects. Stage 5 of FIG. 6B may be similar to stage 10 of FIG. 5D. In some implementations, cavities may be formed in the solder interconnects prior to the plurality of solder interconnects 130, for example, as described in stage 9 of FIG. 5D.

[0053] FIG. 1 is an exemplary flow diagram of a method for manufacturing a package with an integrated device having a back metal layer. In some implementations, manufacturing the package includes several processes. Figure 7 shows an example flow diagram of a method 700 for providing or manufacturing a package including an integrated device having a back metal layer. In some implementations, the method 700 of Figure 7 can be used to provide or manufacture the package 400 described in this disclosure. However, the method 700 can also be used to provide or manufacture any of the packages (e.g., 100) described in this disclosure.

[0054] It should be noted that the method of Figure 7 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing the package. In some implementations, the order of the processes may be changed or modified.

[0055] The method provides (at 705) a package (e.g., 400, 100) including a substrate (e.g., 102), passive components (e.g., 105, 107, 109), an integrated device 104, an encapsulation layer 106, an encapsulation layer 108, and a number of solder interconnects 130. The package may be a double-sided molded package. The package may be provided by a supplier or may be manufactured. Steps 1-5 in Figures 5A and 5B illustrate and describe one embodiment of how the package may be provided or manufactured.

[0056] The method removes (at 710) portions of the plurality of solder interconnects 130 and portions of the encapsulation layer 108. A grinding process may be used to remove the portions of the plurality of solder interconnects 130 and portions of the encapsulation layer 108. By removing the portions of the encapsulation layer 108, a backside surface of the integrated device 104 may be exposed. The surface of the encapsulation layer 108 may be flush with a surface of the backside surface of the integrated device 104 after the grinding process. Step 6 of FIG. 5C illustrates and describes one embodiment of removing the portions of the solder interconnects and portions of the encapsulation layer.

[0057] The method forms (at 715) a metal layer (e.g., 408) on the surface of the encapsulation layer 106, the side of the substrate 102, and the side of the encapsulation layer 108. A sputtering process or a plating process may be used to form the metal layer 408. The metal layer 408 may include stainless steel (SUS) and / or copper (Cu). However, the metal layer 408 may include any type of conductive material. The metal layer 408 may be configured as an EMI shield. Step 7 of FIG. 5C illustrates and describes one example of a metal layer being formed on the surface of the encapsulation layer, the side of the substrate, and the side of the encapsulation layer.

[0058] The method forms (at 720) a back metal layer (e.g., 142) on the back surface of the integrated device 104. A sputtering process and / or a plating process may be used to form the back metal layer 142. In some implementations, a mask (not shown) may be used to form the back metal layer 142. The back metal layer 142 may also be formed on the encapsulation layer 108. The back metal layer 142 may include stainless steel (SUS), copper (Cu), palladium (Pd), and / or gold (Au). However, the back metal layer 142 may include any type of electrically conductive and / or thermally conductive material. Step 8 of FIG. 5C illustrates and describes one example of a back metal layer formed on the back surface of the integrated device. In some implementations, after the back metal layer is formed, portions of the back metal layer 142 may be removed to ensure that the back metal layer 142 does not contact interconnects that are part of the package and / or circuitry of the integrated device. This may be necessary if portions of the back metal layer 142 may fly off onto nearby solder interconnects during the sputtering process, resulting in unintended connections. A laser process may be used to remove portions of the back metal layer 142. In some implementations, the laser process may also be used to form cavities in the plurality of solder interconnects 130. Step 9 of FIG. 5D illustrates and describes one example of removing portions of the back metal layer to form cavities in the solder interconnects.

[0059] The method bonds (at 725) a solder interconnect (e.g., 130) to the substrate 102. Additional solder interconnects 130 can be added, for example to re-form a plurality of solder interconnects 130. Portions of additional solder interconnects can be formed within the cavities of the solder interconnects formed (at 720). A solder reflow process can be used to form the additional solder interconnects. Step 10 of FIG. 5D illustrates and describes one embodiment of adding and bonding a solder interconnect to a substrate.

[0060] The method bonds (at 730) a first solder interconnect (e.g., 144) to the back metal layer 142. A solder reflow process can be used to form and bond the first solder interconnect 144 to the back metal layer 142. Step 11 of Figure 5E illustrates and describes one embodiment of the first solder interconnect being bonded to the back metal layer.

[0061] The packages described in this disclosure (eg, 100, 400) can be manufactured one by one, or can be manufactured together as part of one or more wafers and then singulated into individual packages.

[0062] Exemplary Sequence for Manufacturing a Substrate In some implementations, manufacturing a substrate includes several processes. Figures 8A and 8B show an example sequence for providing or manufacturing a substrate. In some implementations, the sequence of Figures 8A and 8B can be used to provide or manufacture a substrate 102. However, the process of Figures 8A and 8B can also be used to manufacture any of the substrates described in this disclosure.

[0063] 8A-8B may be combined with one or more steps to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0064] 8A , stage 1 illustrates the state after carrier 800 is prepared. A seed layer 801 and interconnects 802 may be disposed on carrier 800. Interconnects 802 may be disposed on seed layer 801. A plating process and an etching process may be used to form interconnects 802. In some implementations, carrier 800 may be provided with seed layer 801 and a metal layer that is patterned to form interconnects 802. Interconnects 802 may represent at least some interconnects from the plurality of interconnects 122.

[0065] Stage 2 shows the state after a dielectric layer 820 is formed over the carrier 800, the seed layer 801, and the interconnects 802. A deposition and / or lamination process may be used to form the dielectric layer 820. The dielectric layer 820 may include a prepreg and / or a polyimide. The dielectric layer 820 may include a photosensitive dielectric. However, different implementations may use different materials for the dielectric layer.

[0066] Stage 3 shows the state after a number of cavities 810 have been formed in the dielectric layer 820. The number of cavities 810 can be formed using an etching process (e.g., a photoetching process) or a laser process.

[0067] Stage 4 shows the state after interconnects 812 have been formed in and on dielectric layer 820, including in and over the plurality of cavities 810. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0068] Stage 5 shows the state after dielectric layer 822 is formed over dielectric layer 820 and interconnect 812. A deposition and / or lamination process may be used to form dielectric layer 822. Dielectric layer 822 may include prepreg and / or polyimide. Dielectric layer 822 may include a photosensitive dielectric. However, different implementations may use different materials for the dielectric layer.

[0069] 8B, stage 6 shows the state after a plurality of cavities 830 have been formed in the dielectric layer 822. The plurality of cavities 830 can be formed using an etching process (e.g., a photoetching process) or a laser process.

[0070] Stage 7 shows the state after interconnects 814 are formed in and on dielectric layer 822, including in and over cavities 830. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects. Interconnects 802, 812, and / or 814 may be represented by interconnects 122. Dielectric layer 820 and / or 822 may be represented by at least one dielectric layer 120. At least one dielectric layer 120 may include a photosensitive dielectric. At least one dielectric layer 120 may include a prepreg and / or a polyimide.

[0071] Stage 8 shows the state after the carrier 800 has been detached (e.g., separated, removed, ground) from the at least one dielectric layer 120 and the seed layer 801, and portions of the seed layer 801 have been removed (e.g., etched) to leave a substrate 102 including at least one dielectric layer 120 and multiple interconnects 122.

[0072] In some implementations, the substrate may include a solder resist layer. Stage 9 shows the state after solder resist layer 124 and solder resist layer 126 are formed on substrate 102. A deposition process may be used to form solder resist layer 124 and solder resist layer 126. In some implementations, zero or one solder resist layer may be formed on at least one dielectric layer 120.

[0073] Different implementations may use different processes to form the metal layers and / or interconnects. In some implementations, the metal layers may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process.

[0074] 1 is an exemplary flow diagram of a method for manufacturing a substrate; In some implementations, manufacturing a substrate includes several processes. Figure 9 shows an example flow diagram of a method 900 for providing or manufacturing a substrate. In some implementations, the method 900 of Figure 9 can be used to provide or manufacture the substrate of Figures 1-4. For example, the method 900 of Figure 9 can be used to manufacture the substrate 102.

[0075] It should be noted that the method 900 of Figure 9 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate, and in some implementations, the order of the processes may be changed or modified.

[0076] The method provides (at 905) a carrier (e.g., 800). Different implementations can use different materials for the carrier 800. The carrier 800 can include a seed layer (e.g., 801). The seed layer 801 can include a metal (e.g., copper). The carrier can include a substrate, glass, quartz, and / or a carrier tape. Step 1 of FIG. 8A illustrates and describes one example of a carrier having a seed layer disposed thereon.

[0077] The method forms and patterns (at 910) interconnects on the carrier 800 and the seed layer 801. The metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer may include a metal layer. The metal layer is disposed on the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 402). Step 1 of FIG. 8A illustrates and describes one example of forming and patterning interconnects on the seed layer and the carrier.

[0078] The method forms (at 915) a dielectric layer 820 over the seed layer 801, the carrier 800, and the interconnect 802. A deposition and / or lamination process may be used to form the dielectric layer 820. The dielectric layer 820 may include prepreg and / or polyimide. The dielectric layer 820 may include a photosensitive dielectric. Forming the dielectric layer 820 may also include forming a plurality of cavities (e.g., 810) in the dielectric layer 820. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 2 and 3 of FIG. 8A illustrate and describe one embodiment of forming a dielectric layer and cavities in the dielectric layer.

[0079] The method forms (at 920) an interconnect in and over the dielectric layer. For example, interconnect 812 may be formed in and over dielectric layer 820. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity in the dielectric layer. Step 4 of FIG. 8A illustrates and describes one embodiment of forming an interconnect in and over the dielectric layer.

[0080] The method forms (at 925) a dielectric layer 822 over the dielectric layer 820 and the interconnect 812. A deposition and / or lamination process may be used to form the dielectric layer 822. The dielectric layer 822 may include prepreg and / or polyimide. The dielectric layer 822 may include a photosensitive dielectric. Forming the dielectric layer 822 may also include forming a plurality of cavities (e.g., 830) in the dielectric layer 822. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 5 and 6 of FIG. 8A and FIG. 8B illustrate and describe one embodiment of forming the dielectric layer and the cavities in the dielectric layer.

[0081] The method forms (at 930) an interconnect in and over the dielectric layer. For example, interconnect 814 may be formed in and over dielectric layer 822. A plating process may be used to form the interconnect. Forming the interconnect may include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnect may also include forming the interconnect in a cavity in the dielectric layer. Step 8 of FIG. 8B illustrates and describes one embodiment of forming an interconnect in and over a dielectric layer.

[0082] The method separates (at 935) the carrier (e.g., 800) from the seed layer (e.g., 801). The carrier 800 may be separated and / or ground. The method may also remove (at 935) portions of the seed layer (e.g., 801). An etching process may be used to remove portions of the seed layer 801. Step 8 of FIG. 8B illustrates and describes one embodiment of separating the carrier and removing the seed layer.

[0083] Different implementations may use different processes to form the metal layer, in some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0084] Exemplary Electronic Devices FIG. 10 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1002, a laptop computer device 1004, a fixed location terminal device 1006, a wearable device 1008, or an automotive vehicle 1010 may include a device 1000 as described herein. The device 1000 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1002, 1004, 1006, and 1008 and the vehicle 1010 illustrated in FIG. 10 are merely examples. Other electronic devices may also feature device 1000, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous cars), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0085] One or more of the components, processes, features, and / or functions shown in Figures 1-4, 5A-5E, 6A, 6B, 7, 8A, 8B, and / or 9, 10 may be rearranged and / or combined into a single component, process, feature, or function, or may be embodied as several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 1-4, 5A-5E, 6A, 6B, 7, 8A, 8B, and / or 9, 10 and the corresponding descriptions thereof in this disclosure are not limited to dies and / or ICs. In some implementations, devices and / or integrated devices can be manufactured, fabricated, prepared, and / or produced using Figures 1-4, 5A-5E, 6A, 6B, 7, 8A, 8B, and / or 9, 10 and corresponding descriptions thereof. In some implementations, the devices can include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0086] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0087] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even if they are not in direct physical contact with each other. Object A, which is coupled to object B, may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two objects that are electrically coupled may or may not propagate electrical current between the two objects. The use of the terms "first," "second," "third," and "fourth" (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The terms "encapsulate," "encapsulating," and / or any derivatives mean that an object may partially or completely encapsulate another object. The terms "top" and "bottom" are arbitrary.A component disposed on top may be disposed on top of a component disposed on bottom. A top component may also be considered a bottom component, and vice versa. As described in this disclosure, a first component disposed "over" a second component may mean that the first component is disposed above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be disposed on (e.g., above) a first surface of the second component, and a third component may be disposed on (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being disposed on another component, the term "over" as used in this application may be used to mean a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but is not in direct contact with the second component, (2) that the first component is present on (e.g., on a surface of) the second component, and / or (3) that the first component is present within (e.g., embedded within) the second component. A first component that is disposed "in" a second component can be partially disposed within the second component or can be completely disposed within the second component. A value that is about X to XX can mean a value that is between X and XX, inclusive of X and XX. The value between X and XX can be discrete or continuous. The term "about 'value X'" or "approximately value X" as used in this disclosure means within a range of 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0088] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace (e.g., a trace interconnect), a via (e.g., a via interconnect), a pad (e.g., a pad interconnect), a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, the interconnects may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process.

[0089] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0090] In the following, further examples are described to facilitate understanding of the invention.

[0091] Aspect 1: A device comprising a package and a board coupled to the board. The package includes a substrate having a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a backside metal layer coupled to a backside of the integrated device, a first solder interconnect coupled to the backside metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The board is coupled to the package via the plurality of solder interconnects, and the first solder interconnect is coupled to the board.

[0092] Aspect 2: The device of aspect 1, wherein the package and board are configured to dissipate heat from the integrated device through the back metal layer, the first solder interconnect, and the board.

[0093] Aspect 3: The device of aspects 1 and 2, wherein the board includes a plurality of board interconnects, and the package and board are configured to dissipate heat from the integrated device through the back metal layer, the first solder interconnect, and at least one board interconnect from the plurality of board interconnects.

[0094] Example 4: The device of Examples 1-3, wherein the back metal layer and the first solder interconnect are configured to be coupled to ground, and the back metal layer is configured as an electromagnetic interference (EMI) shield.

[0095] Embodiment 5: The device of embodiments 1-4, wherein the back surface of the integrated device faces the board.

[0096] Example 6: The device of Examples 1-5, wherein the package further includes a first encapsulation layer disposed over the first surface of the substrate and a second encapsulation layer disposed over the second surface of the substrate.

[0097] Embodiment 7: The device of embodiment 6, wherein the package further comprises a metal layer disposed on a surface of the first encapsulation layer.

[0098] Example 8: The device of example 7, wherein the metal layer is configured to be coupled to ground, the metal layer being configured as an electromagnetic interference (EMI) shield.

[0099] Aspect 9: The device of aspects 1-8, wherein the integrated device includes at least one die substrate via coupled to the back metal layer, and the package and board are configured to dissipate heat from the integrated device through the at least one die substrate via, the back metal layer, the first solder interconnect, and the board.

[0100] Aspect 10: The apparatus of aspects 1-9, wherein the device includes a particular device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle.

[0101] Example 11: A package comprising: a substrate having a first surface and a second surface; a passive component bonded to the first surface of the substrate; an integrated device bonded to the second surface of the substrate; a back metal layer bonded to a back surface of the integrated device; a first solder interconnect bonded to the back metal layer; and a plurality of solder interconnects bonded to the second surface of the substrate.

[0102] Example 12: The package of example 11, wherein the package is configured to dissipate heat from the integrated device through the back metal layer and the first solder interconnect.

[0103] Example 13: The package of Examples 11 and 12, wherein the back metal layer and the first solder interconnect are configured to be coupled to ground, and the back metal layer is configured as an electromagnetic interference (EMI) shield.

[0104] Embodiment 14: The package of embodiments 11-13, wherein the back surface of the integrated device faces away from the substrate.

[0105] Embodiment 15: The package of embodiments 11-14, wherein the package further includes a first encapsulation layer disposed over the first surface of the substrate and a second encapsulation layer disposed over the second surface of the substrate.

[0106] Example 16: The package of Example 15, further comprising a metal layer disposed on a surface of the first encapsulation layer.

[0107] Example 17: The package of example 16, wherein the metal layer is configured to be coupled to ground, the metal layer being configured as an electromagnetic interference (EMI) shield.

[0108] Example 18: The package of Examples 11-17, wherein the integrated device includes at least one die substrate via coupled to the back metal layer.

[0109] Aspect 19: A method including providing a package comprising: a substrate including a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a backside metal layer coupled to a backside of the integrated device, a first solder interconnect coupled to the backside metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The method further comprises coupling the package to a board coupled via the plurality of solder interconnects, the first solder interconnect coupled to the board.

[0110] Example 20: The method of example 19, wherein the package and board are configured to dissipate heat from the integrated device through the back metal layer, the first solder interconnect, and the board.

[0111] Aspect 21: The method of aspects 19 and 20, wherein the board includes a plurality of board interconnects, and the package and board are configured to dissipate heat from the integrated device through the back metal layer, the first solder interconnect, and at least one board interconnect from the plurality of board interconnects.

[0112] Example 22: The method of Examples 19-21, wherein the back metal layer and the first solder interconnect are configured to be coupled to ground.

[0113] Example 23: The method of examples 19-22, wherein the back surface of the integrated device faces the board.

[0114] Example 24: The method of examples 19-23, wherein the package further comprises a first encapsulation layer disposed over the first surface of the substrate and a second encapsulation layer disposed over the second surface of the substrate.

[0115] Example 25: The method of example 24, wherein the package further comprises a metal layer disposed on a surface of the first encapsulation layer.

[0116] Various features of the present disclosure described herein can be implemented in various systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0117] 100, 400 packages 102 Substrate 104 Integrated Devices 105, 107, 109 Passive components 106, 108 Encapsulation layer 110 Board 111, 120 Dielectric layer 112, 112a Board Interconnect 122 Interconnector 124, 126 Solder resist layer 130, 140, 150, 170, 190 Solder Interconnects 142 Back metal layer 144 first solder interconnect 204 Die Substrate 206 Circuit layer 208 Die interconnect part 242 Die Substrate Vias 408 Metal layer 640 Mask 800 Carriers 801 Seed Layer 802, 812, 814 interconnects 810, 830 Cavity 820, 822 Dielectric layer 1000 devices 1002 Mobile Phone Device 1004 Laptop Computer Device 1006 Fixed Location Terminal Device 1008 Wearable Devices 1010 Motor Vehicles

Claims

1. A package, a substrate including a first surface and a second surface; a passive component coupled to the first surface of the substrate; an integrated device coupled to the second surface of the substrate; a backside metal layer coupled to a backside of the integrated device; a first solder interconnect coupled to the backside metal layer; a plurality of solder interconnects coupled to the second surface of the substrate; an encapsulation layer disposed on the second surface of the substrate; the encapsulation layer partially encapsulates the plurality of solder interconnects; the encapsulation layer includes a surface coplanar with a back surface of the integrated device; and a board coupled to the package via the plurality of solder interconnects, the first solder interconnect being coupled to the board.

2. The device of claim 1 , wherein the package and the board are configured to dissipate heat from the integrated device through the backside metal layer, the first solder interconnects, and the board.

3. the board includes a plurality of board interconnects; the package and the board are configured to dissipate heat from the integrated device through the backside metal layer, the first solder interconnect, and at least one board interconnect from the plurality of board interconnects. The device of claim 2 .

4. the backside metal layer and the first solder interconnect are configured to be coupled to ground; the back metal layer is configured as an electromagnetic interference (EMI) shield; The device of claim 1 .

5. The device of claim 1 , wherein the back surface of the integrated device faces the board.

6. The package: a first encapsulation layer disposed over the first surface of the substrate; The device of claim 1 , further comprising: a second encapsulation layer disposed over the second surface of the substrate.

7. The device of claim 6 , wherein the package further comprises a metal layer disposed on a surface of the first encapsulation layer.

8. the metal layer is configured to be coupled to ground; the metal layer is configured as an electromagnetic interference (EMI) shield; The device of claim 7.

9. the integrated device includes at least one die substrate via coupled to the backside metal layer; the package and the board are configured to dissipate heat from the integrated device through the at least one die substrate via, the backside metal layer, the first solder interconnect, and the board. The device of claim 1 .

10. A package, a substrate including a first surface and a second surface; a passive component coupled to the first surface of the substrate; an integrated device coupled to the second surface of the substrate; a backside metal layer coupled to a backside of the integrated device; a first solder interconnect coupled to the backside metal layer; a plurality of solder interconnects coupled to the second surface of the substrate; an encapsulation layer disposed on the second surface of the substrate; the encapsulation layer partially encapsulates the plurality of solder interconnects; providing a package, the encapsulation layer including a surface coplanar with a back surface of the integrated device; and coupling the package to a board coupled via the plurality of solder interconnects, the first solder interconnect being coupled to the board.

11. The method of claim 10 , wherein the package and the board are configured to dissipate heat from the integrated device through the backside metal layer, the first solder interconnects, and the board.

12. the board includes a plurality of board interconnects; the package and the board are configured to dissipate heat from the integrated device through the backside metal layer, the first solder interconnect, and at least one board interconnect from the plurality of board interconnects. The method of claim 11.

13. The method of claim 10 , wherein the backside metal layer and the first solder interconnect are configured to be coupled to ground.

14. The method of claim 10 , wherein the back surface of the integrated device faces the board.

15. The package: a first encapsulation layer disposed over the first surface of the substrate; a second encapsulation layer disposed over the second surface of the substrate; The method of claim 10, wherein the package preferably further comprises a metal layer disposed on a surface of the first encapsulation layer.

Images