Improvements in or relating to quantum computing

Abstract

According to the present invention, there is provided a timing system for an ion trap quantum computer comprising: a clock that outputs a timing signal of period t; a plurality of delay lines coupled to the clock, each configured to input a different delay less than t; and a delay selection mechanism configured to select the delay, wherein the delay through each of the delay lines is a different fraction of the period t.

Description

[Technical field]

[0001] The present invention relates to providing a precisely timed ion trap quantum computer. Summary of the Invention

[0002] In general, unlike so-called "classical computing", quantum computing relies on the quantum mechanical properties of particles or matter to produce or modify data. Data can be represented by quantum bits or "qubits", which are two-state quantum mechanical systems. Unlike classical computing, qubits can be in a superposition of quantum states. Another feature of quantum computing is entanglement between qubits, where the state of one particle or atom is influenced by another particle or atom.

[0003] Quantum mechanical qubits can simultaneously encode information as combinations of zeros and ones. Such properties enable many complex numerical applications that have traditionally been difficult with classical computers. Examples include artificial intelligence, image processing and recognition, cryptography, or secure communications.

[0004] Within an ionic hyperfine electronic state (Zeeman split state) this can be revealed by the use of magnetic fields and the different electronic levels used as different qubit states, and the electrons moved between the levels using microwave radiation or lasers.

[0005] In an ion trap quantum computer (quantum charge coupled device), an ion trap can be used to control ions used in quantum computing, where surface electrodes are used to generate an electric field to manipulate and trap ions suspended in free space. The surface electrode potential of the ion trap is in turn controlled by a DAC. State-of-the-art quantum computers use many DACs of the same type, for example, 16-bit DACs with update rates of over 1 MHz.

[0006] Each individual electrode is independently controllable, and each electrode has a corresponding DAC coupled to it. The timing of setting the electrode voltages must be carefully controlled, and a clock signal is sent to each DAC to ensure that the timing of the DAC signals is carefully controlled.

[0007] Clock signals in quantum systems are often updated at a rate of 1 MHz. Thus, the signals to the electrodes may only be updated every 1 μs. However, for nonadiabatic motion, the signal can be updated at a rate of 10 -6 It is necessary to update the signal with a higher precision than every s.

[0008] For non-adiabatic shuttling, the electrode voltages must be applied at times to match the ion oscillation phase or in such a way as to precisely add or remove momentum impulses to the ions. If the electrode voltages are not applied at the correct time, additional oscillations will occur, which in turn will generate kinetic noise.

[0009] It is therefore an object of the present invention to enable non-adiabatic shuttering with reduced motion noise.

[0010] In accordance with the present invention there is provided an ion trap quantum processor comprising: an ion trap with a plurality of DACs, each coupled to an electrode, the ion trap having a motional (secular) trapping frequency of period t; a clock outputting a timing signal of period tT; a plurality of delay lines coupled to the clock, each configured to input a different delay less than t; and a delay selection mechanism coupled to one of the plurality of DACs and configured to select a delay, wherein the delay through each of the delay lines is different.

[0011] The delay may be less than 10 μs, or preferably less than 2 μs, so as to be less than the period of the trapping frequency for any ion.

[0012] The delay may be a fraction (less than 1) of the period t. Alternatively, it may be a fraction (less than 1) of the period T. This allows for different delays, which are preferably a fraction of the period of the trapping frequency to be selected. The processor may be configured to be an ion trap for a particular ion. As an example, the ion trap may be configured to be an ion trap for ytterbium ions, and the delay may be a fraction of the trapping frequency for ytterbium ions.

[0013] There may be n delay lines, each having a different delay of tx / n, where x is a positive integer from 0 to n-1. Alternatively, there may be a non-linear arrangement of delays for a particular clock signal line.

[0014] The delay selection mechanism is coupled to a first DAC that is coupled to the electrode to apply a precisely timed voltage. There may be a primary buffer coupled between the clock and the delay line. Additionally, there may be a secondary buffer disposed after the delay selection mechanism.

[0015] Each clock signal line may comprise a primary buffer, a plurality of delay lines coupled to the primary buffer, each configured to input a different delay less than t, and a delay selection mechanism configured to select the delay for a particular DAC. Each clock signal line receives a clock signal from a central clock.

[0016] There is preferably a controller which controls the delay selection mechanism to select a delay line within each clock signal line.

[0017] Each DAC and electrode may have a corresponding primary buffer, a plurality of delay lines, and a delay selection mechanism, and the clock outputs the same timing signal to each primary buffer. The processor may form part of a quantum computer.

[0018] In accordance with the present invention, there is provided a method for generating a timing signal in a trapped ion quantum processor comprising an ion trap having a plurality of DACs each coupled to an electrode, the ion trap having a kinetic trapping frequency of period t, the method including generating a clock signal of period T; generating a plurality of delays less than t in a plurality of lines, each of the delays being a different fraction less than t; selecting one of the delays to add to the clock signal; and sending the modified clock signal to one of the plurality of DACs.

[0019] The DAC may include a DC DAC and an RF DAC, and the method may include the DC DAC applying a DC signal to the multiple electrodes, and the RF DAC applying an RF signal to the multiple electrodes. [Brief description of the drawings]

[0020] [Figure 1] 1 shows an array of electrodes for use in connection with the present invention. [Diagram 2] 1 shows a clock delay line according to the present invention. [Diagram 3] 1 shows an arrangement according to the present invention.

[0021] Referring to FIG. 1, there is an exemplary arrangement of electrodes for use in connection with the present invention. FIG. 1 shows an x-junction device 12 in an ion trap quantum computer 10. The x-junction 12 comprises a number of electrodes 22 configured to trap ions in a region of the x-junction device 12. Each electrode 22 is driven by a DAC to perform a function of the region of the x-junction device 12. The x-junction device 12 is divided into regions. The regions of the x-junction device 12 can be divided into crystal operations 14, junction shuttling 16, logic regions / gate zones 18, and linear shuttling 20 depending on the function performed in each region.

[0022] The x-junction is divided into four sections: a north section (above center as shown in FIG. 1), an east section (right of center as shown in FIG. 1), a south section (below center as shown in FIG. 1), and a west section (left of center as shown in FIG. 1). If there are no ions in a section, no signal may be applied to any of the electrodes. Alternatively, there may be a signal, but no change in signal. Similarly, if an ion is being shuttled from the left to the center, no signal may be applied to the electrodes in the northeast or south sections.

[0023] The ion trap includes both DC and radio frequency (RF) DACs that apply signals to the respective electrodes to control the position of the ions in three dimensions. The electrodes coupled to the DC DACs control the position of the ions in the longitudinal direction, and the electrodes coupled to the RF DACs control the position of the ions in the axial direction. The RF electrodes typically emit signals in the range of 10-40 MHz.

[0024] The radio frequency signal may be in the range of 10-40 MHz which generates the axial trapping frequency, for example this may be 3 MHz.

[0025] The DC DAC has a maximum voltage Vdac. The usable (or maximum) range of the DC electrodes controls the gradient of the potential created, and thus the kinetic trapping frequency (for a particular type of ion), which is the frequency at which the ions physically oscillate longitudinally. This may also be called the secular frequency. Typical kinetic trapping frequencies may be in the range of 100-1000 kHz, with an exemplary example being 500 kHz. The period of the kinetic trapping frequency is given by t. Thus, the kinetic trapping frequency is controlled by the longitudinal voltage gradient.

[0026] The ion trap can be configured for specific ions. Examples of ions that may be used are: 171 Yb + , 40 Ca + , 43 Ca + ,9 Be + , Sr + , Hg + The ion trap may be configured for a particular ion. Alternatively, the ion trap may be configured with a delay of less than 10 μs or less than 2 μs that is a fraction of the motional trapping frequency for any type of trapped ion.

[0027] 2 shows a clock signal line 200 according to the present invention. A clock 50 generates a clock signal. In this embodiment, the clock frequency is 100 kHz, but alternative clock frequencies can be used according to the application. The clock signal is a pulse signal, but other signals can be used.

[0028] The clock signal is fed to a buffer 21 and then split into a number of clock delay lines 220, 221, 222, 223. Each of these clock delay lines introduces a delay that is a fraction of a period of the kinetic trapping frequency t. In this embodiment, the first delay line 220 introduces no delay, the second delay line 221 introduces a delay of 0.5 μs, the third delay line introduces a delay of 1 μs and the third delay line introduces a delay of 1.5 μs. The use of delays that are fractions of the kinetic trapping frequency allows the signal to be synchronized to a specific point on the trap oscillation and thus any signal applied to the trapped ion qubit can be precisely timed to the oscillation of the trapped ion qubit. The use of appropriate delays can ensure that any gate function is applied non-adiabatically.

[0029] This embodiment uses four delay lines, but any number of delay lines can be used to generate the correct delay. In this embodiment, the delays introduced by the different delay lines are divided evenly, i.e., for n delay lines operating in a system with a motional trap frequency of period t, each delay line has a delay of (x / n)t for 0≦x≦n-1. However, alternative nonlinear distributions of delays can be used and different delays can be selected as required. For example, if a delay of 5t / 7 is required for a non-adiabatic application.

[0030] Next there is a delay selector 23 which selects which delay line is used and sent to a second clock buffer 24. The delay selector is controlled by a controller 60 which controls which delay line is selected.

[0031] The resulting delayed clock signal is sent to a DAC 25 which controls the electrodes 26 .

[0032] 3 shows an arrangement in which a single clock 50 signal is transmitted to two different clock signal lines: a first clock signal line 200 has four clock delay lines (as shown in FIG. 2) and a second clock signal line 300 has five clock delay lines 320, 321, 322, 323, 324 with delays of 0, 0.4 μs, 0.8 μs, 1.2 μs, and 1.6 μs.

[0033] Each clock signal line has a first buffer 21, 31 and a delay selector 23, 33. The delay selector for each line is controlled by a controller 60. The controller 60 controls each clock signal line independently.

[0034] Each clock signal line controls a signal to a different DAC 25, 35 which sends a voltage signal to a different electrode 26, 36. The same clock signal is used, but different fractional delays can be applied to the different clock signal lines and thus different timings can be applied to the different electrodes. For example, if an ion is being shuttled between gate zones, different timings need to be applied to different electrodes along the ion's path. The present invention allows precise timing (to a greater accuracy than allowed by the clock signal) to be applied to each electrode and therefore to the trapped ion.

[0035] The more delay lines there are, the more different timing delays can be applied to the clock signal lines. More delay lines can result in more different precise timing possibilities, but an alternative is to include only the clock delay lines with the delays used. For example, FIG. 1 shows a series of electrodes, where a different delay can be used on the clock signal line for each electrode along the path.

[0036] The above embodiment uses a delay selector placed after the delay line. However, an alternative is to place the delay selector between the first buffer and the delay line, which avoids sending the clock signal to all delay lines all the time, reducing noise in the system.

[0037] As used herein, "and / or" should be taken as a specific disclosure of each of the two specified features or components with or without the other. For example, "A and / or B" should be taken as a specific disclosure of each of (i) A, (ii) B, and (iii) A and B, as if each were individually set forth herein.

[0038] Unless the context dictates otherwise, the above feature descriptions and definitions are not limited to any particular aspect or embodiment of the invention, but apply equally to all aspects and embodiments described.

[0039] Those skilled in the art will further appreciate that the present invention has been described by way of example with reference to certain embodiments, and is not limited to the disclosed embodiments, alternative embodiments may be constructed without departing from the scope of the invention as defined in the appended claims.

Claims

1. A quantum computer, 1. A quantum processor, comprising: (a) a clock configured to transmit a clock signal; (b) a plurality of delay signal lines, each delay signal line of the plurality of delay signal lines configured to receive the clock signal and add a different delay to the clock signal to generate a modified clock signal, thereby forming a plurality of modified clock signals; (c) a delay selection mechanism configured to be coupled to one or more modules and configured to select a modified clock signal from the plurality of modified clock signals directed to the one or more modules; and a quantum processor communicatively coupled to A quantum computer equipped with

2. The system described in claim 1, wherein the one or more modules further comprise one or more digital-to-analog converters (DACs).

3. The system of claim 1, wherein the delay selection mechanism is configured to select and modify a clock signal from the plurality of modified clock signals to control the timing of gate operations.

4. The system of claim 1, wherein the clock signal is a pulse signal.

5. The system of claim 1, further comprising a buffer configured to transmit the clock signal to each delay signal line of the plurality of delay signal lines.

6. The system of claim 1, wherein each delay associated with the plurality of delay signal lines is less than 10 μs.

7. The system of claim 1, further comprising an ion trap, the ion trap comprising a DAC and an electrode, the electrode corresponding to the DAC.

8. The system of claim 7, wherein the ion trap is configured to have a motional trapping frequency of period t.

9. The system of claim 8, wherein the modified clock signal is less than t.

10. The system described in claim 9, wherein the delay of each delay signal line of the plurality of delay signal lines is t*x / n, where n is the number of delay signal lines of the plurality of delay signal lines, and x is a positive integer between 0 and n-1.

11. The system described in claim 7, wherein the ion trap further comprises a plurality of DACs, each of which has a corresponding electrode, a plurality of delay lines, and a delay selection mechanism, and the clock is configured to output signals of substantially the same timing to each of the plurality of delay lines.

12. The system of claim 11, wherein the ion trap includes a plurality of direct current (DC) DACs and a plurality of radio frequency (RF) DACs.

13. The system of claim 8, wherein the motional trapping frequency is between about 100 kHz and about 1000 kHz.

14. The system described in claim 12, wherein one RF electrode corresponding to one RF DAC among the plurality of RF DACs is configured to emit a signal having a frequency of approximately 10 MHz to approximately 40 MHz.

15. The system of claim 11, wherein a plurality of electrodes corresponding to the plurality of DACs are arranged within an x-junction device.

16. The system described in claim 15, wherein the x-junction device has a plurality of regions, and the electrode is configured to capture ions in one of the plurality of regions of the x-junction device.

17. The system of claim 16, wherein the region of the x-junction device is a crystal operating region, a junction shuttling region, a logic region / gate zone region, or a linear shuttling region.

18. The system of claim 17, wherein the x-junction device has four sections.

19. The system described in claim 18, configured to selectively apply a signal to one of the four sections based at least in part on the occupancy of ions within the section.

20. The system described in claim 7, wherein the ion trap is configured to trap ions selected from the group consisting of 171 Yb +, 40 Ca +, 43 Ca +, 9 Be +, Sr +, and Hg +.

21. A method comprising: (a) generating a plurality of clock signals; (b) adding a different delay to each clock signal of the plurality of clock signals to generate a plurality of modified clock signals; (c) selecting, by a delay selection mechanism, a modified clock signal from the plurality of modified clock signals; (d) applying the modified clock signal to a digital-to-analog converter (DAC), the DAC configured to control gate operations in a quantum processor; A method comprising:

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