STACKED DIE INTEGRATED CIRCUIT (IC) PACKAGE USING INTERPOSER FOR BONDING TOP STACKED DIE TO PACKAGE SUBSTRATE FOR PACKAGE HEIGHT REDUCTION, AND ASSOCIATED FABRICATION METHODS - Patent application

Abstract

A stacked die integrated circuit (IC) package using an interposer for electrically coupling an upper stacked die to a package substrate for package height reduction, and related fabrication methods. The IC package includes an interposer to reduce the height of the IC package while providing a stacked die electrically coupled to the package substrate. The stacked die is disposed between the package substrate and the interposer. One or more wires are coupled (e.g., wire bonded) between the upper die and the interposer to provide an electrical connection between the upper die and the interposer. One or more electrical interconnects (e.g., conductive pillars) are coupled between the interposer and the package substrate to route the electrical connection between the upper die and the package substrate. Thus, the upper die can be electrically coupled to the package substrate without requiring additional clearance areas for wire bonds above the upper die.

Description

[Technical field]

[0001] Priority Application This application claims priority to U.S. patent application Ser. No. 17 / 409,481, filed Aug. 23, 2021, entitled “STACKED DIE INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING INTERPOSER FOR COUPLING AN UPPER STACKED DIE(S) TO A PACKAGE SUBSTRATE FOR PACKAGE HEIGHT REDUCTION, AND RELATED FABRICATION METHODS,” which is incorporated by reference herein in its entirety. [Background technology]

[0002] I. Field of Disclosure The field of the disclosure relates to integrated circuit (IC) packages, and more particularly, to wire bonding of semiconductor dies to package substrates in IC packages.

[0003] II. Background technology Integrated circuits (ICs) are the basis of electronic devices. ICs are packaged in IC packages, also called "semiconductor packages" or "chip packages." An IC package includes one or more semiconductor dice ("die" or "dice") mounted and electrically coupled to a package substrate for providing physical support and an electrical interface to the die as an IC. The package substrate includes one or more metallization layers including electrical traces (e.g., metal lines), and vertical interconnect accesses (vias) couple the electrical traces to each other between adjacent metallization layers to provide an electrical interface between the die. The die are electrically interfaced to metal interconnects exposed on the top or outer layer of the package substrate for electrically coupling the semiconductor die to the electrical traces of the package substrate. The package substrate includes an outer metallization layer coupled to external metal interconnects (e.g., solder bumps) for providing an external interface between the die in the IC package for mounting the IC package to a circuit board for interfacing the die with other circuitry.

[0004] Some IC packages are known as "hybrid" IC packages that contain multiple dies for different purposes or applications. For example, a hybrid IC package may include a modem die as part of a front-end circuit to support a communications interface. A hybrid IC package may also include one or more memory dies that provide memory to support data storage and access by the modem die, such as for buffering and transmitting modulated and / or demodulated data. Thus, in these hybrid IC packages, it is conventional to stack multiple dies on top of each other in the IC package. The bottom die that is directly adjacent to the package substrate of the IC package is electrically coupled by die interconnects to metal interconnects of the upper metallization layer of the package substrate. Other stacked dies that are not directly adjacent to the package substrate of the IC package may be electrically coupled to the metallization layer of the package substrate by wire bonds. The electrical connections between the memory die and the modem die are formed by electrical connections in the package substrate. Summary of the Invention [Means for solving the problem]

[0005] Aspects disclosed herein include a stacked die integrated circuit (IC) package that uses an interposer for electrically coupling an upper stacked die to a package substrate for package height reduction. Related fabrication methods are also disclosed. The IC package includes a package substrate that supports the stacked die. The package substrate includes one or more metallization layers that each include metal interconnects for providing electrical signal routing between external interconnects and the die and between the dies within the IC package. The stacked die is electrically coupled to the package substrate for signal routing. A lower die in the IC package may be electrically coupled directly to the package substrate (e.g., by interconnect bumps) and an active surface of the lower die may be coupled to metal interconnects of an upper metallization layer of the package substrate. However, an upper die stacked above the lower die in the IC package is not positioned directly adjacent to the package substrate. Wire bonds may be used to couple the active surface of the upper die to the package substrate. However, the wire bonds may need to be oriented to extend above the upper die so that they have enough clearance area to extend outward and then downward into the package substrate without interfering with the lower die or other package components. The wire bonds may also require a minimum bend radius to avoid damage, which requires some additional clearance area above the upper die beyond the normal area tolerance between the upper die and the top surface of the IC package overmold. This additional clearance area contributes to the overall height of the IC package and may be undesirable.

[0006] Thus, in an exemplary embodiment, an IC package includes an interposer to reduce the height of the IC package while still providing a stacked die configuration electrically coupled to the package substrate. The stacked die is disposed between the package substrate and the interposer. One or more wires are coupled (e.g., wire bonded) between the active surface of the upper die and the interposer to provide an electrical connection between the upper die and the interposer. One or more electrical interconnects (e.g., conductive pillars) are coupled between the interposer and the package substrate to route an electrical connection between the wires coupled to the upper die and the package substrate. In this manner, the upper die can be electrically coupled to the package substrate without requiring additional clearance areas for coupling wire bonds to the upper die and to the package substrate. The height of the interposer added to the overall height of the IC package may be less than the height of the clearance areas required to wire bond the upper die to the package substrate.

[0007] In this regard, in one exemplary embodiment, an IC package is disclosed. The IC package includes a package substrate. The IC package also includes an interposer. The IC package also includes a first die electrically coupled to the package substrate. The IC package also includes a second die disposed between the first die and the interposer. The IC package also includes one or more second wires coupled to the second die and the interposer. The IC package also includes one or more electrical interconnects coupled to the interposer and the package substrate, each electrically coupling a second wire of the one or more second wires to the package substrate.

[0008] In another exemplary aspect, a method of fabricating an IC package is disclosed. The method includes providing a package substrate. The method also includes providing an interposer. The method also includes electrically coupling a first die to the package substrate. The method also includes disposing a second die between the first die and the interposer. The method also includes coupling one or more second wires to the second die and the interposer. The method also includes coupling one or more electrical interconnects to the package substrate and the interposer to electrically couple a second wire of the one or more second wires to the package substrate. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 1 is a side view of an exemplary integrated circuit (IC) package that includes two stacked semiconductor dies ("die") between a package substrate and an interposer, where the lower die is electrically coupled directly to the package substrate and the upper die is electrically coupled to the package substrate by the interposer for package height reduction. [Figure 1B] FIG. 1 is a side view of an exemplary integrated circuit (IC) package that includes two stacked semiconductor dies ("die") between a package substrate and an interposer, where the lower die is electrically coupled directly to the package substrate and the upper die is electrically coupled to the package substrate by the interposer for package height reduction. [Figure 2A] FIG. 2 is a side view of an IC package that includes stacked dies, but with the top die electrically coupled directly to the package substrate. [Figure 2B] 2B is a side view of the IC package of FIG. 1A and FIG. 1B for height comparison with the IC package of FIG. 2A. [Figure 3A] FIG. 2 is a side view of another exemplary IC package that includes three stacked dies between a package substrate and an interposer, where the bottom die is electrically coupled directly to the package substrate and the top die is electrically coupled to the package substrate by the interposer for package height reduction. [Figure 3B] FIG. 2 is a side view of another exemplary IC package that includes three stacked dies between a package substrate and an interposer, where the bottom die is electrically coupled directly to the package substrate and the top die is electrically coupled to the package substrate by the interposer for package height reduction. [Figure 4] FIG. 1 is a flowchart illustrating an exemplary process for fabricating an IC package, including but not limited to the IC packages of FIGS. 1A-1B and 3A-3B, that includes stacked dies between a package substrate and an interposer, where the lower die is electrically coupled directly to the package substrate and the upper die is electrically coupled to the package substrate by the interposer for package height reduction. [Diagram 5] FIG. 1 is a flowchart illustrating an exemplary process for fabricating an interposer and upper die sub-package included in an IC package, including but not limited to the IC packages of FIGS. 1A-1B and 3A-3B, that includes a stacked die between a package substrate and an interposer, where the lower die is electrically coupled directly to the package substrate and the upper die is electrically coupled to the package substrate by the interposer for package height reduction. [Figure 6A] A diagram showing exemplary fabrication stages during the fabrication of an interposer and upper die subpackage for IC packages including, but not limited to, the IC packages of Figures 1A-1B and 3A-3B according to the exemplary fabrication process of Figure 5. [Figure 6B] A diagram showing exemplary fabrication stages during the fabrication of an interposer and upper die subpackage for IC packages including, but not limited to, the IC packages of Figures 1A-1B and 3A-3B according to the exemplary fabrication process of Figure 5. [Figure 6C] A diagram showing exemplary fabrication stages during the fabrication of an interposer and upper die subpackage for IC packages including, but not limited to, the IC packages of Figures 1A-1B and 3A-3B according to the exemplary fabrication process of Figure 5. [Figure 7] An IC package including, but not limited to, the IC packages of FIGS. 1A-1B and 3A-3B, including a stacked die between a package substrate and an interposer, with a lower die electrically coupled directly to the package substrate and an upper die electrically coupled to the package substrate by the interposer for package height reduction, is a flowchart showing an exemplary process for fabricating the package substrate and the lower die sub-package included in the IC package. [Figure 8A] Illustrative fabrication stages during the fabrication of a package substrate and a lower die sub-package for an IC package including, but not limited to, the IC packages of FIGS. 1A-1B and 3A-3B, according to the exemplary fabrication process of FIG. 7, are shown. [Figure 8B] Illustrative fabrication stages during the fabrication of a package substrate and a lower die sub-package for an IC package including, but not limited to, the IC packages of FIGS. 1A-1B and 3A-3B, according to the exemplary fabrication process of FIG. 7, are shown. [Figure 8C] Illustrative fabrication stages during the fabrication of a package substrate and a lower die sub-package for an IC package including, but not limited to, the IC packages of FIGS. 1A-1B and 3A-3B, according to the exemplary fabrication process of FIG. 7, are shown. [Figure 9A] An IC package including, but not limited to, the IC packages of FIGS. 1A-1B and 3A-3B, including a stacked die between a package substrate and an interposer, with a lower die electrically coupled directly to the package substrate and an upper die electrically coupled to the package substrate by the interposer for package height reduction, is a flowchart showing an exemplary process for assembling an interposer and an upper die sub-package including, but not limited to, the interposer of FIG. 6C and the upper die sub-package, with a package substrate and a lower die sub-package including, but not limited to, the package substrate of FIG. 8C and the lower die sub-package. [Figure 9B] An IC package including, but not limited to, the IC packages of FIGS. 1A - 1B and 3A - 3B, the IC package including a stacked die between a package substrate and an interposer, a lower die being directly electrically coupled to the package substrate, and an upper die being electrically coupled to the package substrate by the interposer for package height reduction. To fabricate the IC package, an interposer and an upper die sub - package including, but not limited to, the interposer of FIG. 6C and the upper die sub - package are assembled with a package substrate and a lower die sub - package including, but not limited to, the package substrate of FIG. 8C and the lower die sub - package. A flowchart showing an exemplary process for the assembly is provided. [Figure 10A] A diagram showing exemplary fabrication stages during the assembly of an interposer and an upper die sub - package with a package substrate and a lower die sub - package for forming an IC package including, but not limited to, the IC packages of FIGS. 1A - 1B and 3A - 3B, according to the exemplary fabrication process of FIGS. 9A and 9B. [Figure 10B] A diagram showing exemplary fabrication stages during the assembly of an interposer and an upper die sub - package with a package substrate and a lower die sub - package for forming an IC package including, but not limited to, the IC packages of FIGS. 1A - 1B and 3A - 3B, according to the exemplary fabrication process of FIGS. 9A and 9B. [Figure 10C] A diagram showing exemplary fabrication stages during the assembly of an interposer and an upper die sub - package with a package substrate and a lower die sub - package for forming an IC package including, but not limited to, the IC packages of FIGS. 1A - 1B and 3A - 3B, according to the exemplary fabrication process of FIGS. 9A and 9B. [Figure 11]FIG. 5 is a block diagram of an exemplary processor-based system that may include components that may include IC packages, including but not limited to the IC packages of FIGS. 1A-1B, 3A-3B, 6A-6C, 8A-8C, and 10A-10C, according to the exemplary fabrication processes of FIGS. 5, 7, and 9A-9B, having stacked dies between a package substrate and an interposer, with a lower die and a middle die electrically coupled directly to the package substrate, and an upper die electrically coupled to the package substrate by an interposer for package height reduction. [Figure 12] FIG. 5 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components that may include an IC package, including but not limited to the IC packages of FIGS. 1A-1B, 3A-3B, 6A-6C, 8A-8C, and 10A-10C, according to the exemplary fabrication processes of FIGS. 5, 7, and 9A-9B, having stacked dies between a package substrate and an interposer, where the lower die and middle die are electrically coupled directly to the package substrate, and the upper die is electrically coupled to the package substrate by the interposer for package height reduction. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0011] Aspects disclosed herein include a stacked die integrated circuit (IC) package that uses an interposer for electrically coupling an upper stacked die to a package substrate for package height reduction. Related fabrication methods are also disclosed. The IC package includes a package substrate that supports the stacked die. The package substrate includes one or more metallization layers that each include metal interconnects for providing electrical signal routing between external interconnects and the die and between the dies within the IC package. The stacked die is electrically coupled to the package substrate for signal routing. A lower die in the IC package may be electrically coupled directly to the package substrate (e.g., by interconnect bumps) and an active surface of the lower die may be coupled to metal interconnects of an upper metallization layer of the package substrate. However, an upper die stacked above the lower die in the IC package is not positioned directly adjacent to the package substrate. Wire bonds may be used to couple the active surface of the upper die to the package substrate. However, the wire bonds may need to be oriented to extend above the upper die so that they have enough clearance area to extend outward and then downward into the package substrate without interfering with the lower die or other package components. The wire bonds may also require a minimum bend radius to avoid damage, which requires some additional clearance area above the upper die beyond the normal area tolerance between the upper die and the top surface of the IC package overmold. This additional clearance area contributes to the overall height of the IC package and may be undesirable.

[0012] Thus, in an exemplary embodiment, an IC package includes an interposer to reduce the height of the IC package while still providing a stacked die configuration electrically coupled to the package substrate. The stacked die is disposed between the package substrate and the interposer. One or more wires are coupled (e.g., wire bonded) between the active surface of the upper die and the interposer to provide an electrical connection between the upper die and the interposer. One or more electrical interconnects (e.g., conductive pillars) are coupled between the interposer and the package substrate to route an electrical connection between the wires coupled to the upper die and the package substrate. In this manner, the upper die can be electrically coupled to the package substrate without requiring additional clearance areas for coupling wire bonds to the upper die and to the package substrate. The height of the interposer added to the overall height of the IC package may be less than the height of the clearance areas required to wire bond the upper die to the package substrate.

[0013] In this regard, FIG. 1A is a side view of an exemplary IC package 100 including two stacked dies 102(1), 102(2) disposed between a package substrate 104 and an interposer 106. The first die 102(1) is considered the “lower” die in this example, meaning that it is disposed below the second “upper” die 102(2) in the vertical Z-axis direction as shown in FIG. 1A. The lower die 102(1) is disposed adjacent to the package substrate 104. The upper die 102(2) is disposed adjacent to the interposer 106. An overmold 105 (e.g., epoxy) surrounds the stacked dies 102(1), 102(2) between the interposer 106 and the package substrate 104. The stacked dies 102(1), 102(2) include ICs for performing electronic functions according to a design. For example, the lower die 102(1) can be a communications modem. The top die 102(2) may be a memory device designed to provide data storage and access to the modem of the bottom die 102(1), such as for buffering data to be modulated for transmission as a radio frequency (RF) signal and data demodulated from a received RF signal.

[0014] The package substrate 104 supports the stacked dies 102(1), 102(2) and includes metallization layers 108(1), 108(2) that include metal interconnects 110(1), 110(2) (e.g., metal lines, metal traces, vertical interconnect access (vias)), respectively, that may provide electrical signal routing between the external interconnects 112 (e.g., solder bumps) and the dies 102(1), 102(2). The metallization layers 108(1), 108(2) may be formed as laminated substrates that are bonded together and / or as redistribution layers (RDLs). Although not shown, it should be noted that the package substrate 104 may also include a core portion that would be a core substrate, as opposed to a coreless substrate. The package substrate 104 in this example includes an exterior metallization layer 108(3) having metal interconnects 110(3) exposed from the package substrate 104, to which the external interconnects 112 may be coupled to provide external signal routing access to the IC package 100. For example, the external interconnects 112 may be soldered to contacts on a printed circuit board (PCB) to physically mount the IC package 100 to the PCB and to couple the IC package 100 to other circuitry. Certain metal interconnects 110(1), 110(2) within the package substrate 104 may also be designated to provide internal signal routing between the dies 102(1), 102(2) themselves.

[0015] 1A, the stacked dies 102(1), 102(2) are electrically coupled to a package substrate 104 for signal routing. The lower die 102(1) in the IC package 100 is shown as being directly electrically coupled to the package substrate 104 by interconnect bumps 114. An active surface 116 of the lower die 102(1) adjacent to the package substrate 104 is coupled to the interconnect bumps 114 which are coupled to metal interconnects 110(1) of the upper metallization layer 108(1) of the package substrate 104. However, the upper die 102(2), which is stacked above the lower die 102(1) in the IC package 100, is not positioned directly adjacent to the package substrate 104. Wire bonds may be used to directly couple the active surface 118 of the upper die 102(2) to the metal interconnects 110(1) of the upper metallization layer 108(1) of the package substrate 104. However, the wire bonds may need to be oriented to extend above the top die 102(2) in the vertical (Z-axis) direction to have enough clearance area to extend outward and then downward into the package substrate 104 without interfering with the lower die 102(1) or other package components. The wire bonds may also require a minimum bend radius to avoid being damaged, which necessitates some additional clearance area above the top die 102(2) in the IC package 100 to have enough area for such wire bonds and to accommodate their required minimum bend radius. This additional clearance area, if present, contributes to the overall height H1 of the IC package 100 and may be undesirable.

[0016] Thus, as shown in an additional side view of the IC package 100 in FIG. 1B, to reduce the height of the IC package 100 while still providing stacked dies 102(1), 102(2) electrically coupled to the package substrate 104, the IC package 100 in FIG. 1B includes an interposer 106. The interposer 106 provides electrical interface routing between one component and another, in this case between the top die 102(2) and electrical interconnects 120 (e.g., metal pillars, metal posts, metal vias) that couple the interposer 106 to the package substrate 104. For example, the interposer 106 may include one or more metallization layers 122 each including one or more metal interconnects, which may be electrically coupled to the top die 102(2) and also electrically coupled to one or more electrical interconnects 120 for routing electrical signals from the top die 102(2) to the package substrate 104. In this manner, the top die 102(2) is electrically coupled to the package substrate 104 for signal routing to the external interconnects 112 and / or other metal interconnects 110(1), 110(2) of the metallization layers 108(1), 108(2) that are coupled to the bottom die 102(1) for die-to-die connections. As shown in FIG. 1B, in this example, one or more wires 124 are coupled (e.g., wire bonded) between the active surface 118 of the top die 102(2) and the interposer 106 to provide an electrical interface connection between the top die 102(2) and the interposer 106. Electrical interconnects 120 are coupled between the interposer 106 and the package substrate 104 to route electrical connections between the wires 124 coupled to the top die 102(2) and the package substrate 104. In this manner, the top die 102(2) can be electrically coupled to the package substrate 104 without requiring additional clearance areas for wire bonds to be bonded to the active surface 118 of the top die 102(2), extend up above the top die 102(2) in the vertical (Z-axis) direction, and then back down into the package substrate 104.The height H2 of the interposer 106 added to the overall height H1 of the IC package 100 may be less than the additional height of the overmold 105 required to provide additional clearance area above the top die 102(2) for wire bonding the top die 102(2) to the package substrate 104. For example, the height H2 of the interposer 106 may be 50 micrometers (μm).

[0017] 2A and 2B are presented to further illustrate an exemplary difference between the IC package 100 of FIGS. 1A and 1B, which includes an interposer 106 for providing an electrical connection between the top die 102(2) and the package substrate 104, and an IC package that uses wire bonding to electrically connect the top die 102(2) to the package substrate 104. FIG. 2B is a side view of the IC package 100 of FIG. 1A. As shown, the IC package 100 has an overall height H1, and the interposer has a height H2 that contributes to the overall height H1 of the IC package 100. FIG. 2A is a side view of an alternative IC package 200 that includes the same package substrate 104 and stacked dies 102(1), 102(2) as the IC package 100 of FIG. 1A. However, as shown in FIG. 2A, the top IC die 102(1) is wire bonded to the package substrate 104 by wires 202. To provide the wire 202 for connection to the package substrate 104, the wire 202 has a bend 204 that extends upward in a vertical (Z-axis) direction from the top die 102(2), then extends outward in a horizontal (X-axis) direction and flips back down toward the package substrate 104 so that it has a clear path to be routed to the package substrate 104. The minimum radius of the bend 204 and the angle θ1 required for the wire 202 to extend down to the package substrate 104 define a minimum wire bond clearance area 205 of height H4 above the top die 102(2) that must be reserved for the wire 202. Also, above the wire bond clearance area 205 there is an additional area 206 of height H5 required to provide a tolerance to the top surface 208 of the overmold 210 for the IC package 200. Thus, providing wire bonds between the top die 102(2) and the package substrate 104 in the IC package 200 of Figure 2A adds a minimum wire bond clearance area 205 of height H4 that contributes to the overall height H3 of the IC package 200. Note that in this example, the overall height H3 of the IC package 200 is greater than the overall height H1 of the IC package 100 of Figure 1A, which uses the interposer 106.For example, the height H2 of the interposer 106 is 50 μm, while the height of the minimum wire bond clearance area 205 and the additional area 206 is 125 μm, resulting in an extra 75 μm difference in the overall height H3 of the IC package 200 of FIG. 2A relative to the overall height H1 of the IC package 100 of FIGS. 1A-1B and 2B.

[0018] 1B , the lower die 102(1) of the IC package 100 has an inactive surface 126 opposite the active surface 116. The active surface 118 of the upper die 102(2) is adjacent to the inactive surface 126 of the lower die 102(4) in this example. At least a portion of the active surface 118 of the upper die 102(2) may be bonded (e.g., by epoxy or compression bonding) to at least a portion of the inactive surface 126 of the lower die 102(1). The upper die 102(2) has an inactive surface 128 opposite the active surface 118 of the upper die 102(2). Wires 124 are coupled to the active surface 118 of the upper die 102(2) and are also coupled to the interposer 106 for electrically coupling the upper die 102(2) to the interposer 106. In this example, the upper die 102(2) is shifted in the horizontal (X-axis) direction to only partially overlap the lower die 102(1) to provide room for bonding the wires 124 between the upper die 102(2) and the interposer 106. In this regard, the active surface 118 of the upper die 102(2) includes a first active surface portion 130 that overlaps a portion of the inactive surface 126 of the lower die 102(2) in the vertical (Z-axis) direction and a second active surface portion 132 that does not overlap the lower die 102(1) in the vertical (Z-axis) direction. In this manner, room exists for the wires 124 to extend downward from the active surface 118 of the upper die 102(2) toward the package substrate 104, then flip upward toward the interposer 106, and then extend to and bond to the interposer 106. This arrangement avoids having bends 134 of wires 124 extend vertically above top die 102(2), which would require additional area above top die 102(2) and increase the height of IC package 100. In this example, wires 124 include concave bends 134 that extend vertically below active surface 118 of top die 102(2) downward from top die 102(2) toward package substrate 104, and then bend upward toward interposer 106.

[0019] It should be noted that while the IC package 100 of FIGS. 1A and 1B includes only two dies 102(1), 102(2), other IC packages can be provided that include an interposer for electrically coupling to the upper die, such IC packages including more than two dies. In this regard, FIG. 3A is a side view of an exemplary IC package 300 including three stacked dies 302(1)-302(3) disposed between a package substrate 304 and an interposer 306. The first die 302(1) is considered the "lower" die in this example, meaning that it is disposed below the second "upper" die 302(2) and the third die 302(3) in the vertical Z-axis direction, as shown in FIG. 3A. The third die 302(3) is considered the "middle" die in this example, meaning that it is disposed between the lower die 302(1) and the upper die 302(2) in the vertical Z-axis direction, as also shown in FIG. 3A. The lower die 302(1) is disposed adjacent to the package substrate 304. The upper die 302(2) is disposed adjacent to the interposer 306. An overmold 305 (e.g., epoxy) surrounds the stacked dies 302(1)-302(3) between the interposer 306 and the package substrate 304. The stacked dies 302(1)-302(3) include ICs for performing electronic functions according to a design. For example, the lower die 302(1) can be a communications modem. The middle and upper dies 302(3), 302(2) can be memory devices designed to provide data storage and access to the modem of the lower die 302(1), such as for buffering data to be modulated for transmission as a radio frequency (RF) signal and data demodulated from a received RF signal.

[0020] The package substrate 304 supports the stacked dies 302(1)-302(3) and also includes metallization layers 308(1), 308(2) that include metal interconnects 310(1), 310(2) (e.g., metal lines, metal traces, vias), respectively, that may provide electrical signal routing between the external interconnects 312 (e.g., solder bumps) and the dies 302(1)-302(3). The metallization layers 308(1), 308(2) may be formed as stacked substrates that are bonded together and / or as RDLs. Although not shown, it should be noted that the package substrate 304 may also include a core portion that is a core substrate, as opposed to a coreless substrate. The package substrate 304 in this example includes an exterior metallization layer 308(3) having metal interconnects 310(3) exposed from the package substrate 304, where the external interconnects 312 may be coupled to the metal interconnects 310(3) to provide external signal routing access to the IC package 300. For example, the external interconnects 312 may be soldered to contacts on a PCB to physically mount the IC package to the PCB and couple the IC package 300 to other circuitry. Certain metal interconnects 310(1), 310(2) within the package substrate 304 may also be designated to provide internal signal routing between the dies 302(1)-302(3) themselves.

[0021] 3A, the stacked dies 302(1)-302(3) are electrically coupled to a package substrate 304 for signal routing. The lower die 302(1) in the IC package 300 is shown as being directly electrically coupled to the package substrate 304 by interconnect bumps 314. The active surface 316 of the lower die 302(1) adjacent to the package substrate 304 is coupled to the interconnect bumps 314 which are coupled to metal interconnects 310(1) of the upper metallization layer 308(1) of the package substrate 304. However, the middle and upper dies 302(3), 302(2) stacked above the lower die 302(1) are not disposed directly adjacent to the package substrate 304. Wire bonds may be used to directly couple the active surface 318 of the upper die 302(2) to the metal interconnects 310(1) of the upper metallization layer 308(1) of the package substrate 304. However, the wire bonds may need to be oriented to extend above the top die 302(2) in the vertical (Z-axis) direction to have sufficient clearance area to extend outward and then downward into the package substrate 304 without interfering with the middle and / or bottom die 302(3), 302(1) or other package components. The wire bonds may also require a minimum bend radius to avoid being damaged, which necessitates some additional clearance area above the top die 302(2) within the IC package 300 to have enough area for such wire bonds and to accommodate their required minimum bend radius. This additional clearance area, if present, contributes to the overall height H6 of the IC package 300 and may be undesirable.

[0022] Thus, as shown in an additional side view of the IC package 300 in FIG. 3B, to reduce the height of the IC package 300 while still providing stacked dies 302(1)-302(3) electrically coupled to a package substrate 304, the IC package 300 in FIG. 3C includes an interposer 306. The interposer 306 provides electrical interface routing between one component and another, in this case between the top die 302(1) and electrical interconnects 320 (e.g., metal pillars, metal posts, metal vias) that couple the interposer 306 to the package substrate 304. For example, the interposer 306 may include one or more metallization layers 322 each including one or more metal interconnects that are also electrically coupled to the top die 302(1) and to the one or more electrical interconnects 320 for routing electrical signals from the top die 302(1) to the package substrate 304. In this manner, the top die 302(2) is electrically coupled to the package substrate 304 for signal routing to the external interconnects 312 and / or other metal interconnects 310(1), 310(2) of the metallization layers 308(1), 308(2) that are coupled to the middle and bottom dies 302(3), 302(1) for die-to-die connections. As shown in FIG. 3B, in this example, one or more wires 324 are coupled (e.g., wire bonded) between the active surface 318 of the top die 302(2) and the interposer 306 to provide an electrical interface connection between the top die 302(2) and the interposer 306. Electrical interconnects 320 are coupled between the interposer 306 and the package substrate 304 to route electrical connections between the wires 324 coupled to the top die 302(2) and the package substrate 304. In this manner, the top die 302(1) may be electrically coupled to the package substrate 304 without requiring additional clearance areas for wire bonds to be bonded to the active surface 318 of the top die 302(1), extend up above the top die 302(1) in the vertical (Z-axis) direction, and then back down into the package substrate 304.The height H7 of the interposer 306, which is added to the overall height H6 of the IC package 300, may be less than the additional height of the overmold required to provide additional clearance area above the top die 302(2) necessary for wire bonding the top die 302(2) to the package substrate 304. For example, the height H7 of the interposer 306 may be 50 micrometers (μm).

[0023] 3B, the bottom die 302(1) of the IC package 300 has an inactive surface 326 opposite the active surface 316. The middle die 302(3) of the IC package 300 has an inactive surface 336 adjacent the inactive surface 326 of the bottom die 302(1). The middle die 302(3) has an active surface 338 adjacent the active surface 318 of the top die 302(2) opposite the inactive surface 336. At least a portion of the inactive surface 336 of the middle die 302(3) may be bonded (e.g., by epoxy or pressure bonding) to at least a portion of the inactive surface 326 of the bottom die 302(1). At least a portion of the active surface 318 of the top die 302(2) may be bonded (e.g., by epoxy or pressure bonding) to at least a portion of the active surface 338 of the middle die 302(3). The upper die 302(2) has an inactive surface 328 opposite the active surface 318 of the upper die 302(2). Wires 324 are coupled to the active surface 318 of the upper die 302(2) and are also coupled to the interposer 306 for electrically coupling the upper die 302(2) to the interposer 306. In this example, the upper die 302(2) is shifted in the horizontal (X-axis) direction to only partially overlap the middle die 302(3) to provide room for coupling the wires 324 between the upper die 302(2) and the interposer 306. In this regard, the active surface 318 of the upper die 302(2) includes a first active surface portion 330 that overlaps a portion of the active surface 338 of the middle die 302(2) in the vertical (Z-axis) direction and a second active surface portion 332 that does not overlap the middle die 302(3) in the vertical (Z-axis) direction. In this way, there is room for wires 324 to extend downward from active surface 318 of top die 302(2) toward package substrate 304, then turn back upward toward interposer 306, and then extend to and bond with interposer 306. This arrangement avoids the need for bends 334 of wires 324 to extend vertically above top die 302(2), which would require additional area above top die 302(2), thereby increasing the height of IC package 300.In this example, the wires 324 include a concave bend 334 that extends vertically below the active surface 318 of the top die 302(2), downward from the top die 302(2) toward the package substrate 304, and then bends upward toward the interposer 306.

[0024] 3B, the intermediate die 302(3) is electrically coupled to the package substrate 304 by wires 340, which in this example may be, for example, wire bonds. Because the active surface 338 of the intermediate die 302(3) includes a first active surface portion 342 that does not overlap the upper die 302(2) in the vertical (Z-axis) direction, there is room for the wires 340 to extend from the active surface 338 of the intermediate die 302(3) upward toward the interposer 306, then flip downward toward the package substrate 304, and then extend to and couple to the package substrate 304. Alternatively, the intermediate die 302(3) can be reversed such that its active surface 338 is adjacent to the lower die 302(1) and its inactive surface 336 is adjacent to the upper die 302(2). In this example, similar to the wires 324 that couple the top die 302(2) to the interposer 306, the wires 340 may then be directed to couple the active surface 338 of the intermediate die 302(3) to the interposer 306. In this latter exemplary scenario, the intermediate die 302(3) may be electrically coupled to the package substrate 304 by connections between the interposer 306 and the electrical interconnects 320.

[0025] Figure 4 is a flow chart illustrating an exemplary process 400 for fabricating an IC package including stacked dies between a package substrate and an interposer, with the lower die electrically coupled directly to the package substrate and the upper die electrically coupled to the package substrate by the interposer for package height reduction. The exemplary process 400 of Figure 4 can be used to fabricate the IC packages 100, 300 of Figures 1A-1B and 3A-3B, respectively. The process 400 of Figure 4 will be described in conjunction with the IC packages 100, 300 of Figures 1A-1B and 3A-3B.

[0026] In this regard, as shown in FIG. 4, one exemplary step of process 400 is providing a package substrate 104, 304 (block 402 of FIG. 4). Another exemplary step of process 400 is providing an interposer 106, 306 (block 404 of FIG. 4). Another exemplary step of process 400 is electrically coupling a first die 102(1), 302(1) to the package substrate 104, 304 (block 406 of FIG. 4). Another exemplary step of process 400 is disposing a second die 102(2), 302(2) between the first die 102(1), 302(1) and the interposer 106, 306 (block 408 of FIG. 4). Another exemplary step of the process 400 is coupling one or more second wires 124, 324 to the second die 102(2), 302(2) and the interposer 106, 306 (block 410 of FIG. 4). Another exemplary step of the process 400 is coupling one or more electrical interconnects 120, 320 to the package substrate 104, 304 and the interposer 106, 306 to electrically couple a second wire 124, 324 of the one or more second wires 124, 324 to the package substrate 104, 304 (block 412 of FIG. 4).

[0027] An IC package including a lower die electrically coupled directly to a package substrate and an upper die electrically coupled to the package substrate by an interposer for package height reduction may be fabricated as a subassembly that is later assembled together. For example, FIG. 5 is a flow chart illustrating an exemplary process 500 for fabricating an interposer and upper die subpackage included in an IC package including a stacked die between a package substrate and an interposer, with the lower die electrically coupled directly to the package substrate and the upper die electrically coupled to the package substrate by an interposer for package height reduction. This may include the IC packages 100, 300 of FIGS. 1A-1B and 3A-3B, respectively. FIGS. 6A-6C show exemplary fabrication stages 600A-600C during fabrication of an interposer and upper die subpackage for IC packages including, but not limited to, the IC packages 100, 300 of FIGS. 1A-1B and 3A-3B according to the exemplary fabrication process 500 of FIG. 5. The process 500 of FIG. 5 will be described with reference to the IC package 300 of FIGS. 3A-3B, along with fabrication stages 600A-600C of FIGS. 6A-6C.

[0028] In this regard, as shown in the exemplary fabrication stage 600A of FIG. 6A, a first step in the process 500 for fabricating the interposer 106 and upper die 102(2) subpackage may be disposing the inactive surface 328 of the upper die 102(2) on the interposer 106 (block 502 of FIG. 5). Then, as shown in the exemplary fabrication stage 600B of FIG. 6B, a next step in the process 500 may be providing wires 324 and coupling (e.g., wire bonding) the wires 324 to the active surface 318 of the upper die 302(2) and the interposer 306 to provide the interposer 306 and upper die 302(2) subpackage (block 504 of FIG. 5). As shown in example fabrication stage 600C of FIG. 6C, the next step in process 500 may then be to invert the interposer 306 and the upper die 302(2) subpackage and prepare it for placement onto the package substrate 304 and the lower die 302(1) subpackage, as described below with respect to FIGS. 7-8C.

[0029] FIG. 7 is a flow chart illustrating an exemplary process 700 for fabricating a package substrate and a lower die subpackage included in an IC package including stacked dies between a package substrate and an interposer, with the lower die electrically coupled directly to the package substrate and the upper die electrically coupled to the package substrate by an interposer for package height reduction. This may include the IC packages 100, 300 of FIGS. 1A-1B and 3A-3B, respectively. FIGS. 8A-8C show exemplary fabrication stages 800A-800C during fabrication of a package substrate and a lower die subpackage for IC packages including, but not limited to, the IC packages 100, 300 of FIGS. 1A-1B and 3A-3B according to the exemplary fabrication process of FIG. 7. The process 700 of FIG. 7 will be described with reference to the IC package 300 of FIGS. 3A-3B, along with the fabrication stages 800A-800C of FIGS. 8A-8C.

[0030] In this regard, as shown in the exemplary fabrication stage 800A of FIG. 8A, a first step in the process 700 for fabricating the package substrate 304 and the lower die 302(2) subpackage may be providing the package substrate 304 and forming the electrical interconnects 320 coupled to the package substrate 304 (block 702 of FIG. 7). As shown in the exemplary fabrication stage 800B of FIG. 8B, a next step in the process 700 for fabricating the package substrate 304 and the lower die 302(2) subpackage may be bonding the lower die 302(1) to the package substrate 304 by the interconnect bumps 314 and stacking the intermediate die 302(3) to the lower die 302(1) (block 704 of FIG. 7). The inactive surface 336 of the intermediate die 302(3) may be bonded to the inactive surface 326 of the lower die 302(1). As previously mentioned, in this example, the intermediate die 302(3) is stacked on the lower die 302(1) such that the intermediate die 302(3) only partially overlaps the lower die 302(1). This provides room for bonding wires 340 to the active surface 338 of the intermediate die 302(3) and the package substrate 304. As shown in the example fabrication stage 800C of FIG. 8C, the next step in the process 700 for fabricating the package substrate 304 and lower die 302(2) subpackage may be providing wires 340 and bonding (e.g., wire bonding) the wires to the active surface 338 of the intermediate die 302(3) and the package substrate 304 to electrically couple the intermediate die 302(3) to the package substrate 304 (block 706 of FIG. 7).

[0031] 9A and 9B are a flow chart 900 illustrating an exemplary process for assembling an interposer and upper die subpackage, including but not limited to the interposer 306 and upper die 302(2) subpackage of FIG. 6C, with a package substrate and lower die subpackage, including but not limited to the package substrate 304 and lower die 302(1) subpackage of FIG. 8C, to fabricate an IC package. The fabricated IC package includes IC packages, including but not limited to the IC packages 100, 300 of FIGS. 1A-1B and 3A-3B, that include stacked dies between the package substrate and the interposer, where the lower die is electrically coupled directly to the package substrate and the upper die is electrically coupled to the package substrate by the interposer for package height reduction. Figures 10A-10C show exemplary fabrication stages 1000A-1000C during assembly of an interposer and an upper die subpackage with a package substrate and a lower die subpackage to form an IC package, including but not limited to the IC packages 100, 300 of Figures 1A-1B and 3A-3B, according to the exemplary fabrication process of Figures 9A-9B. The process 900 of Figures 9A-9B will be described in conjunction with the fabrication stages 1000A-1000C of Figures 1000A-1000C with reference to the interposer 306 and upper die 302(2) subpackage of Figures 3A-3B and 6C, and the package substrate 304 and lower die 302(1) subpackage of Figure 8C.

[0032] In this regard, as shown in example fabrication stages 1000A of FIG. 10A, a first step in a process 900 for fabricating an IC package 300 including the interposer 306 and upper die 302(2) subpackage of FIG. 6C and the package substrate 304 and lower die 302(1) subpackage of FIG. 8C may be providing the interposer 306 and upper die 302(2) subpackage of FIG. 6C and the package substrate 304 and lower die 302(1) subpackage of FIG. 8C (block 902 of FIG. 9A). As shown in the exemplary fabrication stage 1000B of Figure 10B, the next step in the process 900 for fabricating an IC package 300 including the interposer 306 and upper die 302(2) subpackage of Figure 6C and the package substrate 304 and lower die 302(1) subpackage of Figure 8C may be attaching the interposer 306 to the electrical interconnects 320 and bonding the upper die 302(2) to the middle die 302(3) such that the upper die 302(2) and middle die 302(3) overlap (block 904 of Figure 9A). This provides room for wires 340 and 324 to electrically couple the respective middle and upper die 302(3), 302(2) to the respective interposer 306 and package substrate 304. As previously mentioned, in this example, the active surface 318 of the top die 302(2) is bonded to the active surface 338 of the middle die 302(3). As shown in the exemplary fabrication stage 1000C of FIG. 10C, the next step in the process 900 for fabricating an IC package 300 including the interposer 306 and top die 302(2) subpackage of FIG. 6C and the package substrate 304 and bottom die 302(1) subpackage of FIG. 8C may be filling the area between the interposer 306 and the package substrate 304 with an overmold material 344 to form an overmold 305 (block 906 of FIG. 9B). The overmold 305 is formed around the dies 302(1)-302(3) and the bond wires 324, 340 to protect and insulate these components.

[0033] IC packages, including but not limited to those of Figures 1A-1B, 3A-3B, 6A-6C, 8A-8C, and 10A-10B according to the exemplary fabrication processes of Figures 5, 7, and 9A-9B, having stacked dies between a package substrate and an interposer, with the lower die and middle die electrically coupled directly to the package substrate, and the upper die electrically coupled to the package substrate by the interposer for package height reduction, may be provided or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0034] In this regard, FIG. 11 illustrates an example of a processor-based system 1100. A component of the processor-based system 1100 is an IC 1102. Some or all of the IC 1102 of the processor-based system 1100 can be provided in an IC package, including but not limited to the IC packages of FIGS. 1A-1B, 3A-3B, 6A-6C, 8A-8C, and 10A-10B, according to the exemplary fabrication processes of FIGS. 5, 7, and 9A-9B, according to any embodiment disclosed herein, having stacked dies between a package substrate and an interposer, with a lower die and a middle die electrically coupled directly to the package substrate, and an upper die electrically coupled to the package substrate by an interposer for package height reduction. In this example, the processor-based system 1100 can be formed as an IC package 1104 and as a system-on-chip (SoC) 1106. The processor-based system 1100 includes a CPU 1108 that includes one or more processors 1110, sometimes referred to as a CPU core or processor core. The CPU 1108 may have a cache memory 1112 coupled to the CPU 1108 for rapid access to temporarily stored data. The CPU 1108 is coupled to a system bus 1114, which may interconnect master and slave devices included within the processor-based system 1100. As is well known, the CPU 1108 communicates with these other devices by exchanging address, control, and data information via the system bus 1114. For example, the CPU 1108 may communicate bus transaction requests to a memory controller 1116, as an example of a slave device. Although not shown in FIG. 11, multiple system buses 1114 may be provided, with each system bus 1114 constituting a different fabric.

[0035] Other master and slave devices may be connected to the system bus 1114. As shown in FIG. 11, these devices may include, by way of example, a memory system 1120 including a memory controller 1116 and a memory array 1118(s), one or more input devices 1122, one or more output devices 1124, one or more network interface devices 1126, and one or more display controllers 1128. The memory system 1120, the one or more input devices 1122, the one or more output devices 1124, the one or more network interface devices 1126, and the one or more display controllers 1128 may each be provided in the same or different circuit packages. The input device(s) 1122 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. The output device(s) 1124 may include any type of output device, including, but not limited to, audio, video, other visual indicators, and the like. The network interface device(s) 1126 may be any device configured to enable the exchange of data to and from the network 1130. The network 1130 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a Bluetooth network, and the Internet. The network interface device(s) 1126 may be configured to support any type of communication protocol desired.

[0036] The CPU 1108 may also be configured to access a display controller 1128 through the system bus 1114 to control information sent to one or more displays 1132. The display controller 1128 sends information to the display 1132 to be displayed by one or more video processors 1134, which process the information to be displayed into a format suitable for the display 1132. The display controller 1128(s) and the video processor 1134(s) may be included in the IC package 1104 and the same or different circuit package, as well as in the same or different circuit package that includes the CPU 1108, by way of example. The display(s) 1132 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, and the like.

[0037] FIG. 12 illustrates an exemplary wireless communication device 1200 including a radio frequency (RF) component formed from one or more ICs 1202, any of which may include an IC package 1203 having stacked dies between a package substrate and an interposer, including, but not limited to, the IC packages of FIGS. 1A-1B, 3A-3B, 6A-6C, 8A-8C, and 10A-10B, according to the exemplary fabrication processes of FIGS. 5, 7, and 9A-9B, according to any aspect disclosed herein, with a lower die and a middle die electrically coupled directly to the package substrate, and an upper die electrically coupled to the package substrate by an interposer for package height reduction. The wireless communication device 1200 may include, or be provided within, any of the above-mentioned devices, as examples. As shown in FIG. 12, the wireless communication device 1200 includes a transceiver 1204 and a data processor 1206. The data processor 1206 may include a memory for storing data and program codes. The transceiver 1204 includes a transmitter 1208 and a receiver 1210 supporting bidirectional communication. In general, the wireless communication device 1200 may include any number of transmitters 1208 and / or receivers 1210 for any number of communication systems and frequency bands. All or a portion of the transceiver 1204 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0038] The transmitter 1208 or receiver 1210 may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, the signal is frequency converted between RF and baseband in multiple stages in the receiver 1210, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct-conversion architecture, the signal is frequency converted between RF and baseband in one stage. The super-heterodyne architecture and the direct-conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 1200 in FIG. 12, the transmitter 1208 and the receiver 1210 are implemented with a direct-conversion architecture.

[0039] On the transmit path, the data processor 1206 processes data to be transmitted and provides I and Q analog output signals to a transmitter 1208. In the example wireless communication device 1200, the data processor 1206 includes digital-to-analog converters (DACs) 1212(1) and 1212(2) to convert digital signals generated by the data processor 1206 into I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0040] Within the transmitter 1208, low pass filters 1214(1) and 1214(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1216(1), 1216(2) amplify the signals from the low pass filters 1214(1), 1214(2), respectively, and provide I and Q baseband signals. An upconverter 1218 upconverts the I and Q baseband signals using I and Q TX local oscillator (LO) signals from a transmit (TX) LO signal generator 1222 through mixers 1220(1), 1220(2) to provide an upconverted signal 1224. A filter 1226 filters the upconverted signal 1224 to remove unwanted signals caused by frequency upconversion as well as noise in the receive frequency band. A power amplifier (PA) 1228 amplifies the upconverted signal 1224 from filter 1226 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1230 and transmitted by an antenna 1232.

[0041] In the receive path, an antenna 1232 receives a signal transmitted by a base station and provides a received RF signal, which is routed through a duplexer or switch 1230 and provided to a low noise amplifier (LNA) 1234. The duplexer or switch 1230 is designed to operate at a specific RX to TX duplexer frequency separation such that the receive (RX) signal is separated from the TX signal. The received RF signal is amplified by the LNA 1234 and filtered by a filter 1236 to obtain a desired RF input signal. Downconversion mixers 1238(1), 1238(2) mix the output of the filter 1236 with I and Q RX LO signals (i.e., LO_I and LO_Q) from a RX LO signal generator 1240 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1242(1), 1242(2) and further filtered by low pass filters 1244(1), 1244(2) to obtain I and Q analog input signals, which are provided to data processor 1206. In this example, data processor 1206 includes analog-to-digital converters (ADCs) 1246(1), 1246(2) to convert the analog input signals to digital signals for further processing by data processor 1206.

[0042] In the wireless communication device 1200 of FIG. 12, a TX LO signal generator 1222 generates I and Q TX LO signals for use in frequency up-conversion, and a RX LO signal generator 1240 generates I and Q RX LO signals for use in frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. A TX phase-locked loop (PLL) circuit 1248 receives timing information from the data processor 1206 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 1222. Similarly, a RX PLL circuit 1250 receives timing information from the data processor 1206 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 1240.

[0043] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0044] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0045] Aspects disclosed herein may be embodied in hardware and instructions stored in the hardware and may reside in, for example, a random access memory (RAM), a flash memory, a read-only memory (ROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0046] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and explanations. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that the operational steps shown in the flow chart diagrams may be subject to many different modifications, as will be readily apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0047] The preceding description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other examples. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0048] The following numbered clauses describe example implementations. 1. An integrated circuit (IC) package comprising: A package substrate; An interposer; a first die electrically coupled to a package substrate; a second die disposed between the first die and the interposer; one or more second wires coupled to the second die and to the interposer; one or more electrical interconnects coupled to the interposer and the package substrate, each electrically coupling a second wire of the one or more second wires to the package substrate; 2. An integrated circuit (IC) package comprising:

[0049] 2. A first die has a first active side adjacent to and electrically coupled to the package substrate and a first inactive side opposite the first active side; The IC package of claim 1, wherein the second die has a second inactive side adjacent to the interposer and a second active side opposite the second inactive side, and one or more second wires are electrically coupled to the interposer.

[0050] 3. The IC package of claim 2, wherein one or more second wires are coupled to the second active surface of the second die and to the interposer.

[0051] 4. A second active surface of the second die is a first active surface portion vertically overlapping at least a portion of the first die; a second active surface portion that does not vertically overlap the first die; 4. The IC package of claim 3, wherein the one or more second wires are coupled to a second active surface portion of the second active surface.

[0052] 5. The IC package of clause 4, wherein the one or more second wires each extend from the second die beneath the second die toward the package substrate and include a concave bend portion bent upward toward the interposer.

[0053] 6. The IC package of clause 4, wherein the one or more second wires each include a concave bend that bends upwardly toward the interposer.

[0054] 7. The IC package of any one of clauses 2 to 6, wherein at least a portion of the second active surface of the second die is bonded to at least a portion of the first inactive surface of the first die.

[0055] 8. The IC package of any one of clauses 1 to 7, wherein the second die is bonded to the first IC die in a stacked arrangement.

[0056] 9. The IC package of clause 2, further comprising a compression portion between at least a portion of the second active surface of the second die and at least a portion of the first inactive surface of the first die.

[0057] 10. The IC package of clause 2, further comprising an epoxy bonding at least a portion of the second active surface of the second die to at least a portion of the first inactive surface of the first die.

[0058] 11. The IC package of any one of clauses 1 to 10, further comprising one or more interconnect bumps respectively coupling the first die to the package substrate.

[0059] 12. The IC package of any one of clauses 1 to 11, further comprising one or more first wires electrically coupled to the first die and electrically coupled to the package substrate.

[0060] 13. The IC package of any one of clauses 1 to 12, wherein the first die is electrically coupled through the package substrate to at least one electrical interconnect of the one or more electrical interconnects to electrically couple the first die to the second die.

[0061] 14. The IC package of any one of clauses 1 to 13, further comprising a third die disposed between the first die and the second die.

[0062] 15. The IC package of claim 14, further comprising one or more third wires electrically coupled to the third die and the package substrate.

[0063] 16. The IC package of clause 15, wherein the one or more third wires each extend from the third die above the third die toward the interposer and include a convex bend portion bent downward toward the package substrate.

[0064] 17. The IC package of claim 14, further comprising one or more third wires electrically coupled to the third die and the interposer.

[0065] 18. The IC package of clause 17, wherein the one or more third wires each extend from the third die beneath the third die toward the package substrate and include a concave bend portion bent upward toward the interposer.

[0066] 19. The IC package of clause 17, further comprising one or more second electrical interconnects coupled to the interposer and the package substrate and each electrically coupled to a third wire of the one or more third wires.

[0067] 20. The IC package of clause 19, wherein the third die is electrically coupled to at least one electrical interconnect of the one or more electrical interconnects by an interposer to electrically couple the third die to the first die.

[0068] 21. A first die having a first active side adjacent to and electrically coupled to a package substrate and a first inactive side opposite the first active side; a second die having a second inactive side adjacent to the interposer and a second active side opposite the second inactive side; a third die having a third active surface and a third inactive surface opposite the third active surface; 21. An IC package according to any one of clauses 14 to 20.

[0069] 22. The IC package of clause 21, wherein one or more third wires are coupled to a third active surface of the third die and to the package substrate.

[0070] 23. A third active surface of a third die is a first active surface portion vertically overlapping at least a portion of the first die; a second active surface portion that does not vertically overlap the first die; 23. The IC package of claim 21 or 22, wherein the one or more third wires are coupled to the second active surface portion of the third active surface.

[0071] 24. The IC package of any one of clauses 1 to 23 integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.

[0072] 25. A method of fabricating an integrated circuit (IC) package, comprising: providing a package substrate; providing an interposer; Electrically coupling the first die to a package substrate; disposing a second die between the first die and the interposer; coupling one or more second wires to the second die and to the interposer; coupling one or more electrical interconnects to the package substrate and the interposer to electrically couple a second wire of the one or more second wires to the package substrate; The method includes:

[0073] 26. Electrically coupling the first die to the package substrate includes electrically coupling a first active surface of the first die adjacent to the package substrate; coupling the one or more second wires to the second die and the interposer includes coupling the one or more second wires to a second active surface of the second die adjacent to the interposer; The method described in clause 25.

[0074] 27. Disposing the second die between the first die and the interposer includes orienting the second die relative to the first die such that a first active surface portion of the second die overlaps at least a portion of the first die in a vertical direction and a second active surface portion of the second die does not overlap the first die in a vertical direction; coupling the one or more second wires to the second die and the interposer includes coupling the one or more second wires to a second active surface portion of the second active surface; The method described in clause 26.

[0075] 28. The method of any one of clauses 25 to 27, further comprising joining a second die to the first die in a stacked arrangement.

[0076] 29. The method of any one of clauses 25 to 28, further comprising disposing a third die between the first die and the second die.

[0077] 30. The method of claim 29, further comprising coupling one or more third wires to the third die and to the packaging substrate.

[0078] 31. Disposing the third die between the first die and the second die includes orienting the third die relative to the first die such that a first active surface portion of the third die overlaps at least a portion of the first die in a vertical direction and a second active surface portion of the third die does not overlap the first die in a vertical direction; Clause 31. The method of clause 30, wherein bonding the one or more third wires to the third die and the packaging substrate includes bonding the one or more third wires to a second active surface portion of the third die and the packaging substrate.

[0079] 32. The method of claim 29, further comprising coupling one or more third wires to the third die and the interposer.

[0080] 33. Disposing the third die between the first die and the second die includes orienting the third die relative to the first die such that a first active surface portion of the third die overlaps at least a portion of the first die in a vertical direction and a second active surface portion of the third die does not overlap the first die in a vertical direction; 33. The method of claim 32, wherein coupling one or more third wires to the third die and the interposer includes coupling one or more third wires to a second active surface portion of the third die and the interposer.

[0081] 34. The method of any one of clauses 25 to 33, wherein electrically coupling the first die to the package substrate includes coupling one or more die interconnects coupled to the first active surface of the first die to the package substrate.

[0082] 35. Bonding a third die to a first inactive surface of the first die opposite the first active surface; electrically coupling the third die to the package substrate; 35. The method of claim 34, further comprising:

[0083] 36. The method of any one of clauses 25 to 35, wherein disposing the second die between the first die and the interposer further comprises connecting a second inactive side of the second die to the interposer. [Explanation of symbols]

[0084] 100 IC packages 102 Stacked Die 104 Package Substrate 105 Overmolding 106 Interposer 108 Metallized layer 110 Metallic Interconnects 112 External Interconnect 114 Interconnect Bumps 116 Active surface 118 Active surface 120 Electrical Interconnects 122 Metallized layer 124 Wire 126 Inert surface 128 Inert surface 130 First active surface portion 132 Second active surface area 134 Bend 200 IC packages 202 Wire 204 Bend 205 Wirebond Gap Area 206 Additional areas 208 Top surface 210 Overmolding 300 IC packages 302 Stacked Die 304 Package Substrate 305 Overmolding 306 Interposer 308 Metallized layer 310 Metallic Interconnects 312 External Interconnect 314 Interconnect Bumps 316 Active surface 318 Active surface 320 Electrical Interconnects 322 Metallized layer 324 Wire 326 Inert surface 328 Inert surface 330 First active surface portion 332 Second active surface area 334 Bend 336 Inert surface 338 Active surface 340 Wire 342 First active surface part 344 Overmolding Materials 1100 System 1104 IC package 1106 System on Chip (SoC) 1110 Processor 1112 Cache Memory 1114 System Bus 1116 Memory Controller 1118 Memory Array 1120 Memory System 1122 Input Devices 1124 Output Device 1126 Network Interface Device 1128 Display Controller 1130 Network 1132 Display 1134 Video Processor 1200 Wireless Communication Devices 1203 IC package 1204 Transceiver 1206 Data Processor 1208 Transmitter 1210 Receiver 1212 Digital to Analog Converter (DAC) 1214 Low-pass filter 1216 Amplifier (AMP) 1218 Upconverter 1220 Mixer 1222 Signal Generator 1224 signal 1226 Filter 1228 Power Amplifier (PA) 1230 Switch 1232 Antenna 1234 Low Noise Amplifier (LNA) 1236 Filter 1238 Downconversion mixer 1240 LO signal generator 1244 Low Pass Filter 1246 Analog-to-Digital Converter (ADC) 1248 Circuit 1250 PLL circuit

Claims

1. An integrated circuit (IC) package, comprising: a package substrate; an interposer; a first die electrically coupled to the package substrate; a second die disposed between the first die and the interposer; one or more second wires coupled to the second die and the interposer; one or more electrical interconnects coupled to the interposer and the package substrate, each electrically coupling a respective one of the one or more second wires to the package substrate; wherein the second die is coupled to the first die in a stacked arrangement; the second die has a second inactive surface adjacent to the interposer and a second active surface opposite the second inactive surface; a first portion of the second active surface of the second die overlaps at least a portion of the first die and is directly coupled to at least a portion of the first die, and a second portion of the second active surface of the second die does not overlap the first die; the one or more second wires are electrically coupled to the second portion of the second active surface of the second die and the interposer; an integrated circuit (IC) package.

2. The first die has a first active surface adjacent to and electrically coupled to the package substrate, and a first inactive surface opposite the first active surface. The IC package according to claim 1.

3. In a vertical direction, the first portion of the second active surface of the second die overlaps at least a portion of the first die and is directly coupled to at least a portion of the first die, the vertical direction extending from the interposer to the package substrate. The IC package according to claim 2.

4. Each of the one or more second wires extends downward from the second die toward the package substrate and has a concave bend that bends upward toward the interposer, where downward is the direction toward the package substrate and upward is the direction toward the interposer. The IC package according to claim 3.

5. The IC package according to claim 2, further comprising a crimping portion between at least a portion of the second active surface of the second die and at least a portion of the first inactive surface of the first die.

6. The IC package according to claim 1, further comprising one or more interconnect bumps that respectively couple the first die to the package substrate.

7. The IC package according to claim 1, further comprising one or more first wires that are electrically coupled to the first die and electrically coupled to the package substrate.

8. The IC package according to claim 1, wherein the first die is electrically coupled through the package substrate to at least one of the one or more electrical interconnects for electrically coupling the first die to the second die.

9. A method of fabricating an integrated circuit (IC) package, comprising: providing a package substrate; providing an interposer; electrically coupling a first die to the package substrate; disposing a second die between the first die and the interposer; coupling one or more second wires to the second die and the interposer; coupling one or more electrical interconnects to the package substrate and the interposer to electrically couple a second wire of the one or more second wires to the package substrate; including: further comprising coupling the second die to the first die in a stacked arrangement; wherein the second die has a second inactive surface adjacent to the interposer and a second active surface opposite the second inactive surface; a first portion of the second active surface of the second die overlaps at least a portion of the first die and is directly coupled to at least a portion of the first die, and a second portion of the second active surface of the second die does not overlap the first die; wherein the one or more second wires are electrically coupled to the second portion of the second active surface of the second die and the interposer; method.

10. The method according to claim 9, wherein electrically coupling the first die to the package substrate includes electrically coupling a first active surface of the first die adjacent to the package substrate. The method according to claim 9. **Claim 11**: In the vertical direction, the first portion of the second active surface of the second die overlaps at least a portion of the first die and is directly coupled to at least a portion of the first die, and the vertical direction extends from the interposer to the package substrate. The method according to claim 10. **Claim 12** The method according to claim 9, wherein electrically coupling the first die to the package substrate includes coupling one or more die interconnects coupled to a first active surface of the first die to the package substrate.

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