Semiconductor device thermal bumps

Abstract

A semiconductor device, such as a power amplifier, is disclosed in which, unlike conventional power amplifiers, the thermal bumps are patterned to cover only the active devices, allowing the dimensions of the semiconductor device to be reduced.

Description

[Technical field]

[0001] The present disclosure relates generally to semiconductor devices, and more particularly, but not exclusively, to thermal bumps and fabrication techniques in semiconductor devices such as power amplifiers. [Background technology]

[0002] Integrated circuit technology has achieved great strides in increasing computing power by miniaturizing active and passive components. Packaged devices can be found in many electronic devices including processors, servers, radio frequency (RF) integrated circuits, etc. Packaging technologies have become cost-effective for high pin count devices and / or high production volume parts.

[0003] In today's radio frequency front-end (RFFE) modules, power amplifiers (PAs) can occupy a significant amount of the module's area. For example, a gallium arsenide (GaAs) PA can occupy an area of ​​approximately 1000 μm×1000 μm. Thus, there is a need for systems, devices, and methods that overcome the shortcomings of conventional PA designs, including the methods, systems, and devices provided herein. Summary of the Invention [Means for solving the problem]

[0004] The following presents a simplified summary of one or more aspects and / or examples related to the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview of all contemplated aspects and / or examples, nor should the following summary be considered to identify key or critical elements of all contemplated aspects and / or examples or to delineate the scope related to any particular aspect and / or example. As such, the following summary is intended only to present certain concepts of one or more aspects and / or examples related to the apparatus and methods disclosed herein in a simplified form prior to the detailed description presented below.

[0005] An exemplary semiconductor device is disclosed. The semiconductor device may include a plurality of unit cells comprising a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and be aligned along a first length in a second direction. The semiconductor device may also include a first metal layer patterned to form a plurality of thermal pads on the plurality of active devices. The semiconductor device may further include a second metal layer patterned to form first and second thermal bump ends and a thermal bump connected therebetween. The thermal bump may have a second width in the first direction and a second length in the second direction. The thermal bump may be formed on the plurality of thermal pads. The semiconductor device may further include a third metal layer patterned to form a thermal bar on the thermal bump. The semiconductor device may further include a thermal pillar formed on the thermal bar. The plurality of active devices may be thermally coupled to the thermal pillar via the plurality of thermal pads, the thermal bumps, and the thermal bar. The first and second thermal bump ends may each have a width greater than the second width. The area between the first and second thermal bump ends may be divided into an active area and a non-active area. The active area may be a portion of the area occupied by the thermal bump and the non-active area may be the remainder of the area. The second width and second length of the thermal bump may be oriented such that the active area overlaps with the first width and first length of the plurality of active devices.

[0006] A method of fabricating a semiconductor device is disclosed. The method may include forming a plurality of unit cells comprising a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and be aligned along a first length in a second direction. The method may also include patterning a first metal layer to form a plurality of thermal pads on the plurality of active devices. The method may further include patterning a second metal layer to form first and second thermal bump ends and a thermal bump connected therebetween. The thermal bump may have a second width in the first direction and a second length in the second direction. The thermal bump may be formed on the plurality of thermal pads. The method may further include patterning a third metal layer to form a thermal bar on the thermal bump. The method may further include forming a thermal pillar formed on the thermal bar. The plurality of active devices may be thermally coupled to the thermal pillars via the plurality of thermal pads, the thermal bumps, and the thermal bar. The first and second thermal bump ends may each have a width greater than the second width. The area between the first and second thermal bump ends may be divided into an active area and a non-active area. The active area may be a portion of the area occupied by the thermal bump and the non-active area may be the remainder of the area. The second width and second length of the thermal bump may be oriented such that the active area overlaps with the first width and first length of the plurality of active devices.

[0007] Another exemplary semiconductor device is disclosed. The semiconductor device may include a plurality of unit cells including a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and be aligned along a first length in a second direction. The semiconductor device may also include a first metal layer patterned to form a plurality of thermal pads on the plurality of active devices. The semiconductor device may further include a second metal layer patterned to form first and second thermal bump ends and a thermal bump connected therebetween. The thermal bump may have a second width in the first direction and a second length in the second direction. The thermal bump may be formed on the plurality of thermal pads. The semiconductor device may further include a thermal pillar formed on the thermal bump. The plurality of active devices may be thermally coupled to the thermal pillar via the plurality of thermal pads and the thermal bumps. The first and second thermal bump ends may each have a width greater than the second width. The area between the first and second thermal bump ends may be divided into an active area and a non-active area. The active area may be a portion of the area occupied by the thermal bump and the non-active area may be the remaining portion of the area. The second width and second length of the thermal bump may be oriented such that the active area overlaps with the first width and first length of the plurality of active devices.

[0008] A method of fabricating a semiconductor device is disclosed. The method may include forming a plurality of unit cells comprising a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and be aligned along a first length in a second direction. The method may also include patterning a first metal layer to form a plurality of thermal pads on the plurality of active devices. The method may further include patterning a second metal layer to form first and second thermal bump ends and thermal bumps connected therebetween. The thermal bumps may have a second width in the first direction and a second length in the second direction. The thermal bumps may be formed on the plurality of thermal pads. The method may further include forming a thermal pillar on the thermal bump. The plurality of active devices may be thermally coupled to the thermal pillar via the plurality of thermal pads and thermal bumps. The first and second thermal bump ends may each have a width greater than the second width. The area between the first and second thermal bump ends may be divided into an active area and a non-active area. The active area may be a portion of the area occupied by the thermal bump and the non-active area may be the remaining portion of the area. The second width and second length of the thermal bump may be oriented such that the active area overlaps with the first width and first length of the plurality of active devices.

[0009] Other features and advantages associated with the apparatus and methods disclosed herein will become apparent to one with ordinary skill in the art upon review of the following drawings and detailed description.

[0010] A more complete appreciation of the same will be readily obtained as the aspects of the present disclosure and many of its attendant advantages become better understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, which are presented merely to illustrate and not to limit the disclosure, and in which: [Brief description of the drawings]

[0011] [Figure 1A] 1 shows an XY plan view of a conventional power amplifier. [Figure 1B] 1 shows an XY plan view of a conventional power amplifier. [Diagram 2] 1 shows an XY plan view of a conventional power amplifier. [Figure 3A] FIG. 1 illustrates an XY plan view of an exemplary semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 3B] FIG. 1 illustrates an XY plan view of an exemplary semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 4A] FIG. 2 illustrates an XY plan view of another exemplary semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 4B] FIG. 2 illustrates an XY plan view of another exemplary semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 5A] 1A and 1B show an XY plan view and a cross-sectional view of a conventional unit cell of a conventional power amplifier. [Figure 5B] 1A and 1B show an XY plan view and a cross-sectional view of a conventional unit cell of a conventional power amplifier. [Figure 5C] 1A and 1B show an XY plan view and a cross-sectional view of a conventional unit cell of a conventional power amplifier. [Figure 6A] 1A-1C show XY plan and cross-sectional views of an exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 6B] 1A-1C show XY plan and cross-sectional views of an exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 6C] 1A-1C show XY plan and cross-sectional views of an exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 7A] 1A-1C show XY plan and cross-sectional views of another exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 7B] 1A-1C show XY plan and cross-sectional views of another exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 7C] 1A-1C show XY plan and cross-sectional views of another exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 7D]1A-1C show XY plan and cross-sectional views of another exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 8A] 1A-1C show XY plan and cross-sectional views of another exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 8B] 1A-1C show XY plan and cross-sectional views of another exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 8C] 1A-1C show XY plan and cross-sectional views of another exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 8D] 1A-1C show XY plan and cross-sectional views of another exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 9A] 1 shows an XY plan view of another conventional power amplifier. [Figure 9B] 1 shows an XY plan view of another conventional power amplifier. [Figure 10] 1 shows an XY plan view of another conventional power amplifier. [Figure 11A] FIG. 2 illustrates an XY plan view of another exemplary semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 11B] FIG. 2 illustrates an XY plan view of another exemplary semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 12A] FIG. 2 illustrates an XY plan view of another exemplary semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 12B] FIG. 2 illustrates an XY plan view of another exemplary semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 13A] 1A and 1B show an XY plan view and a cross-sectional view of a conventional unit cell of a conventional power amplifier. [Figure 13B] 1A and 1B show an XY plan view and a cross-sectional view of a conventional unit cell of a conventional power amplifier. [Figure 13C] 1A and 1B show an XY plan view and a cross-sectional view of a conventional unit cell of a conventional power amplifier. [Figure 14A]1A-1C show XY plan and cross-sectional views of an exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 14B] 1A-1C show XY plan and cross-sectional views of an exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 14C] 1A-1C show XY plan and cross-sectional views of an exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 15A] FIG. 1 illustrates an XY plan view of another exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 15B] FIG. 1 illustrates an XY plan view of another exemplary unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 16A] 1 illustrates example steps for fabricating a unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 16B] 1 illustrates example steps for fabricating a unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 16C] 1 illustrates example steps for fabricating a unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 16D] 1 illustrates example steps for fabricating a unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 16E] 1 illustrates example steps for fabricating a unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 16F] 1 illustrates example steps for fabricating a unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 16G] 1 illustrates example steps for fabricating a unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 16H] 1 illustrates example steps for fabricating a unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 16I] 1 illustrates example steps for fabricating a unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 16J]1 illustrates example steps for fabricating a unit cell of a semiconductor device in accordance with one or more embodiments of the present disclosure. [Figure 17A] 1 illustrates another example of a stage for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 17B] 1 illustrates another example of a stage for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 17C] 1 illustrates another example of a stage for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 17D] 1 illustrates another example of a stage for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 17E] 1 illustrates another example of a stage for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 17F] 1 illustrates another example of a stage for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 17G] 1 illustrates another example of a stage for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 17H] 1 illustrates another example of a stage for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 17I] 1 illustrates another example of a stage for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 18] 1 illustrates a flowchart of an exemplary method for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 19] 1 illustrates a flowchart of another exemplary method for fabricating a unit cell of a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 20] 1 illustrates various electronic devices in which one or more aspects of the present disclosure may be utilized. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Other objects and advantages associated with the aspects disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. According to common practice, features illustrated by the drawings may not be drawn to scale. Thus, dimensions of illustrated features may be arbitrarily expanded or reduced for clarity. According to common practice, some of the drawings have been simplified for clarity. Thus, the drawings may not show all components of a particular apparatus or method. Moreover, like reference numerals refer to like features throughout the specification and figures.

[0013] Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternative aspects or embodiments may be devised without departing from the scope of the teachings herein. In addition, well-known elements of the exemplary embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

[0014] In some described exemplary implementations, instances are identified where portions of the structure and operation of various components may be derived from known conventional techniques and configured in accordance with one or more exemplary embodiments. In such instances, some internal details of the structure and / or operation of known conventional components may be omitted to help avoid potentially obscuring the concepts illustrated in the exemplary embodiments disclosed herein.

[0015] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates otherwise. It is further to be understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0016] As mentioned above, PAs can occupy a significant area of ​​an RFFE module. For example, a GaAs PA can occupy an area of ​​about 1000 μm×1000 μm. Since GaAs is more expensive than silicon (Si), such a large design size can be costly. To address such issues, it is proposed to reduce the size by patterning the thermal bumps only or substantially only on the active devices.

[0017] FIG. 1A shows an XY plan view of a conventional power amplifier (PA) 100. As can be seen, the conventional PA 100 includes a plurality of unit cells 150 formed on a substrate 110. The plurality of unit cells 150 includes a plurality of active devices (which will be further described below). The PA 100 also includes a first metal layer 120, a second metal layer 130, and a third metal layer 140 patterned on the substrate 110 and on the plurality of active devices. In the conventional PA 100, a thermal bump 135 is formed by the second metal layer 130 and the third metal layer 140. A portion of the second metal layer 130 corresponding to the bump 135 is connected to the third metal layer 140 through a large via, as shown in FIG. 1B.

[0018] FIG. 2 also shows an XY plan view of the conventional PA 100 to illustrate one or more problems associated with conventional PAs. In FIG. 2, a thermal bump 135 is shown connected to a first thermal bump end 136 and a second thermal bump end 138. The area between the first thermal bump end 136 and the second thermal bump end 138 includes an active area 132 and a non-active area 134. In this example, the second metal layer 130 on which the thermal bump 135 is formed covers or overlaps both the active area 132 and the non-active area 134. This means that a long power path to the base of a heterojunction bipolar transistor (an example of an active device) is required. This is mostly wasted space below the thermal bump 135.

[0019] 3A and 3B show an XY plan view of a semiconductor device 300, e.g., a power amplifier, that addresses one or more problems of the conventional PA 100. As can be seen, the semiconductor device 300 may include a plurality of unit cells 350 formed on a substrate 310. The plurality of unit cells 350 include a plurality of active devices 355 (again, as described further below). The plurality of active devices 355 may have a first width in a first direction (e.g., the X direction) and may be aligned along a first length in a second direction (e.g., the Y direction) (not shown).

[0020] The semiconductor device 300 may also include a first metal layer 320, a second metal layer 330, and a third metal layer 340 patterned over the substrate 310 and over the plurality of active devices 355 (see, e.g., FIGS. 6C, 7C, etc.). The first metal layer 320 may be patterned to form a plurality of thermal pads 322 over the plurality of active devices 355.

[0021] The second metal layer 330 may be patterned to form thermal bumps 335 on the multiple thermal pads 322 (see, e.g., FIG. 6C, FIG. 7C, etc.). Compared to the conventional PA 100, the thermal bumps 335 may be connected to the third metal layer 340 through much smaller vias, as shown in FIG. 3B. The thermal bumps 335 may have a second width in a first direction and a second length in a second direction.

[0022] The second metal layer 330 may also be patterned to form a first thermal bump end 336 and a second thermal bump end 338 between which the thermal bump 335 is connected. The first thermal bump end 336 and the second thermal bump end 338 may each have a width greater than the second width. Also, for ease of explanation, the area between the first thermal bump end 336 and the second thermal bump end 338 may be divided into an active area 332 and a non-active area 334. The active area 332 may be considered to be a portion of the area occupied by the thermal bump 335, and the non-active area 334 may be considered to be the remaining portion of the area. The second width and second length of the thermal bump 335 may be oriented such that the active area 332 overlaps with the first width and first length of the plurality of active devices 355. In fact, the thermal bump 335 may completely overlap with the plurality of active devices 355. At a minimum, the second width of the thermal bump 335 may be equal to or substantially equal to the first width of the plurality of active devices 355 .

[0023] The third metal layer M3 may be patterned to form a thermal bar 342 (see, for example, FIGS. 6B, 6C, 7B, 7C, etc.) on the thermal bump 335. In one embodiment, the active devices 355 are thermally coupled to the thermal pillar 370 via the thermal pads 322, the thermal bumps 335, and the thermal bar 342. For example, they may be in physical contact with each other. For example, the thermal pads 322 may be on and in contact with the active devices 355. Alternatively or in addition, the thermal bumps 335 may be on and in contact with the thermal pads 322. Also, alternatively or in addition, the thermal bar 342 may be on and in contact with the thermal bumps 335. Further alternatively or in addition, the thermal pillar 370 may be formed on and in contact with the thermal bar 342.

[0024] 4A and 4B show an XY plan view of another example semiconductor device according to one or more aspects of the present disclosure. In this example, the semiconductor device may also include one or more thermal fingers 395 formed from the second metal layer 330. The one or more thermal fingers 395 may be connected to the thermal bump 335 and extend therefrom in a first direction into the non-active area 334. This may improve heat dissipation and mechanical robustness of the semiconductor device 300.

[0025] Further description of the unit cell. Figures 5A, 5B and 5C show XY plan view and cross-sectional view of a conventional unit cell 150 of a conventional power amplifier. As seen in Figure 5A, the conventional unit cell 150 includes a resistor 190, an active device 155 and a capacitor 157 adjacent to the active device 155 in the X direction. Also shown are the active area 132 and the non-active area 134. Also shown are the widths of the thermal pillar 170, the thermal bump 135 and the thermal bar 142. It should be noted that in the conventional three-metal layer unit cell 150, the thermal bump 135, the thermal bar 142 and the thermal pillar 170 all occupy both the active area 132 and the non-active area 134.

[0026] 5B shows a cross-section of unit cell 150 along line "1-1" in non-active area 134. In this cross-section, conventional unit cell 150 includes substrate 110, patterned first metal layer 120, dielectric 125, patterned second and third metal layers forming conventional thermal bump 135 and thermal bar 142, final passivation 145, and thermal pillars 170.

[0027] 5C shows a cross-section of unit cell 150 along line "2-2" in active area 132. In this cross-section, unit cell 150 includes substrate 110, transistor 180, thermal pad 122, dielectric 125, thermal bump 135, thermal bar 142, final passivation 145, and thermal pillar 170.

[0028] 6A, 6B, and 6C illustrate XY plan and cross-sectional views of an example unit cell 350 of a semiconductor device 300 (e.g., a power amplifier (PA)) in accordance with one or more aspects of the present disclosure. As seen in FIG. 6A, the unit cell 350 may include an active device 355 and a capacitor 357 adjacent to the active device 355 in a first direction (e.g., the X direction). In addition to the active device 355 and the capacitor 357, the unit cell 350 may include one or more resistors 390.

[0029] Also shown are active areas 332 and non-active areas 334. Additionally, widths of thermal pillars 370, thermal bumps 335 (e.g., formed from patterning second metal layer 330), and thermal bars (e.g., formed from patterning third metal layer 340) are also shown. Note that unlike conventional PA 100, thermal bumps 335 only cover, or substantially only cover, active devices 355. This means that the second width of thermal bumps 335 is equal to, or substantially equal to, the first width of the plurality of active devices 355.

[0030] 6B shows a cross-section of unit cell 350 along line "1-1" in non-active area 334. In this cross-section, unit cell 350 may include substrate 310, patterned first metal layer 320, dielectric 325, thermal bar 342 (e.g., formed from patterned third metal layer 340), final passivation 345, and thermal pillars 370.

[0031] 6C shows a cross-section of unit cell 350 along line "2-2" in active area 332. In this cross-section, unit cell 350 may include substrate 310, transistor 380, a patterned first metal layer 320 on substrate 310, a thermal pad 322 (e.g., formed from first metal layer 320) on transistor 380, dielectric 325, thermal bump 335, thermal bar 342, final passivation 345, and thermal pillar 370.

[0032] Note that in Figure 5B, the second metal layer 130 is still present in the non-active area 134 of the conventional unit cell 150. However, in the example unit cell 350 of Figure 6B, the second metal layer 330 is not present in the non-active area 334. This allows desired properties to be achieved, as described further below.

[0033] In one embodiment, the active device 355 of one or more unit cells 350 can be a bipolar transistor, such as a heterojunction bipolar transistor (HBT), a high electron mobility transistor (HEMT), such as a pHEMT, or the like. This is illustrated in FIGS. 7A-7D. The unit cell 350 of FIG. 7A can include similar components to the unit cell 350 of FIG. 6A. That is, the unit cell 350 of FIG. 7A can include an active device 355, a capacitor 357 adjacent to the active device 355 in a first direction (e.g., X-direction), and one or more resistors 390. Also illustrated are the active and non-active areas 332 and 334, as well as the widths of the thermal pillars 370, the thermal bumps 335, and the thermal bars 342.

[0034] In this case, at least a portion of the capacitor 357 may be in the non-active area 334, i.e., much closer to the active device 355. This is made possible because the second metal layer 330 is not in the non-active area 334. This allows for a reduction in size in a first direction (e.g., the X-direction) of the semiconductor device 300. For example, the size reduction may be 30-50 μm in the first direction.

[0035] 7B shows a cross section of the unit cell 350 along line "1-1" in the non-active area 334. In this cross section, the unit cell 350 may include a capacitor 357 that may comprise a bottom plate 327, a top plate 337, and a capacitor dielectric 367 between the bottom plate 327 and the top plate 337. The first metal layer 320 may be patterned to form the bottom plate 327. The second metal layer 330 or some other metal layer may be patterned to form the top plate 337. That is, the top plate 337 may be electrically coupled to or patterned from the second metal layer 330. On top of the top plate 337, the unit cell 350 may further comprise a thermal bar 342, a final passivation 345, and a thermal pillar 370. A dielectric 333 may be formed between the top plate 337 and the thermal bar 342.

[0036] Figure 7C shows a cross-section of unit cell 350 along line "2-2" in active area 332. This cross-section is similar to the cross-section shown in Figure 6C.

[0037] 7D shows a cross-section of unit cell 350 along line "0-0" outside active area 332 and non-active area 334. This cross-section shows capacitor 357 as described with respect to FIG. 7B. However, in this case, patterned third metal layer 340 may be electrically coupled to top plate 337.

[0038] 8A, 8B, 8C, and 8D show XY plan and cross-sectional views of another exemplary unit cell 350 of a semiconductor device according to one or more aspects of the present disclosure. Here, the active device 355 may be assumed to be a bipolar transistor such as an HBT. As seen in FIG. 8A, the transistor 380 may include an emitter 387 and a collector 389.

[0039] Again, the active and non-active areas 332 and 334 are shown, as well as the widths of the thermal pillars 370, the thermal bumps 335, and the thermal bars 342. In this case, at least a portion of the capacitor 357 may be in the non-active area 334, i.e., much closer to the active device 355. Thus, similar to the unit cell of FIGS. 7A-7B, allowing for a reduction in size of the semiconductor device 300 in a first direction (e.g., the X-direction). Additionally, one or more resistors 390 (e.g., ballast resistors) may also be in the non-active area 334. Again, this is made possible because the second metal layer 330 is not in the non-active area 334.

[0040] Figure 8B shows a cross-section of unit cell 350 taken along line "1-1" in non-active area 334. This cross-section is similar to the cross-section shown in Figure 7B and will not be described further.

[0041] Figure 8D shows a cross-section of unit cell 350 along line "0-0" in the area outside active area 332 and non-active area 334. This cross-section is similar to the cross-section shown in Figure 7D and will not be described further.

[0042] FIG. 8C illustrates a cross-section of the unit cell 350 along line "2-2" in the active region 332. As can be seen, the emitter 387 may be thermally coupled to the thermal bump 335 through the thermal pad 322 corresponding to the active device 355. Also, the collector 389 may not be electrically coupled to the thermal bump 335. The collector pad 361 may be formed on the collector 389 and electrically coupled thereto. The collector pad 361 may comprise a first collector pad 321 formed from the patterned first metal layer 320 and may be on the collector 389. The collector pad 361 may also comprise a second collector pad 331 formed from the patterned second metal layer 330 on the first collector pad 321. This allows the current carrying capacity of the collector 389 to be improved. This in turn allows the size of the semiconductor device 300 in the second direction (e.g., Y direction) to be reduced. The unit cell 350 may further comprise a dielectric 325 , a thermal bar 342 , a final passivation 345 , and a thermal pillar 370 .

[0043] 8A, it should be noted that the collector 389 may be formed on one or both sides in the second direction (e.g., Y direction) of the emitter 387. This means that the collector pad 361 may be formed on one or both sides in the second direction of the emitter 387. This means that the size reduction in the second direction can be from one or both sides of the emitter 387.

[0044] Also, note that resistor 390 may be adjacent to active device 355 of unit cell 350 in a first direction (e.g., X-direction), as seen in FIG. 8A. At least a portion of resistor 390 may be in non-active area 334. In one aspect, capacitor 357 may be a ballast capacitor. Alternatively, or in addition, resistor 390 may be a ballast resistor.

[0045] A three metal layer semiconductor device has been described above. However, similar problems may exist for two metal layer power amplifiers. Therefore, the proposed solution may also be applied to two metal layer semiconductor devices.

[0046] FIG. 9A shows an XY plan view of a conventional two-metal layer power amplifier (PA) 900. As can be seen, the conventional PA 900 includes a plurality of unit cells 950 formed on a substrate 910. The plurality of unit cells 950 includes a plurality of active devices 955. The PA 900 also includes a first metal layer 920 and a second metal layer 930 patterned on the substrate 910 and on the plurality of active devices. In the conventional PA 900, a thermal bump 935 is formed by the second metal layer 930. A portion of the second metal layer 930 corresponding to the thermal bump 935 is connected to a thermal pillar 970 through a large via, as shown in FIG. 9B.

[0047] FIG. 10 also shows an XY plan view of a conventional PA 900. In FIG. 10, a thermal bump 935 is shown connected to a first thermal bump end 936 and a second thermal bump end 938. The area between the first thermal bump end 936 and the second thermal bump end 938 includes an active area 932 and a non-active area 934. In this case, the second metal layer 930 covers or overlaps both the active area and the non-active area 934. This means that a long power path to the base of a heterojunction bipolar transistor (an example of an active device) is required. This is mostly wasted space below the thermal bump 935.

[0048] 11A and 11B show an XY plan view of a semiconductor device 1100, e.g., a power amplifier, that addresses one or more problems of the conventional PA 900. As can be seen, the semiconductor device 1100 may include a plurality of unit cells 1150 formed on a substrate 1110. The plurality of unit cells 1150 include a plurality of active devices 1155. The plurality of active devices 1155 may have a first width in a first direction (e.g., the X direction) and may be aligned along a first length in a second direction (e.g., the Y direction) (not shown).

[0049] The semiconductor device 1100 may also include a first metal layer 1120 and a second metal layer 1130 patterned over the substrate 1110 and over the plurality of active devices 1155. The first metal layer 1120 may be patterned to form a plurality of thermal pads 1122 over the plurality of active devices 1155.

[0050] The second metal layer 1130 may be patterned to form thermal bumps 1135 on the multiple thermal pads 1122. Compared to the conventional PA900, the thermal bumps 1135 may be connected to the thermal pillars 1170 through much smaller vias, as shown in FIG. 11B. The thermal bumps 1135 may have a second width in a first direction and a second length in a second direction.

[0051] The second metal layer 1130 may also be patterned to form a first thermal bump end 1136 and a second thermal bump end 1138 between which the thermal bump 1135 is connected. The first thermal bump end 1136 and the second thermal bump end 1138 may each have a width greater than the second width. The area between the first thermal bump end 1136 and the second thermal bump end 1138 may be divided into an active area 1132 and a non-active area 1134. The active area may be considered to be a portion of the area occupied by the thermal bump 1135, and the non-active area 1134 may be considered to be the remaining portion of the area. The second width and second length of the thermal bump 1135 may be oriented such that the active area 1132 overlaps with the first width and first length of the plurality of active devices 1155. The thermal bump 1135 may completely overlap the plurality of active devices 1155. At least, the second width of the thermal bump 1135 may be equal to or substantially equal to the first width of the plurality of active devices 1155.

[0052] In one aspect, the active devices 1155 are thermally coupled to the thermal pillars 1170 via the thermal pads 1122 and the thermal bumps 1135. For example, they may be in physical contact with one another. For example, the thermal pads 1122 may be on and in contact with the active devices 1155. Alternatively or in addition, the thermal bumps 1135 may be on and in contact with the thermal pads 1122. Also, alternatively or in addition, the thermal pillars 1170 may be on and in contact with the thermal bumps 1135.

[0053] 12A and 12B show an XY plan view of another example semiconductor device according to one or more aspects of the present disclosure. In this example, the semiconductor device may also include one or more thermal fingers 1195 formed from the second metal layer 1130. The one or more thermal fingers 1195 may be connected to a thermal bump 1135 and extend therefrom in a first direction into the non-active area 1134. This may improve heat dissipation and increase the mechanical robustness of the semiconductor device 1100.

[0054] For the purposes of illustrating the unit cell in the two metal layer example, Figures 13A, 13B, and 13C show XY plan and cross-sectional views of a conventional unit cell 950 of a conventional power amplifier. As seen in Figure 13A, the conventional unit cell 950 includes a resistor 990, an active device 955, and a capacitor 957 adjacent in the X direction from the active device 955. Also shown are the active area 932 and the inactive area 934. Additionally, the widths of the thermal pillars 970 and the thermal bumps 935 are also shown. Note that in the conventional two metal layer unit cell 950, all of the thermal bumps 935 and the thermal pillars 970 occupy both the active area 932 and the inactive area 934.

[0055] 13B shows a cross-section of unit cell 950 along line "1-1" in non-active area 934. Note that this is also outside the width of thermal pillar 970. In this cross-section, conventional unit cell 950 includes substrate 910, patterned first metal layer 920, thermal pad 922, dielectric 925, patterned second metal layer forming conventional thermal bump 935, final passivation 945, and thermal pillar 970.

[0056] 13C shows a cross-section of unit cell 950 along line "2-2" in active area 932. In this cross-section, unit cell 950 includes substrate 910, transistor 980, patterned first metal layer 920, dielectric 925, thermal bump 935, final passivation 945, and thermal pillar 970.

[0057] 14A, 14B, and 14C show XY plan and cross-sectional views of an exemplary unit cell 1150 of a semiconductor device 1100 (e.g., a power amplifier (PA)) according to one or more aspects of the present disclosure. As seen in FIG. 14A, the unit cell 1150 may comprise an active device 1155 and a capacitor 1157 adjacent to the active device 1155 in a first direction (e.g., X-direction). Also shown are the active area 1132 and the non-active area 1134, as well as the width of the thermal pillar 1170 and the thermal bump 1135. In this case, at least a portion of the capacitor 1157 may be in the non-active area 1134, i.e., much closer to the active device 1155. This is made possible because the second metal layer 1130 is not in the non-active area 1134.

[0058] 14B shows a cross-section of a unit cell 1150 along line "1-1" in the non-active area 1134. In this cross-section, the unit cell 1150 may include a bottom plate 1127, a top plate 1137, and a capacitor 1157, which may include a capacitor dielectric 1167 between the bottom plate 1127 and the top plate 1137. The first metal layer 1120 may be patterned to form the bottom plate 1127. The second metal layer 1130, or some other metal layer, may be patterned to form the top plate 1137. That is, the top plate 1137 may be electrically coupled to or patterned from the second metal layer 1130.

[0059] 14C shows a cross-section of a unit cell 1150 along line "2-2" in the active area 1132. In this cross-section, the unit cell 1150 may include a substrate 1110, a transistor 1180, a patterned first metal layer 1120 on the substrate 1110, a thermal pad 1122 (e.g., formed from the first metal layer 1120) on the transistor 1180, a dielectric 1125, a thermal bump 1135, a final passivation 1145, and a thermal pillar 1170.

[0060] The unit cells of Figures 14A-14C can be viewed as two metal layer versions of the three metal layer unit cells of Figures 7A-7D, and thus similar size reduction advantages can be achieved.

[0061] Plan views of some other exemplary unit cells are shown in Figures 15A and 15B. The unit cell 1150 of Figure 15A can be a two metal layer version of the three metal layer unit cell shown in Figures 6A-6C. Note that unlike the conventional two metal layer unit cell of Figures 13A-13C, the thermal bump 1135 of the unit cell of Figure 15A is only over the active device. It should be relatively easy to reach the unit cell 1150 of Figure 15A.

[0062] The unit cell of FIG. 15B, which includes a transistor with emitter 1187 and collector 1189, may be a two-metal-layer version of the three-metal-layer unit cell shown in FIGS. 8A-8D. That is, at least a portion of the capacitor 1157 may be located in the non-active area 1134. As a result, a size reduction in the first direction may be achieved. Alternatively or additionally, one or more resistors 1190 may be in the non-active area 1134 as well. Further alternatively or additionally, the current capacity of an active device (e.g., an HBT) may be improved by electrically coupling the collector 1189 to a collector pad formed from the first and second metal layers. Again, it should be relatively easy to reach the unit cell of FIG. 15B.

[0063] Figures 16A-16J show exemplary stages in fabricating a three metal layer unit cell of a semiconductor device, each of which may be a view along any one or more of lines "0-0," "1-1," or "2-2" in Figures 6A, 7A, and 8A.

[0064] FIG. 16A illustrates a stage at which a transistor 380 (or more generally an active device 355 ) may be fabricated on a substrate 310 .

[0065] 16B illustrates a stage where a first metal layer 320 may be deposited and patterned to form various components. For example, a thermal pad 322 may be formed on a transistor 380. The first metal layer 320 may be gold (Au), an Au alloy, copper (Cu), aluminum (Al), or the like, or any combination thereof. The first metal layer 320 may be formed by evaporation, plating, an etching process, a lift-off process, or the like.

[0066] FIG. 16C illustrates the steps in which a dielectric layer may be deposited and patterned to form a capacitor dielectric 367, and a capacitor metal may be deposited and patterned to form a top plate 337. The capacitor dielectric may be formed from silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like, or any combination thereof. The capacitor dielectric may be formed by spin coating, plasma enhanced chemical vapor deposition (PECVD), sputtering, atomic layer deposition (ALD), or the like. The capacitor metal may be Au, Au alloy, Cu, Al, or the like, or any combination thereof. The first metal layer 320 may be formed by evaporation, plating, an etching process, a lift-off process, or the like, and in one embodiment, the capacitor metal may be the second metal layer 330. In another embodiment, the capacitor metal may be a metal separate from the second metal layer 330.

[0067] 16D and 16E show stages where a dielectric layer may be deposited and patterned to form dielectric 325. The dielectric layer may be SiO2, SiN, SiON, benzocyclobutene (BCB), polyimide, or any combination thereof. To better reduce parasitic capacitance, a thicker layer may be preferred. The dielectric layer may be formed by spin coating, plasma enhanced chemical vapor deposition (PECVD), sputtering, atomic layer deposition (ALD), etc.

[0068] 16F illustrates a stage where a second metal layer 330 may be deposited and patterned to form thermal bumps 335. The second metal layer 330 may be Au, an Au alloy, Cu, Al, etc., or any combination thereof. The second metal layer 330 may be formed by evaporation, plating, an etching process, a lift-off process, etc.

[0069] FIG. 16G shows a stage where a dielectric layer may be deposited and patterned to form a dielectric 333 between the second metal layer 330 and the third metal layer 340, for example between the thermal bump 335 and the thermal bar 342. The dielectric layer may be SiO2, SiN, SiON, BCB, polyimide, or any combination thereof. To better reduce parasitic capacitance, a thicker layer may be preferred. The dielectric layer may be formed by spin coating, PECVD, sputtering, ALD, etc.

[0070] 16H illustrates a stage where a third metal layer 340 may be deposited and patterned to form various components. For example, a thermal bar 342 may be formed. The third metal layer 340 may be Au, an Au alloy, Cu, Al, etc., or any combination thereof. The third metal layer 340 may be formed by evaporation, plating, an etching process, a lift-off process, etc.

[0071] FIG. 16I shows a stage where a dielectric layer may be deposited and patterned to form a final passivation 345. The final dielectric layer may be SiO2, SiN, SiON, BCB, polyimide, or any combination thereof. To better reduce parasitic capacitance, a thicker layer may be preferred. The final dielectric layer may be formed by spin coating, PECVD, sputtering, ALD, etc.

[0072] 16J shows a stage where thermal pillars 370 may be formed. For example, a thick Cu layer may be electroplated to form thermal pillars 170. A seed layer 372 may be formed prior to forming thermal pillars 370, and a cap layer may be plated on thermal pillars 370 to form caps 374. A high temperature reflow may be performed after cap layer plating.

[0073] Figures 17A-17J show exemplary stages in fabricating a three metal layer unit cell of a semiconductor device, each of which may be a view along any one or more of lines "0-0," "1-1," or "2-2" in Figures 14A, 15A, and 15B.

[0074] FIG. 17A illustrates a stage at which a transistor 1180 (or more generally an active device 1155 ) may be fabricated on a substrate 1110 .

[0075] 17B illustrates a stage where a first metal layer 1120 may be deposited and patterned to form various components. For example, a thermal pad 1122 may be formed on a transistor 1180. The first metal layer 1120 may be Au, an Au alloy, Cu, Al, etc., or any combination thereof. The first metal layer 1120 may be formed by evaporation, plating, an etching process, a lift-off process, etc.

[0076] 17C illustrates the steps in which a dielectric layer may be deposited and patterned to form the capacitor dielectric 1167, and the capacitor metal may be deposited and patterned to form the top plate 1137. The capacitor dielectric may be formed from SiO2, SiN, SiON, Al2O3, etc., or any combination thereof. The capacitor dielectric may be formed by spin coating, PECVD, sputtering, ALD, etc., and the capacitor metal may be Au, Au alloy, Cu, Al, etc., or any combination thereof. The first metal layer 1120 may be formed by deposition, plating, an etching process, a lift-off process, etc., and in one embodiment, the capacitor metal may be the second metal layer 1130. In another embodiment, the capacitor metal may be a metal separate from the second metal layer 1130.

[0077] 17D and 17E show stages where a dielectric layer may be deposited and patterned to form dielectric 1125. The dielectric layer may be SiO2, SiN, SiON, BCB, polyimide, or any combination thereof. To better reduce parasitic capacitance, a thicker layer may be preferred. The dielectric layer may be formed by spin coating, PECVD, sputtering, ALD, etc.

[0078] 17F and 17G show stages where a second metal layer 1130 may be deposited and patterned to form various components. For example, a thermal bump 1135 may be formed. The second metal layer 1130 may be Au, Au alloy, Cu, Al, etc., or any combination thereof. The second metal layer 1130 may be formed by deposition, plating, an etching process, a lift-off process, etc., and in one embodiment, the second metal layer 1130 may be combined with a cap metal.

[0079] FIG. 17H shows a stage where a dielectric layer may be deposited and patterned to form a final passivation 1145. The final dielectric layer may be SiO2, SiN, SiON, BCB, polyimide, or any combination thereof. To better reduce parasitic capacitance, a thicker layer may be preferred. The final dielectric layer may be formed by spin coating, PECVD, sputtering, ALD, etc.

[0080] 17I shows a stage where thermal pillars 1170 may be formed. For example, a thick Cu layer may be electroplated to form thermal pillars 1170. A seed layer 1172 may be formed prior to forming thermal pillars 1170, and a cap layer may be plated on thermal pillars 1170 to form caps 1174. A high temperature reflow may be performed after cap layer plating.

[0081] 18 shows a flow chart of an exemplary method 1800 of fabricating a semiconductor device such as a three metal layer power amplifier. The blocks of the method 1800 correspond to the stages in FIGS. 16A-16J.

[0082] At block 1810, a plurality of unit cells may be formed. The plurality of unit cells may comprise a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and be aligned along a first length in a second direction.

[0083] In block 1820, the first metal layer may be patterned to form a plurality of thermal pads over the plurality of active devices.

[0084] At block 1830, the second metal layer may be patterned to form first and second thermal bump ends and a thermal bump connected therebetween. The thermal bump may have a second width in a first direction and a second length in a second direction. The thermal bump may be formed on a plurality of thermal pads.

[0085] In block 1840, the third metal layer may be patterned to form a thermal bar on the thermal bumps.

[0086] At block 1850, a thermal pillar may be formed on the thermal bar. A plurality of active devices may be thermally coupled to the thermal pillar via a plurality of thermal pads, thermal bumps, and the thermal bar. The first and second thermal bump ends may each have a width greater than the second width. The area between the first and second thermal bump ends may be divided into an active area and a non-active area. The active area may be a portion of the area occupied by the thermal bump, and the non-active area may be the remaining portion of the area. The second width and second length of the thermal bump may be oriented such that the active area overlaps with the first width and first length of the plurality of active devices.

[0087] FIG. 19 illustrates a flow chart of an exemplary method 1900 of fabricating a semiconductor device, such as a two-metal layer power amplifier.

[0088] At block 1910, a plurality of unit cells may be formed. The plurality of unit cells may comprise a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and be aligned along a first length in a second direction.

[0089] In block 1920, the first metal layer may be patterned to form a plurality of thermal pads over the plurality of active devices.

[0090] At block 1930, the second metal layer may be patterned to form first and second thermal bump ends and a thermal bump connected therebetween. The thermal bump may have a second width in a first direction and a second length in a second direction. The thermal bump may be formed on a plurality of thermal pads.

[0091] At block 1950, a thermal pillar may be formed on the thermal bump. A plurality of active devices may be thermally coupled to the thermal pillar via a plurality of thermal pads, thermal bumps, and a thermal bar. The first and second thermal bump ends may each have a width greater than the second width. The area between the first and second thermal bump ends may be divided into an active area and a non-active area. The active area may be a portion of the area occupied by the thermal bump, and the non-active area may be the remaining portion of the area. The second width and second length of the thermal bump may be oriented such that the active area overlaps with the first width and first length of the plurality of active devices.

[0092] It will be understood that the foregoing fabrication process and related description are provided merely as general illustrations of some of the aspects of the present disclosure, and are not intended to limit the scope of the present disclosure or the appended claims. Furthermore, many details in the fabrication process known to those skilled in the art may be omitted or combined in a summary process section to facilitate understanding of the various aspects disclosed without detailed description of each detail and / or all possible process variations. Furthermore, it will be understood that the illustrated configurations and descriptions are provided merely to aid in the explanation of the various aspects disclosed herein. For example, the number and location of MIM capacitors and / or inductors, the metallization structure may have more or fewer conductive and insulating layers, the orientation, size of the cavities, whether formed of multiple cavities, closed or open, and other aspects may have variations driven by specific application design features, such as the number of antennas, antenna type, frequency range, power, etc. Thus, the foregoing illustrative examples and related figures should not be construed as limiting the various aspects disclosed and claimed herein.

[0093] 20 illustrates various electronic devices 2000 that may be integrated with any of the aforementioned semiconductor devices according to various aspects of the present disclosure. For example, a mobile phone device 2002, a laptop computer device 2004, and a stationary terminal device 2006 may each be generally considered user equipment (UE) and may include a semiconductor device as described herein. The devices 2002, 2004, 2006 illustrated in FIG. 20 are merely examples. Other electronic devices may also include RF filters including groups of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented within automotive vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0094] The devices and functions disclosed above may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer readable medium. Some or all of such files may be provided to a fabricator who fabricates devices based on such files. The resulting product may include semiconductor wafers that are then cut into semiconductor dies and packaged with antennas on glass devices. The antennas on glass devices may then be used in devices described herein.

[0095] The following numbered clauses describe example implementations. Clause 1: A method for fabricating a semiconductor device comprising: a plurality of unit cells comprising a plurality of active devices on a substrate, the plurality of active devices having a first width in a first direction and aligned along a first length in a second direction; a first metal layer patterned to form a plurality of thermal pads on the plurality of active devices; a second metal layer patterned to form first and second thermal bump ends and thermal bumps connected therebetween, the thermal bumps having a second width in the first direction and a second length in the second direction, the thermal bumps being formed on the plurality of thermal pads; and a third metal layer patterned to form a thermal bar on the thermal bumps. a metal layer and a thermal pillar formed on the thermal bar, a plurality of active devices are thermally coupled to the thermal pillar via a plurality of thermal pads, thermal bumps, and the thermal bar, a first and second thermal bump ends each have a width greater than a second width, an area between the first bump ends and the second bump ends is divided into an active area and a non-active area, the active area being a portion of the area occupied by the thermal bump and the non-active area being the remainder of the area, and a second width and a second length of the thermal bump being oriented such that the active area overlaps with a first width and a first length of the plurality of active devices.

[0096] Clause 2: The semiconductor device of clause 1, wherein the thermal bump completely overlaps the plurality of active devices.

[0097] Clause 3: The semiconductor device of clause 2, wherein the second width of the thermal bump is substantially equal to the first width of the plurality of active devices.

[0098] Clause 4: A semiconductor device according to any one of clauses 1 to 3, wherein the active device of at least one unit cell is a bipolar transistor.

[0099] Clause 5: The semiconductor device of clause 4, wherein the bipolar transistor is a heterojunction bipolar transistor (HBT).

[0100] Clause 6: A semiconductor device described in any of clauses 4 to 5, wherein the emitter of the bipolar transistor is thermally coupled to the thermal bump via a thermal pad corresponding to the active device, and the collector of the bipolar transistor is not electrically coupled to the thermal bump.

[0101] Clause 7: The semiconductor device of clause 6, further comprising a collector pad on the collector and electrically coupled to the collector, the collector pad comprising a first collector pad on the collector and a second collector pad on the first collector pad, the first collector pad being formed from a patterned first metal layer and the second collector pad being formed from a patterned second metal layer.

[0102] Clause 8: The semiconductor device of clause 7, wherein a collector pad is formed on one or both sides of the emitter in the second direction.

[0103] Clause 9: A semiconductor device described in any of clauses 1 to 8, wherein at least one unit cell further comprises a capacitor on the substrate adjacent to the active device of the at least one unit cell in a first direction, at least a portion of the capacitor being within the non-active area.

[0104] Clause 10: A semiconductor device as described in clause 9, wherein the capacitor comprises a lower plate, an upper plate, and a capacitor dielectric between the lower plate and the upper plate, the lower plate being patterned from a first metal layer and the upper plate being electrically coupled to a patterned third metal layer.

[0105] Clause 11: A semiconductor device described in any of clauses 1 to 10, wherein at least one unit cell further comprises a resistor on the substrate adjacent in a first direction to the active device of the at least one unit cell, at least a portion of the resistor being within a non-active area.

[0106] Clause 12: A semiconductor device described in any of items 1 to 11, further comprising one or more thermal fingers formed from a second metal layer, the one or more thermal fingers being connected to the thermal bump and extending from the thermal bump in a first direction into the non-active area.

[0107] Clause 13: A semiconductor device described in any of clauses 1 to 12, wherein a plurality of thermal pads are on and in contact with a plurality of active devices, a thermal bump is on and in contact with a plurality of thermal pads, a thermal bar is on and in contact with the thermal bumps, and a thermal pillar is on and in contact with the thermal bar.

[0108] Clause 14: A method for fabricating a semiconductor device comprising: a plurality of unit cells comprising a plurality of active devices on a substrate, the plurality of active devices having a first width in a first direction and aligned along a first length in a second direction; a first metal layer patterned to form a plurality of thermal pads on the plurality of active devices; a second metal layer patterned to form first and second thermal bump ends and thermal bumps connected therebetween, the thermal bumps having a second width in the first direction and a second length in the second direction, the thermal bumps being formed on the plurality of thermal pads; and a thermal pillar having a first width and a second length, a plurality of active devices thermally coupled to the thermal pillar via a plurality of thermal pads and thermal bumps, a first and second thermal bump ends each having a width greater than a second width, an area between the first bump ends and the second bump ends being divided into an active area and a non-active area, the active area being a portion of the area occupied by the thermal bump and the non-active area being the remainder of the area, and a second width and a second length of the thermal bump being oriented such that the active area overlaps with a first width and a first length of the plurality of active devices.

[0109] Clause 15: The semiconductor device of clause 14, wherein the thermal bump completely overlaps the plurality of active devices.

[0110] Clause 16: The semiconductor device of clause 15, wherein the second width of the thermal bump is substantially equal to the first width of the plurality of active devices.

[0111] Clause 17: A semiconductor device according to any one of clauses 14 to 16, wherein the active device of at least one unit cell is a bipolar transistor.

[0112] Clause 18: The semiconductor device of clause 17, wherein the bipolar transistor is a heterojunction bipolar transistor (HBT).

[0113] Clause 19: A semiconductor device described in any of clauses 17 to 18, wherein the emitter of the bipolar transistor is thermally coupled to the thermal bump via a thermal pad corresponding to the active device, and the collector of the bipolar transistor is not electrically coupled to the thermal bump.

[0114] Clause 20: The semiconductor device of clause 19, further comprising a collector pad on the collector and electrically coupled to the collector, the collector pad comprising a first collector pad on the collector and a second collector pad on the first collector pad, the first collector pad being formed from a patterned first metal layer and the second collector pad being formed from a patterned second metal layer.

[0115] Clause 21: The semiconductor device of clause 20, wherein a collector pad is formed on one or both sides of the emitter in the second direction.

[0116] Clause 22: A semiconductor device described in any of clauses 14 to 21, wherein at least one unit cell further comprises a capacitor on the substrate adjacent to the active device of the at least one unit cell in a first direction, at least a portion of the capacitor overlapping with the inactive width of the thermal bar.

[0117] Clause 23: A semiconductor device as described in clause 22, wherein the capacitor comprises a lower plate, an upper plate, and a capacitor dielectric between the lower plate and the upper plate, the lower plate being patterned from a first metal layer and the upper plate being patterned from a second metal layer.

[0118] Clause 24: A semiconductor device as described in clauses 14 to 23, wherein at least one unit cell further comprises a resistor on the substrate adjacent in a first direction to the active device of the at least one unit cell, at least a portion of the resistor overlapping with an inactive width of the thermal bar.

[0119] Clause 25: A semiconductor device as described in clauses 14 to 24, further comprising one or more thermal fingers formed from a second metal layer, the one or more thermal fingers being connected to the thermal bump and extending in a first direction from the thermal bump.

[0120] Clause 26: A semiconductor device as described in clauses 14 to 25, wherein a plurality of thermal pads are on and in contact with a plurality of active devices, a thermal bump is on and in contact with a plurality of thermal pads, and a thermal pillar is on and in contact with the thermal bump.

[0121] Clause 27: A method of fabricating a semiconductor device, comprising: forming a plurality of unit cells on a substrate, the plurality of active devices having a first width in a first direction and aligned along a first length in a second direction; patterning a first metal layer to form a plurality of thermal pads on the plurality of active devices; patterning a second metal layer to form first and second thermal bump ends and thermal bumps connected therebetween, the thermal bumps having a second width in the first direction and a second length in the second direction, the thermal bumps being formed on the plurality of thermal pads; patterning a third metal layer to form a plurality of thermal pads on the substrate; forming a thermal pillar on the thermal bar by thermal padding, wherein a plurality of active devices are thermally coupled to the thermal pillar via the plurality of thermal pads, the thermal bumps, and the thermal bar, wherein first and second thermal bump ends each have a width greater than a second width, wherein an area between the first bump ends and the second bump ends is divided into an active area and a non-active area, wherein the active area is a portion of the area occupied by the thermal bump and the non-active area is the remainder of the area, and wherein the second width and second length of the thermal bump are oriented such that the active area overlaps with the first width and first length of the plurality of active devices.

[0122] Clause 28: The method of clause 27, wherein the thermal bump completely overlaps the plurality of active devices, and the second width of the thermal bump is substantially equal to the first width of the plurality of active devices.

[0123] Clause 29: A method of fabricating a semiconductor device, comprising: forming a plurality of unit cells on a substrate, the plurality of active devices having a first width in a first direction and aligned along a first length in a second direction; patterning a first metal layer to form a plurality of thermal pads on the plurality of active devices; and patterning a second metal layer to form first and second thermal bump ends and thermal bumps connected therebetween, the thermal bumps having a second width in the first direction and a second length in the second direction, the thermal bumps being formed on the plurality of thermal pads. and forming a thermal pillar formed on the thermal bump, wherein a plurality of active devices are thermally coupled to the thermal pillar via a plurality of thermal pads and thermal bumps, a first and second thermal bump ends each having a width greater than a second width, an area between the first thermal bump ends and the second thermal bump ends is divided into an active area and a non-active area, the active area being a portion of the area occupied by the thermal bumps and the non-active area being the remainder of the area, and a second width and a second length of the thermal bump are oriented such that the active area overlaps with a first width and a first length of the plurality of active devices.

[0124] Clause 30: The method of clause 29, wherein the thermal bump completely overlaps the plurality of active devices, and the second width of the thermal bump is substantially equal to the first width of the plurality of active devices.

[0125] As used herein, terms such as "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal", and variations thereof may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in automobiles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short range radio, etc.). These terms are also intended to include a device that communicates with another device capable of receiving wireless communication and / or navigation signals, such as by a short-range wireless connection, an infrared connection, a wired connection, or other connection, regardless of whether the satellite signal reception, assistance data reception, and / or location-related processing occurs on that device or on another device. Furthermore, these terms are intended to include all devices, including wireless and wired communication devices, that can communicate with a core network via a Radio Access Network (RAN) through which the UE can connect to external networks, such as the Internet, and to other UEs. Of course, other mechanisms for connecting to a core network and / or the Internet are also possible for a UE, such as via a wired access network, a Wireless Local Area Network (WLAN) (e.g., based on IEEE 802.11, etc.), etc.A UE may be embodied by any of several types of devices, including, but not limited to, a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smart phone, a tablet, a tracking device, an asset tag, etc. A communication link through which a UE may transmit signals to a RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). A communication link through which a RAN may send signals to a UE is called a downlink channel or a forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein, the term traffic channel (TCH) may refer to either an uplink / reverse traffic channel or a downlink / forward traffic channel.

[0126] Wireless communication between electronic devices can be based on various technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP® Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread) or other protocols that may be used within wireless or data communication networks. Bluetooth® Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group that aims to significantly reduce power consumption and cost while maintaining a similar communication range. BLE was integrated into the main Bluetooth standard in 2010 by adopting the Bluetooth Core Specification Version 4.0 and was updated in Bluetooth 5.

[0127] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as advantageous over other examples. Likewise, the term "example" does not imply that all examples include the described features, advantages or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0128] It should be noted that the terms "connected" and "coupled," or any variation thereof, mean any direct or indirect connection or coupling between elements, unless the connection is expressly disclosed as being directly connected, and may encompass the presence of intermediate elements between two elements that are "connected" or "coupled" together through intermediary elements.

[0129] Any reference herein to an element using a designation such as "first," "second," etc. is not intended to limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of an element. Also, unless otherwise stated, a set of elements can comprise one or more elements.

[0130] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0131] Nothing described, illustrated, or shown in this application is intended to disclose to the public any element, act, feature, benefit, advantage, or equivalent, whether or not that element, act, feature, benefit, advantage, or equivalent is recited in a claim.

[0132] In the above detailed description, it can be seen that various features are grouped together in each example. This method of disclosure should not be understood as the claimed examples having more features than are expressly recited in each claim. Rather, the disclosure may include fewer features than all of the individual examples disclosed. Thus, the following claims are hereby considered incorporated into this description, with each claim standing alone as a separate example. Although each claim standing alone as a separate example, it should be noted that a dependent claim may refer to a specific combination with one or more claims within the scope of the claim, while other examples may include or include a combination of said dependent claim with the subject matter of any other dependent claim, or a combination of any feature with other dependent claims and independent claims. Such combinations are suggested herein unless it is expressly stated that no specific combination is intended. It is further intended that features of a claim may be included in any other independent claim, even if said claim is not directly dependent on the independent claim.

[0133] It is further noted that the methods, systems and apparatus disclosed in the present description or claims may be implemented by a device comprising means for performing the respective acts and / or functions of the disclosed methods.

[0134] Further, in some instances, an individual act may be subdivided into or include one or more sub-acts, and such sub-acts may be included in and become part of the disclosure of the individual act.

[0135] Although the above disclosure illustrates examples of the present disclosure, it should be noted that various modifications and changes can be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or acts of the method claims according to the examples of the present disclosure described herein need not be performed in any particular order. In addition, well-known elements may not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. Furthermore, although elements of the present disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated. [Explanation of symbols]

[0136] 300 Semiconductor Devices 310 Substrate 320 First metal layer 321 1st collector pad 322 Thermal Pad 325 Dielectric 327 Lower Plate 330 Second metal layer 331 Second Collector Pad 332 Active region 333 Dielectric 334 Inactive region 335 Thermal Bump 336 first thermal bump end 337 Upper Plate 338 Second Thermal Bump End 340 Third Metal Layer 342 Thermal Bar 345 Final Passivation 350 unit cells 355 Active Devices 357 Capacitor 361 Collector Pad 367 Capacitor Dielectrics 370 Thermal Pillar 372 Seed Layer 374 Cap 380 Transistors 387 Emitter 389 Collector 390 resistor 395 Thermal Finger 1100 Semiconductor Devices 1110 Board 1120 First metal layer 1122 Thermal Pad 1125 Dielectric 1127 Lower Plate 1130 Second metal layer 1132 Active region 1134 Inactive region 1135 Thermal Bump 1136 first thermal bump end 1137 Top Plate 1138 Second Thermal Bump End 1145 Final Passivation 1150 unit cell 1155 Active Devices 1157 Capacitor 1167 Capacitor Dielectric 1170 Thermal Pillar 1172 Seed Layer 1174 Cap 1180 Transistor 1187 Emitter 1189 Collector 1190 resistor 1195 Thermal Finger 2000 Electronic Devices 2002 Mobile phone devices 2004 Laptop Computer Device 2006 Fixed terminal device

Claims

1. A plurality of unit cells each having a plurality of active devices on a substrate, wherein the plurality of active devices have a first width in a first direction and are aligned along a first length in a second direction; the plurality of unit cells; A first metal layer patterned to form a plurality of thermal pads on the plurality of active devices; A second metal layer patterned to form first and second thermal bump ends and a thermal bump connected therebetween, the thermal bump having a second width in the first direction and a second length in the second direction and being formed on the plurality of thermal pads; A thermal pillar formed on the thermal bump; A semiconductor device comprising: The plurality of active devices are thermally coupled to the thermal pillar via the plurality of thermal pads and the thermal bump; The first and second thermal bump ends each have a width greater than the second width, and a region between the first and second thermal bump ends is divided into an active region and an inactive region, the active region being a part of the region occupied by the thermal bump, and the inactive region being the remaining part of the region; The second width and the second length of the thermal bump are oriented such that the active region overlaps the first width and the first length of the plurality of active devices. A semiconductor device.

2. A third metal layer patterned to form a thermal bar on the thermal bump; The thermal pillar formed on the thermal bar; and The plurality of active devices are thermally coupled to the thermal pillar via the plurality of thermal pads, the thermal bump, and the thermal bar. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 1 or 2, wherein the thermal bump completely overlaps the plurality of active devices.

4. The semiconductor device according to claim 3, wherein the second width of the thermal bump is substantially equal to the first width of the plurality of active devices.

5. The semiconductor device according to claim 1 or 2, wherein the active device of at least one unit cell is a bipolar transistor.

6. The semiconductor device according to claim 5, wherein the bipolar transistor is a heterojunction bipolar transistor, HBT.

7. The emitter of the bipolar transistor is thermally coupled to the thermal bump via a thermal pad corresponding to the active device, The semiconductor device according to claim 5, wherein the collector of the bipolar transistor is not electrically coupled to the thermal bump.

8. Further comprising a collector pad on the collector and electrically coupled to the collector, the collector pad a first collector pad on the collector; a second collector pad on the first collector pad; comprising The first collector pad is formed from the patterned first metal layer, and the second collector pad is formed from the patterned second metal layer, The semiconductor device according to claim 7, wherein the collector pad is formed on one or both sides of the emitter in the second direction.

9. At least one unit cell further comprises a capacitor on the substrate adjacent to the active device of the at least one unit cell in the first direction, At least a portion of the capacitor is in the non-active region, The semiconductor device according to claim 2, wherein the capacitor comprises a lower plate, an upper plate, and a capacitor dielectric between the lower plate and the upper plate, the lower plate being patterned from the first metal layer, and the upper plate being electrically coupled to the patterned third metal layer.

10. At least one unit cell further comprises a resistor on the substrate adjacent to the active device of the at least one unit cell in the first direction, At least a portion of the resistor is in the non-active region, or one or more thermal fingers formed from the second metal layer, connected to the thermal bump and extending into the non-active region in the first direction from the thermal bump, or The plurality of thermal pads are on the plurality of active devices and in contact with the plurality of active devices, the thermal bumps are on the plurality of thermal pads and in contact with the plurality of thermal pads, the thermal bar is on the thermal bumps and in contact with the thermal bumps, and the thermal pillar is on the thermal bar and in contact with the thermal bar. The semiconductor device according to claim 2.

11. At least one unit cell further includes a capacitor on the substrate adjacent to the active device of the at least one unit cell in the first direction, At least a part of the capacitor overlaps with the inactive region, The capacitor includes a lower plate, an upper plate, and a capacitor dielectric between the lower plate and the upper plate. The lower plate is patterned from the first metal layer, and the upper plate is patterned from the second metal layer. The semiconductor device according to claim 1.

12. At least one unit cell further includes a resistor on the substrate adjacent to the active device of the at least one unit cell in the first direction, At least a part of the resistor overlaps with the inactive region, or One or more thermal fingers formed from the second metal layer, connected to the thermal bumps and extending in the first direction from the thermal bumps. The semiconductor device according to claim 1 further includes one or more thermal fingers. The plurality of thermal pads are on the plurality of active devices and in contact with the plurality of active devices, the thermal bumps are on the plurality of thermal pads and in contact with the plurality of thermal pads, the thermal pillar is on the thermal bumps and in contact with the thermal bumps. The semiconductor device according to claim 1.

13. A method of manufacturing a semiconductor device, Forming a plurality of unit cells each including a plurality of active devices on a substrate, the plurality of active devices having a first width in a first direction and being aligned along a first length in a second direction. Patterning a first metal layer to form a plurality of thermal pads on the plurality of active devices; Patterning a second metal layer to form first and second thermal bump ends and a thermal bump connected therebetween, the thermal bump having a second width in the first direction, a second length in the second direction, and being formed on the plurality of thermal pads; Forming a thermal pillar on the thermal bump; The plurality of active devices are thermally coupled to the thermal pillar via the plurality of thermal pads and the thermal bump; The first and second thermal bump ends each have a width greater than the second width, and the region between the first thermal bump end and the second thermal bump end is divided into an active region and an inactive region, the active region being a portion of the region occupied by the thermal bump, and the inactive region being the remaining portion of the region; The second width and the second length of the thermal bump are oriented such that the active region overlaps the first width and the first length of the plurality of active devices; Method. **Claim 14**: Patterning a third metal layer to form a thermal bar on the thermal bump; Forming the thermal pillar on the thermal bar; Further comprising; The method according to claim 13, wherein the plurality of active devices are thermally coupled to the thermal pillar via the plurality of thermal pads, the thermal bump, and the thermal bar. **Claim 15** The thermal bump completely overlaps the plurality of active devices; The method according to claim 13 or claim 14, wherein the second width of the thermal bump is substantially equal to the first width of the plurality of active devices.

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