Bonded Structure with Active Interposer

Abstract

A bonded structure is disclosed. The bonded structure may include a first semiconductor element having a first contact pad. An interposer may have a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad being bonded to the first contact pad, and the bonded structure may further include a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuit may be configured to switch between a first electrical connection between the second contact pad and the third contact pad and a second electrical connection between the second contact pad and the fourth contact pad.

Description

[Technical field]

[0001] The technical field relates to bonded structures with active interposers.

[0002] [Citation to Related Applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 2483115 (title: BONDED STRUCTURE WITH ACTIVE INTERPOSER), filed on September 24, 2021, which is incorporated by reference in its entirety. [Background technology]

[0003] Multi-layer semiconductor elements (e.g., integrated device dies) may be stacked on top of each other in various applications, such as high bandwidth memory (HBM) devices or other devices that utilize vertical integration. The stacked elements may communicate electrically with each other through an array of contact pads. It may be important to ensure that the contact pads on opposing semiconductor elements are aligned with each other, and that the electrical connection between the contact pads on the two opposing semiconductor elements is reliable. Summary of the Invention

[0004] In one embodiment, the bonded structure may include a first semiconductor element having a first contact pad and an interposer having a second contact pad located on a first side of the interposer and a fourth contact pad located on a second side of the interposer opposite the first side, the second contact pad being bonded to the first contact pad, and the bonded structure may further include a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad, and a switching circuit configured to switch between a first electrical connection state of the second contact pad and the third contact pad and a second electrical connection state of the second contact pad and the fourth contact pad.

[0005] In some embodiments, the switching circuitry is disposed within the interposer. In some embodiments, the switching circuitry is disposed within at least one of the first semiconductor element and the second semiconductor element. In some embodiments, the second contact pad and the third contact pad are laterally offset from one another. In some embodiments, the first semiconductor element comprises a first plurality of contact pads including the first contact pad, and the second semiconductor element comprises a second plurality of contact pads including a fifth contact pad and a sixth contact pad, the first plurality of contact pads having a first pitch, the first pitch matching a second pitch of the second plurality of contact pads. In some embodiments, the first semiconductor element comprises a first plurality of contact pads including the first contact pad, and the second semiconductor element comprises a second plurality of contact pads including a fifth contact pad and a sixth contact pad, the first plurality of contact pads having a first pitch, the first pitch differing from a second pitch of the second plurality of contact pads. In some embodiments, the interposer comprises a third plurality of contact pads located on the second surface, the third plurality of contact pads including a set of contact pads each connectable to a second contact pad on the first surface via a switching circuit, the contact pad set including the third contact pad, a fourth contact pad, and one or more additional contact pads.

[0006] In some embodiments, a set of contact pads is 100 μm 2 In some embodiments, the set of contact pads is located within an area of ​​10 μm 2 In some embodiments, the set of contact pads is located within an area of ​​1 μm 2 Located in the following areas:

[0007] In some embodiments, the bonded structure includes a test circuit configured to calculate a bonding offset between the first semiconductor device and the second semiconductor device. In some embodiments, the test circuit is configured to send a signal representative of the bonding offset to the switching circuit. In some embodiments, the switching circuit is programmed to create a first electrical connection state or a second electrical connection state based at least in part on the calculated bonding offset. In some embodiments, the test circuit includes a plurality of test pads in the first semiconductor device, a plurality of vias in the interposer bonded to the first plurality of test pads, and a probe pad in the second semiconductor device bonded to a first via of the plurality of vias. In some embodiments, the plurality of test pads includes a two-dimensional array of test pads, and the plurality of vias includes a two-dimensional array of vias. In some embodiments, the test circuit further includes a reference pad connected to the probe pad, and the signal sent to the switching circuit is based at least in part on determining continuity of a signal between the probe pad and the reference pad. In some embodiments, the second contact pad is bonded directly to the first contact pad without any intervening adhesive, and the fifth contact pad is bonded directly to the third contact pad without any intervening adhesive.

[0008] In some embodiments, the first semiconductor element has a first non-conductive field region having a first contact pad at least partially embedded therein, the first side of the interposer has a second non-conductive field region having a second contact pad at least partially embedded therein, and the first non-conductive field region and the second conductive field region are bonded directly to one another without an intervening adhesive. In some embodiments, the second side of the interposer has a third non-conductive field region having a second contact pad and a third contact pad at least partially embedded therein, and the second semiconductor element has a fourth non-conductive field region having a fifth contact pad and a sixth contact pad at least partially embedded therein, and the third non-conductive field region and the fourth conductive field region are bonded directly to one another without an intervening adhesive.

[0009] In some embodiments, the switching circuit includes a multi-bit switch multiplexer. In some embodiments, the switching circuit includes a plurality of switches capable of electrically connecting a plurality of contact pads, including a second contact pad, located on the first side of the interposer to a third contact pad located on the second side of the interposer. In some embodiments, a diameter of the first contact pad is different from a diameter of the second contact pad. In some embodiments, a diameter of the first contact pad is smaller than a diameter of the second contact pad, and the bonded structure further includes a plurality of contact pads disposed in the first semiconductor device, the plurality of contact pads including the first contact pad and at least one additional contact pad, and the plurality of contact pads are bonded to the second contact pad. In some embodiments, a diameter of the first contact pad is larger than a diameter of the second contact pad, and the bonded structure further includes a plurality of contact pads located on the first surface of the interposer, the plurality of contact pads including the second contact pad and at least one additional contact pad, and the plurality of contact pads are bonded to the second contact pad.

[0010] In another embodiment, the bonded structure may include a first semiconductor element and an interposer having a first plurality of contact pads located on a first surface of the interposer and a second plurality of contact pads located on a second surface of the interposer, the first surface of the interposer being bonded to the first semiconductor element, the first plurality of contact pads being electrically connected to the first semiconductor element, the bonded structure may further include a second semiconductor element bonded to the second surface of the interposer, the second plurality of contact pads being electrically connected to the second semiconductor element, and the bonded structure may further include a switching circuit configured to switch an electrical connection state between each contact pad of the first plurality of contact pads and a number of contact pads forming a set of the second plurality of contact pads.

[0011] In some embodiments, the switching circuit is configured to switch an electrical connection state between each of the second plurality of contact pads and a second set of a number of the first plurality of contact pads. In some embodiments, the switching circuit is disposed within the interposer. In some embodiments, the switching circuit is disposed within at least one of the first semiconductor element and the second semiconductor element. In some embodiments, the first semiconductor element has a third plurality of contact pads bonded directly to the first plurality of contact pads without an intervening adhesive, and the second semiconductor element has a fourth plurality of contact pads bonded directly to the second plurality of contact pads without an intervening adhesive. In some embodiments, the first semiconductor element has a first non-conductive field region at least partially disposed within the third contact pads, and the first surface of the interposer has a second non-conductive field region at least partially disposed within the first plurality of contact pads, and the first non-conductive field region and the second non-conductive field region are bonded directly to each other without an adhesive. In some embodiments, the second surface of the interposer has a third non-conductive field region at least partially disposed with the second plurality of contact pads, and the second semiconductor device has a fourth non-conductive field region at least partially disposed with a fourth contact pad, and the third non-conductive field region and the fourth non-conductive field region are directly bonded without adhesive. In some embodiments, a first contact pad of the first plurality of contact pads is directly bonded to a second contact pad of the third plurality of contact pads, and a diameter of the first contact pad is different from a diameter of the second contact pad. In some embodiments, a diameter of the first contact pad is smaller than a diameter of the second contact pad, and the second contact pad is directly bonded to the first contact pad and the at least one additional contact pad. In some embodiments, a diameter of the first contact pad is larger than a diameter of the second contact pad, and the first contact pad is directly bonded to the second contact pad and the at least one additional contact pad. In some embodiments, the first plurality of contact pads has a pitch that matches the pitch of the second plurality of contact pads.In some embodiments, the first plurality of contact pads has a different pitch than the pitch of the second plurality of contact pads.

[0012] In some embodiments, the contact pads in a pair are 100 μm 2 In some embodiments, the contact pads in a set are located within an area of ​​10 μm 2 In some embodiments, the contact pads in a pair are located within an area of ​​1 μm 2 Located in the following areas:

[0013] In some embodiments, the bonded structure further comprises a test circuit configured to determine a bonding offset between the first semiconductor device and the second semiconductor device and send a signal representative of the bonding offset to the switching circuit. In some embodiments, the test circuit comprises a plurality of test pads in the first semiconductor device, a plurality of vias in the interposer bonded to the first plurality of test pads, and a probe pad in the second semiconductor device bonded to a first via of the plurality of vias. In some embodiments, the plurality of test pads comprises a two-dimensional array of test pads and the plurality of vias comprises a two-dimensional array of vias. In some embodiments, the switching circuit comprises a multi-bit switch multiplexer.

[0014] In another embodiment, the interposer has a first contact pad located on a first surface of the interposer, a second contact pad and a third contact pad located on a second surface of the interposer opposite the first surface, and a switching circuit configured to switch between a first electrical connection state of the first contact pad and the second contact pad and a second electrical connection state of the third contact pad and the fourth contact pad.

[0015] In some embodiments, the interposer has a plurality of contact pads located on the second surface, the plurality of test pads including a set of contact pads each connectable to a second contact pad on the first surface via a switching circuit, the set of contact pads including the second contact pad, the third contact pad, and one or more additional contact pads. In some embodiments, the set of contact pads includes a contact pad having a size of 100 μm or less. 2 In some embodiments, the contact pads in a set are located within an area of ​​10 μm 2 In some embodiments, the contact pads in a pair are located within an area of ​​1 μm 2 Located in the following areas:

[0016] In some embodiments, the bonded structure may include test circuitry to calculate a bonding offset between the interposer and one or more semiconductor devices to which the interposer is to be bonded, the test circuitry configured to send a signal representative of the bonding offset to the switching circuitry. In some embodiments, the test circuitry includes a plurality of vias disposed in the interposer and configured to be bonded to corresponding test pads of the one or more semiconductor devices. In some embodiments, the plurality of vias includes a two-dimensional array of vias. In some embodiments, the switching circuitry includes a multi-bit switch multiplexer.

[0017] In another embodiment, a method of making a bonded structure includes bonding a first contact pad of a first semiconductor element to a second contact pad located on a first surface of an interposer, bonding third and fourth contact pads located on a second surface of the interposer to fifth and sixth contact pads of a second semiconductor element, respectively, and switching between a first electrical connection state of the second contact pad and the third contact pad and a second electrical connection state of the second contact pad and the fourth contact pad.

[0018] In some embodiments, the first semiconductor element comprises a first plurality of contact pads including the first contact pad, the second semiconductor element comprises a second plurality of contact pads including a fifth contact pad and a sixth contact pad, and the interposer comprises a third plurality of contact pads located on the second surface, the third plurality of contact pads including a set of contact pads each connectable to a second contact pad on the first surface via a switching circuit, the contact pad set including the third contact pad, a fourth contact pad, and one or more additional contact pads. In some embodiments, the method further includes bonding the second semiconductor element to the interposer using a tool having a misalignment tolerance area, the contact pad set being located within a pad area equal to or less than the misalignment tolerance area.

[0019] In some embodiments, bonding the first plurality of contact pads to the second contact pads includes directly bonding the first contact pads to the second contact pads without an intervening adhesive. In some embodiments, directly bonding the third and fourth contact pads to the fifth and sixth contact pads, respectively, without an intervening adhesive. In some embodiments, the method may include directly bonding a first non-conductive field region of the first semiconductor element to a second non-conductive field region of the interposer without an intervening adhesive. In some embodiments, the method may include directly bonding a third non-conductive field region of the second side of the interposer to a fourth non-conductive field region of the second semiconductor element without an intervening adhesive. In some embodiments, the switching circuitry is provided in the interposer. In some embodiments, the switching circuitry is provided in at least one of the first and second semiconductor elements.

[0020] In another embodiment, a bonded structure includes a first semiconductor element having a circuit element, a first contact pad, and a second contact pad, a second semiconductor element having a third contact pad bonded to the first contact pad and a fourth contact pad bonded to the second contact pad, a switching circuit configured to switch a first electrical connection state of the circuit element and the first contact pad and a second electrical connection state of the circuit element and the second contact pad, and a test circuit configured to calculate a bonding offset between the first semiconductor element and the second semiconductor element.

[0021] In some embodiments, the third contact pad is directly bonded to the first contact pad without an intervening adhesive, and the fourth contact pad is directly bonded to the second contact pad without an intervening adhesive. In some embodiments, the first semiconductor element has a first non-conductive field region in which the first and second contact pads are at least partially embedded, and the second semiconductor element has a second non-conductive field region in which the third and fourth contact pads are at least partially embedded, and the first non-conductive field region and the second conductive field region are directly bonded to each other without an intervening adhesive. In some embodiments, a test circuit is provided along the dicing lane, and the test circuit is at least partially destroyed by the dicing step. In some embodiments, the switching circuit is programmed to effect the first electrical connection state or the second electrical connection state based at least in part on the calculated bonding offset. In some embodiments, the test circuit is configured to send a signal representative of the bonding offset to the switching circuit. [Brief description of the drawings]

[0022] [Figure 1A] FIG. 2 is a schematic cross-sectional side view showing two elements prior to direct hybrid bonding. [Figure 1B] FIG. 1B is a schematic cross-sectional side view of the two elements shown in FIG. 1A after direct hybrid bonding. [Figure 2A]3 is a schematic cross-sectional view of a first semiconductor element, an interposer, and a second semiconductor element before bonding. [Figure 2B] 2B is a schematic cross-sectional view of a bonded structure including the component of FIG. 2A, according to one embodiment. [Figure 3A] FIG. 2 illustrates another embodiment of a first semiconductor element, an interposer, and a second semiconductor element prior to bonding, in accordance with one embodiment. [Figure 3B] 3B is a schematic cross-sectional view of a bonded structure including the component of FIG. 3A according to one embodiment. [Figure 4A] 4 is a schematic cross-sectional view of a first semiconductor element, an interposer, and a second semiconductor element prior to bonding in accordance with another embodiment. [Figure 4B] 4B is a schematic cross-sectional view of a bonded structure including the component of FIG. 4A according to one embodiment. [Figure 5A] 1 is a cross-sectional side view of a bonded structure including a test circuit configured to determine a bonding offset between a first semiconductor element and a second semiconductor element and send a signal representative of the bonding offset to a switching circuit. [Figure 5B] 5B is a schematic cross-sectional plan view of a bonded structure including the component of FIG. 5A according to one embodiment. [Figure 5C] 1 is a schematic cross-sectional plan view of a semiconductor device including test pads and vias arranged in a two-dimensional (2D) array to accommodate 2D misalignment. [Figure 6] FIG. 1 is a schematic cross-sectional plan view of opposed contact pads of different diameters to enhance placement accuracy. [Figure 7] 1 is a schematic cross-sectional side view of a bonded structure having a circuit element. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Overview There is an increasing demand for direct bonding of semiconductor devices having contact pads arranged at fine pitches to increase interconnection density and improve electrical capabilities. However, accurately aligning contact pads arranged at fine pitches can be a challenge because pick-and-place and / or bonding tools have tolerances for misalignment. If the pitch of pads to be bonded is less than or approximately equal to the misalignment tolerance, a pad on one device may be bonded to an incorrect pad on an opposing device, resulting in poor electrical performance. Various embodiments disclosed herein compensate for misalignment during bonding by providing a switching circuit configured to switch electrical connections between opposing pads to ensure that the pads are accurately connected to each other.

[0024] Examples of direct bonding methods and direct bonded structures Various embodiments disclosed herein relate to a bonded structure in which two elements can be directly bonded together without an intervening adhesive. FIGS. 1A and 1B show a schematic process of forming a direct bonded structure without an intervening adhesive, according to some embodiments. In FIGS. 1A and 1B, a bonded structure 100 has two elements 102, 104 that can be directly bonded together without an intervening adhesive. Two or more semiconductor elements (e.g., integrated circuit dies, wafers, etc.) 102, 104 can be stacked or bonded together to form the bonded structure 100. A conductive feature 106a (e.g., a contact pad, an exposed end of a via (e.g., TSV), or a through-substrate electrode) of a first element 102 can be electrically connected to a corresponding conductive feature 106b of a second element 104. The conductive feature can include a metal pad formed in a non-conductive bonding region and can be connected to an underlying metallization, such as a redistribution layer (RDL) (sometimes referred to as a surface wiring). Any suitable number of elements may be stacked within the bonded structure 100. For example, a third element (not shown) may be stacked on the second element 104, a fourth element (not shown) may be stacked on the third element, and so on. Additionally or alternatively, one or more additional elements (not shown) may be stacked laterally adjacent to one another along the first element 102. In some embodiments, the laterally stacked additional elements may be smaller than the second element. In some embodiments, the laterally stacked additional elements may be 1 / 2 the size of the second element.

[0025] In some embodiments, the elements 102, 104 are directly bonded to each other without adhesive. In various embodiments, a non-conductive field region comprising a non-conductive or dielectric material may serve as the first bonding layer 108a of the first element 102, and the first bonding layer 108a may be directly bonded to a corresponding non-conductive field region comprising a non-conductive or dielectric material that serves as the second bonding layer 108b of the second element 104 without adhesive. The non-conductive bonding layers 108a, 108b may be provided on the device portions 110a, 110b, e.g., on the front surfaces 114a, 114b of the semiconductor (e.g., silicon) portions of the elements 102, 104, respectively. Active devices and / or circuits may be patterned and / or otherwise provided in or on the device portions 110a, 110b. Active devices and / or circuits may be provided at or near the front surfaces 114a, 114b of the device portions 110a, 110b and / or at or near the opposite back surfaces 116a, 116b of the device portions 110a, 110b. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer 108a of the first element 102. In some embodiments, the non-conductive bonding layer 108a of the first element 102 may be directly bonded to a corresponding non-conductive bonding layer 108b of the second element 104 using a dielectric-to-dielectric bonding technique. For example, the dielectric-to-dielectric bond may be formed without adhesive using direct bonding techniques as disclosed at least in U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference in its entirety and incorporated herein by reference for all purposes. It should be appreciated that in various embodiments, the bonding layers 108a and / or 108b may be comprised of a non-conductive material, such as a dielectric material, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon.Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, or may include materials containing carbon, such as silicon carbide, silicon oxycarbonitride, low-k dielectrics, SICOH dielectrics, silicon carbonitride, or diamond-like carbon or diamond surfaces. Such carbon-containing ceramic materials may be considered inorganic despite the carbon content. In some embodiments, the dielectric does not include a polymeric material, such as an epoxy, resin, or molding compound.

[0026] In various embodiments, the direct hybrid bond can be formed without an intervening adhesive. For example, the non-conductive bonding surfaces 112a, 112b can be polished to a high degree of smoothness. The bonding surfaces 112a, 112b can be cleaned and exposed to a plasma and / or an etchant to activate the surfaces 112a, 112b. In some embodiments, the surfaces 112a, 112b can be terminated with chemical species after or during activation (e.g., during a plasma and / or etch process). Without being bound by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surfaces, and a termination process can provide one or more additional chemical species at the bonding surfaces 112a, 112b that improve the bonding energy during direct bonding. In some embodiments, activation and termination can be provided in the same step, for example, using a plasma to activate and terminate the surfaces 112a, 112b. In other embodiments, the bonding surfaces 112a, 112b may be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination chemical species may include nitrogen. For example, in some embodiments, the bonding surfaces 112a, 112b may be subjected to a nitrogen-containing plasma. Additionally, in some embodiments, the bonding surfaces 112a, 112b may be exposed to fluorine. For example, one or multiple fluorine peaks may be generated at or near the interface 118 between the first element 102 and the second element 104. Thus, in the direct bonded structure 100, the bonding interface 118 between the two non-conductive materials (e.g., the bonding layers 108a, 108b) may comprise a very smooth interface with a high nitrogen content and / or fluorine peak at the bonding interface 118. Additional examples of activation and / or end group treatments can be found throughout U.S. Pat. Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference and incorporated herein in its entirety for all purposes.

[0027] In various embodiments, the conductive feature 106a of the first element 102 may also be directly bonded to the corresponding conductive feature 106b of the second element 104. For example, hybrid bonding techniques may be used to provide inter-conductor direct bonds along the bond interface 118 that includes a covalently directly bonded non-conductor-to-conductor (e.g., inter-dielectric) surface that has been pretreated as described above. In various embodiments, the inter-conductor (e.g., conductive feature 106a-conductive feature 106b) direct bonds and inter-dielectric hybrid bonds may be formed using direct bonding techniques as disclosed at least in U.S. Pat. Nos. 9,716,033 and 9,852,988, each of which is incorporated by reference herein in its entirety for all purposes.

[0028] For example, the non-conductive (dielectric) bonding surfaces 112a, 112b (e.g., including inorganic dielectric surfaces) can be pretreated and bonded directly to one another without an intervening adhesive as described above. The conductive contact features (e.g., conductive features 106a, 106b), which may be at least partially surrounded by a non-conductive dielectric field region in the bonding layers 108a, 108b, can also be bonded directly to one another without an intervening adhesive. In various embodiments, the conductive features 106a, 106b may include separate pads at least partially embedded in the non-conductive field region. In some embodiments, the conductive contact features may include exposed contact surfaces of through-substrate vias (TSVs). In some embodiments, the conductive features 106a, 106b may be recessed below the dielectric field region or the outer surface (e.g., top surface) of the non-conductive bonding layers 108a, 108b, respectively, by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. In various embodiments, prior to direct bonding, the recesses of the opposing elements may be dimensioned such that the total gap between the opposing contact pads is less than 15 nm, or less than 10 nm. In some embodiments, the non-conductive bonding layers 108a, 108b may be directly bonded to each other at room temperature without adhesive, and the bonded structure 100 may then be annealed. Upon annealing, the conductive features 106a, 106b may expand and contact each other, thereby forming a metal-to-metal direct bond. Beneficially, Direct Bond Interconnect, or DBI (registered trademark) technology, commercially available from Adeia, Inc. of San Jose, California, can be used to connect high density conductive features 106a, 106b across the direct bond interface 118 (e.g., with small or fine pitch for regular arrays).In some embodiments, the pitch of the conductive features 106a, 106b, e.g., the conductive traces embedded in one of the bonding surfaces of the bonded elements, may be less than 40 microns, less than 10 microns, or even less than 2 microns. For some applications, the ratio of the pitch of the conductive features 106a, 106b to one of the dimensions of the bonding pad (e.g., the diameter) is less than 5, less than 3, or even desirably less than 2. In other applications, the width of the conductive traces embedded in one of the bonding surfaces of the bonded elements may range from 0.3 microns to 20 microns, e.g., from 0.3 microns to 3 microns. In various embodiments, the conductive features 106a, 106b may be made of copper, although other metals may be suitable.

[0029] Thus, in a direct bonding process, the first element 102 may be directly bonded to the second element 104 without an intervening adhesive. In some configurations, the first element 102 may comprise a singulated element, such as a singulated integrated device die. In other configurations, as shown in Figures 1A and 1B, the first element 102 may comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element 104 may comprise a singulated element, such as a singulated integrated device die, as shown in Figures 1A and 1B. In other configurations, the second element 104 may comprise a carrier or substrate (e.g., a wafer). Thus, the embodiments disclosed herein may be applicable to wafer-to-wafer, die-to-die, or die-to-wafer bonding processes. In a wafer-to-wafer (W2W) process, two or more wafers may be directly bonded together (e.g., direct hybrid bonding) and then singulated using an appropriate singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially coplanar with one another and may include indicia indicative of the singulation process (e.g., saw marks if a saw-based singulation process is used).

[0030] As described herein, the first element 102 and the second element 104 can be directly bonded to each other without adhesive, which is different from a deposition process. In one application, the width of the first element 102 in the bonded structure is approximately the same as the width of the second element 104. In some other embodiments, the width of the first element 102 in the bonded structure 100 is different from the width of the second element 104. Similarly, the width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Thus, the first and second elements 102, 104 can be comprised of non-deposited elements. Furthermore, unlike deposited layers, the directly bonded structure 100 can include defect areas along the bond interface 118 where nanoscale voids (nanovoids) exist. The nanovoids can be formed due to activation (e.g., exposure to plasma) of the bonding surfaces 112a, 112b. As discussed above, the bond interface 118 may include condensation of materials resulting from activation and / or the final chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak may form at the bond interface 118. The nitrogen peak may be detectable using a secondary ion mass spectrometer. In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding layer to a nitrogen-containing plasma) may replace a hydrolyzed (OH-terminated) surface with NH2 molecules, resulting in a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, an oxygen peak may form at the bond interface 118. In some embodiments, the bond interface 118 may be comprised of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As discussed herein, the direct bond includes a covalent bond, which is stronger than a van der Waals bond. The bonding layers 108a, 108b may further have a polished surface that is planarized to a high degree of smoothness.

[0031] In various embodiments, the intermetallic bonds between the contact pads 106a, 106b may be bonded such that the copper grains grow into one another across the bond interface 118. In some embodiments, the copper may have grains oriented along the 111 crystal plane to improve diffusion of the copper across the bond interface 118. The bond interface 118 may extend substantially completely to at least a portion of the bonded conductive features 106a, 106b, such that there is substantially no gap between the non-conductive bonding layers 108a, 108b at or near the bonded conductive features 106a, 106b. In some embodiments, a barrier layer may be provided under the conductive features 106a, 106b (which may include copper, for example). However, in other embodiments, there may not be a barrier layer underneath the conductive features 106a, 106b, as described, for example, in U.S. Pat. No. 11,195,748, the entire contents of which are incorporated by reference herein for all purposes.

[0032] Beneficially, the use of the hybrid bonding techniques described herein allows for very fine pitches of adjacent contact pads 106a, 106b and / or small pad sizes. For example, in various embodiments, the pitch p between adjacent conductive features 106a (or 106b) (i.e., edge-to-edge or center-to-center distance as shown in FIG. 1A) may be in the range of 0.5 microns to 50 microns, 0.75 microns to 25 microns, 1 micron to 25 microns, 1 micron to 10 microns, or 1 micron to 5 microns. Furthermore, the major lateral dimensions (e.g., pad diameter) may also be small, e.g., in the range of 0.25 microns to 30 microns, 0.25 microns to 5 microns, or 0.5 microns to 5 microns.

[0033] Exemplary embodiments of bonded structures FIG. 2A illustrates a first semiconductor element 202 having a first semiconductor 208a with a first bonding layer 208a located on the device portion 210a, an interposer 220, and a second semiconductor element 204 with a second bonding layer 208b located on the device portion 210b prior to bonding. The device portions 210a, 210b may be comprised of a semiconductor material patterned with one or more devices (e.g., one or more active devices, e.g., transistors, and / or one or more passive devices). In the following figures, the device portions 210a, 210b of the first and second semiconductor elements 202, 204 are omitted for clarity of illustration. An active switching circuit 222 may be provided in the interposer 220. The switching circuit 222 may include an active circuit implemented with one or many transistors, and may include any suitable type of switch, e.g., a multi-bit switch multiplexer, a multi-bit bus switch, etc. Each of the first semiconductor element 202, the interposer 220, and the second semiconductor element 204 may have a corresponding conductive contact pad 206 configured to allow electrical connection to another element. The contact pads 206 may include separate conductive pads disposed within a non-conductive field region 208 (e.g., a non-conductive bonding layer). In other embodiments, the contact pads 206 may comprise ends of through-substrate vias (TSVs) configured to couple to another element. In FIG. 2A, the contact pads on the first semiconductor element 202, the first side of the interposer 220a, the second side of the interposer 220b, and the second semiconductor element 204 may match one another and have respective pitches p that are, for example, approximately identical. As discussed above, a pick-and-place or bonding tool may have a maximum placement error (MPE) that spans the misalignment tolerance area of ​​the elements. Using a pick and place or bonding tool to align opposing contact pads without proper compensation can result in inaccurate connections of the opposing pads.To provide a solution for the maximum potential placement error, potential connections 207 may be provided that extend along the misalignment tolerance area, allowing electrical connections and / or signals to be made between the correct conductive pads. In some cases, the contact pad pitch may be smaller than the maximum placement error of the pick-and-place or bonding tool.

[0034] 2B illustrates one embodiment of the bonded structure 200 in which the second semiconductor element 204 is offset from the first semiconductor element 202 and the interposer 220 by a placement error (PE). As shown in FIG. 2B, the interposer 220 may have a first plurality of contact pads 206a disposed on a first side of the interposer 220a and a second plurality of contact pads 206b disposed on a second side of the interposer 220B opposite the first side. The first side of the interposer 220a may be bonded (e.g., directly bonded without an intervening adhesive) to the first semiconductor element 202 with the first plurality of contact pads 206a electrically connected to the first semiconductor element 202. The second semiconductor element 204 may be bonded (e.g., directly bonded without an intervening adhesive) to the second surface of the interposer 220b with the second plurality of contact pads 206b electrically connected to the second semiconductor element 204. The switching circuit 222 may be configured to switch an electrical connection between each of the first plurality of contact pads 206a and a set of multiple pads of the second plurality of contact pads 206b. In some embodiments, the switching may be permanent, i.e., non-reversible, such that once the switching circuit switches the electrical connection, the connection cannot be reversed or switched to another pad (e.g., the switch may include a fuse or an anti-fuse). In other embodiments, the switching may be reversible, such that the switch can be reversed or the electrical connection between the pads can be changed after the initial switch is fabricated. For example, in such an embodiment, the reversible switching may be programmable such that the active circuitry can switch between two states or pads, or between three or more states or pads.

[0035] 2B, the first semiconductor element 202 may have a first contact pad 206(1) and the interposer may have a second contact pad 206(2) on a first side 220a of the interposer 220. The second contact pad 206(2) may be bonded (e.g., directly bonded without an intervening adhesive) to the first contact pad 206(1). The interposer 220 may have a third contact pad 206(3) and a fourth contact pad 206(4) on a second side 220b of the interposer opposite the first side 220a. The second semiconductor element 204 may have a fifth contact pad 206(5) bonded (e.g., directly bonded without an intervening adhesive) to the third contact pad 206(3) and a sixth contact pad 206(6) bonded (e.g., directly bonded without an intervening adhesive) to the fourth contact pad 206(4). The switching circuit 222 may be configured to switch between a first electrical connection between the second and third contact pads 206(2), 206(3) and a second electrical contact between the second and fourth contact pads 206(2), 206(4) to provide an established connection state 209. As shown, the second and fourth contact pads 206(2), 206(4) may be laterally offset from one another. Thus, electrical connections and / or signals are connected in a one-to-one relationship such that electrical connections can only occur between one pair of contact pads. Additionally, power and / or ground do not need to be reconfigured after bonding the first semiconductor device, the second semiconductor device, and the interposer.

[0036] 2A and 2B, second contact pad 206(2) may be connectable to a set of multiple contact pads including third and fourth pads 206(3), 206(4) and one or more additional contact pads. In various embodiments, the set of multiple contact pads connectable to second pad 206(2) may be provided within a pad area that is less than or equal to a misalignment tolerance area M. In various embodiments, the set of contact pads may be provided within or equal to a pad area that is less than or equal to a misalignment tolerance area M. 2 Within the pad area below, 25μm2 Within the contact area of ​​10 μm 2 Within the pad area below, 5μm 2 Within the pad area below or 1μm 2 The pad area may be provided below the first pad 206(2) and the second pad 206(3). Beneficially, therefore, a number of pads in a set connectable to the second pad 206(2) may be within the misalignment tolerance of the bonding tool, such that the second pad 206(2) is bonded to one of the pads in the set (and not to a pad not in the set).

[0037] 3A and 3B show an embodiment generally similar to that of FIGS. 2A and 2B. However, unlike the embodiment of FIGS. 2A and 2B, the interposer 320 may be configured to connect semiconductor elements having different pitches p1, p2 to each other. For example, the pads of the first semiconductor element 302 may have a larger pitch than the pads of the second semiconductor element 304. The pads on the first side of the interposer 320a may have a larger pitch to match the pads of the first semiconductor element 302, and the pads on the second side of the interposer 320b may have a smaller pitch to match the pads of the second element. Beneficially, the embodiment of FIGS. 3A and 3B allows for the connection of semiconductor elements 302, 304 having different pitches to each other.

[0038] 4A and 4B show an embodiment similar to that of FIGS. 2A-3B. However, unlike the embodiment of FIGS. 2A-3B in which the active switching circuitry is provided in the interposer, the active switching circuitry 422 may be provided in at least one of the first and second semiconductor elements 402, 404. In FIGS. 4A and 4B, for example, the switching circuitry 422 may be provided in the second semiconductor element 404. In other embodiments, the switching circuitry 422 may additionally or alternatively be provided in the first semiconductor element 402. It should be understood that while FIGS. 2A-4B show a one-to-many connection between the pads of the first semiconductor element and the pads of the second semiconductor element, in various embodiments, there may additionally or alternatively be a one-to-many relationship between the pads of the second semiconductor element and the pads of the first semiconductor element.

[0039] 5A and 5B show a test circuit 550 configured to determine a bonding offset between a first semiconductor element 502 and a second semiconductor element 504 and send a signal representative of the bonding offset of the bonded structure 500 to a switching circuit 522. The test circuit 550 may include a plurality of test pads 526 in the first semiconductor element 502, a plurality of vias 524 in the interposer 520 bonded to the first plurality of test pads 526, and a probe pad 528 in the second semiconductor element 504 bonded to a first via of the plurality of vias 524. The test circuit 550 further includes a reference pad 530 connected to the probe pad 528. The test circuit 550 may be configured to monitor the continuity of a signal between the probe pad 528 and the reference pad 530 to identify the test pad 526 to which the probe pad 528 is connected. As shown in Figures 5A and 5B, the bonding offset due to misalignment may be determined based at least in part on which test pad and via the probe pad is coupled to. In Figure 5A, for example, probe pad 528 bonds to test pad 526 and via that are offset by one position (+1) relative to the correct alignment (0). In some embodiments, test circuitry 550 may be electrically connected to active circuitry 522 and may send a signal to the active circuitry to switch the electrical connection to the opposing pad in the +1 position. In other embodiments, test circuitry 550 may not be electrically connected to active circuitry 522. Alternatively, in such embodiments, switching circuitry 522 may be programmed to effect the first electrical connection or the second electrical connection based at least in part on the determined bonding offset.

[0040] As shown in FIG. 5C, in various embodiments, the test pads 526 and vias 524 may be provided in a two-dimensional (2D) array to allow for 2D misalignment. Thus, in FIG. 5C, the test pads 526 and vias 524 may be provided at bond offsets in two dimensions represented by (x,y) coordinates. The test pads may be located at any suitable location on the first semiconductor device. For example, in various embodiments, the test pads may be provided in a dicing lane, along the edge of the wafer, or within the footprint of a singulated die. Thus, in some embodiments, the test circuitry may be damaged during the dicing process.

[0041] 6, in some embodiments, to improve placement accuracy, the diameters of opposing contact pads may be different from each other. For example, pad 606a on first semiconductor element 620 may be smaller than pad 606b on interposer 620, and vice versa. The large pad may be at least equal to or larger than a set of pads on the opposing surface, so that at least some of the small pads can contact and electrically couple to the large opposing pads, thereby providing placement benefits.

[0042] FIG. 7 illustrates another embodiment of a bonded structure 700. In FIG. 7, the bonded structure 700 includes a first semiconductor element 702 with a circuit element 703, a first contact pad 706(1), and a second contact pad 706(2). The circuit element 703 may include at least a portion of an active circuit, a trace connected to the active circuit, or other signal transmission circuitry. The bonded structure 700 may include a second semiconductor element 704 with a third contact pad 706(3) bonded to the first contact pad 706(1) and a fourth contact pad 706(4) bonded to the second contact pad 706(2). In some embodiments, the first and second semiconductor elements 702, 704 may be directly hybrid bonded to one another as described herein. The bonded structure 700 may include a switching circuit 722 configured to switch between a first electrical connection state between the circuit element 703 and a first contact pad 706(1) and an electrical connection state between the circuit element 703 and a second contact pad 706(2). As shown in Figures 5A-5C, the test circuit 750 may be configured to calculate or determine a bonding offset between the first semiconductor element 702 and the second semiconductor element 704 and send a signal representative of the bonding offset to the switching circuit 722. As discussed above, the test circuit 750 may be located in any suitable location within these elements.

[0043] 7, the bonded structure 700 may not include an interposer between the first semiconductor element 702 and the second semiconductor element 704. Instead, the first and second semiconductor elements 702, 704 may be directly bonded to one another. The switching circuit 722 may be located entirely within the first semiconductor element 702 in some embodiments (or, in alternative embodiments, entirely within the second semiconductor element). In other embodiments, the switching circuit 722 may span the entire bond interface such that a first portion of the switching circuit 722 is located within the first semiconductor element 702 and a second portion of the switching circuit 722 is located within the second semiconductor element 704.

[0044] terminology Unless the context clearly requires otherwise, throughout the specification and claims, the terms "comprise", "comprising", "include", "including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to", as opposed to an exclusive or exhaustive sense. As used generally herein, the term "coupled" means two or more elements that are either directly connected to each other or connected to each other by one or more intermediate elements. Similarly, as used generally herein, the term "coupled" means two or more elements that are either directly connected to each other or connected to each other by one or more intermediate elements. In addition, the terms "herein," "above," "below," and words of similar import as used in the parent application refer to the application as a whole and not to any particular portion of the application. Furthermore, as used herein, when a first element is described as being located "on" or "over" a second element, the first element may be directly located on or over the second element such that the first element and the second element are in direct contact with each other, or the first element may be indirectly located on or over the second element such that one or more elements are interposed between the first element and the second element. Where the context permits, terms in the above detailed description using the singular or plural may include the plural or singular, respectively. The term "or" in reference to a list of two or more items includes all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0045] Furthermore, conditional terms used in the specification, particularly "can," "could," "might," "may," "eg," "for example," "such as," and the like, unless expressly specified otherwise or understood otherwise within the context in which they are used, are generally intended to imply that certain embodiments include certain features, elements, and / or conditions and that other embodiments do not include certain features, elements, and / or conditions. Thus, such conditional terms are not generally intended to imply that features, elements, and / or conditions are present in any required manner for one or more embodiments.

[0046] Although certain embodiments have been described, these embodiments are provided by way of example only and are not intended to limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and furthermore, various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the scope of the invention. For example, although blocks are shown in a given arrangement, alternative embodiments may perform substantially the same functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, divided, combined, and / or modified. Each of these blocks may be embodied in a wide variety of ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the invention as set forth in the appended claims and equivalents thereto is intended to include such forms or modifications within the scope and spirit of the invention.

Claims

1. A bonded structure comprising: a first semiconductor element having a first contact pad; an interposer having second contact pads located on a first side of the interposer and fourth contact pads located on a second side of the interposer opposite the first side, the second contact pads being bonded to the first contact pads; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad, wherein the second surface of the interposer and the second semiconductor element are hybrid bonded to each other without an intervening adhesive; a bonded structure having a switching circuit configured to switch between a first electrical connection state of the second contact pad and the third contact pad and a second electrical connection state of the second contact pad and a fourth contact pad.

2. The bonded structure of claim 1 , wherein the switching circuit is provided within the interposer.

3. 2. The bonded structure of claim 1, wherein the switching circuit is provided within at least one of the first semiconductor device and the second semiconductor device.

4. 4. The bonded structure of claim 1, wherein the second contact pad and the third contact pad are laterally offset from each other.

5. 4. A bonded structure as described in any one of claims 1 to 3, wherein the first semiconductor element has a first plurality of contact pads including the first contact pad, the second semiconductor element has a second plurality of contact pads including the fifth contact pad and the sixth contact pad, the first plurality of contact pads having a first pitch, and the first pitch matches a second pitch of the second plurality of contact pads.

6. 4. A bonded structure as described in any one of claims 1 to 3, wherein the first semiconductor element has a first plurality of contact pads including the first contact pad, the second semiconductor element has a second plurality of contact pads including the fifth contact pad and the sixth contact pad, the first plurality of contact pads having a first pitch, and the first pitch is different from a second pitch of the second plurality of contact pads.

7. A bonded structure as described in any one of claims 1 to 3, wherein the interposer has a third plurality of contact pads located on the second surface, the third plurality of contact pads including a set of contact pads each connectable to the second contact pad on the first surface via the switching circuit, the set of contact pads including the third contact pad, the fourth contact pad, and one or more additional contact pads.

8. The set of contact pads is 100 μm 2 8. The bonded structure of claim 7, wherein the bonded structure is located in an area:

9. The set of contact pads is 10 μm 2 9. The bonded structure of claim 8, wherein the bonded structure is located in an area:

10. The set of contact pads is 1 μm 2 9. The bonded structure of claim 8, wherein the bonded structure is located in an area:

11. 4. The bonded structure of claim 1, further comprising a test circuit configured to calculate a bonding offset between the first semiconductor device and the second semiconductor device.

12. The bonded structure of claim 11 , wherein the test circuitry is configured to send a signal representative of the bonding offset to the switching circuitry.

13. 12. The bonded structure of claim 11, wherein the switching circuitry is programmed to effect the first electrical connection state or the second electrical connection state based at least in part on the calculated bonding offset.

14. 12. The bonded structure of claim 11, wherein the test circuit comprises a plurality of test pads provided in the first semiconductor element, a plurality of vias provided in the interposer and bonded to the first plurality of test pads, and a probe pad provided in the second semiconductor element and bonded to a first via of the plurality of vias.

15. The bonded structure of claim 14 , wherein the plurality of test pads comprises a two-dimensional array of test pads and the plurality of vias comprises a two-dimensional array of vias.

16. 13. The bonded structure of claim 12, wherein the test circuit further comprises a reference pad connected to a probe pad, and the signal sent to the switching circuit is based at least in part on determining continuity of the signal between the probe pad and the reference pad.

17. 4. The bonded structure of claim 1, wherein the second contact pad is bonded directly to the first contact pad without any intervening adhesive.

18. 18. The bonded structure of claim 17, wherein the first semiconductor element has a first non-conductive field region in which the first contact pad is at least partially embedded, the first surface of the interposer has a second non-conductive field region in which the second contact pad is at least partially embedded, and the first non-conductive field region and the second non-conductive field region are bonded directly to each other without an intervening adhesive.

19. 4. The bonded structure of claim 1, wherein the switching circuit comprises a multi-bit switch multiplexer.

20. A bonded structure as described in any one of claims 1 to 3, wherein the switching circuit has a plurality of switches capable of electrically connecting a plurality of contact pads located on the first surface of the interposer, including the second contact pad, to the third contact pad located on the second surface of the interposer.

21. 4. The bonded structure of claim 1, wherein the diameter of the first contact pad is different from the diameter of the second contact pad.

22. 22. The bonded structure of claim 21, wherein the diameter of the first contact pad is smaller than the diameter of the second contact pad, and the bonded structure further comprises a plurality of contact pads provided within the first semiconductor element, the plurality of contact pads including the first contact pad and at least one additional contact pad, and the plurality of contact pads are bonded to the second contact pad.

23. 22. The bonded structure of claim 21, wherein the diameter of the first contact pad is larger than the diameter of the second contact pad, and the bonded structure further comprises a plurality of contact pads located on the first surface of the interposer, the plurality of contact pads including the second contact pad and at least one additional contact pad, and the plurality of contact pads are bonded to the second contact pad.

24. 1. A bonded structure comprising: a first semiconductor element; an interposer having a first plurality of contact pads located on a first surface of the interposer and a second plurality of contact pads located on a second surface of the interposer, the first surface of the interposer being bonded to the first semiconductor device, and the first plurality of contact pads being electrically connected to the first semiconductor device; a second semiconductor element bonded to the second surface of the interposer, the second plurality of contact pads being electrically connected to the second semiconductor element; A bonded structure having a switching circuit configured to switch an electrical connection state between each contact pad of the first plurality of contact pads and a set of multiple contact pads of the second plurality of contact pads.

25. 25. The bonded structure of claim 24, wherein the switching circuitry is configured to switch an electrical connection state between each contact pad of the second plurality of contact pads and a second set of multiple contact pads of the first plurality of contact pads.

26. 26. The bonded structure according to claim 24, wherein the switching circuit is provided within the interposer.

27. 26. The bonded structure of claim 24, wherein the switching circuit is provided within at least one of the first semiconductor element and the second semiconductor element.

28. 26. The bonded structure of claim 24 or 25, wherein the first semiconductor element has a third plurality of contact pads bonded directly to the first plurality of contact pads without any intervening adhesive, and the second semiconductor element has a fourth plurality of contact pads bonded directly to the second plurality of contact pads without any intervening adhesive.

29. 29. The bonded structure of claim 28, wherein the first semiconductor element has a first non-conductive field region in which the third plurality of contact pads are at least partially disposed, the first surface of the interposer has a second non-conductive field region in which the first plurality of contact pads are at least partially disposed, and the first non-conductive field region and the second non-conductive field region are directly bonded without adhesive.

30. 29. The bonded structure of claim 28, wherein the second surface of the interposer has a third non-conductive field region at least partially provided with the second plurality of contact pads, the second semiconductor element has a fourth non-conductive field region at least partially provided with the fourth plurality of contact pads, and the third non-conductive field region and the fourth non-conductive field region are directly bonded without adhesive.

31. 30. The bonded structure of claim 28, wherein a first contact pad of the first plurality of contact pads is directly bonded to a second contact pad of the third plurality of contact pads, and wherein a diameter of the first contact pad is different from a diameter of the second contact pad.

32. 32. The bonded structure of claim 31, wherein the diameter of the first contact pad is smaller than the diameter of the second contact pad, and the second contact pad is directly bonded to the first contact pad and at least one additional contact pad.

33. 32. The bonded structure of claim 31, wherein the diameter of the first contact pad is larger than the diameter of the second contact pad, and the first contact pad is directly bonded to the second contact pad and at least one additional contact pad.

34. 26. The bonded structure of claim 24 or 25, wherein the first plurality of contact pads has a pitch that matches the pitch of the second plurality of contact pads.

35. 26. The bonded structure of claim 24 or 25, wherein the first plurality of contact pads has a pitch that is different from the pitch of the second plurality of contact pads.

36. The contact pads in the set are 100 μm 2 26. The bonded structure of claim 24 or 25, provided in the following area:

37. The contact pads in the set are 10 μm 2 37. The bonded structure of claim 36, located in an area:

38. The contact pads in the set are 1 μm 2 37. The bonded structure of claim 36, located in an area:

39. 26. The bonded structure of claim 24 or 25, further comprising a test circuit configured to calculate a bonding offset between the first semiconductor device and the second semiconductor device and send a signal representative of the bonding offset to the switching circuit.

40. 40. The bonded structure of claim 39, wherein the test circuitry comprises a plurality of test pads provided in the first semiconductor element, a plurality of vias provided in the interposer and bonded to the first plurality of test pads, and a probe pad provided in the second semiconductor element and bonded to a first via of the plurality of vias.

41. 41. The bonded structure of claim 40, wherein the plurality of test pads comprises a two-dimensional array of test pads and the plurality of vias comprises a two-dimensional array of vias.

42. 26. The bonded structure of claim 24 or 25, wherein the switching circuitry comprises a multi-bit switch multiplexer.

43. An interposer, first contact pads located on a first surface of the interposer; second and third contact pads located on a second surface of the interposer opposite the first surface; An interposer having a switching circuit configured to switch between a first electrical connection state of the first contact pad and the second contact pad and a second electrical connection state of the third contact pad and the fourth contact pad.

44. 44. The interposer of claim 43, wherein the interposer has a plurality of contact pads located on the second surface, the plurality of test pads including a set of contact pads each connectable to the second contact pad on the first surface via the switching circuit, the set of contact pads including the second contact pad, the third contact pad, and one or more additional contact pads.

45. The contact pads in the set are 100 μm 2 45. The interposer of claim 44, wherein the interposer is located in an area:

46. The contact pads in the set are 10 μm 2 46. ​​The interposer of claim 45, wherein the interposer is disposed in an area:

47. The contact pads in the set are 1 μm 2 46. ​​The interposer of claim 45, wherein the interposer is disposed in an area:

48. An interposer as described in any one of claims 43 to 47, further comprising a test circuit that calculates a bonding offset between the interposer and one or more semiconductor elements to which the interposer is to be bonded, the test circuit being configured to send a signal representing the bonding offset to the switching circuit.

49. 49. The interposer of claim 48, wherein the test circuitry comprises a plurality of vias disposed on the interposer and configured to be bonded to corresponding test pads of the one or more semiconductor devices.

50. 50. The interposer of claim 49, wherein the plurality of vias comprises a two-dimensional array of vias.

51. 48. The interposer of any one of claims 43 to 47, wherein the switching circuitry includes a multi-bit switch multiplexer.

52. 1. A method of making a bonded structure, comprising: bonding first contact pads of a first semiconductor device to second contact pads located on a first surface of an interposer; bonding third and fourth contact pads located on the second surface of the interposer to fifth and sixth contact pads of a second semiconductor device, respectively; switching a first electrical connection state between the second contact pad and the third contact pad and a second electrical connection state between the second contact pad and the fourth contact pad.

53. 53. The method of claim 52, wherein the first semiconductor element comprises a first plurality of contact pads including the first contact pad, the second semiconductor element comprises a second plurality of contact pads including a fifth contact pad and a sixth contact pad, and the interposer comprises a third plurality of contact pads located on the second surface, the third plurality of contact pads including a set of contact pads each connectable to the second contact pad on the first surface via a switching circuit, the set of contact pads including the third contact pad, the fourth contact pad, and one or more additional contact pads.

54. 54. The method of claim 53, further comprising bonding the second semiconductor element to the interposer using a tool having a misalignment tolerance area, wherein the set of contact pads is provided within a pad area that is less than or equal to the misalignment tolerance area.

55. 55. The method of any one of claims 52 to 54, wherein the step of bonding the first contact pad to the second contact pad comprises directly bonding the first contact pad to the second contact pad without an intervening adhesive.

56. 56. The method of claim 55, further comprising directly bonding the third and fourth contact pads to the fifth and sixth contact pads, respectively, without any intervening adhesive.

57. 57. The method of claim 56, further comprising directly bonding a first non-conductive field region of the first semiconductor device to a second non-conductive field region of the interposer without an intervening adhesive.

58. 58. The method of claim 57, further comprising directly bonding a third non-conductive field region of the second surface of the interposer to a fourth non-conductive field region of the second semiconductor device without an intervening adhesive.

59. The method of any one of claims 52 to 54, wherein switching circuitry is provided within the interposer.

60. A method according to any one of claims 52 to 54, wherein a switching circuit is provided within at least one of the first and second semiconductor devices.

61. 1. A bonded structure comprising: a first semiconductor element having a circuit element, a first contact pad, and a second contact pad; a second semiconductor device having a third contact pad bonded to the first contact pad and a fourth contact pad bonded to the second contact pad; a switching circuit configured to switch between a first electrical connection state between the circuit element and the first contact pad and a second electrical connection state between the circuit element and the second contact pad; and a test circuit configured to calculate a bonding offset between the first semiconductor device and the second semiconductor device.

62. 62. The bonded structure of claim 61, wherein the third contact pad is bonded directly to the first contact pad without any intervening adhesive, and the fourth contact pad is bonded directly to the second contact pad without any intervening adhesive.

63. 63. The bonded structure of claim 62, wherein the first semiconductor element has a first non-conductive field region in which the first and second contact pads are at least partially embedded, and the second semiconductor element has a second non-conductive field region in which the third and fourth contact pads are at least partially embedded, and the first non-conductive field region and the second non-conductive field region are bonded directly to each other without an intervening adhesive.

64. 64. The bonded structure of claim 62 or 63, wherein the test circuitry is provided along a dicing lane, and wherein the test circuitry is at least partially destroyed by a dicing step.

65. 62. The bonded structure of claim 61, wherein said switching circuitry is programmed to effect said first electrical connection state or said second electrical connection state based at least in part on said calculated bonding offset.

66. 62. The bonded structure of claim 61, wherein the test circuitry is configured to send a signal representative of the bonding offset to the switching circuitry.

67. A bonded structure as described in claim 1, wherein the switching circuit is configured to switch between the electrical connection between the second contact pad and the fifth contact pad and the electrical connection state between the second contact pad and the sixth contact pad.

68. A bonded structure as described in claim 28, wherein the switching circuit is configured to switch the electrical connection state between each contact pad of the first plurality of contact pads and a plurality of contact pads forming a group of the fourth plurality of contact pads.

Images