Bypass gate transistors with improved stability

Abstract

The transistor device includes a plurality of gate fingers extending in a first direction and spaced apart from one another in a second direction, each of the gate fingers including at least first and second gate finger segments that are generally collinear, spaced apart, and electrically connected to one another. The first gate finger segment is separated in the first direction from the second gate finger segment by a gap region extending in the second direction. A resistor is disposed in the gap region.

Description

[Technical field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 492,032, filed October 1, 2021, which is a continuation-in-part of U.S. Patent Application No. 16 / 907,983, filed June 22, 2020, which is a divisional application of U.S. Patent Application No. 15 / 587,830, filed May 5, 2017, both of which are incorporated herein by reference in their entirety. This application is a continuation of U.S. patent application Ser. No. 16 / 182,642, filed November 7, 2018, which claims priority under U.S.C. 35 U.S.C. 35 U.S.C. 36, which claims priority under U.S.C. 35 U.S.C. 36 as a continuation-in-part of U.S. patent application Ser. No. 15 / 073,201, filed March 17, 2016, which claims priority under U.S.C. 35 U.S.C. 36, the contents of each of which are incorporated herein by reference in their entireties.

[0002] The inventive concepts described herein relate to microelectronic devices, and more particularly to high power, high frequency transistors having unit cell based structures. [Background technology]

[0003] In recent years, electrical circuits that require high power handling capabilities while operating at high frequencies such as radio frequency (500 MHz), S-band (3 GHz) and X-band (10 GHz) have become more prevalent. As high power, high frequency circuits increase, there is an increasing demand for transistors that can operate reliably at radio and microwave frequencies while handling large power loads.

[0004] To provide high power, transistors with large gate perimeters have been developed. One technique for increasing the effective gate perimeter of a transistor is to have multiple transistor cells connected in parallel. For example, a high power transistor may include multiple gate fingers that extend in parallel between respective elongated source and drain contacts, as shown in Figure 1.

[0005] In particular, FIG. 1 illustrates a metal layout of a conventional transistor structure 10 including a gate pad 12, a source pad 22, and a drain pad 32 on a semiconductor structure 20. FIG. 1 illustrates a plan view of the device (i.e., a top-down view of the device). As illustrated in FIG. 1, in the conventional transistor 10, the gate pad 12 is connected by a gate bus 14 to a number of gate fingers 16 that extend parallel in a first direction (e.g., the y-direction in FIG. 1). The source pad 22 is connected via a source bus 24 to a number of parallel source contacts 26, and the drain pad 32 is connected via a drain bus 34 to a number of drain contacts 36. Each gate finger 16 extends along the y-direction between a pair of adjacent source contacts 26 and drain contacts 36. A unit cell of the transistor 10 is illustrated by a box 40 and includes a gate finger 16 that extends between adjacent source contacts 26 and drain contacts 36. "Gate length" refers to the distance of the gate metallization in the x-direction, and "gate width" is the distance that the source contact 26 and drain contact 36 overlap in the y-direction. That is, the "width" of a gate finger 16 refers to the dimension of the gate finger 16 that extends parallel to adjacent source contacts 26 and drain contacts 36 (the distance along the y-direction). The gate perimeter of a device refers to the sum of the gate widths of each gate finger 16 of the device 10.

[0006] In addition to adding unit cells, the gate perimeter of a multicell transistor device can be increased by making the gate fingers wider (i.e., longer in the y-direction). However, making the gate fingers of a device wider can adversely affect the high frequency performance of the device. In addition, making the gate fingers wider generally means that the gate fingers must handle increased current densities, which can cause electromigration of the gate finger metallization. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] US Patent Application Publication No. 2002 / 0066908A1 [Patent Document 2] US Patent Application Publication No. 2002 / 0167023A1 [Patent Document 3] US Patent Application Publication No. 2004 / 0061129 [Patent Document 4] U.S. Patent No. 7,906,799 [Patent Document 5] U.S. Patent No. 6,316,793 [Patent Document 6] US Patent Application Publication No. 2003 / 0102482A1 Summary of the Invention [Means for solving the problem]

[0008] A transistor device according to some embodiments includes a source contact extending in a first direction, a gate finger extending in the first direction adjacent to the source contact, and a drain contact adjacent to the gate finger. The gate finger is between the drain contact and the source contact. A gate pad is electrically connected to the gate finger at a plurality of points along the gate finger.

[0009] The transistor device further includes a gate jumper extending in the first direction and conductively connected to the gate pad, the gate pad being conductively connected through the gate jumper to at least one of a plurality of points along the gate finger.

[0010] The transistor device may further include a gate bus connected to the gate jumper and the gate finger, and a gate signal distribution bar spaced in the first direction from the gate bus connecting the gate jumper to the gate finger.

[0011] A transistor device according to a further embodiment includes a gate pad, a gate finger in conductive contact with the gate pad at a first location on the gate finger and extending in a first direction, and a gate jumper in conductive contact with the gate pad and extending in the first direction, the gate jumper conductively connected to the gate finger at a second location spaced from the first location on the gate finger, such that a gate signal received at the gate pad is applied to the gate finger at both the first and second locations.

[0012] A transistor device according to a further embodiment includes a gate bus, a gate finger in conductive contact with the gate bus at a first location on the gate finger and extending in a first direction, and a gate jumper in conductive contact with the gate bus and extending in the first direction, the gate jumper in conductive contact with the gate finger at a location along the gate finger that is spaced in the first direction from the gate bus.

[0013] A transistor device according to a further embodiment includes a substrate, a gate bus on the substrate, and first and second source contact segments extending in a first direction on the substrate, the first source contact segment and the second source contact segment being separated from each other in the first direction by an air gap. The transistor device further includes a gate finger on the substrate and connected to the gate bus, the gate finger extending in the first direction adjacent to the source contact segment. The transistor device further includes a drain contact on the substrate adjacent to the gate finger, the drain contact having the gate finger between the drain contact and the source contact segment, a gate jumper disposed over the source contact segment and connected to the gate bus, the gate jumper extending in the first direction, and a gate signal distribution bar on the substrate, the gate signal distribution bar extending from the air gap between the first source contact segment and the second source contact segment to the gate finger. A gate signal distribution bar contacts the gate fingers at gate signal distribution points spaced in a first direction from the gate bus and is conductively connected to the gate jumpers.

[0014] A transistor according to a further embodiment includes a drain contact extending along a first axis, a source contact extending along a second axis parallel to the first axis, gate fingers extending between the source and drain contacts, and a plurality of spaced apart gate resistors electrically connected to the gate fingers, at least a first of the gate resistors being disposed in a portion of a region between the first and second axes that is between first and second ends of the gate fingers when viewed from the top of the transistor.

[0015] In some embodiments, the gate finger may include a plurality of collinear, discontinuous gate finger segments electrically connected to one another. The transistor may further include a gate jumper electrically connected between the gate bus and the first gate finger segment. The first gate resistor may be inserted along an electrical path between the gate jumper and the first gate finger segment. The transistor may also include a first gate signal distribution bar inserted along an electrical path between the gate jumper and the first gate finger segment. The first gate resistor may be inserted along an electrical path between the first gate signal distribution bar and the first gate finger segment. Each gate finger segment may be part of a respective gate split, and the transistor may further include an odd mode resistor disposed between two adjacent gate splits.

[0016] In some embodiments, the source contact includes a plurality of collinear, discontinuous source contact segments, with a gate jumper extending over the source contact. A first gate signal distribution bar may extend into a gap between two adjacent source contact segments. An odd-mode resistance may be inserted between the first gate signal distribution bar and a second gate signal distribution bar collinear with the first gate signal distribution bar. Still further, the transistor may include a second source contact including a plurality of collinear, discontinuous source contact segments, with no gate jumper extending over the source contact segments, and there may be an odd-mode resistance between two adjacent source contact segments of the second source contact.

[0017] A transistor according to a further embodiment includes a source contact extending in a first direction, a gate jumper extending in the first direction, and a gate finger having a plurality of discontinuous gate finger segments that may be collinear with one another. The transistor further includes a plurality of spaced apart gate resistors electrically connected to the gate jumper. A first gate finger segment is connected to the gate jumper through the first gate resistor.

[0018] In some embodiments, the source contact includes a plurality of discontinuous source contact segments, with a first gate resistance in a gap between two adjacent source contact segments. A gate jumper may extend across at least some of the source contact segments. The transistor may further include a drain contact extending in a first direction adjacent to the first gate finger, with the first gate finger extending between the source contact and the drain contact, a second gate finger including a plurality of collinear discontinuous gate finger segments extending in the first direction, with the drain contact extending between the first gate finger and the second gate finger, and a second source contact including a plurality of discontinuous source contact segments extending in the first direction adjacent to the second gate finger. An odd-mode resistance may be provided in a gap between two adjacent source contact segments of the second source contact.

[0019] A first gate signal distribution bar may extend between the gate jumper and the first gate finger segment of the first gate finger and between the gate jumper and the first gate finger segment of the second gate finger. The first gate signal distribution bar may be disposed in a gap between two adjacent source contact segments of the source contact. An odd-mode resistor may be connected between the first gate signal distribution bar and a second gate signal distribution bar connecting the gate finger segments of the multiple additional gate fingers to the second gate jumper.

[0020] A transistor according to a further embodiment includes a plurality of gate fingers extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction, each of the gate fingers including at least a generally collinear, spaced apart first gate finger segment and a second gate finger segment, the first gate finger segment separated in the first direction from the second gate finger segment by a gap region extending in the second direction, and a resistor disposed in the gap region.

[0021] In some embodiments, the transistor further includes a plurality of source contacts extending in the first direction, each source contact including a plurality of discontinuous source contact segments, each source contact extending between a gate finger of a respective pair of gate fingers and a plurality of drain contacts extending in the first direction, each drain contact extending between a respective pair of gate fingers. A gate bus may be electrically connected to the gate fingers, and a gate jumper may be electrically connected to the gate bus, the gate jumper being interposed along the electrical path between at least some of the gate finger segments and the gate bus.

[0022] In some embodiments, the resistor may be an odd-mode resistor disposed between two adjacent source contact segments of one of the source contacts. In other embodiments, the resistor may be a gate resistor inserted along the electrical path between the gate jumper and the first gate finger segment of the first gate finger. In these embodiments, the gate resistor may be inserted along a first gate signal distribution bar that extends between the gate jumper and the first gate finger segment of the first gate finger.

[0023] According to a further embodiment of the invention, there is provided a transistor comprising a semiconductor layer structure having a top surface formed with a source contact, a drain contact, and a gate finger disposed between the source contact and the drain contact, the transistor further comprising a gate jumper disposed over the source contact electrically connected to at least a portion of the gate finger, the source contact extending continuously over the top surface of the semiconductor layer structure without any gaps dividing the source contact into segments.

[0024] In some embodiments, the gate finger may comprise a plurality of non-contiguous gate finger segments.

[0025] In some embodiments, the transistor may further include a gate bus, where at least one of the discontinuous gate finger segments is electrically connected to the gate bus through a gate jumper.

[0026] In some embodiments, there may be a source contact on a first major surface of the semiconductor layer structure, and the transistor may further comprise a source bus layer on a second major surface of the semiconductor layer structure, and a plurality of source contact plugs extending through the semiconductor layer structure electrically connecting the source contact to the source bus layer.

[0027] In some embodiments, the source contact may include at least a first enlarged portion, a second enlarged portion, and a narrowed portion physically and electrically connecting the first enlarged portion to the second enlarged portion, and the first and second enlarged portions may be wider than the narrowed portion in a direction perpendicular to a longitudinal axis of the source contact and parallel to a bottom surface of the semiconductor layer structure.

[0028] In some embodiments, the transistor may further comprise a gate signal distribution bar that is flush with the gate jumper above the semiconductor layer structure and extends from the gate jumper toward the gate finger. In some embodiments, the gate signal distribution bar is interposed in an electrical path between the gate jumper and at least a portion of the gate finger. In some embodiments, the gate signal distribution bar may be electrically connected to the gate finger by a conductive via.

[0029] In some embodiments, the transistor may further comprise a series gate resistor inserted in the electrical path connecting the gate bus to the gate signal distribution bar.

[0030] In some embodiments, a longitudinal axis of the source contact, a longitudinal axis of the drain contact, and a longitudinal axis of the gate finger each extend in a first direction.

[0031] According to a further embodiment of the present invention there is provided a transistor comprising a semiconductor layer structure, a source contact extending in a first direction on a top surface of the semiconductor layer structure, a drain contact extending in the first direction on the top surface of the semiconductor layer structure, and a gate finger extending in the first direction on the top surface of the semiconductor layer structure, the gate finger being disposed between the source contact and the drain contact, wherein one of the source contact and the drain contact includes a first enlarged portion and a second enlarged portion on the top surface of the semiconductor layer structure that are physically and electrically connected to each other by a narrowed portion.

[0032] In some embodiments, the source contact may include first and second widening portions and a narrowing portion, the first and second widening portions may be wider than the narrowing portion in a direction perpendicular to a longitudinal axis of the source contact and parallel to a bottom surface of the semiconductor layer structure.

[0033] In some embodiments, the transistor may further include a gate bus and a gate jumper electrically connected to the gate bus, the gate jumper being disposed over the source contact, and at least a portion of the gate finger may be electrically connected to the gate bus through the gate jumper.

[0034] In some embodiments, the gate fingers may be a plurality of discontinuous gate finger segments.

[0035] In some embodiments, the transistor may further include a gate signal distribution bar formed in the same metal layer as the gate jumper and extending from the gate jumper toward the gate finger, hi some embodiments, the gate signal distribution bar may be electrically connected to at least a portion of the gate finger by a vertical contact plug.

[0036] In some embodiments, a plane perpendicular to the longitudinal axis of the gate jumper and the plane defined by the bottom surface of the semiconductor layer structure can extend through both the narrowed portion of the source contact and the perpendicular contact plug.

[0037] In some embodiments, the transistor may further comprise a series gate resistor inserted in the electrical path connecting the gate bus to the gate signal distribution bar.

[0038] In some embodiments, the transistor may further comprise a source bus layer and a plurality of source contact plugs electrically connecting the source contacts to the source bus layer.

[0039] In some embodiments, a first gate finger segment of the discontinuous gate finger segments may be electrically connected to the gate bus through a series gate resistor and may not be electrically connected to the gate bus through a gate jumper.

[0040] According to a further embodiment of the present invention there is provided a transistor comprising: a semiconductor layer structure; a source contact extending in a first direction on a top surface of the semiconductor layer structure; a drain contact extending in the first direction on the top surface of the semiconductor layer structure; a gate finger extending in the first direction on the top surface of the semiconductor layer structure, the gate finger disposed between the source contact and the drain contact; a plurality of discontinuous gate finger segments; a gate bus; and a gate jumper electrically connected to the gate bus, the gate jumper having a longitudinal axis extending in the first direction overlying the source contact and a gate signal distribution bar formed in the same metal layer as the gate jumper, the gate signal distribution bar extending from the gate jumper towards a first one of the discontinuous gate finger segments.

[0041] In some embodiments, the source contact includes a first enlarged section and a second enlarged section on a top surface of the semiconductor layer structure that are physically and electrically connected to each other by a narrowed section, and a gate jumper is disposed over the source contact, and a first gate finger segment of the discontinuous gate finger segments is electrically connected to a gate bus through the gate jumper.

[0042] In some embodiments, the gate signal distribution bar may be electrically connected to a first one of the discontinuous gate finger segments by a vertical contact plug.

[0043] In some embodiments, a plane perpendicular to the longitudinal axis of the gate jumper and the plane defined by the bottom surface of the semiconductor layer structure can extend through both the narrowed portion of the source contact and the perpendicular contact plug.

[0044] In some embodiments, the transistor may further include a series gate resistor inserted in the electrical path connecting the gate bus to the gate signal distribution bar, hi some embodiments, the series gate resistor may be implemented as part of a gate jumper.

[0045] In some embodiments, the transistor may further comprise a series gate resistor inserted in the electrical path connecting the gate bus to the gate signal distribution bar.

[0046] In some embodiments, a second one of the discontinuous gate finger segments may be electrically connected to the gate bus through a series gate resistor and may not be electrically connected to the gate bus through a gate jumper.

[0047] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this application, illustrating specific embodiment(s) of the invention. [Brief description of the drawings]

[0048] [Figure 1] FIG. 1 is a plan view of a metal layout for a conventional multi-cell transistor. [Diagram 2] FIG. 2 is a plan view of a metal layout of a transistor according to some embodiments. [Diagram 3] FIG. 3 is a partial isometric view of the transistor of FIG. 2. [Figure 4] 3 is a partial cross-sectional view of the transistor of FIG. 2 taken along line A-A' of FIG. 2; [Diagram 5] FIG. 3 is a plan view of a larger version of the transistor of FIG. 2. [Figure 6]FIG. 6 is a detailed plan view of a small portion of the transistor of FIG. 5. [Figure 7] FIG. 3 is a cross-sectional view taken along line B-B' of a unit cell of the transistor device of FIG. 2. [Figure 8] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment. [Figure 9A] FIG. 9 is a partial cross-sectional view taken along line AA' in FIG. 8. [Figure 9B] 9 is a partial cross-sectional view taken along line BB' in FIG. 8. [Figure 10] FIG. 9 is a plan view of a larger version of the transistor of FIG. 8. [Figure 11] FIG. 11 is a detailed plan view of a small portion of the transistor of FIG. [Figure 12] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment. [Figure 13] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment. [Figure 14] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment. [Figure 15] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment. [Figure 16] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment of the present invention. [Figure 17] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment of the present invention. [Figure 18] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment of the present invention. [Figure 19] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment of the present invention. [Figure 20] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment of the present invention. [Figure 21] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment of the present invention. [Figure 22] FIG. 13 is a plan view of a metal layout of a transistor according to a further embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] The inventive concepts are described more fully below with reference to the accompanying drawings, in which embodiments of the invention are shown. The inventive concepts may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concepts to those skilled in the art. Like numbers refer to like elements throughout.

[0050] An embodiment of the inventive concept provides a multi-cell transistor device having a large effective gate width. By providing a gate signal to the gate finger at multiple locations along the width of the gate finger, the high frequency gain performance of the transistor may be improved and electromigration problems normally associated with wide gate fingers may be mitigated. According to some embodiments, the larger gate width of the multi-cell transistor device may be incorporated by adding a second layer of metal acting as a gate jumper over the source region of the unit cell. The gate jumpers are connected to the gate fingers at various locations along the gate finger, effectively dividing the gate finger into multiple segments. The gate jumpers may be provided by a second layer of metal extending over the source contacts connecting the gate pad to the gate segments. In some embodiments, the gate jumpers may extend over the drain contacts or gate fingers rather than over the source contacts.

[0051] By effectively dividing the gate fingers into segments and distributing the gate signal to each of the gate finger segments by gate jumpers, the gain performance of the transistor may be improved and electromigration problems may be mitigated.

[0052] Thus, an embodiment of the inventive concept provides a transistor layout that defines a plurality of unit cells in series for each gate finger. Each of the unit cells individually has a shorter effective gate width. However, when connected in series, the unit cells can increase the effective length of a single gate finger. The gate fingers of the series-connected unit cells are connected to a gate bus by a second metal bridge that extends across the source contacts of the unit cells. The metal bridge is connected between the source contacts to a connection bar that extends along the surface of the substrate between the source contacts and connects to the gate fingers.

[0053] A transistor having a layout as described herein may have higher frequency performance and higher output power, while at the same time reducing current density and improving device reliability.

[0054] According to a further embodiment of the present invention, a multi-cell transistor having a large effective gate width is provided in which multiple series gate resistors (also referred to herein as "gate resistors") are distributed throughout the device. For example, the multi-cell transistor may have segmented gate fingers, and each gate finger segment or pair of gate finger segments may be provided with a series gate resistor. This approach breaks up long feedback loops within the gate fingers and drains of the transistor structure by making the feedback loop losses large enough to prevent high levels of instability. The distributed series gate resistors may be located, for example, in gap regions provided between the gate finger segments of the gate fingers.

[0055] Thus, in some embodiments, a transistor is provided that includes a drain contact extending along a first axis, a source contact extending along a second axis parallel to the first axis, and a gate finger extending between the source and drain contacts. The gate finger may include a number of collinear, physically discontinuous gate finger segments that are electrically connected to one another by one or more other structures (e.g., gate jumpers). The transistor further includes a number of spaced apart gate resistors that are electrically connected to the gate fingers. At least one of the gate resistors is disposed in a portion of the region between the first and second axes that is between the first and second ends of the gate finger when viewed from the top of the transistor. In some embodiments, the gate jumper may be electrically connected to the gate finger and the gate bus. A gate jumper can be inserted along an electrical path between the first gate finger segment and the gate bus, and a first gate resistor can be inserted along the electrical path between the gate jumper and the first gate finger segment.

[0056] In another embodiment, a transistor is provided that includes a source contact extending in a first direction, a gate jumper extending in the first direction, and a gate finger having a plurality of discontinuous gate finger segments extending in the first direction. The transistor further includes a plurality of spaced apart gate resistors each electrically connected to the gate jumper. A first gate finger segment is connected to the gate jumper through the first gate resistor.

[0057] In accordance with further embodiments of the present invention, a multi-cell transistor having a large effective gate width is provided with a plurality of odd-mode resistors distributed throughout the device. In an exemplary embodiment, the odd-mode resistors may be provided in gap regions formed between "gate splits," where a gate split refers to a region where multiple gate finger segments extend parallel to one another. To further improve the stability of the transistor, the odd-mode resistors may be distributed throughout these gap regions. The aforementioned gate resistors may also be located in these gap regions.

[0058] Thus, additional embodiments provide a transistor including a plurality of gate fingers extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction, each of the gate fingers including at least first and second gate finger segments that are generally collinear and electrically connected to one another at a distance, the first gate finger segment being separated in the first direction from the second gate finger segment by a gap region extending in the second direction, and at least one resistor disposed in the gap region. The at least one resistor may be an odd-mode resistor and / or a series gate resistor.

[0059] Transistors according to embodiments of the inventive concepts may have a large effective gate width, aiding in increased power density levels, and may exhibit improved frequency response over conventional transistors. In addition, when gate series resistors and odd-mode resistors are provided, they may help prevent feedback loops that may generate unwanted signals at frequencies low enough that they are within or close to the operating frequency of the transistor. Thus, the transistors may also exhibit improved stability and therefore have improved production yields and / or better reliability.

[0060] It will be appreciated that the above embodiments may be combined in any manner. For example, a transistor may be provided that includes both a distributed gate resistor and a distributed odd-mode resistor. Similarly, a transistor having non-segmented gate fingers may include either or both a distributed gate resistor and a distributed odd-mode resistor.

[0061] Next, an embodiment of the present invention will be described in more detail with reference to FIGS.

[0062] Figure 2 is a plan view of a metal layout of a transistor 100, according to some embodiments. The transistor is formed on a semiconductor structure 120 that includes one or more device epitaxial layers, which are described in more detail below. The layout of Figure 2 is simplified for clarity and includes a gate pad 112 connected to a gate bus 114 and a drain pad 132 connected to a drain bus 134. The source pad and source bus are omitted from Figure 2 for clarity of illustration, but are shown in Figures 5 and 6.

[0063] A plurality of gate fingers 116 are connected to gate bus 114 and extend in the y-direction. Similarly, a plurality of drain contacts 136 are connected to drain bus 134 and extend adjacent to and parallel to each of gate fingers 116. Although only four gate fingers 116 and three drain contacts 136 are shown in Figure 2, it will be appreciated that transistor 100 may have many more gate fingers 116 and drain contacts 136, and thus many more unit cells.

[0064] A source contact 162 is also provided and extends parallel to adjacent gate fingers 116 in the y-direction. The source contact 162 is divided in the y-direction into respective source contact segments 162a, 162b, and 162c. The source contact segments may be connected by a source contact bar 128 (FIG. 6) that extends laterally (in the x-direction) across the device structure. The source contact segments 162a, 162b, 162c may be connected by other means. For example, a source contact plug may be provided that electrically connects each source contact segment 162a, 162b, 162c to a common conductive layer disposed, for example, at a lower level of the device.

[0065] Adjacent ones of the source contact segments 162a-162c are separated by an air gap 162g. Although Fig. 2 shows three source contact segments 162a-162c for each source contact 162, it will be appreciated that the inventive concept is not limited to such a configuration and that a source contact 162 may include two or more source contact segments 162a-162c.

[0066] The gate fingers 116 may extend parallel to the source contacts 162 for the entire length of the source contacts 162. However, because the source contacts 162 are divided into source contact segments 162a-162c, the source contact segments 162a, 162b, and 162c define a plurality of series unit cells 40a, 40b, and 40c for each of the gate fingers 116. That is, each gate finger 116 serves as a gate contact for a plurality of unit cells 40a, 40b, and 40c that are laid out in a direction (y-direction) along which the gate finger 116 extends, defining the width of the gate finger 116. Thus, the total width that each gate finger 116 contributes to the gate perimeter of the overall device is equal to the distance that the gate finger 116 overlaps in the y-direction with adjacent source contact segments 162a, 162b, and 162c.

[0067] The transistor 100 further includes a number of gate jumpers 172 extending parallel along the y-direction to the gate fingers 116. The gate jumpers 172 may be formed over the source contacts 162 and may be insulated from the source contacts 162 by, for example, a dielectric layer and / or an air gap. The gate jumpers 172 are electrically connected to the gate bus 114 and connect each gate finger 116 to the gate bus 114 at a number of locations along the gate fingers 116.

[0068] In particular, gate signal distribution bars 174 connecting the gate jumpers 172 to the gate fingers 116 are provided at multiple locations along the width of the device and extend laterally (in the x-direction) in the gaps 162g between adjacent ones of the source contact segments 162a, 162b, and 162c. The gate signal distribution bars 174 connect to the gate fingers 116 at respective gate signal distribution points 176. Thus, an electrical signal applied to the gate pad 112 (the "gate signal") is conducted from the gate bus 114 to the gate jumpers 172 and distributed by the gate jumpers 172 to the gate fingers 116 at multiple locations (the gate signal distribution points 176) along the width of the gate fingers 116. Thus, in the embodiment of FIG. 2, rather than being conducted by the gate fingers 116 across the entire width of the device, the gate signal is conducted by the gate jumpers 172 across most of the width of the device and then distributed to the gate fingers 116 at various locations along the width of the device.

[0069] The gate jumpers 172 may have a larger cross-sectional area than the gate fingers 116 and therefore can better handle higher current densities than the gate fingers 116 without the problems typically associated with increased gate widths, such as electromigration and reduced high frequency gain performance.

[0070] Figure 3 is a partial isometric view of a metal layout of transistor 100, and Figure 4 is a partial cross-sectional view taken along line A-A' in Figure 2. As can be seen in Figures 3 and 4, the metal level on which gate jumper 172 is formed is higher than the metal level of source contact segments 162a, 162b, 162c, gate fingers 116, gate bus 114, and gate signal distribution bar 174. Gate jumper 172 is connected to gate bus 114 and gate signal distribution bar 174 by vertical contact plugs 178.

[0071] The gate jumpers 172, gate buses 114, vertical contact plugs 178 and gate signal distribution bars 174 may be formed of a conductive material such as copper or aluminum and have very low resistance.

[0072] FIG. 5 is a plan view of a larger version of transistor 100, and FIG. 6 is a detailed plan view of a small portion 150 of the metal layout of FIG. 5 (i.e., the portion within the dashed box in FIG. 5). Transistor 100 includes a number of unit cells 40 extending vertically (in the y-direction). Each of the unit cells 40 includes one gate finger 116 that extends across the entire width of the device and is subdivided into vertically (y-direction) arranged series unit cells 40a, 40b, 40c as described above. In the embodiment shown in FIGS. 5 and 6, each of the unit cells 40 has an overall width of 1120 microns, and the series unit cells 40a, 40b, and 40c have widths of 370 microns, 380 microns, and 370 microns, respectively, although the inventive concept is not limited to these particular dimensions. In this manner, the effective gate width of the device may be increased.

[0073] 6, a gate pad 112 and gate bus 114 are provided at one end of the structure, and a drain pad 132 and drain bus 134 are provided at the other end of the structure. A source pad 122 is provided on the side of the structure and is connected to a source bus 124. The source bus 124 is connected to a number of source contact bars 128 that extend laterally (x-direction) to contact source contact segments 162a, 162b, 162c. As previously mentioned, the source contact segments 162a, 162b, 162c may be electrically connected in other manners, such as using source contact plugs that electrically connect each to a common conductive layer.

[0074] In FIG. 6, a detailed view 150 of a portion of the device layout of transistor 100 also shows gate fingers 116 , gate jumpers 172 , gate signal distribution bars 174 that contact gate fingers 116 , and gate signal distribution points 176 .

[0075] 7 is a cross-sectional view taken along line B-B' of the unit cell 40 of the transistor device 100 of FIG. 2. The transistor structure 100 includes a semiconductor structure 120 including a substrate 200, which may include, for example, 4H-SiC or 6H-SiC. A channel layer 210 is formed on the substrate 200, and a barrier layer 220 is formed on the channel layer 210. The channel layer 210 and the barrier layer 220 may include III-nitride based materials, and the material of the barrier layer 220 has a larger band gap than the material of the channel layer 210. For example, the channel layer 210 may include GaN, and the barrier layer 220 may include AlGaN.

[0076] A two-dimensional electron gas (2DEG) is induced in the channel layer 210 at the junction between the channel layer 210 and the barrier layer 220 due to the band gap difference between the barrier layer 220 and the channel layer 210 and the piezoelectric effect at the interface between the barrier layer 220 and the channel layer 210. The 2DEG acts as a highly conductive layer, allowing conduction between the source region of the device, which is under the source contact segment 162b, and the drain region, which is under the drain contact 136, respectively. The source contact segment 162b and the drain contact 136 are formed on the barrier layer 220. The gate finger 116 is formed between the drain contact 136 and the source contact segment 162b on the barrier layer 220. A gate jumper 172 is provided on top of the source contact segment 162b and is connected to the gate finger 116 through a vertical contact plug 178 and a gate signal distribution bar 174. Vertical contact plugs 178 and gate signal distribution bars 174 are disposed in gaps 162g between adjacent ones of source contact segments 162a-162c and do not physically contact source contact segments 162a-162c. Note that source contact segment 162b is offset in the y-direction from the cut along line B-B' (see FIG. 2) and therefore is not actually present in the cross section of FIG. 7, but is shown in FIG. 7 to facilitate the above discussion.

[0077] A first interlayer insulating layer 232 is formed over the drain contacts 136, the gate fingers 116, the source contact segments 162b, and the gate signal distribution bars 174. The interlayer insulating layer 232 may include a dielectric material such as SiN, SiO2, etc. A vertical contact plug 178 penetrates the first interlayer insulating layer 232. A gate jumper 172 is formed on the first interlayer insulating layer 232 insulating the gate jumper 172 from the source contact segments 162b. A second interlayer insulating layer 234 may be formed over the first interlayer insulating layer 232 and the gate jumper 172. The second interlayer insulating layer 234 may include a dielectric material such as SiN, SiO2, etc.

[0078] The material of the gate fingers 116 may be selected based on the composition of the barrier layer 220. However, in particular embodiments, materials capable of making Schottky contacts to nitride-based semiconductor materials include Ni, Pt, NiSi, and the like. x Conventional materials such as TiN, Cu, Pd, Cr, W and / or WSiN may be used. The drain contact 136 and source contact segments 162 may include a metal such as TiAlN that can form an ohmic contact to GaN.

[0079] High power transistors according to embodiments of the present invention may include series gate resistors and odd mode resistors to stabilize feedback loops inside the gate fingers and drain of the device. In high power devices, the gate may have a long gate width to increase the gate perimeter of the device, resulting in a long feedback loop. Because these high power transistors have large transconductance values, the feedback loops are prone to instability. In particular, the feedback loops may generate unwanted signals input to or output from the operating frequency band of the transistor. In either case, the generation of such signals is problematic and may render the transistor unusable. Feedback loop instability tends to increase with the length of the feedback loop.

[0080] High power transistors provided in accordance with further embodiments of the present invention include multiple series gate resistors and / or odd mode resistors distributed throughout the device, particularly along the long gate fingers. Distributed series gate resistors and / or odd mode resistors may be advantageous, particularly in transistors with segmented gate fingers, as such devices may include void regions between "gate splits" that are natural locations for placing series gate resistors and / or odd mode resistors along the width of the gate fingers. As used herein, the term "gate split" refers to a shorter arrangement of gate finger segments that results when a long gate finger is segmented into multiple gate finger segments, as discussed above with reference to Figures 2-7. The void regions that exist between adjacent gate splits may be convenient locations for implementing distributed series gate resistors and odd mode resistors, as discussed in more detail below.

[0081] It has been found that distributing the series gate resistors and / or odd-mode resistors along the extended width of the gate fingers can provide sufficient losses in the feedback loop to overcome potential instabilities. Thus, distributing the series gate resistors and / or odd-mode resistors along the extended width of the gate fingers can improve device yields and / or reduce device failure rates in the field. Furthermore, when distributing the series gate resistors and / or odd-mode resistors between and along the gate finger segments of a segmented gate finger, the resistance levels used can be relatively small. For example, if a transistor has three gate splits, the size of the resistance levels used can be about 1 / 3 of that used if the gate fingers were not segmented. Furthermore, it has been found that in practice the reduction in resistance value can be even greater. For example, when three gate splits are used, the resistance value of the series resistor included along each gate segment can be 1 / 4 to 1 / 5 of the resistance value of the series gate resistor implemented at the gate pad. Using resistors with lower resistance values ​​results in lower losses and therefore a transistor with greater gain while also being more stable.

[0082] FIG. 8 is a plan view (top view) of a metal layout of a transistor 300 according to a further embodiment that implements both series gate resistance and odd-mode resistance in a distributed manner as discussed above. The transistor 300 is formed on a semiconductor structure 320 that includes one or more device epitaxial layers. The semiconductor structure 320 may be identical to the semiconductor structure 120 discussed above with reference to FIG. 7. As with the previous figures, the layout of FIG. 8 is simplified for clarity and includes a pair of gate pads 312 connected to a respective pair of gate buses 314, and a drain pad 332 connected to a drain bus 334. The transistor 300 also includes a source pad 322 and a source bus, which are omitted from FIG. 8 for clarity of illustration. The source pad 322 is shown in FIG.

[0083] A number of gate fingers 316 are connected to respective gate buses 314 and extend in the y-direction. Each gate finger 316 is divided in the y-direction into three gate finger segments 316a, 316b, and 316c. As described below, the gate finger segments 316a, 316b, and 316c of each gate finger 316 may be electrically connected to one another via gate jumpers 372, gate signal distribution bars 374, and vertical contact plugs 378 (FIG. 9A). A number of drain contacts 336 are connected to the drain buses 334 and extend adjacent and parallel to each of the gate fingers 316. The gate signal distribution bars 374 may be formed at a different vertical level in the device than the gate distribution bars 174 of the transistor 100 so as to be able to pass over the drain contacts 336, as described below. A source contact 362 is also provided and extends parallel to adjacent gate fingers 316 in the y-direction. The source contact 362 is divided in the y-direction into respective source contact segments 362a, 362b, and 362c. The source contact segments 362a, 362b, 362c may be electrically connected to each other via a source contact plug 364. Each source contact plug 364 may electrically connect each source contact segment 362a, 362b, 362c to a common conductive layer that serves as a source bus. The source bus may be located, for example, at a lower level in the device. In some embodiments, multiple source contact plugs 364 may be provided for each source contact segment 362a, 362b, 362c. In FIG. 8, two representative source contact plugs 364 are shown on one source contact segment 362c. The source contact plugs 364 for the other source contact segments 362a, 362b, 362c have been omitted from FIG. 8 (as well as FIGS. 9A-9B and 12-13) to simplify the drawings.10 and 11 show, for example, that a pair of source contact plugs 364 may be provided for each source contact segment 362a, 362b, 362c. The source contact segments 362a, 362b, 362c may also be electrically connected by other means, such as, for example, a source contact bar. A total of 16 segmented gate fingers 316, eight segmented source contacts 362, and eight drain contacts 336 are shown in FIG. 8. However, it will be appreciated that the transistor 300 may have many more gate fingers 316, source contacts 362, and drain contacts 336, and thus many more unit cells. In other embodiments, fewer gate fingers 316, source contacts 362, and drain contacts 336 may be provided.

[0084] Adjacent ones of the gate finger segments 316a-316c are separated by a gap 316g, and adjacent ones of the source contact segments 362a-362c are separated by a gap 362g. Although FIG. 8 shows three gate finger segments 316a-316c and three source contact segments 362a-362c for each gate finger 316 and source contact 362, the inventive concepts are not limited to such a configuration. Thus, it will be appreciated that a gate finger 316 may include more than one gate finger segment and a source contact 362 may include more than one source contact segment.

[0085] The gate fingers 316 may extend parallel to the source contacts 362 for the entire length of the source contacts 362. Because the gate fingers 316 and the source contacts 362 are segmented, a number of unit cells 340a, 340b, 340c are defined along each gate finger 316. That is, each gate finger segment 316a-316c serves as a gate contact for each unit cell 340a, 340b, 340c laid out in the direction in which the gate fingers 316 extend (the y-direction). The sum of the widths of the gate finger segments 316a-316c defines the total width of each gate finger 316. Thus, the total width that each gate finger 316 contributes to the gate perimeter of the entire device is equal to the sum of the widths of the gate finger segments 316a-316c in the y-direction.

[0086] The transistor 300 further includes a number of gate jumpers 372 extending parallel to the gate fingers 316 along the y-direction. The gate jumpers 372 may be formed at a metal level higher than the metal levels of the source contact segments 362, the gate fingers 316, and the gate bus 314. The gate jumpers 372 may be formed on the source contacts 362 and may be insulated from the source contacts 362 by, for example, a dielectric layer and / or an air gap. The gate jumpers 372 need not extend beyond the source contact segment 362c that is furthest from the gate bus 314. The gate jumpers 372 are electrically connected to the gate bus 314. The gate jumpers 372 may electrically connect some or all of the gate finger segments 316a-316c of each gate finger 316 to one of the gate buses 314. 8, each gate jumper 372 electrically connects gate finger segments 316b and 316c to gate bus 314, with gate finger segment 316a connected to gate bus 314 by a more direct connection. In other embodiments, gate finger segment 316a may be connected to gate bus 314 by gate jumper 372. In some embodiments, gate jumper 372 may be located over drain contact 336 or gate finger 316 rather than over source contact 362.

[0087] FIG. 9A is a partial cross-sectional view taken along line A-A' in FIG. 8. FIG. 9B is a partial cross-sectional view taken along line B-B' in FIG. 8. As seen in FIG. 8 and FIG. 9A, a plurality of gate jumpers 372, gate signal distribution bars 374, and vertical contact plugs 378 are provided. The gate jumpers 372 are connected to the gate bus 314 and the gate signal distribution bars 374 by the vertical contact plugs 378. The gate jumpers 372, the gate signal distribution bars 374, and the vertical contact plugs 378 are used to connect each gate finger segment 316b-316c to one of the gate buses 314. The gate signal distribution bars 374 may be formed in a metal layer that is higher in the device than the gate fingers 316. For example, as shown in FIG. 9A, the gate signal distribution bars 374 may be formed in the same metal layer as the gate jumpers 372 of the device. A vertical contact plug 378 may connect the gate jumper 372 to the gate bus 314. Additional vertical contact plugs 378 (not seen in the cross section of FIG. 9A, but located in the plan view of FIG. 8 at the points where each gate signal distribution bar avoids the gate resistor 380) may physically and electrically connect the gate signal distribution bar 374 to the gate resistor and its associated gate finger segment 316a-c. As previously mentioned, the gate jumper 372 may extend over the source contacts 362. In contrast to the transistor 100 of FIGS. 2-7, which includes a gate jumper 172 that extends over every source contact 162, as seen in FIG. 8, the gate jumper 372 is provided over every other source contact 362. 8-9B, each gate jumper 372 provides four gate fingers 316 rather than two gate fingers 116 as in transistor 100. Each gate signal distribution bar 374 is formed in a metal layer that is higher in the device than the gate distribution bars 174 of transistor 100, such that it can pass over the two drain contacts 336 and connect to the outer ones of the four gate finger segments 316a-c.

[0088] The gate jumpers 372, gate buses 314, vertical contact plugs 378 and gate signal distribution bars 374 may be formed of a conductive material such as copper or aluminum and have very low resistance.

[0089] 8 and 9A, the gate signal distribution bars 374 extend laterally (x-direction) in the gaps 362g between adjacent ones of the source contact segments 362a, 362b, and 362c. The gate signal distribution bars 374 coupled to the first gate finger segment 316a may be coupled to two of the gate finger segments 316a. Each of the gate signal distribution bars 374 coupled to the second gate finger segment 316b or the third gate finger segment 316c may be coupled to four of the gate finger segments 316b or 316c. As seen in FIG. 8, each gate signal distribution bar 374 coupled to the first gate finger segment 316a may be connected to one of the gate buses 314 by a gate resistor 380. The gate signal distribution bar 374 that connects to the gate finger segment 316a does not need to cross the drain contact 336 and may therefore be part of the same metal layer as the gate finger 316 or the gate jumper 372. As seen in Figures 8 and 9A, each gate signal distribution bar 374 coupled to either the second gate finger segment 316b or the third gate finger segment 316c may connect to one of the gate buses 314 through one of the gate jumpers 372 and to the gate finger segment 316b, 316c through a respective vertical contact plug 378. A series gate resistor 380 is provided in the electrical path between each gate finger segment 316b, 316c and its associated gate signal distribution bar 374.

[0090] 8 and 9A, we will now discuss the distribution of an electrical signal applied from the left gate pad 312 in FIG. 8 to the leftmost gate finger segments 316a, 316b, 316c in FIG. 8. A gate signal applied to the gate pad 312 is conveyed to the left gate bus 314. The gate signal travels from the left gate bus 314 through a first gate signal distribution bar 374 and a first series gate resistor 380 to the first gate finger segment 316a. The gate signal also travels from the left gate bus 314, in order, through a first vertical contact plug 378 that connects the gate bus 314 to a gate jumper 372, through the gate jumper 372, through a second gate signal distribution bar 374, through a second series gate resistor 380 to a second vertical contact plug 378 that connects the gate bus 314 to the leftmost second gate finger segment 316b. Similarly, the gate signal travels from the left gate bus 314, through the first vertical contact plug 378, the gate jumper 372, the third gate signal distribution bar 374, and through the third series gate resistor 380 to the third vertical contact plug 378 which connects to the leftmost third gate finger segment 316b.

[0091] 8 and 9A, the gate signal does not travel the entire length of any one gate finger 316, but only along the length of the gate finger segment (e.g., gate finger segment 316a), or the length of the gate finger segment and a portion of the gate jumper 372 (e.g., gate finger segment 316b), or the length of the gate finger segment and the entire length of the gate jumper 372 (e.g., gate finger segment 316c). The gate jumper 372 may have a larger cross-sectional area than the gate fingers 316 and therefore can better handle higher current densities than the gate fingers 316 without the problems typically associated with increased gate width, such as electromigration and reduced high frequency gain performance. The gate signal also travels along a portion of the gate signal distribution bar 374 and the vertical contact plug 378. However, it should be noted that Figure 8 is not to scale, and that the distance that the gate signal travels along any gate signal distribution bar 374 is very short (e.g., less than 5%) compared to the length of the gate finger segment in the y-direction, as seen in Figures 10-11. The distance traveled along the vertical contact plugs 378 is also very short. Thus, the distance that the gate signal travels along the narrow conductor line may be reduced.

[0092] As discussed above, transistor 300 includes a plurality of series gate resistors 380 distributed throughout the device. In particular, series gate resistors 380 are provided at or near one end of each of gate finger segments 316a, 316b, 316c. As shown in FIG. 8, gate finger 316 is divided into three "gate splits," a first gate split 382a that includes gate finger segment 316a, a second gate split 382b that includes gate finger segment 316b, and a third gate split 382c that includes gate finger segment 316c. A first void region 384a is provided between the gate bus 314 and the first gate split 382a, a second void region 384b is provided between the gate splits 382a and 382b, and a third void region 384c is provided between the gate splits 382b and 382c.

[0093] As shown in FIG. 8, the series gate resistor 380 may be formed in the aforementioned void regions 384a-384c. The series gate resistor 380 may be formed, for example, by depositing a conductive material having a higher resistivity than the conductive materials used to form the gate fingers 316, the drain contact 336, the source contact 362, etc. The series gate resistor 380 may be provided at any suitable vertical level of the transistor 300. In an exemplary embodiment, as can be seen or inferred from FIGS. 8 and 9A, the series gate resistor 380 may be formed at the same metallization level as the source contact 362, the drain contact 336, and the gate fingers 316. It will also be appreciated that the gate resistor 380 (or odd-mode resistor 390 discussed below) may be replaced with other lossy elements, such as, for example, a series inductor-capacitor circuit, that act as a functional equivalent to a resistor.

[0094] Rather than the distributed series gate resistors 380 included in transistors according to certain embodiments of the present invention, a single series gate resistor 80 may be provided between each gate pad 312 and its associated gate bus 314, as discussed below with reference to FIG. 12. When the series gate resistors are implemented as a single series gate resistor 80 between each gate pad 312 and its corresponding gate bus 314, each series gate resistor 80 may need to have a relatively high resistance value to reduce or prevent instability in the device. In the transistor 300, multiple series gate resistors 380 are placed between the gate splits 382 of the device. Each of the gate resistors 380 may have a much lower resistance value compared to the gate resistor 80 that would be required if only the gate resistor 80 were placed between the gate pad 312 and the gate bus 314.

[0095] In some embodiments, a series gate resistor 380 may be provided for each gate finger segment 316a, 316b, 316c, while in other embodiments, some gate finger segments may share a series gate resistor 380. In the particular embodiment depicted in FIG. 8, all of the gate finger segments 316b, 316c have their own associated series gate resistor 380, while the paired gate finger segment 316a shares a single series gate resistor 380. It will also be appreciated that in other embodiments, some of the gate finger segments 316a-316 may not have an associated gate resistor 380.

[0096] By distributing the series gate resistors at two or more locations along the gate finger 316, the feedback loops within the gate finger and drain of the transistor may gain sufficient losses to reduce or eliminate instability. This may improve device yield in the field and / or reduce the rate of device failure. Furthermore, as explained above and as seen in FIG. 8, the current path along any particular gate finger segment 316a, 316b, 316c need only pass through a single series gate resistor 380. Because the series gate resistor 380 may have a relatively small resistance, power losses are reduced and thus the transistor 300 may support higher gain levels for a given size device.

[0097] As seen in FIG. 8 , the transistor 300 includes a drain contact 336 extending in the y-direction along a first axis, a source contact 362 extending in the y-direction along a second axis parallel to the first axis, and a gate finger 316 extending between the source contact 362 and the drain contact 336. The gate finger 316 includes a plurality of collinear, discontinuous gate finger segments 316a, 316b, 316c electrically connected to one another. The transistor 300 further includes a plurality of spaced apart gate resistors 380 electrically connected to the gate fingers 316. Each gate resistor 380 may be coupled between a respective one of the gate finger segments 316a, 316b, 316c and a respective gate signal distribution bar 374. At least one of the gate resistors 380 is disposed between the first axis and the second axis. Gate jumpers 372 are inserted along the electrical paths between gate bus 314 and gate fingers 316. Gate jumpers 372 are inserted along the respective electrical paths between gate finger segments 316b and 316c and gate bus 314, and respective gate resistors 380 are inserted along the respective electrical paths between gate jumpers 372 and gate finger segments 316b, 316c.

[0098] 8, the transistor 300 includes a source contact 362 extending in the y-direction, a gate jumper 372 extending in the y-direction, and a gate finger 316 comprising a plurality of electrically connected discontinuous gate finger segments 316a, 316b, 316c. The transistor 300 further includes a plurality of spaced apart gate resistors 380. The gate finger segments 316b and 316c are connected to the gate jumper 372 through respective first and second gate resistors 380. The pair of gate finger segments 316a are connected to the gate bus 314 through respective gate resistors 380.

[0099] As further shown in FIG. 8, the transistor 300 also includes odd-mode resistors 390. The odd-mode resistors 390 are provided to break up the long odd-mode instability feedback loop in the device. In particular, as the number of gate fingers 316 provided by the gate jumpers 372 increases, instability may occur. For example, the transistor may be stable with four gate fingers 316 provided by the gate jumpers 372, and instability may begin when a gate jumper 372 providing eight gate fingers 316 is used. When instability occurs may be a function of the width of the gate fingers and the operating frequency of the device. The odd-mode resistors 390 may be inserted between adjacent gate signal distribution bars 374. When the transistor 300 operates normally, the voltage on both sides of each odd-mode resistor 390 should be the same and no current should flow between adjacent gate signal distribution bars 374.

[0100] The odd-mode resistor 390 may be disposed in the gap region 384 between adjacent gate splits 382. As shown in Figures 8 and 9B, the odd-mode resistor 390 may be implemented, for example, on the same metallization level as the gate signal distribution bar 374 and the source contact 362 and may be directly connected between two adjacent gate distribution bars 374. The odd-mode resistor 390 may also be inserted between adjacent gate buses 314.

[0101] Thus, the transistor 300 may include a number of gate fingers 316 extending in the y-direction and spaced apart from one another in the x-direction. Each of the gate fingers 316 may include a number of generally collinear, spaced apart gate finger segments 316a, 316b, 316c that are electrically connected to one another and disposed in respective gate splits 382a, 382b, 382c separated by gap regions 384b, 384c. An odd-mode resistor 390 is disposed in the gap region 384b, 384c. In an exemplary embodiment, the odd-mode resistor 390 may be interposed between adjacent gate signal distribution bars 374.

[0102] It will also be appreciated that in some embodiments, it is not necessary to segment the source contacts 362. In particular, both the gate resistors 380 and the odd-mode resistors may be implemented in the same metal layer as the gate signal distribution bars 374 and the gate jumpers 372. In such implementations, it is not necessary to segment the source contacts 362. Thus, it will be appreciated that in other embodiments, the resistors 380, 390 may be implemented directly on the source contacts 362, or on the top and sides of the source contacts 362, and each source contact 362 may be a single continuous (i.e., non-segmented) source contact 362.

[0103] It will be appreciated that although FIG. 8 depicts transistor 300 including segmented gate fingers 316 and segmented source contacts 362, embodiments of the invention are not so limited. For example, in other embodiments, drain contacts 336 may be segmented in a similar manner, such that each drain contact includes, for example, three separate segments. When drain contacts 336 are segmented, they may be electrically connected to each other, for example, by a drain contact plug and another metallization layer in the device. In embodiments where the drain contacts are segmented, source contacts 362 may or may not be segmented. Additionally, gate fingers 316 may be segmented as shown in FIG. 8 or may not be segmented as shown in FIG. 2 (as well as FIGS. 14-15). Segmenting the drain contacts may provide additional space in the region between the gate splits for gate resistor 380 and / or odd-mode resistor 390. As a simple example of such an embodiment having segmented drain contact 336, transistor 300 of Figure 8 may be modified such that 332, 334, and 336 are source pad, source bus, and source contact, respectively, and 362, 362a / 362b / 362c may be modified to be drain contact segments, and 364 to be a drain contact plug. In other words, Figure 8 may be viewed as an embodiment having segmented gate fingers 316 and segmented drain contact 362, simply by reversing the source and drain functions.

[0104] Figure 10 is a plan view of a larger version of transistor 300 of Figure 8. Figure 11 is a detailed plan view of a small portion 302 of transistor 300 of Figure 10.

[0105] 10 and 11, transistor 300 includes a plurality of unit cells extending in the vertical direction (y-direction). Each of the unit cells includes a gate finger 316 that extends across the entire width of the device and is subdivided into vertically (y-direction) arranged series unit cells 340a, 340b, 340c as described above. In the embodiment shown in FIGS. 10-11, each of the unit cells 340 has an overall width of 1120 microns, and the series unit cells 340a, 340b, and 340c have widths of 370 microns, 380 microns, and 370 microns, respectively, although the inventive concept is not limited to these particular dimensions.

[0106] A number of gate busses 314 are provided at one end of the structure, and a drain bus 334 is provided at the other end of the structure. Source pads 322 are provided on the sides of the structure and are connected to the source busses, for example, located in a lower metallization level of the device (not shown). Source contact segments 362a, 362b, 362c are connected to the source busses by source contact plugs 364.

[0107] The detailed view 302 of a portion of the device layout of transistor 300 in FIG. 11 also shows gate fingers 316 , gate jumpers 372 , gate signal distribution bars 374 , series gate resistors 380 and odd-mode resistors 390 .

[0108] A transistor according to an embodiment of the inventive concept may include a semiconductor structure that is a multi-layer structure. For example, the semiconductor structure 120 of the transistor 100 as discussed above with reference to FIG. 7 may include a substrate 200 (e.g., 4H-SiC or 6H-SiC) on which at least a channel layer 210 and a barrier layer 220 are formed. The same is true for other transistors according to embodiments of the inventive concept described herein. Thus, it should be recognized that the discussion of the semiconductor structure 120 of FIG. 7 applies to the semiconductor structures of each of the other embodiments described herein as well, although the metallization and other aspects of the device will vary based on the differences between the various embodiments depicted in the figures. Thus, for example, it will be recognized that all of the transistors described herein may include a silicon carbide substrate and III-nitride based channel and barrier layers, and the semiconductor structures of these transistors may operate in the manner described with reference to FIG. 7.

[0109] 12 is a plan view of a metal layout of a transistor 400 in accordance with a further embodiment of the inventive concept. Transistor 400 is similar to transistor 300 discussed above with reference to FIGS. 8-11, except that transistor 400 utilizes a series gate resistor 80 connected between each gate pad 312 and a respective gate bus 314 instead of the distributed series gate resistor 380 included in transistor 300. Other than this modification, the two transistors 300 and 400 can be essentially identical, so further discussion of transistor 400 is omitted.

[0110] Figure 13 is a plan view of a metal layout of a transistor 500 in accordance with a further embodiment of the inventive concept. Transistor 500 is similar to transistor 300 discussed above with reference to Figures 8-11, except that transistor 500 uses a single odd-mode resistor 90 between each pair of adjacent gate buses 314 and does not include the distributed odd-mode resistor 390 located in gap regions 384b, 384c of transistor 300 of Figure 8. Other than this modification, the two transistors 300 and 500 can be essentially identical, so further discussion of transistor 500 is omitted.

[0111] It will be appreciated that the features of the above-described embodiments may be combined in any manner to create multiple additional embodiments. For example, FIG. 14 is a plan view of a metal layout of a transistor 100' identical to transistor 100 described above, except modified to include series gate resistor 180, which may be identical to series gate resistor 380 of FIG. 8. As another example, FIG. 15 is a plan view of a metal layout of a transistor 300' similar to transistor 300 described above, except that gate fingers 316 are not segmented and the location of series gate resistor 380 has been modified accordingly. It will be appreciated that FIGS. 14 and 15 are provided to illustrate some possible combinations of the various embodiments to yield additional embodiments.

[0112] As discussed above, in some embodiments, source contacts 362 are not segmented, but rather are each implemented as a single continuous source contact 362. Figure 16 is a plan view of a metal layout of transistor 600 in accordance with an embodiment of the inventive concept including such a configuration. Transistor 600 is similar to transistor 300 discussed above with reference to Figures 8-11, and therefore the following description will focus on the differences between transistor 600 and transistor 300.

[0113] As shown in FIG. 16, each source contact 662 is implemented as a single continuous source contact 662 without segmentation. Thus, the y-direction length of each source contact 662 may be approximately the same as the y-direction length of each drain contact 336. Meanwhile, as discussed above, the segmented source contact segments 362a, 362b, 362c forming each source contact 362 of the transistor 300 are commonly connected to a source bus layer below the semiconductor layer structure 320 through a source via 364, and the electrical path connecting each source contact segment 362a, 362b, 362c to an adjacent source contact segment 362a, 362b, 362c may be relatively long, introducing parasitic inductance. As a result, the behavior of the transistor may be distorted, adversely affecting the performance, frequency response, and / or stability of the transistor, especially when operating near or above a "corner" frequency. Parasitic inductance can also make it difficult to accurately model transistor behavior, complicating the design process. The undesirable effects discussed above can be mitigated or eliminated by using a continuous, non-segmented source contact 662 on the top surface of the semiconductor layer structure 320, as shown in FIG.

[0114] Because the source contact 662 is continuous rather than segmented, there is less space between the gate splits for adding circuit elements. As a result, as shown in FIG. 16, the odd-mode resistor 390 in the gap 362g between the source contact segments 362a, 362b, 362c of the transistor 300 is omitted in the transistor 600. Similarly, the series gate resistor 380 for the second and third gate splits (i.e., the gate splits including the source contact segments 362b and 362c, respectively) in the transistor 300 of FIG. 8 is omitted in the transistor 600 and replaced with a plurality of series gate resistors 380a formed along the electrical path in the gate bus 314 to the respective gate jumpers 372. 16 shows the series gate resistor 380a formed in the gate bus 314, it will be appreciated that the series gate resistor 380a may be formed anywhere along the gate signal path between the gate bus 314 and the second or subsequent gate split. For example, in other embodiments, the gate resistors may be formed in conductive vias connecting the gate bus 314 to the gate signal distribution bar 374 (FIG. 17) or to the respective gate jumpers 372 inside the gate jumpers 372 (see FIG. 18).

[0115] In addition, in transistor 600, a gate jumper 372 is formed over every source contact 662, whereas in transistor 300, gate jumpers 372 are formed only over every other source contact 362. As a result, each gate jumper 372 in transistor 600 only provides two gate fingers 316, whereas the gate jumpers 372 in transistor 300 each provide four gate fingers 316. One possible advantage of each gate jumper 372 providing only two gate fingers 316 is that the gate signal distribution bar 374 does not need to cross the drain contact 336. This may simplify manufacturing and may also help reduce parasitic gate-to-drain capacitance. Furthermore, by adding the extra gate jumper 372, the length of the conductive path that each gate signal must traverse to reach the far end of each gate finger 316 may be the same, which was not the case in transistor 300 of FIGS. 8-11. The design of transistor 600 can help mitigate phase variation issues that arise based on differences in the length of the gate signal paths, which can result in a loss of gain and are therefore undesirable.

[0116] As discussed above with reference to FIG. 9A, in transistor 300, gate signal distribution bar 374 is formed in the same metal layer as gate jumper 372. Although not seen in the cross section of FIG. 9A, conductive vias 378 physically and electrically connect each gate signal distribution bar 374 to each segment of discontinuous gate finger 316, as discussed above with reference to FIGS. 8-11. These conductive vias 378 are shown in FIG. 16. The transistor 300 of FIG. 8 uses discontinuous source contacts 362, and therefore sufficient space for conductive vias 378 is provided in gaps 362g between adjacent source contact segments 362a, 362b, 362c. Transistor 600 does not have gaps 362g (because source contact 662 is continuous), and therefore there may not be space for conductive vias 378 that maintain sufficient tolerance between conductive vias 378 and other metallization, such as source contacts 662 and drain contacts 336. As a result, a notch may be formed in each source contact 662, where the source contact is narrower (i.e., smaller in the x-direction) than the remainder of the source contact 662. As a result, each source contact 662 may include two or more enlarged portions 662a, with adjacent enlarged portions 662a connected by intervening narrowed portions 662b. The provision of narrowed portions 662b creates additional space for conductive vias 378 that connect each gate distribution bar 374 to a respective gate finger segment 316a, 316b, 316c. The conductive vias 378 are disposed adjacent to the narrowed portions 662b of the source contacts 662. Thus, for each conductive via 378, a plane perpendicular to the longitudinal axis of its associated gate jumper 372 (i.e., a plane extending in the x-direction in FIG. 16 ) and perpendicular to the plane defined by the bottom surface of the semiconductor layer structure 320 (i.e., a plane extending in the z-direction in FIG. 16 ) extends through both the conductive via 378 and the narrowed portion 662 b of its associated source contact 662.

[0117] It will be appreciated that in other embodiments, the narrowed portion 662b of the source contact 662 may be omitted (eg, when there is sufficient space in the source contact 662 for the unnotched conductive via 378).

[0118] Thus, according to some embodiments of the present invention, as shown in Figure 16, a transistor 600 is provided that includes a semiconductor layer structure 320. A source contact 662, a drain contact 336, and a gate finger 316 disposed between the source contact 662 and the drain contact 336 are formed on an upper surface of the semiconductor layer structure 320. The transistor 600 further includes a gate jumper 372 disposed on the source contact 662 that is electrically connected to at least a portion of the gate finger 316. The source contact 662 extends continuously on the upper surface of the semiconductor layer structure 320 without any gaps dividing the source contact 662 into segments.

[0119] In some embodiments, the gate finger 316 comprises a plurality of discontinuous gate finger segments 316a, 316b, 316c. The transistor 600 may further comprise a gate bus 314, with at least one of the discontinuous gate finger segments 316a, 316b, 316c electrically connected to the gate bus 314 by a gate jumper 372. The source contact 662 may include at least a first enlarged portion 662a-1, a second enlarged portion 662a-2, and a narrowed portion 662b physically and electrically connecting the first enlarged portion 662a-1 to the second enlarged portion 662a-2. The first enlarged portion 662a-1 and the second enlarged portion 662a-2 may be wider than the narrowed portion 662b-1 in a direction perpendicular to a longitudinal axis of the source contact 662 and parallel to a bottom surface of the semiconductor layer structure 320 (i.e., the x-direction in FIG. 16 ).

[0120] The transistor 600 may further include a gate signal distribution bar 374 at the same height as the gate jumper 372 over the semiconductor layer structure 320. The gate signal distribution bar 374 may extend from the gate jumper 372 toward the gate finger 316 and may be interposed in an electrical path between the gate jumper 372 and at least a portion of the gate finger 316. The gate signal distribution bar 374 may be electrically connected to the gate finger 316 by a conductive via 378. A series gate resistor 380a may be interposed in an electrical path connecting the gate bus 314 to the gate signal distribution bar 374. Furthermore, the longitudinal axis of the source contact 662, the longitudinal axis of the drain contact 336, and the longitudinal axis of the gate finger 316 may each extend in a first direction (the y-direction in FIG. 16 ).

[0121] 16, according to a further embodiment of the present invention, a transistor is provided that includes a semiconductor layer structure 320, a source contact 662, a drain contact 336, and a gate finger 316 disposed between the source contact 662 and the drain contact 336, formed on an upper surface of the semiconductor layer structure 320. The source contact 662 includes a first enlarged portion 662a-1 and a second enlarged portion 662a-2 that are physically and electrically connected to each other by a narrowed portion 662b. The first enlarged portion 662a-1 and the second enlarged portion 662a-2 may be wider than the narrowed portion 662b in a direction perpendicular to a longitudinal axis of the source contact 662 and parallel to a lower surface of the semiconductor layer structure 320 (i.e., the x-direction). The transistor may further include a gate bus 314 and a gate jumper 372 electrically connected to the gate bus 314, and the gate jumper 372 may be disposed above the source contact 662. At least a portion of the gate fingers 316 may be electrically connected to the gate bus 314 through a gate jumper 372 .

[0122] 16, in accordance with a further embodiment of the present invention, a transistor is provided that includes a semiconductor layer structure 320, a source contact 662, a drain contact 336, and a gate finger 316 having a plurality of discontinuous gate finger segments 316a, 316b, 316c. The source contact 662, the drain contact 336, and the gate finger 316 each extend in a first direction (x-direction) on a top surface of the semiconductor layer structure 320, and the gate finger 316 is disposed between the source contact 662 and the drain contact 336. The transistor further includes a gate bus 314 and a gate jumper 372 electrically connected to the gate bus 314, the gate jumper 372 having a longitudinal axis overlying the source contact 662 and extending in the first direction. The transistor also includes a gate signal distribution bar 374 in the same metal layer as the gate jumper 372, the gate signal distribution bar 374 extending from the gate jumper 372 toward the first one of the discontinuous gate finger segments 316b.

[0123] 16 depicts transistor 600 including three gate splits, it will be appreciated that embodiments of the invention are not so limited. For example, in other embodiments, transistor 600 may include only two gate splits, or may include four or more gate splits.

[0124] FIG. 17 is a plan view of a metal layout of a transistor 600' that is a modified version of the transistor 600 of FIG. 16 in accordance with an embodiment of the inventive concept. The transistor 600' may be identical to the transistor 600 except that it includes series gate resistors 380 along all three gate splits and omits the series gate resistors 380a that were added to the transistor 600. In the embodiment of FIG. 17, the series gate resistors 380 are implemented in the gate signal distribution bar 374 similar to the embodiments depicted in FIGS. 14 and 15. In other embodiments, the series gate resistors 380 may instead be implemented within the gate finger segments 316b, 316c or within the conductive vias 378 that connect the gate signal distribution bar 374 to the gate finger segments 316b, 316c. Apart from this modification, the two transistors 600 and 600' may be essentially identical, and therefore further discussion of the transistor 600' is omitted.

[0125] FIG. 18 is a plan view of a metal layout of transistor 600″, which is another modified version of transistor 600 of FIG. 16 , in accordance with an embodiment of the inventive concept. Transistor 600″ may be identical to transistor 600, except that it includes series gate resistors 380b implemented along each gate jumper 372, and omits series gate resistors 380a that were added to transistor 600. Apart from this modification, the two transistors 600 and 600″ may be essentially identical, and therefore further discussion of transistor 600″ will be omitted.

[0126] FIG. 19 is a plan view of a metal layout of a transistor 700 in accordance with a further embodiment of the inventive concept. The transistor 700 is similar to the transistor 600 of FIG. 16, but includes several notable differences. First, the transistor 700 includes only two gate splits instead of the three included in the transistor 600. In addition, the transistor 700 includes a continuous gate finger 316 instead of the gate finger divided into discontinuous segments 316a, 316b, 316c in the transistor 600. Finally, the transistor 700 omits the direct connections between the gate bus 314 and the ends of adjacent gate fingers 316, whereas the transistor 600 includes the insertion of series gate resistors 380 along these direct connections. As a result, each gate finger 316 is centrally fed through one of the gate jumpers 372. This design may be advantageous because it further reduces phase variation in that it further reduces the phase difference between the gating signal applied to the center of each gating finger 316 and the gating signal applied to the end of each gating finger 316. This may result in increased gain.

[0127] 20 is a plan view of a metal layout of a transistor 800 in accordance with a further embodiment of the inventive concept. Transistor 800 is similar to transistor 600 of FIG. 16, except that the gate distribution bars 374 of transistor 800 are disposed at an angle of approximately 45° to the longitudinal axis of each gate jumper 372, rather than at a right angle as shown in other previously described embodiments. This approach may advantageously shorten the gate signal path. Any of the embodiments disclosed herein may be modified to have gate signal distribution bars 374 disposed at an angle other than 90° to the longitudinal axis of each gate jumper 372 (i.e., gate signal distribution bars 374 disposed at an oblique angle to the longitudinal axis of each gate jumper 372).

[0128] It will also be appreciated that in other embodiments, segmented source contacts, such as source contact 362 of transistor 300 in Figures 8-11, may be used, and individual electrical connections may be provided on the top surface of semiconductor layer structure 320 that electrically connect the discontinuous source contact segments 362a, 362b, 362c on the top surface of semiconductor layer structure 320. For example, the source connector segments may be implemented in the same metal layer as gate jumper 372 or in a different metal layer (higher or lower). These source connector segments may be electrically connected to the discontinuous source contact segments 362a, 362b, 362c through conductive vias.

[0129] Figure 21 is a plan view of a small portion of a metal layout of a transistor 900 including such a source connector segment. As shown in Figure 21, the transistor 900 includes a discontinuous source contact 362 including three source contact segments 362a, 362b, 362c. Source connector segments 963 are also implemented in a metal layer above the metal layer including the gate jumper 372 (i.e., higher than the semiconductor layer structure). Conductive vias 964 electrically connect each source connector segment 963 to the underlying source contact segments 362a, 362b, 362c.

[0130] In the embodiment shown in the previous figures, as previously described, the gate jumpers 372 are positioned to extend over the respective source contacts 362 / 662, however, the embodiments of the present invention are not so limited. FIG. 22 is a plan view of a metal layout of a transistor 1000 in accordance with a further embodiment of the inventive concept, in which the gate jumpers 372 extend over the drain contacts 336. It will be appreciated that each drain contact 336 extends to approximately the gate bus 314, however, only approximately 1 / 3 of each drain contact 336 is visible in FIG. 22 because most of each drain contact 336 is covered by the respective gate jumper 372. In the depicted embodiment, both the drain contacts 336 and the source contacts 1062 are implemented as continuous contacts without any notches formed therein. It will be appreciated that in other embodiments, source contact 1062 may be replaced with a discontinuous source contact, such as source contact 362 of FIG. 8, or a continuous source contact with a notch, such as source contact 662 of FIG.

[0131] Embodiments of the inventive concept may be particularly well suited for applications relating to III-nitride based high electron mobility transistor (HEMT) devices. As used herein, the term "III-nitrides" refers to semiconductor compounds formed between nitrogen and elements from group III of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to tertiary and quaternary compounds such as AlGaN and AlInGaN. All of these compounds have an empirical formula of one mole of nitrogen combined with one mole of the total group III elements.

[0132] Suitable structures for GaN-based HEMTs utilizing embodiments of the present invention are described, for example, in commonly assigned U.S. Patent Application Publication No. 2002 / 0066908A1, published June 6, 2002, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same," U.S. Patent Application Publication No. 2002 / 0167023A1, published November 14, 2002, entitled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer," and U.S. Patent Application Publication No. 2004 / 02366114, entitled "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact No. 7,906,799, issued Mar. 15, 2011, and entitled "Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess," and U.S. Pat. No. 6,316,793, issued Nov. 13, 2001, and entitled "Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates," the disclosures of which are hereby incorporated by reference in their entireties.

[0133] In particular embodiments of the present invention, the substrate 200 may be a semi-insulating silicon carbide (SiC) substrate, such as the 4H polytype of silicon carbide. Other possible silicon carbide polytypes include the 3C, 6H, and 15R polytypes.

[0134] Optional buffer, nucleation and / or transition layers (not shown) may be provided on the substrate 200 below the channel layer 210. For example, an AlN buffer layer may be included to provide a suitable crystal structure transition between the silicon carbide substrate and the remainder of the device. In addition, a strain balanced transition layer(s) may also be provided as described in commonly assigned U.S. Patent Application Publication No. 2003 / 0102482 A1, entitled "Strain Balanced Nitride Hetrojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors," published June 5, 2003, the disclosure of which is incorporated herein by reference as if fully set forth herein. Still further, one or more capping layers, such as a SiN capping layer, may be provided on the barrier layer 220.

[0135] Silicon carbide has a much closer crystal lattice match to III-nitrides than sapphire (Al2O3), a very common substrate material for III-nitride devices. The closer lattice match of SiC can result in higher quality III-nitride films than those commonly available on sapphire. Silicon carbide also has a very high thermal conductivity, so the total output power of III-nitride devices on silicon carbide is not typically limited by the heat dissipation of the substrate, as is the case for the same devices formed on sapphire. The availability of semi-insulating silicon carbide substrates can also result in reduced isolation and parasitic capacitance of the device. Suitable SiC substrates are manufactured, for example, by Cree Corporation of Durham, North Carolina, the assignee of the present invention.

[0136] Silicon carbide may be used as the substrate material, although embodiments of the invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP, etc. In some embodiments, a suitable buffer layer may also be formed.

[0137] In some embodiments of the present invention, the channel layer 210 is made of Al x Ga 1-x In the present embodiment, the channel layer 210 is a III-nitride such as GaN, GaN, AlGaN, or GaN. The channel layer 210 may be an InGaN or GaN-Nitride, such as GaN, ...

[0138] Channel layer 210 may have a bandgap smaller than the bandgap of barrier layer 220 and may have an electron affinity greater than the electron affinity of barrier layer 220. In certain embodiments of the inventive concepts, barrier layer 220 is AlN, AlInN, AlGaN, or AlInGaN and has a thickness between about 0.1 nm and about 10 nm. In certain embodiments of the inventive concepts, barrier layer 220 is sufficiently thick and has a sufficiently high Al composition and doping to induce a significant carrier concentration at the interface between channel layer 210 and barrier layer 220.

[0139] The barrier layer 220 may be a III-nitride having a larger bandgap than the channel layer 210 and a smaller electron affinity than the channel layer 210. Thus, in certain embodiments of the present invention, the barrier layer 220 may include AlGaN, AlInGaN, and / or AlN, or combinations of layers thereof. The barrier layer 220 may have a thickness of, for example, about 0.1 nm to about 30 nm. In certain embodiments of the present invention, the barrier layer 220 may be undoped or may be doped with an n-type dopant at a thickness of about 10 nm to about 30 nm. 19 cm -3 In some embodiments of the present invention, the barrier layer 220 is doped to a concentration of less than Al. x Ga 1-xIt is N, where 0 < x < 1. In a specific embodiment, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 220 includes AlGaN with an aluminum concentration of about 5% to about 100%. In a specific embodiment of the present invention, the aluminum concentration is higher than about 10%.

[0140] Embodiments of the present invention are described with reference to a GaN high electron mobility transistor (HEMT) structure, but the inventive concept is not limited to such devices. Thus, embodiments of the present invention may include other transistor devices having multiple unit cells and control electrodes. Embodiments of the present invention may be suitable for use in any semiconductor device where a wider control electrode is desirable and where multiple unit cells of the device exist. Thus, for example, embodiments of the present invention may be suitable for use in various types of devices such as MESFETs, MMICs, SITs, LDMOSs, BJTs, pHEMTs, etc., manufactured using SiC, GaN, GaAs, silicon, etc.

[0141] In this specification, terms such as first, second, etc. may be used to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element may also be referred to as the second element, and similarly, the second element may also be referred to as the first element. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0142] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprise", "comprising", "including" and / or "comprising", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0143] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. It will be further understood that the meaning of the terms used herein should be interpreted in accordance with the meaning in the context of the present specification and the related art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0144] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that the element can be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it will also be understood that the element can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0145] Relative terms such as "lower," "upper," "upper," "lower," "horizontal," "lateral," or "vertical" may be used herein to describe the relationship of one element, layer, or region shown in the figures to another element, layer, or region. It will be understood that these terms are intended to encompass other orientations of the device in addition to the orientation shown in the figures.

[0146] Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. In addition, variations from the shapes of the illustrations are expected as a result, for example, of production techniques and / or tolerances. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein which may include deviations in shapes that result, for example, from manufacturing.

[0147] In the drawings and specification, exemplary embodiments of the invention are disclosed and specific terms are employed, but they are used in a generic and descriptive sense only and not for the purpose of limiting the scope of the invention which is set forth in the following claims.

Claims

1. A semiconductor layer structure, a source contact extending in a first direction on an upper surface of the semiconductor layer structure, a drain contact extending in the first direction on the upper surface of the semiconductor layer structure, a gate finger extending in the first direction on the upper surface of the semiconductor layer structure, the gate finger being disposed between the source contact and the drain contact, and one of the source contact and the drain contact includes a first enlarged portion and a constricted portion on the upper surface of the semiconductor layer structure, a transistor device.

2. The transistor device according to claim 1, wherein the source contact includes the first enlarged portion and the constricted portion.

3. The transistor device according to claim 2, wherein the source contact further includes a second enlarged portion, and the first enlarged portion and the second enlarged portion are physically and electrically connected to each other by the constricted portion.

4. The transistor device according to claim 3, wherein the first and second enlarged portions are wider than the constricted portion in a direction perpendicular to a longitudinal axis of the source contact and parallel to a lower surface of the semiconductor layer structure.

5. The transistor device according to any one of claims 1 to 4, further comprising a gate bus and a gate jumper electrically connected to the gate bus, the gate jumper being disposed on the source contact, and at least a part of the gate finger being electrically connected to the gate bus through the gate jumper.

6. The transistor device according to claim 1, wherein the gate finger includes a plurality of discontinuous gate finger segments.

7. The transistor device according to claim 5, further comprising a gate signal distribution bar formed in the same metal layer as the gate jumper, the gate signal distribution bar extending from the gate jumper toward the gate finger.

8. The transistor device according to claim 7, wherein a plane perpendicular to a longitudinal axis of the gate jumper and a plane defined by a bottom surface of the semiconductor layer structure extends through both the constricted portion of the source contact and a conductive via.

9. The transistor device according to claim 7, further comprising a series gate resistor inserted in an electrical path connecting the gate bus to the gate signal distribution bar.

10. The transistor device according to claim 6, wherein a first gate finger segment of the discontinuous gate finger segments is electrically connected to the gate bus through a series gate resistor and is not electrically connected to the gate bus through the gate jumper.

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