COMPUTER PROCESSING APPARATUS WITH DYNAMIC SHARED CACHE LINE COPY RETENTION POLICY SELECTION - Patent application

Abstract

Systems and techniques for dynamic selection of a policy that determines whether a copy of a shared cache line within a processor core complex should be stored and maintained in a level 3 (L3) cache of the processor core complex, according to various embodiments, are based on one or more cache line sharing parameters or on counters that track L3 cache misses and cache-to-cache (C2C) transfers within the processor core complex. The shared cache line is shared between processor cores or threads. By comparing either the cache line sharing parameters or the counters to a corresponding threshold, a policy is set that defines whether a copy of the shared cache line at such index should be kept in the L3 cache.

Description

[Background technology]

[0001] A computing device, such as a central processing unit (CPU) or a graphics processing unit (GPU), typically includes multiple processor cores, each coupled to a hierarchy of caches for temporarily storing data for potential use by computer applications being executed by such computing device. Data stored in the caches of a given computing device is traditionally organized into cache lines, some of which are shared between two or more processing cores or threads of the computing device.

[0002] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief description of the drawings]

[0003] [Figure 1] 1 is a block diagram of a computer processing apparatus configured to selectively enable one or more policies for storing copies of shared cache lines in a level 3 (L3) cache, in accordance with some embodiments. [Diagram 2] FIG. 1 is a block diagram of a computer processing apparatus configured to implement a set-during mechanism for selectively enabling one or more policies for storing copies of shared cache lines in an L3 cache, in accordance with some embodiments. [Diagram 3] FIG. 1 is a flow diagram illustrating a method for selecting a shared cache line copy retention policy based on one or more cache line sharing parameters of a given core complex of a computer processing device, according to some embodiments. [Figure 4]FIG. 1 is a flow diagram illustrating a method for selecting a shared cache line copy retention policy according to a set-during mechanism implemented in a level 2 (L2) cache of a core complex of a computer processing device, according to some embodiments. [Diagram 5] FIG. 1 is a flow diagram illustrating a method for selecting a shared cache line copy retention policy according to a set-during mechanism implemented in an L3 cache of a core complex of a computer processing device, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] A computing device, such as a central processing unit (CPU) or a graphics processing unit (GPU), typically includes multiple processing cores (sometimes referred to herein as "cores"), each coupled to a hierarchical cache architecture including, for example, a level 1 (L1), a level 2 (L2), and a level 3 (L3) cache. In the cache architecture, each core is assigned at least one L1 cache and an L2 cache, and the L3 cache is shared among the multiple cores. In some cases, data stored in the cache architecture is shared among multiple cores or multiple threads, and each cache line of data that is shared between two or more cores or cache lines in this manner is referred to as a "shared cache line." In order to reduce the need to transfer shared cache lines between L2 caches associated with cores or threads that share the shared cache line, it may be desirable to keep a copy of such shared cache line in the L3 cache. For example, it may take less time to retrieve a cache line from the L3 cache than to perform a cache-to-cache (C2C) transfer between the L2 caches of different cores, thereby advantageously improving the performance of the computing device, and in some cases, advantageously reducing its power consumption by keeping a copy of the shared cache line in the L3 cache. However, storing a copy of a shared cache line in an L3 cache occupies space that could otherwise be used to increase the inherent cache line storage capacity of the L3 cache and impacts the cache hit rate of the L3 cache. Thus, the systems and techniques described herein relate to dynamic policy selection of whether a shared cache line copy should be kept in the L3 cache.

[0005] For example, according to various embodiments, a first policy causes shared cache line copies to be retained (e.g., stored and maintained) in the L3 cache and a second policy prevents shared cache line copies from being retained in the L3 cache, with either the first policy or the second policy being selected based on one or more cache line sharing parameters or based on a counter value together with a set-during mechanism. In some embodiments, such cache line sharing parameters include an amount of shared cache lines indicated in an L2 shadow tag maintained by the L3 cache (sometimes referred to herein as a “shadow tag-based cache line sharing parameter”) and an amount of shared cache lines indicated based on memory access requests issued by multiple cores for the same cache line (sometimes referred to herein as a “memory access request-based cache line sharing parameter”). In some embodiments, the set-during mechanism causes a first dedicated set of cache line indexes of the L2 or L3 cache to be allocated for use of the first policy and a second dedicated set of cache line indexes of the L2 or L3 cache to be allocated for use of the second policy. The value of the counter is updated, for example, based on observed L3 cache misses and C2C forwarding occurring in association with either the first dedicated set of cache line indexes or the second dedicated set of cache line indexes. The computer processing device then selects either the first policy or the second policy for the other set of cache line indexes (sometimes referred to as a "follower set") of the L2 or L3 cache based on the value of the counter relative to a predetermined threshold.

[0006] 1 illustrates a computer processing system 100 for dynamically selecting a policy for retaining shared cache line copies in an L3 cache. Computer processing system 100 is generally configured to execute a set of instructions organized in the form of a computer program to perform tasks on behalf of an electronic device. Thus, processing system 100 may be used in any of a variety of electronic devices, such as a desktop or laptop computer, a server, a smart phone, a tablet, a game console, etc.

[0007] As shown, the computer processing device 100 includes a core complex 122 having multiple cores 102, an L1 cache 104, an L2 cache 106, and a shared L3 cache 108. Each of the L1 cache 104, the L2 cache 106, the L3 cache 108, and the main memory 110 is generally a memory device configured to store data and may thus be a random access memory (RAM) memory module, a non-volatile memory device (e.g., flash memory), or the like, according to various embodiments. The core complex 122 is coupled to the main memory 110. Each core 102 is associated with the L1 cache 104 and the L2 cache 106. For example, the core 102-1 is coupled to the L1 cache 104-1, coupled to the L2 cache 106-1 via the L1 cache 104-1, and coupled to the L3 cache 108 via the L1 cache 104-1 and the L2 cache 106-1. Continuing with the example, L1 cache 104-1 and L2 cache 106-1 are configured to temporarily store data for only core 102-1, and L3 cache 108 is configured to temporarily store data for any of cores 102-1.

[0008] Cores 102 are configured to generate memory access requests, which represent requests to load or store data known to be used or required by programs being executed by one or more of cores 102. L1 cache 104, L2 cache 106, and L3 cache 108 each include a respective set of memory cells for storing data (i.e., a "cache memory"), and each include an individual cache controller configured to perform tasks such as copying data from main memory 110 or other caches to the cache memory, and attempting to fulfill memory access requests issued by cores 102 by searching in the cache memory for data requested in such memory access requests.

[0009] In some embodiments, computer processing device 100 includes several core complexes structurally similar to core complex 122, each coupled to main memory 110, and can transfer data between different core complexes as needed via a scalable input / output (I / O) fabric. In some embodiments, each core 102 can execute multiple threads simultaneously (e.g., 2, 4, 8, etc.), sometimes referred to as "simultaneous multithreading."

[0010] In some embodiments, the L3 cache 108 is configured to perform the function of a victim cache that stores cache lines evicted from the L2 cache 106. The L3 cache 108 attempts to satisfy a memory access request in response to an L2 cache miss in any of the L2 caches 106. Generally, the L3 cache attempts to satisfy a memory access request before passing the memory access request to a memory controller in the main memory 110. In some embodiments, the L3 cache 108 maintains a list of L2 shadow tags 112 that replicate L2 state and tag entries for every cache line index in each of the L2 caches 106. In response to an L2 miss or a cache probe from an external core complex, the L3 cache controller checks the L2 shadow tags 112, typically in parallel with checking cache lines stored in the L3 cache 108 itself, to determine whether the data requested in the corresponding memory access request is present in any of the L2 caches 106. By checking the L2 shadow tag 112 with the L3 cache 108 rather than performing a check in each L2 cache 106, strain on L2 cache bandwidth is reduced. For example, if a memory access request from core 102-1 misses in L2 cache 106-1 and L3 cache 108, and a check of the L2 shadow tag 112 indicates a hit in L2 cache 106-2, a cache controller associated with either or both of L2 cache 106-2 and L3 cache 108 initiates a cache-to-cache (C2C) transfer of the requested cache line from L2 cache 106-2 to L2 cache 106-1. Such a C2C transfer typically indicates that the requested cache line is a shared cache line (shared between core 102-1 and core 102-2 in this example). In some embodiments, the L2 cache line index state information included in the L2 shadow tag 112 indicates whether the cache line stored at a particular L2 cache line index in either L2 cache is in a shared state.

[0011] In some embodiments, core complex 122 includes logic, counters, or both for use in selecting a policy for storing and maintaining shared cache line copies (sometimes referred to herein as a “shared cache line copy retention policy”), including either sharing detection logic 114, set-during module 116, or performance monitor 120.

[0012] In a first example, the sharing detection logic 114 monitors one or more cache line sharing parameters 115 and sets a shared cache line retention policy based on whether a given cache line sharing parameter 115 exceeds a corresponding threshold. According to various embodiments, the sharing detection logic 114 is implemented in each of the L2 caches 106, only the L3 cache 108, or each of the L2 caches 106 and the L3 caches 108. In some embodiments, the cache line sharing parameters 115 include either or both of a shadow tag-based cache line sharing parameter (i.e., the number of shared cache lines indicated in the L2 shadow tags 112 maintained by the L3 cache 108) and a memory access request-based cache line sharing parameter (i.e., the number of shared cache lines indicated based on memory access requests issued by multiple cores 102 for the same cache line). In some embodiments, each cache line sharing parameter 115 is calculated over a predetermined period of time and based on relevant data collected during that period. In some embodiments, the period is defined by a rolling window, and each cache line sharing parameter is updated continuously or periodically as the relevant data contained within the window changes.

[0013] In some embodiments in which cache line sharing parameters 115 include only a shadow tag-based cache line sharing parameter, the value of this parameter is determined based on L2 shadow tags 112 over a predetermined time period (e.g., defined by a rolling window) and compared to a predetermined cache line sharing threshold to select a shared cache line copy retention policy. In some embodiments, sharing detection logic 114 calculates the shadow tag-based cache line sharing parameter by determining the number of cache lines in each of the L2 caches 106 that are in a shared state based on the L2 cache line index state information included in L2 shadow tags 112 and setting the shadow tag-based cache line sharing parameter equal to the determined number. In some embodiments, sharing detection logic 114 calculates the shadow tag-based cache line sharing parameter by analyzing L2 shadow tags 112 to determine the number of individual cache lines stored in two or more L2 caches 106 (indicating that such cache lines are shared among multiple cores) and setting the shadow tag-based cache line sharing parameter equal to the determined number. If the shadow tag-based cache line sharing parameter value exceeds a predetermined cache line sharing threshold, indicating a relatively high amount of cache line sharing in the core complex 122, the sharing detection logic 114 causes a cache controller associated with either or both of the L2 cache 106 and the L3 cache 108 to set a first shared cache line copy retention policy to cause a copy of the shared cache line from the L2 cache 106 to be retained in the L3 cache 108.Otherwise, if the shadow tag-based cache line sharing parameter value does not exceed the predetermined cache line sharing threshold, indicating a relatively small amount of cache line sharing in the core complex 122, the sharing detection logic 114 causes the cache controller to set a second shared cache line copy retention policy to prevent shared cache line copies from being retained in the L3 cache 108 (and, in some cases, this causes such copies already stored in the L3 cache 108 to be evicted from the L3 cache 108).

[0014] In some embodiments, the first shared cache line copy retention policy configures the L3 cache 108 to retain a copy of the shared cache line when transferring the shared cache line from one L2 cache 106 to another L2 cache 106 (i.e., during a C2C transfer) or when processing a victim cache line that has been evicted from either L2 cache 106 and also has a copy in another L2 cache 106. In contrast, the second shared cache line copy retention policy configures the L3 cache 108 to prevent retaining a copy of the shared cache line in the L3 cache 108 in such scenarios. The first shared cache line copy retention policy typically improves performance of the computer processing device 100 when a copy of the shared cache line stored in the L3 cache 108 is requested by another core 102 in the core complex 122 (i.e., a core 102 not associated with the L2 cache 106 to which the shared cache line was copied) or a core of an external core complex. This is because L3 cache 108 can satisfy such requests from a copy of the shared cache line more quickly than if the original shared cache line had to be obtained from its L2 cache 106. The second shared cache line copy retention policy typically improves performance of computer processing device 100 when cache line sharing between cores is infrequent (e.g., when single core workloads or independent workloads that do not require cache line sharing are being processed) because storage capacity in L3 cache 108 that would otherwise be allocated to storing shared cache line copies is instead made available to store more unique cache lines, generally resulting in a higher cache hit rate across L2 cache 106 and L3 cache 108.

[0015] In some embodiments where cache line sharing parameters 115 include only a memory access request-based cache line sharing parameter, the value of this parameter is determined based on memory access requests, cache probes, or both during a predetermined time period (e.g., defined by a rolling window) and then compared to a predetermined cache line sharing threshold to select a shared cache line copy retention policy. In some embodiments, sharing detection logic 114 determines the memory access request-based cache line sharing parameter value by monitoring memory access requests issued by cores 102 and incrementing the memory access request-based cache line sharing parameter value for each cache line of L2 cache 106 requested by two or more cores of core 102 (e.g., within a predetermined time period). In some embodiments, sharing detection logic 114 is configured to increment the memory access request-based cache line sharing parameter value in response to determining that a cache probe from an external core complex is requesting a cache line stored in any of L2 caches 106, to effectively make the cache line a shared cache line (in this case shared between cores of different core complexes). In some embodiments, only cache probes that are non-invalidating and leave a shared copy of the cache line at core complex 120 are considered when calculating the memory access request-based cache line sharing parameter. If the memory access request-based cache line sharing parameter value exceeds a predefined cache line sharing threshold, indicating a relatively large amount of cache line sharing at core complex 122, sharing detection logic 114 causes the cache controller to set a first shared cache line copy retention policy, as described above. Alternatively, if the memory access request-based cache line sharing parameter value does not exceed a predefined cache line sharing threshold, indicating a relatively small amount of cache line sharing at core complex 122, sharing detection logic 114 causes the cache controller to set a second shared cache line copy retention policy, as described above.

[0016] In some embodiments where cache line sharing parameters 115 used as a basis for selecting a shared cache line copy retention policy is a collection of multiple cache line sharing parameters, sharing detection logic 114 calculates an average (possibly a weighted average) of the shadow tag-based cache line sharing parameter values ​​and the memory access request-based cache line sharing parameter values ​​and then compares the average to a predefined cache line sharing threshold. If the average exceeds the predefined cache line sharing threshold, indicating a relatively high amount of cache line sharing at core complex 122, sharing detection logic 114 causes the cache controller to set the first shared cache line copy retention policy described above. Otherwise, if the average does not exceed the predefined cache line sharing threshold, indicating a relatively low amount of cache line sharing at core complex 122, sharing detection logic 114 causes the cache controller to set the second shared cache line copy retention policy described above.

[0017] In some embodiments, rather than determining a cache line sharing parameter 115 for the entire core complex 122 and having the cache controller set all of the shared cache line copy retention policies for the L3 cache 108 and the L2 cache 106, the sharing detection logic 114 is configured to determine a different cache line sharing parameter 115 for each of the cores 102 or each of the threads executing in each of the cores 102, and to selectively set the shared cache line copy retention policy to retain a shared cache line copy of the shared cache line in a given L2 cache 106 in the L3 cache 108 based on a comparison of the cache line sharing parameter 115 of the corresponding core 102 or corresponding thread to a predetermined threshold. For example, if the first cache line sharing parameter 115 for core 102-1 and the second cache line sharing parameter 115 for core 102-2 each exceed their respective cache line sharing thresholds, and the third cache line sharing parameter 115 for core 102-3 and the fourth cache line sharing parameter 115 for core 102-4 each do not exceed their respective cache line sharing thresholds, then the sharing detection logic 114 may responsively instruct the cache controller to use the first shared cache line copy retention policy. 108) and configures the cache controller to use a second shared cache line copy retention policy (preventing copies of shared cache lines in L2 caches 106-3 and 106-4 from being retained in the L3 cache 108, and possibly evicting existing copies of such shared cache lines from the L3 cache 108). In some embodiments, the first shared cache line copy retention policy causes all shared cache lines in the L2 cache 106 to be copied (e.g., in bulk) to the L3 cache 108 upon selection and implementation of the policy.In some embodiments, the first shared cache line copy retention policy causes the L3 cache 108 to store a copy of the shared cache line in the L2 cache 106 when such a shared cache line is introduced into the L3 cache 108 as part of another process (e.g., when the shared cache line passes through the L3 cache 108 during a C2C transfer or when the shared cache line is evicted from one of the L2 caches 106 to the L3 cache 108).

[0018] In a second example, the computer processing device implements a set-dueing mechanism with set-dueing module 116 for dynamic selection of a shared cache line copy retention policy. According to various embodiments, the set-dueing mechanism is implemented by set-dueing module 116 for either one or more of L3 cache 108 or L2 cache 106. As used herein, "set-dueing" refers to a technique in which a cache controller (e.g., associated with either or both of L2 cache 106 and L3 cache 108) allocates a first set of cache line indexes (sometimes referred to herein as a "first dedicated set") to be used with a first policy, allocates a second set of cache line indexes (sometimes referred to herein as a "second dedicated set") to be used with a second policy, and allocates a set of all other cache line indexes not included in the first and second dedicated sets (sometimes referred to herein as a "follower set") to be used with either the first policy or the second policy based on one or more counters (counter 118 in this example).

[0019] In some embodiments, the performance monitor 120 is configured to separately detect and track occurrences of each of the L3 cache misses or C2C transfers for each of the first and second dedicated sets. In some embodiments, the set-during module 116 maintains a single counter 118 that is incremented each time an L3 cache miss or C2C transfer is detected by the performance monitor 120 for any cache line index in the first dedicated set and that is decremented each time an L3 cache miss or C2C transfer is detected by the performance monitor 120 for any cache line index in the second dedicated set. As used herein, an "L3 cache miss" refers to an instance in which a cache controller attempting to fulfill a memory access request is unable to find the requested data (e.g., in the corresponding cache line) in the L3 cache. According to various embodiments, the amount by which the counter is incremented or decremented is different for L3 cache misses compared to the amount of C2C transfers, effectively weighting L3 cache misses and C2C transfers differently. The set-during module 116 then compares the value of the counter 118 to a counter threshold. In response to determining that the value of counter 118 exceeds the counter threshold, set-during module 116 configures the cache controller to cause L3 cache 108 to use a first policy with the follower set. In response to determining that the value of counter 118 does not exceed the counter threshold, set-during module 116 configures the cache controller to cause L3 cache 108 to use a second policy with the follower set. In some embodiments, the first policy is the first shared cache line copy retention policy described above, and the second policy is the second shared cache line copy retention policy described above.

[0020] For embodiments in which the set-during mechanism is implemented in the L2 cache 106, the one or more cache controllers allocate a first dedicated set of L2 cache lines in the L2 cache 106 for use in combination with a first shared cache line copy retention policy that causes shared cache line copies (corresponding to shared cache lines in the L2 cache 106 using the policy) to be retained in the L3 cache 108, and allocate a second dedicated set of L2 cache line indexes in the L2 cache 106 for use in combination with a second shared cache line copy retention policy that prevents shared cache line copies (corresponding to shared cache lines in the L2 cache 106 using the policy) from being retained in the L3 cache 108. In some embodiments, separate set-during mechanisms are implemented for each of the L2 caches 106, while in other embodiments a single set-during mechanism is implemented to allocate the first and second dedicated sets and follower sets across some or all of the L2 caches 106.

[0021] The counter 118 is incremented or decremented by the set-during module 116 based on L3 cache misses and C2C forwardings detected by the performance monitor 120 resulting from memory access requests to shared cache lines of the first dedicated set or from memory access requests to shared cache lines of the second dedicated set, respectively. The set-during module 116 periodically compares the value of the counter 118 to a counter threshold. In response to determining that the value of the counter 118 exceeds the counter threshold, the set-during module 116 configures the one or more cache controllers to cause the L3 cache 108 to use a first shared cache line copy retention policy for the follower set of the L2 cache 106. In response to determining that the value of the counter 118 does not exceed the counter threshold, the set-during module 116 configures the one or more cache controllers to cause the L3 cache 108 to use a second shared cache line copy retention policy for the follower set of the L2 cache 106.

[0022] For embodiments in which the set-during mechanism is implemented in the L3 cache 108, the one or more cache controllers allocate a first dedicated set of L3 cache line indexes for the L3 cache 108 for use in conjunction with a first shared cache line copy retention policy that causes shared cache line copies to be retained in the L3 cache 108, and allocate a second dedicated set of L3 cache line indexes for the L3 cache 108 for use in conjunction with a second shared cache line copy retention policy that prevents shared cache line copies from being retained in the L3 cache 108. For example, the first shared cache line copy retention policy causes the first dedicated set of L3 cache line indexes to hold copies of shared cache lines stored in the L2 cache 106 or the L1 cache 104, and the second shared cache line copy retention policy prevents the second dedicated set of L3 cache line indexes from holding copies of shared cache lines stored in the L2 cache 106 or the L1 cache 104.

[0023] The counter 118 is incremented or decremented based on L3 cache misses and C2C forwardings detected by the set-during module 116 for each of the first or second dedicated sets. The set-during module 116 periodically compares the value of the counter 118 to a counter threshold. In response to determining that the value of the counter 118 exceeds the counter threshold, the set-during module 116 configures the one or more cache controllers to cause the L3 cache 108 to use a first shared cache line copy retention policy for the follower set of the L3 cache 108. In response to determining that the value of the counter 118 does not exceed the counter threshold, the set-during module 116 configures the one or more cache controllers to cause the L3 cache 108 to use a second shared cache line copy retention policy for the follower set of the L3 cache 108.

[0024] 2 illustrates a computer processing device 200 (e.g., one embodiment of computer processing device 100 of FIG. 1) that dynamically selects a shared cache line copy policy for an L3 cache using a set-during mechanism, according to some embodiments. Computer processing device 200 is generally configured to execute a set of instructions organized in the form of a computer program to perform tasks on behalf of an electronic device. Thus, computer processing device 200 may be used in any of a variety of electronic devices, such as desktop or laptop computers, servers, smartphones, tablets, game consoles, etc.

[0025] Computer processing device 200 includes cores 202 (i.e., processor cores), cache controller 205, L2 cache 206, and L3 cache 208. In some embodiments, computer processing device 200 includes multiple cores 202, cache controller 205, and L2 cache 206, although it should be understood that only one of each of these components is shown in the present example. In some embodiments, each module of computer processing device 200 is formed on the same semiconductor die, and main memory 210 is formed on a different semiconductor die and is connected to computer processing device 200 via one or more buses or signal lines. In some embodiments, at least a portion of main memory 210 is formed on the same semiconductor die as the modules of computer processing device 200.

[0026] Cache controller 205 is generally a module configured to manage the memory hierarchy of computer processing device 200 by moving data between L2 cache 206, L3 cache 208, and main memory 210. In particular, L2 cache 206 and L3 cache 208 are memory devices each including multiple entries, with each entry associated with one or more addresses in main memory 210. In response to a memory access request, cache controller 205 reviews data stored in one or more entries of L2 cache 206 to determine whether any of the entries store data associated with the memory address targeted by the memory access request. If so, cache controller 105 indicates a cache hit and satisfies the memory access request in the identified entry by either storing the data in the entry (in the case of a store operation) or by providing the data in the identified entry to processor core 202 (in the case of a load operation).

[0027] If the data associated with the memory address is not stored in an entry of the L2 cache 206, the cache controller 205 indicates a cache miss and issues a request to the L3 cache 208. In response to the memory access request, the cache controller 205 (or in some embodiments, another cache controller associated with the L3 cache 208) reviews the data stored in one or more entries of the L3 cache 208 to determine whether any of the entries store data associated with the memory address that is the subject of the memory access request. If so, the cache controller 205 indicates a cache hit and satisfies the memory access request in the identified entry by either storing the data in the entry (in the case of a store operation) or by providing the data of the identified entry to the L2 cache 206, from which the data is then provided to the processor core 202 (in the case of a load operation). If the data associated with the memory address is not stored in an entry of the L3 cache 208, the cache controller 205 indicates a cache miss and requests the data of the memory address from the main memory 210. Upon receiving data from main memory 210, cache controller 205 stores the data in an entry in L3 cache 208, from where it is transferred to L2 cache 206, which then provides the data to processor core 202 to fulfill memory access requests.

[0028] In the example of FIG. 2, the L2 cache 206 includes three regions, namely, private sets 224 and 226 (corresponding to respective test regions) and a follower set 228 (corresponding to a non-test region). The cache controller 205 also stores first and second shared cache line copy retention policies 211, 213 that differ in at least one aspect, such as whether or not a copy of a shared cache line in the L2 cache 206 is retained in the L3 cache 208. Thus, in the example of FIG. 2, the first shared cache line copy retention policy 211 mandates that a shared cache line copy from the L2 cache 206 is retained in the L3 cache 208. In contrast, the second shared cache line copy retention policy 213 mandates that a shared cache line copy from the L2 cache 206 is not retained in the L3 cache 208. The first shared cache line copy retention policy 211 generally improves the performance of the computer processing device 200 because if shared cache lines in the L2 cache 206 are requested more frequently by cores associated with other L2 caches or cores in an external core complex, the L3 cache 208 can process such requests more quickly if a copy of the requested cache line is stored therein. The second shared cache line copy retention policy 212 provides more space in the L3 cache 208 to store unique cache lines, which typically improves the cache hit ratio of a cache hierarchy that includes the L3 cache 208. The rate at which shared cache lines in the L2 cache 206 are requested by other cores typically varies over time, and as a result, the cache 110 operates more efficiently under different forwarding policies at different times. The first dedicated set 224 is allocated for use in combination with the first shared cache line copy retention policy 211, and the second dedicated set 226 is allocated for use in combination with the second shared cache line copy retention policy 213.For the follower set 228, the cache controller 205 selects the shared cache line copy retention policy 211, 213 depending on the performance characteristics of the first dedicated set 224 and the second dedicated set 226 (e.g., the L3 cache miss rate and the number of C2C transfers corresponding to memory access requests associated with each set).

[0029] Illustratively, the computing device 200 includes a performance monitor 220 (e.g., one embodiment of the set-during module 120 of FIG. 1 ) that monitors and records performance characteristics, such as L3 cache miss rate and number of C2C transfers, for each of the first dedicated set 224 and the second dedicated set 226. The cache controller 205 selects one of the shared cache line copy retention policies 211 and 213 to apply to the follower set 228 based on one or more or a combination of the performance characteristics of the first dedicated set 224 and the second dedicated set 226. For example, each time an L3 cache miss is detected by the performance monitor 220 of the first dedicated set 224, the set-during module 216 increases the value of the counter 218 by a first amount, each time an L3 cache miss is detected by the performance monitor 220 of the second dedicated set 226, the set-during module 216 decreases the value of the counter 218 by the first amount, each time a C2C transfer is detected by the performance monitor 220 of the first dedicated set 224, the set-during module 216 increases the value of the counter 218 by a second amount, and each time a C2C transfer is detected by the performance monitor 220 of the second dedicated set 226, the set-during module 216 decreases the value of the counter 218 by the second amount. In some embodiments, the follower set 228 includes a majority of the entries of the L2 cache 206. In this manner, cache controller 205 improves the overall efficiency of L2 cache 206 and L3 cache 208 by selecting the shared cache line copy retention policy for L2 cache 206 and L3 cache 208 as the policy shown to be most efficient based on the performance characteristics detected by performance monitor 220. Furthermore, as the performance characteristics of first and second private sets 224 and 226 change over time, the cache controller changes the shared cache line copy policy to a policy (e.g., first shared cache line copy retention policy 211 and second shared cache line copy retention policy 213) that is more efficient for a given set of performance characteristics.

[0030] In the example of FIG. 2, the implemented set-during mechanism allocates first and second dedicated sets 224 and 226 and follower set 228 within L2 cache 206, although it should be understood that according to various other embodiments, the set-during mechanism may instead be implemented within L3 cache 208 or across multiple L2 caches (e.g., an embodiment of L2 cache 106 of FIG. 1).

[0031] 3 illustrates a method 300 for dynamically selecting a shared cache line copy retention policy based on one or more cache line sharing parameters of a given core complex of a computing processing device. For ease of illustration, method 300 is described with respect to the exemplary embodiment of computing processing device 100 and its constituent components of FIG. 1. In some embodiments, an embodiment of computing processing device 100 performs method 300, at least in part, by executing computer readable instructions in one or more of cores 102 and cache controllers of L2 cache 106 and L3 cache 108.

[0032] In block 302, the sharing detection logic 114 determines one or more cache line sharing parameter values ​​(e.g., values ​​corresponding to some embodiments of the cache line sharing parameters 115) during operation of the computer processing device 100. In some embodiments, the sharing detection logic 114 monitors memory access requests issued by the cores 102 to determine a memory access request-based cache line sharing parameter value. For example, if the sharing detection logic 114 determines that a given cache line is requested within memory access requests issued by more than one core 102 during a given time period, the given cache line is identified as a shared cache line, and the sharing detection logic 114 increments the memory access request-based cache line sharing parameter value accordingly. In some embodiments, the sharing detection logic 114 increments the memory access request-based cache line sharing parameter value in response to determining that a cache probe originating from another core complex is requesting a cache line stored in any of the L2 caches 106 to indicate that the requested cache line is a shared cache line and that such requests can be satisfied more quickly if a copy of the shared cache line is stored in the L3 cache 108. In some embodiments, the sharing detection logic 114 checks the L2 shadow tags 112 to determine a shadow tag-based cache line sharing parameter value. For example, the sharing detection logic 114 sets the shadow tag-based cache line sharing parameter value equal to a number of L2 cache lines that are indicated to be shared by multiple cores 102 based on state or tag information included in the L2 shadow tags 112. According to various embodiments, the determined cache line sharing parameter value is either a shadow tag-based cache line sharing parameter, a memory access request-based cache line sharing parameter, or an aggregate cache line sharing parameter (e.g., an average of the shadow tag-based cache line sharing parameter value and the memory access request-based cache line sharing parameter value).

[0033] At block 304, the sharing detection logic 114 compares the determined cache line sharing parameter value to a cache line sharing threshold. In some embodiments, the cache line sharing parameter value corresponds to a memory access request-based cache line sharing parameter value that represents a number of shared cache lines determined based on an amount of memory access requests, cache probes, or both that target shared cache lines in the core complex 120, and the cache line sharing threshold corresponds to a threshold number of such memory access requests, cache probes, or both. In some embodiments, the cache line sharing parameter value corresponds to a shadow tag-based cache line sharing parameter value that represents an amount of shared cache lines represented in L2 shadow tags 112 of the L3 cache 108, and the cache line sharing threshold corresponds to a threshold number of such shared cache lines. A determination that the cacheline sharing threshold exceeds the cacheline sharing parameter value indicates a high incidence of cacheline sharing among multiple cores 102 of core complex 120 (or, in some cases, cores outside of core complex 120), such that implementation of a policy (e.g., a first shared cacheline copy retention policy) that maintains shared cacheline copies in L3 cache 108 improves performance of computer processing device 100. If sharing detection logic 114 determines that the cacheline sharing parameter value exceeds the cacheline sharing threshold, method 300 proceeds to block 306. If sharing detection logic 114 determines that the cacheline sharing parameter value does not exceed the cacheline sharing threshold, method 300 proceeds to block 308.

[0034] In response to determining that the cacheline sharing parameter value exceeds the cacheline sharing threshold at block 306, the sharing detection logic 114 subjects the L3 cache 108 to a first policy (e.g., a first shared cacheline retention policy) whereby the L3 cache 108 retains a copy of the shared cacheline (corresponding to the shared cacheline in the L2 cache 106) in the L3 cache 108. In some embodiments, a cache controller associated with the L3 cache 108 sets the first policy in response to receiving an indication from the sharing detection logic 114 that the cache sharing threshold has been exceeded by the cacheline sharing parameter value.

[0035] In response to determining at block 308 that the cacheline sharing threshold has not been exceeded by the cacheline sharing parameter value, the sharing detection logic 114 causes the L3 cache 108 to follow a second policy (e.g., a second shared cacheline retention policy) that prevents the L3 cache 108 from retaining a shared cacheline copy (corresponding to the shared cacheline in the L2 cache 106) in the L3 cache 108. In some embodiments, a cache controller associated with the L3 cache 108 sets the second policy in response to receiving an indication from the sharing detection logic 114 that the cache sharing threshold has not been exceeded by the cacheline sharing parameter value. Note that the second policy does not prevent the L3 cache 108 from temporarily storing a copy of the shared cacheline, for example when servicing a C2C transfer, but instead prevents the L3 cache 108 from storing a copy of the shared cacheline that is already stored in one or more of the L2 cache 106 or the L1 cache 104.

[0036] 4 illustrates a method 400 for dynamically selecting a shared cache line copy retention policy according to a set-during mechanism implemented in one or more L2 caches of a core complex of a computer processing device. For ease of illustration, the method 400 is described with respect to an exemplary embodiment of computer processing device 100 and its constituent components of FIG. 1. However, it should be understood that the method 400 is performed in some embodiments using one or more embodiments of computer processing device 200 of FIG. 2. In some embodiments, an embodiment of computer processing device 100 performs method 400, at least in part, by executing computer-readable instructions in one or more of core 102 and cache controllers of L2 cache 106 and L3 cache 108.

[0037] In block 402, the set-during module 116 causes one or more cache controllers associated with the L2 cache 106 to assign L2 cache line indexes of the first dedicated set for use in conjunction with a first policy (e.g., a first shared cache line retention policy) pursuant to which shared cache line copies originating from the first dedicated set are retained in the L3 cache 108.

[0038] In block 404, the set-during module 116 causes one or more cache controllers to allocate a second dedicated set of L2 cache line indexes for use in conjunction with a second policy (e.g., a second shared cache line retention policy) pursuant to which a shared cache line copy originating from the second dedicated set is not retained in the L3 cache 108.

[0039] At block 406, the performance monitor 120 detects L3 cache misses and C2C transfers associated with the first dedicated set of L2 cache line indexes, and separately detects the L3 cache misses and C2C transfers associated with the first dedicated set of L2 cache line indexes, and the set-during module 116 tracks these events using the counters 118. For example, the set-during module 116 increments the counter by a first amount for each detected L3 cache miss associated with a memory access request to a cache line in the first dedicated set, increments the counter by a second amount for each detected C2C transfer associated with a memory access request to a cache line in the first dedicated set, decrements the counter by a first amount for each detected L3 cache miss associated with a memory access request to a cache line in the second dedicated set, and decrements the counter by a second amount for each detected C2C transfer associated with a memory access request to a cache line in the second dedicated set. In some embodiments, the first amount and the second amount are the same. In some embodiments, the second amount is greater than the first amount, which effectively weights C2C transfers higher than L3 cache misses in terms of their respective impact on the value of the counter. In some alternative embodiments, the set-during logic uses a first counter of counters 118 to track L3 cache misses and C2C transfers associated with a first dedicated set and a second counter of counters 118 to track L3 cache misses and C2C transfers associated with a second dedicated set.

[0040] At block 408, the set-during module 116 compares the counter value to a counter threshold. If the counter value exceeds the counter threshold, the method 400 proceeds to block 410. If the counter value does not exceed the counter threshold, the method 400 proceeds to block 412.

[0041] At block 410, the set-during module 116 causes the L3 cache 108 to use a first policy for the follower set of the L2 cache line index, the first policy causing the L3 cache 108 to retain shared cache line copies resulting from the follower set. In some embodiments, a cache controller associated with the L3 cache 108 sets the first policy for the follower set in response to receiving an indication from the set-during module 116 that a counter threshold has been exceeded by a counter value.

[0042] At block 412, the set-during module 116 causes the L3 cache 108 to use a second policy for the follower set of the L2 cache line index, the second policy preventing shared cache line copies resulting from the follower set from being retained in the L3 cache 108. In some embodiments, a cache controller associated with the L3 cache 108 sets the second policy for the follower set in response to receiving an indication from the set-during module 116 that the counter threshold has not been exceeded by the counter value.

[0043] 5 illustrates a method 500 for dynamically selecting a shared cache line copy retention policy according to a set-during mechanism implemented in one or more L2 caches of a core complex of a computer processing device. For ease of illustration, method 500 is described with respect to an exemplary embodiment of computer processing device 100 and its constituent components of FIG. 1. However, it should be understood that method 500 is performed in some embodiments using one or more embodiments of computer processing device 200 of FIG. 2. In some embodiments, an embodiment of computer processing device 100 performs method 500, at least in part, by executing computer-readable instructions in one or more of core 102 and cache controllers of L2 cache 106 and L3 cache 108.

[0044] In block 502, the set-during module 116 causes a cache controller associated with the L3 cache 108 to allocate a first dedicated set of L3 cache line indexes for use in conjunction with a first policy (e.g., a first shared cache line retention policy) that causes shared cache line copies originating from the L2 cache 106 to be retained in a first dedicated set of L3 cache line indexes in the L3 cache 108.

[0045] In block 504, the set-during module 116 causes the cache controller to allocate a second dedicated set of L3 cache line indexes for use in conjunction with a second policy (e.g., a second shared cache line retention policy) whereby shared cache line copies originating from the L2 cache 106 are not retained in a second dedicated set of L3 cache line indexes in the L3 cache 108.

[0046] At block 506, the performance monitor 120 detects L3 cache misses and C2C transfers associated with the first dedicated set of L3 cache line indexes, and separately detects the L3 cache misses and C2C transfers associated with the first dedicated set of L3 cache line indexes, and the set-during module tracks these events using the counters 118. For example, the set-during module 116 increments the counter by a first amount for each detected L3 cache miss associated with a memory access request to a cache line in the first dedicated set, increments the counter by a second amount for each detected C2C transfer associated with a memory access request to a cache line in the first dedicated set, decrements the counter by the first amount for each detected L3 cache miss associated with a memory access request to a cache line in the second dedicated set, and decrements the counter by a second amount for each detected C2C transfer associated with a memory access request to a cache line in the second dedicated set. In some embodiments, the first amount and the second amount are the same. In some embodiments, the second amount is greater than the first amount, which effectively weights C2C transfers higher than L3 cache misses in terms of their respective impact on the value of the counter. In some alternative embodiments, the set-during logic uses a first counter of counters 118 to track L3 cache misses and C2C transfers associated with a first dedicated set and a second counter of counters 118 to track L3 cache misses and C2C transfers associated with a second dedicated set.

[0047] At block 508, the set-during module 116 compares the counter value to a counter threshold. If the counter value exceeds the counter threshold, the method 500 proceeds to block 510. If the counter value does not exceed the counter threshold, the method 500 proceeds to block 512.

[0048] At block 510, the set-during module 116 causes the L3 cache 108 to use a first policy for the follower set of the L3 cache line index, the first policy causing the shared cache line copy originating from the L2 cache 106 to be maintained in the follower set of the L3 cache line index in the L3 cache 108. In some embodiments, a cache controller associated with the L3 cache 108 sets the first policy for the follower set in response to receiving an indication from the set-during module 116 that the counter threshold has been exceeded by the counter value.

[0049] At block 512, the set-during module 116 causes the L3 cache 108 to use a second policy for the follower set of the L3 cache line index, the second policy preventing a shared cache line copy originating from the L2 cache 106 from being held in the follower set of the L3 cache line index in the L3 cache 108. In some embodiments, a cache controller associated with the L3 cache 108 sets the second policy for the follower set in response to receiving an indication from the set-during module 116 that the counter threshold has not been exceeded by the counter value.

[0050] As disclosed herein, in some embodiments, a method includes determining a cacheline sharing parameter indicative of an amount of shared cachelines in a plurality of caches of a computer processing device, and setting a shared cacheline copy retention policy for a cache coupled to the plurality of caches based on the cacheline sharing parameter. In one aspect, determining the cacheline sharing parameter includes identifying a cacheline requested by two or more cores as a first shared cacheline based on a memory access request issued by a core of the computer processing device, and determining the cacheline sharing parameter based at least in part on the first shared cacheline. In another aspect, determining the cacheline sharing parameter further includes identifying a cacheline of the plurality of caches requested in the cache probe as a second shared cacheline based on a cache probe issued by a core of an outer core complex, the cacheline sharing parameter being determined further based on the second shared cacheline. In yet another aspect, determining the cacheline sharing parameter includes determining the cacheline sharing parameter based on a number of shared cachelines indicated in a shadow tag stored in the cache, the shadow tag providing a list of all cachelines in the plurality of caches.

[0051] In one aspect, the method includes determining a cacheline sharing parameter including identifying a cacheline requested by two or more cores as a first shared cacheline based on memory access requests issued by the cores of the computer processing apparatus, determining a first cacheline sharing parameter based at least in part on the first shared cacheline, determining a second cacheline sharing parameter based on a number of shared cachelines indicated in shadow tags stored in the cache, the shadow tags providing a list of all cachelines in the multiple caches, and determining the cacheline sharing parameter as an average of the first cacheline sharing parameter and the second cacheline sharing parameter. In another aspect, a shared cacheline copy retention policy for a cache determines whether copies of a shared cacheline of the multiple caches are retained in the cache.

[0052] In some embodiments, the method includes implementing set-during in a core complex of a computer processing device to select a shared cache line copy retention policy for the set of the first level cache and the second level cache. In one aspect, implementing the set-during includes assigning a first dedicated set of cache line indexes for use in conjunction with the first shared cache line copy retention policy, assigning a second dedicated set of cache line indexes for use in conjunction with the second shared cache line copy retention policy, using a counter to separately track cache misses associated with the second level cache and cache-to-cache (C2C) transfers associated with each of the first and second dedicated sets, and configuring the second level cache to use either the first shared cache line copy retention policy or the second first shared cache line copy retention policy for one or more follower sets of the cache line indexes based on the counter. In another aspect, the first dedicated set of cache line indexes, the second dedicated set of cache line indexes, and the one or more follower sets of cache line indexes are cache line indexes of the set of the first level cache of the core complex. In yet another aspect, the first dedicated set of cache line indexes, the second dedicated set of cache line indexes, and the one or more follower sets of cache line indexes are cache line indexes of a second level cache. In yet another aspect, the first shared cache line copy retention policy causes the second level cache to retain copies of shared cache lines of the set of the first level cache of the core complex, and the second shared cache line copy retention policy causes the second level cache to not retain copies of shared cache lines of the set of the first level cache.

[0053] In some embodiments, a computer processing apparatus includes a set of a first level cache and a second level cache coupled to the set of first level caches, the computer processing apparatus configured to dynamically select a shared cache line copy retention policy that determines whether a shared cache line of at least one cache of the set of first level caches is retained in the second level cache. In one aspect, the computer processing apparatus includes sharing detection logic configured to determine a cache line sharing parameter indicative of an amount of shared cache lines in at least one cache of the set of first level caches, the second level cache configured to dynamically select a shared cache line copy retention policy based on the cache line sharing parameter. In another aspect, a computer processing apparatus according to the claims includes a plurality of processor cores coupled to the set of first level caches, the sharing detection logic configured to identify a cache line of at least one cache of the set of first level caches requested by two or more cores as being a first shared cache line based on a memory access request issued by any of the plurality of processor cores, and to determine a cache line sharing parameter based at least in part on the amount of the first shared cache line.

[0054] In one aspect, the sharing detection logic is configured to determine the cache line sharing parameter based on a number of shared cache lines indicated in a shadow tag stored in the second level cache, the shadow tag providing a list of all cache lines in the set of the first level cache. In another aspect, the computer processing apparatus includes a set-during module configured to implement a set-during mechanism within the computer processing apparatus, and the second level cache is configured to dynamically select a shared cache line copy retention policy based on a counter associated with the set-during mechanism.

[0055] In one aspect, the set-during module is configured to allocate a first dedicated set of cache line indexes for use in conjunction with the first shared cache line copy retention policy and allocate a second dedicated set of cache line indexes for use in conjunction with the second shared cache line copy retention index policy, and to track cache misses associated with the second level cache and cache-to-cache (C2C) transfers associated with each of the first and second dedicated sets using counters separately, and the second level cache is configured to select one of the first shared cache line copy retention policy and the second first shared cache line copy retention policy to be used for the one or more follower sets of the cache line indexes based on the counters. In another aspect, the first dedicated set of cache line indexes, the second dedicated set of cache line indexes, and the one or more follower sets of cache line indexes are cache line indexes of at least one of the sets of the first level cache. In yet another aspect, the first dedicated set of cache line indexes, the second dedicated set of cache line indexes, and the one or more follower sets of cache line indexes are cache line indexes of a second level cache. In yet another aspect, the first shared cache line copy retention policy causes the second level cache to retain a copy of the shared cache line in at least one of the set of the first level cache, and the second shared cache line copy retention policy causes the second level cache to not retain a copy of the shared cache line in at least one of the set of the first level cache.

[0056] In some embodiments, the above-described apparatus and techniques are implemented in a system that includes one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the computer processing device 100 described above with reference to FIG. 1. Electronic design automation (EDA) and computer aided design (CAD) software tools can be used in the design and manufacture of these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs include code executable by the computer system to operate the computer system to operate on code representing circuits of one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system for manufacturing the circuits. This code may include instructions, data, or a combination of instructions and data. The software instructions representing the design or manufacturing tools are typically stored in a computer readable storage medium accessible to the computing system. Similarly, code representing one or more stages of the design or manufacture of the IC devices is stored in and accessed from the same computer readable storage medium or a different computer readable storage medium.

[0057] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS) based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0058] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied in a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by the one or more processors, operate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as a flash memory, a cache, a random access memory (RAM), or other non-volatile memory device(s), etc. The executable instructions stored in the non-transitory computer-readable storage medium may be implemented as source code, assembly language code, object code, or other form of instructions that can be interpreted or otherwise executed by one or more processors.

[0059] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, some of the specific activities or devices may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Thus, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0060] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and features by which any benefit, advantage, or solution may occur or be manifested are not to be construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, as the disclosed invention may be modified and practiced in different but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as set forth in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. 1. A method comprising: determining a cache line sharing parameter indicative of an amount of shared cache lines in a plurality of first level caches of the computer processing unit; and setting a shared cache line copy retention policy of a second level cache coupled to the plurality of caches based on the cache line sharing parameters. method.

2. Determining the cache line sharing parameters includes: identifying a cache line requested by two or more cores as a first shared cache line based on memory access requests issued by the cores of the computer processing device; determining the cache line sharing parameters based at least in part on the first shared cache line; 10. The method of claim 1.

3. Determining the cache line sharing parameters includes: and identifying, based on a cache probe issued by a core of an outer core complex, a cache line of the plurality of caches requested in the cache probe as a second shared cache line, wherein the cache line sharing parameters are determined based on the second shared cache line. The method of claim 2.

4. Determining the cache line sharing parameters includes: determining the cache line sharing parameter based on a number of shared cache lines indicated in shadow tags stored in the second level cache, the shadow tags providing a list of all cache lines in the plurality of caches; 10. The method of claim 1.

5. Determining the cache line sharing parameters includes: identifying a cache line requested by two or more cores as a first shared cache line based on memory access requests issued by the cores of the computer processing device; determining a first cache line sharing parameter based at least in part on the first shared cache line; determining a second cache line sharing parameter based on a number of shared cache lines indicated in shadow tags stored in the second level cache, the shadow tags providing a list of all cache lines in the plurality of caches; determining the cache line sharing parameter as an average of the first cache line sharing parameter and the second cache line sharing parameter.

10. The method of claim 1.

6. a shared cache line copy retention policy of the second level cache that determines whether copies of shared cache lines of the plurality of caches are retained in the second level cache; The method of any one of claims 1 to 5.

7. 1. A computer processing device comprising: a set of first level caches; a second level cache coupled to the set of first level caches, wherein the computer processing device is configured to dynamically select a shared cache line copy retention policy that determines whether shared cache lines of at least one cache in the set of first level caches are retained in the second level cache; Computer processing unit.

8. sharing detection logic configured to determine a cache line sharing parameter indicating an amount of shared cache lines in at least one of the set of first level caches, the second level cache being configured to dynamically select the shared cache line copy retention policy based on the cache line sharing parameter; The computer processing device of claim 7.

9. a plurality of processor cores coupled to the set of first level caches; The sharing detection logic: identifying a cache line of at least one cache of the set of first level caches requested by two or more cores as a first shared cache line based on a memory access request issued by any of the plurality of processor cores; determining the cache line sharing parameter based at least in part on the amount of the first shared cache line; configured to: The computer processing device of claim 8.

10. the sharing detection logic is configured to determine the cache line sharing parameter based on a number of shared cache lines indicated in shadow tags stored in the second level cache; the shadow tag provides a list of all cache lines in the set of first level caches; The computer processing device of claim 9.

11. a set-during module configured to implement a set-during mechanism on the computer processing device, wherein the second level cache is configured to dynamically select the shared cache line copy retention policy based on a counter associated with the set-during mechanism; The computer processing device of claim 7.

12. The set-during module Allocating a first dedicated set of cache line indexes for use in conjunction with a first shared cache line copy retention policy; allocating a second dedicated set of cache line indexes for use in conjunction with a second shared cache line copy retention policy; using the counters to separately track cache misses associated with the second level cache and cache-to-cache (C2C) transfers associated with each of the first and second dedicated sets, wherein the second level cache is configured to select one of the first shared cache line copy retention policy and a second shared cache line copy retention policy for use for one or more follower sets of a cache line index based on the counters; configured to: The computer processing device of claim 11.

13. the first dedicated set of cache line indexes, the second dedicated set of cache line indexes, and the one or more follower sets of cache line indexes are cache line indexes of at least one cache of the set of first level caches; The computer processing device of claim 12.

14. the first dedicated set of cache line indexes, the second dedicated set of cache line indexes, and the one or more follower sets of cache line indexes are cache line indexes of the second level cache. The computer processing device of claim 12.

15. the first shared cache line copy retention policy causes the second level cache to retain a copy of the shared cache line in at least one cache in the set of first level caches, and the second shared cache line copy retention policy causes the second level cache not to retain a copy of the shared cache line in at least one cache in the set of first level caches; The computer processing device of claim 12.

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