Systems and methods for using multiple entangled linear qubit arrays for quantum computing

Abstract

A quantum computing (QC) system includes a plurality of qubits arranged in a plurality of substantially linear regions having longitudinal axes that are substantially parallel to one another, at least a portion of the substantially linear regions including two or more qubits, one or more qubits in each substantially linear region configured to interact with one or more qubits in at least one other substantially linear region.

Description

Detailed Description of the Invention

[0001] [background] [Field] This application relates generally to quantum computing (QC), and more particularly to quantum computer architectures that utilize lattice array structures in two or more dimensions.

[0002] [Description of Related Art] The technological paths towards scalable quantum computing are diversifying. Performance, as demonstrated by various figures of merit, varies widely depending on the type of physical quantum bits (also called "qubits") employed in each approach. Approaches based on either trapped ions or superconducting qubits have consistently led the field for over two decades.

[0003] [overview] In certain embodiments, a quantum computing (QC) system is provided. The system comprises a plurality of qubits arranged in a plurality of substantially linear regions having longitudinal axes that are substantially parallel to one another. At least a portion of the substantially linear regions comprise two or more qubits, and one or more qubits in each substantially linear region are configured to interact with one or more qubits in at least one other substantially linear region.

[0004] Certain embodiments disclosed herein provide quantum computer architectures that utilize two or more dimensional lattice array structures to implement and interconnect quantum gates that can simultaneously entangle three or more logical qubits (e.g., each logical qubit includes one or more physical qubits). Certain embodiments disclosed herein provide quantum microprocessor configurations and gate array design platforms for quantum processing chips, similar to field programmable gate arrays (FPGAs), that can advantageously provide a degree of reconfigurability. Certain embodiments disclosed herein provide quantum microprocessor configurations and gate array design platforms for quantum processing chips or substrates (e.g., electrical and / or optical circuits), similar to application specific integrated circuits (ASICs), that can advantageously be optimized for a particular application and that can advantageously provide custom design flexibility.

[0005] Certain embodiments disclosed herein comprise a lattice structure comprising a plurality of fully connected qubits arranged as an array of three-dimensional (3D) lattice structures (e.g., cells), where the qubits arranged in a geometric layout enable simultaneous multi-qubit gate operations. For example, certain embodiments may be configured as a plurality of one-dimensional (1D) (e.g., linear) qubit arrays (e.g., rows, columns, lattices, chains) that are substantially parallel to one another. In such examples, the array of cells may be analogized to or referred to as a 3D crystal structure. Although various embodiments are described herein as utilizing trapped ion (e.g., charged atom) qubits (e.g., in a microchip structure) to illustrate the nature of the quantum interactions that are utilized (e.g., optimized), other embodiments may use one or more alternative qubit technologies (e.g., uncharged, Rydberg atom qubits, superconducting qubits) without loss of generality.

[0006] Certain embodiments disclosed herein provide a quantum computing (QC) system comprising a plurality of qubits substantially arranged in a plurality of linear arrays that are substantially parallel to one another, at least a portion of the linear arrays comprising two or more qubits, one or more qubits of each linear array configured to directly interact (e.g., be directly entangled) with one or more qubits of at least one adjacent linear array. For example, the QC system can comprise a multi-qubit gate array comprising a plurality of qubits arranged as a plurality of multi-qubit gates located in a region between two or more substrates. The qubits of the multi-qubit gate array can comprise a surface electrode trap configured to contain ions (e.g., charged atoms, charged molecules) at or near a surface of at least one of the substrates, and can be substantially arranged in a plurality of linear arrays, at least a portion of the qubits of at least one linear array configured to interact (e.g., be quantum mechanically entangled) with at least a portion of the qubits of at least one other (e.g., adjacent) linear array.

[0007] [Brief description of the drawings] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments described herein and, together with the description, explain these embodiments. [Brief description of the drawings]

[0008] [Figure 1A-1B] 1A-1B are schematic side and side views, respectively, of an exemplary QC system comprising multiple qubits arranged in multiple substantially linear regions in accordance with certain embodiments described herein. [Figure 1C] FIG. 1C illustrates a schematic side view of another exemplary QC system 100' comprising multiple qubits 105' arranged in multiple substantially linear regions in accordance with certain embodiments described herein. [Figure 2A-2B] 2A-2B are schematic illustrations of exploded perspective and side views, respectively, of an exemplary triangular prism array in accordance with certain embodiments described herein. [Fig. 2C-2D] 2C-2D are schematic diagrams illustrating assembled perspective and side views, respectively, of an exemplary triangular prism array according to certain embodiments described herein. [Figure 2E] FIG. 2E illustrates generally four linear chains of coupled qubits of the exemplary triangular prism array of FIGS. 2A-2D in accordance with certain embodiments described herein. [Figure 3A-3B] FIG. 3A generally illustrates an exploded perspective view of an exemplary cubic prism array according to certain embodiments described herein, and FIG. 3B generally illustrates an assembled perspective view of an exemplary cubic prism array according to certain embodiments described herein. [Figure 3C] FIG. 3C illustrates a schematic diagram of an assembled perspective view of an exemplary cube prism array in accordance with certain embodiments described herein. [Figure 4A-4B] 4A-4B generally illustrate perspective views of an exemplary hexagonal pillar array in accordance with certain embodiments described herein. [Figure 4C] FIG. 4C illustrates a schematic cross-sectional view of an exemplary hexagonal prism array having a plurality of single logical qubits, each of which comprises a single physical qubit in a central linear region, and a plurality of single logical qubits, each of which comprises a single physical qubit in an outer linear region, in accordance with certain embodiments described herein. [Figure 4D] FIG. 4D illustrates a schematic cross-sectional view of an exemplary hexagonal prism array having a plurality of single logical qubits, each comprising a cluster of six physical qubits in a central linear region, and a plurality of single logical qubits, each comprising a single physical qubit in an outer linear region, in accordance with certain embodiments described herein. [Figure 5A] FIG. 5A illustrates a schematic diagram of an exemplary system comprising at least one hexagonal pillar array having an exemplary QC structure according to certain embodiments described herein. [Figure 5B] FIG. 5B illustrates a schematic diagram of an exemplary system comprising at least one hexagonal pillar array having an exemplary QC structure according to certain embodiments described herein. [Figure 5C] FIG. 5C illustrates a schematic diagram of an exemplary system comprising at least one hexagonal pillar array having an exemplary QC structure according to certain embodiments described herein. [Figure 5D] FIG. 5D illustrates a schematic diagram of an exemplary system comprising at least one hexagonal pillar array having an exemplary QC structure according to certain embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Overview] Certain embodiments of the quantum computing (QC) systems described herein advantageously provide a multi-dimensional architecture to allow an optimal number of qubits to be entangled simultaneously between nearest and second nearest neighbors. Certain embodiments include electrical and optical access channels for addressing, control, detection, and readout as required to design a scalable quantum processor. An array of fully connected qubits provides more efficient and flexible options for executing quantum algorithms in hardware than designs where entangled gate operations are limited to specific pairs due to the type of qubits utilized or their layout. This improved efficiency and flexibility grows exponentially with the number of qubits in the array. By adding the ability to perform gate operations involving three or more qubits at a time, efficiency gains can be accelerated significantly over designs limited to one-qubit and two-qubit gates, replacing dozens of those qubit gates with a single four-qubit gate. Certain implementations described herein use multiple qubit arrays (e.g., multiple directly connected planar and / or linear arrays) to advantageously avoid problems with one- and two-dimensional geometry (e.g., connectivity limitations, gate spacing can be significantly increased, crowding of electrodes required to control each qubit within a gate). In certain implementations, multidimensional cells of qubits are formed that resemble crystals such as pyrochlore. In certain implementations, the multidimensional cells of qubits are reconfigurable and can be formed into a variety of crystal structures where nearest and second nearest qubits (e.g., within a cell, across multiple cells, across multiple layers) are entangled accordingly for selected gate operations. Utilizing many qubits to participate per gate can also reduce circuit depth, error correction and interference mitigation requirements. Interchangeable component cells can enable quantum FPGA (QFPGA) and ASIC (QASIC) layouts (e.g., chips).

[0010] Certain embodiments of the QC systems described herein include a multi-layer structure with multiple fully connected qubits arranged as an array of three-dimensional (3D) lattice structures (e.g., cells), where the qubits are arranged in a geometric layout to enable simultaneous multi-qubit gate operations. For example, multiple linear qubit arrays (e.g., rows, columns, lattices, chains) can be substantially parallel to one another to form an array of 3D cells that resembles or can be referred to as a crystal structure. In certain embodiments, qubits may be suspended (e.g., trapped) above and below (or above and below, left and right, etc.) or equivalently within multiple co-aligned qubit-containing zones (e.g., parallel opposed atomic trap arrays) to enable optimal coherent connections (e.g., entanglement) directly between nearest neighbor qubits, second nearest neighbor qubits, etc. across multiple array regions without requiring in situ processing, lossy conversion of qubits to other types or data bits or inefficient photonic or other interconnects that entail significant time delays (e.g., qubit swapping, quantum teleportation). Certain such embodiments utilize geometrically symmetric cell structures that provide the ability to perform gate operations involving more than two qubits at a time, which can accelerate efficiency gains significantly over designs limited to one-qubit and two-qubit gates. Certain multidimensional implementations may be composed of multiple one-dimensional (1D) qubit lattice arrangements (e.g., linear lattices, columns, chains) that are substantially parallel to one another and aligned together (e.g., arranged about a common longitudinal axis) to form a three-dimensional (3D) array, where each qubit is configured to be able to directly interact (e.g., be quantum mechanically entangled) with at least a portion of the qubits in more than one dimension (e.g., be fully connected in more than one dimension simultaneously).

[0011] Although various embodiments according to the physics of trapped ion (e.g., charged atoms) qubit techniques are described herein, other qubit techniques (e.g., uncharged, Rydberg atoms, superconducting qubits) may also be used in accordance with certain implementations described herein without loss of generality.

[0012] Certain embodiments of the QC system described herein include a plurality of multi-qubit three-dimensional (3D) gate cells, each cell including at least three qubits that can be fully connected simultaneously across three dimensions, and a plurality of multi-qubit cells configured for gate operations of two or more of the multi-qubit gates. The QC system of certain such embodiments can include a plurality of co-aligned qubit-containing zones, such as parallel opposing ion trap arrays, that enable optimal coherent connection or entanglement directly between nearest neighbor qubits, second nearest neighbor qubits, etc. across multiple array regions without requiring photonic or other interconnects. The multi-qubit cells can be configured using geometric symmetries to allow the multi-qubit gates to be natively performed in one gate operation without relying on the concatenation of multiple one- and two-qubit gates. By exploiting the symmetry of equilateral coupling distances between multiple qubits in the cell, it is possible to perform gate operations with more than two entangled qubits at a time that would otherwise require many more qubit gate operations involving only one- and two-qubit gates.

[0013] Certain embodiments of the QC system disclosed herein comprise a plurality of qubits arranged substantially in a plurality of linear arrays that are aligned together substantially parallel to one another, at least a portion of the linear arrays comprising two or more qubits, one or more qubits of each linear array configured to directly interact with one or more qubits of at least one adjacent linear array. The QC system may comprise a multi-qubit gate array comprising a plurality of qubits arranged as a plurality of multi-qubit gates positioned within a region between two or more 1D lattice-arranged layers (e.g., linear traps, substrates) that are aligned together about a common longitudinal axis as sides / edges of a geometric prism (e.g., triangular prism, cube, pentagonal prism, hexagonal prism, heptagonal prism, octagonal prism, etc.). For example, the qubits of a multi-qubit gate array can include electrode traps configured to contain ions at or near the surface of a substrate or trapping region (see, e.g., Stick, D. et al., "Ion Trap in a Semiconductor Chip," Nature Phys 2, 36-39 (2006); Maunz, P., "Characterization of a High-Optical-Access surface trap optimized for quantum information processing," online charts (2015)), and a plurality of these substrates or trapping regions can be arranged substantially in a plurality of linear arrays, with at least a portion of the qubits of at least one linear array configured to interact (e.g., be quantum mechanically entangled) with at least a portion of the qubits of at least one other (e.g., adjacent) linear array.

[0014] Certain embodiments disclosed herein provide a QC system comprising a plurality of qubits substantially arranged in a plurality of atomic trapping regions (e.g., 1D traps, linear surface traps) that are substantially parallel to one another, and the QC system can further comprise a multi-qubit 3D gate array comprising a plurality of qubits arranged as a plurality of multi-qubit gates positioned in regions between and / or within the trapping regions. For example, the qubits of the multi-qubit gate array can comprise a 1D trap array configured to contain atomic qubits including ions (e.g., charged atoms, charged molecules), neutral atoms (e.g., uncharged atoms, Rydberg states), or other qubit species. In the example of atomic qubits, atoms are trapped in potential wells, which may be created at or near a surface of at least one of the trapping regions or lattices and may be arranged substantially in a plurality of substantially parallel trap array regions, with at least a portion of the qubits in at least one 1D trap array layer configured to directly interact (e.g., be quantum mechanically entangled) with at least a portion of the qubits in at least one other (e.g., adjacent) substantially parallel trap array region.

[0015] In each of the embodiments of the QC system described herein, a symmetric or equilateral coupling arrangement of multiple qubits per cell may allow more complex quantum gates to be implemented in a single gate operation, additionally reducing the circuit depth, error correction and interference mitigation requirements. Interchangeable component cells may enable quantum FPGA (QFPGA) and ASIC (QASIC) layouts (e.g., chips) that can be highly reconfigurable.

[0016] Certain embodiments of the QC systems described herein advantageously provide a three-dimensional (3D) layout of qubits and / or qubit gates that facilitate more qubits and / or qubit gates being used in a computation than are provided using a one-dimensional (1D) layout. For example, certain embodiments described herein provide a 3D layout of qubit gates, each containing multiple ions (e.g., three or more simultaneously entangled ions), while providing sufficient spacing and line-of-sight access angles to facilitate electrical connections and optical paths for addressing, manipulating, controlling, readout, and possibly sideband cooling of each qubit.

[0017] A particular arrangement or set of qubits allows any qubit to be directly quantum mechanically entangled with any other qubit in the set, and these qubits can be described as being "fully connected." Furthermore, a small number of qubits, including fully connected ions in a one-dimensional linear ion trap, can demonstrate potential processing powers that are clearly greater than would be possible with the same number of qubits that are only pairwise connected (see, for example, NM Linke et al., "Experimental comparison of two quantum computing architectures," PNAS, Vol. 114, no.13 (2017)).

[0018] Quantum computing (QC) designs demonstrated over the past two decades have shown that the parameter that most influences how quickly quantum computers will outperform their classical counterparts is not simply based on the number of qubits wired together in some fashion. This is exemplified by the greater interest in circuit-model QC hardware, which often has fewer than the 100 qubits claimed by leading quantum annealing techniques that do not perform single gate operations. The demonstrated performance of such systems comes down to qubit fidelity (e.g., the precision with which the system can perform gate operations), the way the qubits are interconnected, and the amount of overhead used to enable the qubits to cooperate to compute solutions to difficult problems.

[0019] One-qubit gates simply involve flipping the qubit itself from “0” to “1” or a special quantum superposition of “0” and “1”. Two-qubit gates connect two qubits using superposition combined with quantum entanglement so that anything done to one of them affects the other. In such two-qubit gates, the target qubit may start in state “0” or state “1” and can be in any superposition of “0” and “1” (e.g., intermediate between “0” and “1”). For example, the function of a quantum controlled NOT (CNOT) gate is to flip the target qubit if the control qubit is in state “1” and do nothing otherwise. One- or two-qubit gates can be implemented straightforwardly in many different quantum gate-based architectures. For more complex gate operations, implementations that can entangle more than two qubits at a time can have a significant impact on the total number of qubits and the total number of steps taken to execute the operations and algorithms that incorporate them (see, for example, C. Figgatt et al., “Parallel entangling operations on a universal ion-trap quantum computer,” Nature, Vol. 571 (2019); Y. Lu et al., “Global entangling gates on arbitrary qubits,” Nature, Vol. 571 (2019)). The obvious reduction in the number of qubits and steps used up front can, in some cases, result in a dramatic reduction in the overhead to achieve a successful result. One example is a prototype demonstration that can provide solutions to otherwise intractable problems with fewer attendant costs, even in terms of time, without significant error correction.

[0020] Certain implementations described herein use multiple fully connected, high fidelity qubits. The advantage of such certain implementations (e.g., how much more efficient a particular quantum gate operation can be as opposed to using a combination of one and two qubit gates) is illustrated in the exemplary quantum triple-controlled NOT (C) with four fully connected, high fidelity qubits. 3 This can be illustrated by considering the C NOT gate. 3 The NOT gate is also called the super-Toffoli gate. 3 In a NOT gate, all three control qubits must be in a specified state (e.g., "1, 1, 1") to flip the fourth target qubit from "1" to "0". When combined with one or more single-qubit gate operations, such multi-qubit quantum gates can be used to complete a universal set for quantum computing. Multiply controlled NOT gates are generally described in the literature as including an extended series of one- and two-qubit gate operations (see, for example, MA Nielsen and IL Chuang, "Quantum Computing and Quantum Information," 1st ed. (Cambridge Univ. Press, 2000)). The extent to which these one- and two-qubit gate series are even more extensive in physical implementations depends on the type of qubits used and the number of qubits that can be fully connected and entangled with each other. However, in the appropriate physical layout, it is possible to implement a C gate using four fully connected and multiply entangled qubits simultaneously. 3 The NOT gate can be implemented using only one and two qubit gates. 3 It can be constructed using a small fraction of the number of quantum gate operations used in a NOT gate. This is a much simpler C 2This can be done by starting with an extension of the methods described for the implementation of the NOT Toffoli gate (see, for example, J. I. Cirac and P. Zoller, "Quantum Computations with Cold Trapped Ions," Phys. Rev. Lett. Vol. 74 (20) (1995)), and can be later demonstrated (see, for example, T. Monz et al., "Realization of the Quantum Toffoli gate with Trapped Ions," Phys. Rev. Lett. Vol. 102, 040501 (2009)). 2 The NOT implementation already exhibits a significant reduction in the number of contributing gates and time required to complete the entire gate operation, while still providing a net fidelity improvement over a concatenation of one- and two-qubit gates due to the aggregation of gate errors, even if the individual fidelities of the one- and two-qubit gates are much higher. This three-qubit gate can be realized in a single linear trap without strong requirements on geometric symmetry. In contrast, certain implementations described herein utilize the full 3D symmetry of the designs described herein to achieve a C n Thus, the above-referenced examples of improved efficiency are achieved through the concomitant reduction in quantum gates required to implement them. n This can be greatly scaled up according to the number of controls in the NOT gate. Other multiply-controlled gate operations, including phase rotation, can exhibit similar efficiency improvements using physical configurations with three or more entangled qubits simultaneously. These prior improvements can greatly reduce error correction.

[0021] Even the highest quality qubits exhibit a significant error rate, which may be small per qubit, but can be magnified by the number of gates used to execute the algorithm. If error correction is required to perform an even smaller set of quantum operations that have a reasonable chance of giving a reliable result, once the aggregate error rate reaches a threshold, the efficiency of the architecture drops off immediately in proportion to the amount of overhead required for error correction.

[0022] For small-scale quantum computers with hundreds of relatively high-quality qubits intended to perform logical operations, the overhead of error-correction qubits plus accessories may represent an order of magnitude or roughly a factor of ten increase in the number of qubits, with proportionally reduced efficiency. For larger systems, the overhead may increase by several more orders of magnitude. However, in certain embodiments described herein, quantum computers that benefit from the aggregation efficiency of fully connected, high-quality qubits and utilize multi-qubit gate operations (e.g., implemented natively by utilizing multidimensional geometries) can use significantly fewer steps and significantly fewer total qubits. As used herein, the term "native" gate operations indicates that the geometric layout allows for more than two qubits to participate simultaneously. Certain native multi-qubit gate implementations described herein can advantageously implement algorithms without significant error-correction overhead. In addition, significant improvements in overall design efficiency due to reduced overhead can be achieved using orders of magnitude fewer quantum resources to both implement fundamental quantum computing algorithms or subroutines and demonstrate practical utility at increased speeds compared to classical computing systems.

[0023] To date, most QC systems using trapped ions utilize one-dimensional (e.g., linear) traps that can then be electrically or photonically interconnected (see, e.g., U.S. Pat. No. 9,858,531; Debnath et al., “Demonstration of a small programmable quantum computer with atomic qubits,” Nature, Vol. 536, p. 63 (2016)). Such 1D traps allow linear qubit chains to be fully connected within a common potential well or trapping zone. The degree of full connectivity is limited by the number of qubits that can be chained together before the coupling strength between qubits at or near opposite ends of the linear chain becomes too weak to be usable for reliable multi-qubit gate operations, and so it may be desirable to create interconnections between multiple linear traps of limited strength. For example, optical interconnections can be utilized by transferring the qubit state from an ion to a photon and then feeding the photon into another linear trap where the quantum state is transferred to another ion. One type of protocol commonly used for such processes is referred to as "quantum teleportation." Such interconnects impart time delays and potential inefficiencies in conversion (e.g., from a trapped ion qubit to a photon and a second trapped ion). Certain implementations described herein advantageously provide alternative configurations for simultaneously optimizing more direct qubit-to-qubit interactions than can be efficiently achieved using linear or 2D elements with optical interconnects. When scaled to larger numbers of qubits, certain such implementations can advantageously reduce or eliminate the number of optical interconnects between nodes, along with their associated penalties (e.g., time delays, ion-to-photon conversion losses).

[0024] Rectangular two-dimensional (2D) grid configurations have been previously employed for several trapped-ion and superconducting qubit (SCQ) schemes. However, interactions between qubits are limited to one- and two-qubit operations performed within the trapped-ion grid lanes (e.g., by shuttling the qubit in and out of the lanes through intersections). Such approaches typically rely on significant redundancy to add a degree of fault tolerance to raise the probability of successful execution of the algorithm to a usable level. For example, some approaches use global addressing of an ensemble of qubits, which are shuttled in and out of aligned intersections in the grid to redundantly perform a single one- or two-qubit operation among many qubits and then average to reduce errors. The overhead in such approaches, in terms of the number of redundant qubits to perform a single logical operation with sufficient fidelity, grows rapidly with the scale of logical operations implemented by the quantum computer. Conversely, in certain embodiments described herein, entanglement between three or more qubits is enabled by simultaneously operating on qubits arranged in two or more dimensions to directly or natively perform multi-qubit gate operations.

[0025] The ability to scale up high-fidelity trapped-ion configurations with high connectivity (e.g., full connectivity, many-to-many connectivity) between nearest-neighbor and second-nearest-neighbor qubits is limited by the physical properties of the interactions between them. For example, the coupling strength is highly dependent on the inter-ion distance (d), and the coupling strength or exchange frequency Ω ex is expressed as 1 / d 3 decreases with

[0026]

number

[0027] In the formula, Ω exchis the exchange frequency or coupling strength, and for the most common case where more than one ion species may be used, q1 is the charge of the ion in the first potential well, identified here as potential well "1", q2 is the charge of the ion in the second potential well, identified here as potential well "2", m1 and m2 are the masses of the ions in potential wells 1 and 2, respectively, ω1 and ω2 are the frequencies of potential wells 1 and 2, respectively, and d is the distance between the ions (see, e.g., DJ Wineland et al., J. Res. Natl. Inst. Stand. Technol. Vol. 103, 259 (1998)). In a 2D layout, crowding of surface electrodes to control trapped ions for gate operation can be raised due to the area of ​​multiple surface electrodes and feed lines providing full control of the ions in their potential wells, which limits how closely together the ion trapping zones can be placed while still allowing a strong enough coupling for effective gate interaction. In 1D traps to date, up to about 25 ions spaced a few micrometers apart in linear chains in a single potential well can be directly coupled and used for valid gate operations, typically in selectable pairwise combinations. Longer ion chains can be formed in the laboratory, but the spacing between qubits is only another 3-4 micrometers, and previous work to implement valid two-qubit gate operations between ions at opposite ends of a 1D chain of more than 25 trapped ions required relying on optical or other types of interconnects between separate linear traps. Entanglement between qubits in separate traps is performed by a series of swapping operations, conversion from one qubit type or species to another (e.g., from ions to photons and vice versa, different ion species), and / or optical interconnects, but these impose significant time delays and inefficiencies.

[0028] Certain embodiments described herein advantageously facilitate solutions to additional hardware challenges that grow exponentially when designing gated model QC structures scaled up from networked or optically interconnected 1D ion traps, and that appear to be prohibitively difficult and infeasible. For example, certain embodiments described herein incorporate optical elements (e.g., lasers, optical ports, fibers, detectors) into the QC structure for addressing, manipulation, readout, and possibly sideband cooling of each qubit, providing line-of-sight access angles that advantageously enable simultaneous entanglement between multiple qubits across three dimensions.

[0029] Certain implementations described herein advantageously provide scalable hardware configurations that allow complex quantum algorithms to be directly "written" and executed by enabling simultaneous entanglement between an optimal number of nearby qubits. In certain implementations, multi-dimensional quantum gate implementations can be directly written and flexibly reprogrammed in the form of multi-qubit gates, similar to traditional firmware such as field programmable gate arrays (FPGAs).

[0030] Certain implementations described herein advantageously enable multiply controlled quantum gate operations to be natively performed by utilizing multi-dimensional geometries. In certain embodiments, quantum gate operations are performed on a quantum firmware platform in a minimal number of steps (e.g., without relying on concatenation of one- and two-qubit gate operations to perform a multiply controlled NOT operation).

[0031] Certain embodiments described herein advantageously provide a feasible engineering architecture that allows the quantum firmware platform to be scaled up as needed by incorporating electrical and optical channels for full control and readout of each qubit in a circuit model architecture to enable universal quantum computing.

[0032] Certain embodiments described herein advantageously provide multi-layer quantum computing structures configured to allow an optimal number of qubits to be entangled simultaneously among nearest neighbors, second nearest neighbors, and possibly beyond. Certain such embodiments include electrical and optical access channels for addressing, controlling, and reading out qubits in a scalable quantum processor. For example, an array of fully connected qubits advantageously provides an option for executing quantum algorithms in hardware that is more efficient and flexible than do other designs in which entangled gate operations are limited to specific pairs (e.g., due to the type of qubits utilized or their layout). This improved efficiency and flexibility can grow exponentially with the number of qubits in the array.

[0033] Certain implementations described herein are also advantageously capable of performing gate operations involving more than two qubits at a time, thereby providing significant efficiency improvements over previous designs limited to one- and two-qubit gates (e.g., by replacing tens of those gates with one four-qubit gate). Certain implementations described herein advantageously overcome the connection limitations found in one- and two-dimensional geometries using trapped ions. For example, by arranging qubits into multiple qubit arrays (e.g., multiple co-aligned linear qubit arrays) with direct connections (e.g., entanglement) between the qubit arrays, the significant time delays and inefficiencies of converting ion qubits to photon qubits and back again can be overcome to continue to scale up from a limited number of tens of ions in a 1D chain.

[0034] Certain embodiments described herein advantageously utilize a first set of ions trapped above a first surface and a second set of ions trapped below a second surface, the second surface facing the first surface, where at least some ions of the first set of ions are entangled with at least some ions of the second set of ions. By incorporating and interleaving the first and second sets of trapped ions, and by adjusting the trapping position (e.g., height, longitudinal or lateral position) of the central ion of the qubit gate relative to the ions at the apexes of the qubit gate, certain embodiments advantageously provide multi-dimensional entanglement geometries similar to complex 3D crystal structures (e.g., pyrochlore). In addition, the space between the first and second surfaces of certain embodiments advantageously provides optical access from the side for globally or locally addressing the qubits, and for readout by a detector. Because gravity is not the governing force on the trapped ions, the entire configuration can be oriented at any angle (e.g., tilted 90 degrees, 45 degrees, etc.) For other types of qubits, this general orientation insensitivity of trapped ions may not apply to the same extent, and other types of qubits may have limited orientation options.

[0035] Exemplary Implementations Certain embodiments described herein utilize multi-dimensional cells of qubits, which may resemble 3D crystal structures (e.g., pyrochlore). In certain embodiments, the 3D cells may be formed symmetrically in 3D space between, for example, substantially parallel 1D trapping zones / channels. Certain embodiments utilize many qubits per gate, advantageously reducing (e.g., minimizing) circuit depth, error correction, and interference mitigation requirements. Certain embodiments utilize interchangeable component cells, which may advantageously enable Quantum FPGA (QFPGA) and Quantum ASIC (QASIC) chips.

[0036] Although the physical configurations of certain embodiments are described herein as using high fidelity trapped ion qubits (e.g., low error rates), any type of qubit (e.g., naturally occurring, artificially formed) that can be entangled in multiple dimensions simultaneously with multiple other qubits can be used in accordance with certain embodiments described herein. Examples of qubits that are compatible with certain embodiments described herein include, but are not limited to, subatomic particles, neutral atoms, ions, neutral molecules, charged molecules, Bose-Einstein condensates, electrons, electron holes, excitons, magnetic qubits, nitrogen defect centers in diamond, phonons, photons, quantum dots, Rydberg atoms, spins in silicon, and, in some cases, superconducting qubits. In certain embodiments, the qubits are suitable for directly (e.g., natively) performing gate operations between three or more qubits in a specified configuration. For example, the physical architecture of certain embodiments can advantageously provide complex gate operations such as multiple controlled NOT or phase rotation directly without relying on serial concatenation of one- and two-qubit gates.

[0037] The trapped ion qubits utilized in certain embodiments described herein exhibit quantum interaction properties that should be optimized. Trapped ions exhibit Gell-Mann figures of merit including, but not limited to, (i) the fact that they are identical within a given species and thus advantageously avoid significant calibration or tuning, (ii) the ability to form qubits with extremely long-lived stability, and (iii) sustained demonstrated high-fidelity gate operation compared to competing qubit technologies. In certain embodiments described herein, simultaneous multi-qubit gate operation can be enabled by ions arranged in a 3D geometric layout of multiple identical fully connected qubits. In certain embodiments, the 3D geometric layout of fully connected qubits can advantageously incorporate two or more qubit types (e.g., utilizing one species of ion for multiple control qubits and a different ion species for adjacent cells utilizing a second ion species as a target).

[0038] Linear (1D) surface trap qubits (e.g., ions) are typically trapped in potential wells designed to be centered at a distance of tens of micrometers from the electrode surface. The distance of the qubits from the electrodes as well as the linear movement and positioning of individual qubits along the long axis of the trap can be controlled by voltages applied to the DC and RF electrodes that comprise the trapping region (see, e.g., Stick 2006). DC voltages, RF frequencies and / or other electrical settings can be adjusted to optimize quantum gate performance, including minimizing errors due to noise (e.g., due to heating, RF interference, stray magnetic fields), according to the particular characteristics of the qubits (e.g., the mass of the ion species chosen). Another potential well or RF null region (sometimes referred to as "ancillary" or "serendipitous") can be formed approximately twice as far from each surface (e.g., substrate) (see, e.g., M. Mielenz et al., "Arrays of individually controlled ions suitable for two-dimensional quantum simulations," Nature Communications, 7:11839 (2016)) and used as a loading zone. In certain embodiments, the substrate region includes a portion of an electrically insulating and / or semiconductor (e.g., silicon dioxide, silicon) chip, and at least some of the electrical traces can be in electrical communication with electrodes in the electrode region. At least some of the other electrical traces can be in electrical communication with electrodes in the electrode region of a portion of another proximate qubit. For example, the electrical traces and the electrodes in the electrode region can include a conductive material (e.g., aluminum, copper, gold) deposited on a surface of the substrate region and can include at least one hermetic coating configured to hermetically seal the conductive material from contaminants and / or corrosion. The electrodes in the electrode regions can be configured to create a potential well configured to contain (e.g., suspend, trap) a single ion or a linear chain of ions at a location spaced apart from the planar substrate regions (e.g., in a direction substantially perpendicular to the substrate regions).

[0039] 1A-4D illustrate various aspects of an exemplary multi-qubit gate formed between 1D linear trapping regions and using potential wells to trap ions that are entangled with other trapped ions, according to certain embodiments described herein. A vertical orientation is not required, and therefore the terms "upper" and "lower" are not used. In certain embodiments described herein, multiple linear trapping regions are aligned together, such that two or more qubits from a first trapping region can simultaneously directly interact (e.g., be entangled) with two or more qubits in a second, third, fourth, fifth, sixth, seventh, etc., co-aligned trapping region and / or with qubits in other co-aligned trapping regions. In certain embodiments described herein, incidental (e.g., auxiliary) trapping zones may be used as additional intended trapping zones for gate operation, if desired, with appropriate adjustments for optimal distance from the trapping electrodes, linear displacement placement along the long axis of the trap to allow interleaving of qubits between prismatic lattice layers (e.g., into triangular prismatic, cubic prismatic, pentagonal prismatic, hexagonal prismatic, etc.), and optimal motion stability.

[0040] In certain embodiments, the quantum computing (QC) system comprises a plurality of qubits arranged in a plurality of substantially linear regions having longitudinal axes that are substantially parallel to each other, at least a portion of the substantially linear regions comprising two or more qubits, one or more qubits of each substantially linear region being configured to interact with one or more qubits of at least one other substantially linear region. For example, the plurality of substantially linear regions may comprise a central linear region having a central longitudinal axis along which a central qubit of the central linear region is arranged. The plurality of substantially linear regions may further comprise at least one outer linear region having a corresponding outer longitudinal axis along which an outer qubit of the outer linear region is arranged.

[0041] In certain embodiments, the at least one outer substantially linear region comprises at least two outer substantially linear regions each having a corresponding outer longitudinal axis along which the outer qubits of the outer substantially linear region are disposed. The central longitudinal axis can be spaced apart from each of the outer longitudinal axes and can be substantially parallel to each of the outer longitudinal axes, each of the outer longitudinal axes being at a different azimuthal position about the central longitudinal axis. The outer linear regions can be formed from potential wells closest to corresponding electrode surfaces, and the central linear regions can be formed from accidental trapping zones or RF null regions corresponding to the potential wells forming the outer linear regions, and the alignment and spacing of the outer linear regions are designed such that their corresponding accidental trapping zones or RF null regions overlap (e.g., at the center of a symmetric alignment of parallel linear regions). For example, each of the outer longitudinal axes can be spaced substantially equidistant and parallel from a common (e.g., overlapping) central longitudinal axis, and the centerlines of each of the outer longitudinal axes can be symmetrically disposed (e.g., at equal azimuthal angles) about the common central longitudinal axis to form either a 2D plane or a 3D geometric prism.

[0042] For example, the two outer longitudinal axes can be spaced apart from each other by an azimuth angle of about 180 degrees centered on the central longitudinal axis (e.g., the two outer linear regions are on opposite sides of the central longitudinal axis and have two outer longitudinal axes that are coplanar with the central longitudinal axis). As other examples, three outer longitudinal axes can be separated from each other by an azimuth angle of about 120 degrees about the central longitudinal axis (e.g., three outer linear regions have three outer longitudinal axes), four outer longitudinal axes can be separated from each other by an azimuth angle of about 90 degrees or about 180 degrees about the central longitudinal axis (e.g., four outer linear regions have four outer longitudinal axes), five outer longitudinal axes can be separated from each other by an azimuth angle of about 72 degrees or about 144 degrees about the central longitudinal axis (e.g., five outer linear regions have five outer longitudinal axes), and six outer longitudinal axes can be separated from each other by an azimuth angle of about 60 degrees, about 120 degrees, or about 180 degrees about the central longitudinal axis (e.g., six outer linear regions have six outer longitudinal axes).

[0043] 1A-1B are schematic side and side views, respectively, of an exemplary QC system 100 with a plurality of qubits 105 arranged in a plurality of substantially linear regions, according to certain embodiments described herein. FIG 1C is schematic side and side view of another exemplary QC system 100' with a plurality of qubits 105' arranged in a plurality of substantially linear regions, according to certain embodiments described herein.

[0044] 1A-1B are grouped into a number of groups: a central group of qubits 112 disposed within a central substantially linear region 110, a first outer group of qubits 122 disposed within a first outer substantially linear region 120, and a second outer group of qubits 132 disposed within a second outer substantially linear region 130. As shown in FIGS. 1A-1B, within the first outer substantially linear region 120, the first outer group of qubits 122 (e.g., within a first outer qubit trapping zone) are arranged in a substantially linear chain above a first substantially linear surface trap 116 of a first substrate 118, and the second outer group of qubits 132 (e.g., within a second outer qubit trapping zone) are substantially parallel to the first outer region 120 and arranged in a substantially linear chain below a second substantially linear surface trap 126 of a second substrate 128. A central group of qubits 112 are substantially parallel to the first outer region 120 and arranged in a substantially linear chain between the first outer region 120 and the second outer region 130. The central substantially linear region 110 includes an accidental trap region created by a first substantially linear surface trap 116 and a second substantially linear surface trap 126.

[0045] The plurality of qubits 105' in FIG. 1C are grouped into one group of qubits 112' arranged in a substantially linear chain in a substantially linear region 110' and another group of qubits 122' arranged in a substantially linear chain in a substantially linear region 120' substantially parallel to the substantially linear region 110'. As shown in FIG. 1C, both groups of qubits 112', 122' are between a substantially linear surface trap 116' in a first substrate 118' and a second substantially linear surface trap 126' in a second substrate 128'. The substantially linear region 110' includes a primary trapping region created by the surface traps 126' and an overlapping accidental trapping region created by the surface traps 116', and the substantially linear region 120' includes a primary trapping region created by the surface traps 116' and an overlapping accidental trapping region created by the surface traps 126'.

[0046] In certain embodiments, the plurality of qubits 105, 105' includes ions that are confined (e.g., trapped) within corresponding potential wells created by voltages applied to the electrodes of the surface traps 116, 126, 116', 126'. An example of an ion that is compatible with certain embodiments described herein is Ba. + , B.E. + , Cd + , Ca + , Mg + , Hg + , Sr + , Yb + In certain other embodiments, alternative qubit technologies can be used, such as uncharged atoms (e.g., neutral atoms, Rydberg states).

[0047] 1A-1B show an exemplary configuration of a linear chain of qubits 105 that are aligned together and arranged within a gate of multiple simultaneous entangled qubits across three dimensions and are at least partially confined by a linear trap (e.g., a 1D trap) that can uniquely enable native, multiply controlled gate operations (e.g., by exploiting geometric symmetry). The configuration of FIG. 1A-1B can be conceptualized by starting with two exemplary linear surface traps 116, 126 as building blocks. As shown in FIG. 1A-1B, by inverting one of the linear surface traps 116, 126 over the other and suspending the linear chain of ions in a designed potential well closest to each linear trap 116, 126, the ions in each chain (e.g., qubits 122, 132) can be positioned to interact (e.g., be entangled) with both other ions in the same chain and ions in adjacent chains. In certain embodiments described herein, the distance between the co-aligned outer linear regions 120, 130 can be advantageously adjusted such that an "accidental" trapping zone or RF null that occurs naturally approximately twice as far from the linear surface trap 116 as a first outer (e.g., designed) trapping zone or RF null overlaps with another "accidental" trapping zone or RF null that occurs naturally approximately twice as far from the linear surface trap 126 as a second outer (e.g., designed) trapping zone or RF null. In certain embodiments, these overlapping accidental zones can be utilized to form a central linear region 110 (e.g., a central or central linear trapping region) that is adjacent to and approximately equidistant from the first outer linear region 120 and the second outer linear region 130 (e.g., trapping zones).In certain embodiments, the two outer longitudinal axes 124, 134 of the first outer linear region 120 and the second outer linear region 130 are separated from each other by an azimuth angle of 180 degrees centered on the central longitudinal axis 114 of the central linear region 110 (e.g., the first outer linear region 120 and the second outer linear region 130 have two outer longitudinal axes 124, 134 on opposite sides of the central longitudinal axis 114 and coplanar with the central longitudinal axis 114).

[0048] In certain embodiments described herein, additional electrodes and / or voltage adjustments can be incorporated for additional control and stability depending on the intended quantum gate operation (e.g., for multi-qubit gates) to be performed on the qubits between the central linear region 110, the first outer linear region 120, and the second outer linear region 130. In certain embodiments described herein, appropriate adjustment of the linear displacement arrangement of the trapped qubits up (and down) along the long axis of the trap allows the qubits to be interleaved in a triangular lattice between layers to allow equilateral triangular, hexagonal, and other symmetric nearest neighbor entanglement connections to be advantageously formed in two or more dimensions (e.g., as shown in Figures 2A-2E, 3A-3C, 4A-4D) for the purpose of natively performing multi-controlled quantum gate operations with three or more qubits simultaneously entangled across three or more dimensions. For example, Figures 1A-1B show two C-shaped lattices connected in a plane. 6 We present as an example two connected 7-qubit hexagonal cells optimizing nearest neighbor connections as NOT gates.

[0049] In certain embodiments described herein, the QC system 100 comprises three or more linear surface traps to form 3D configurations. In these 3D configurations, the linear regions closest to each of the three or more linear surface traps are substantially parallel to one another, and the incidental linear regions of the three or more linear surface traps are aligned (e.g., collinear) with one another to form a single central linear trapping region adjacent to the outer linear regions closest to each of the three or more linear surface traps (e.g., having longitudinal axes at different azimuthal positions relative to the longitudinal axis of the central linear trapping region). As described herein, the azimuthal angle between the longitudinal axes of the adjacent outer linear trapping regions can be adjusted to form a geometric prism for additional control and stability of the central linear trapping region (e.g., the incidental trapping zone of the linear surface traps) depending on the intended quantum gate operation (e.g., for a multi-qubit gate) to be performed on the qubits of the multiple linear trapping regions.

[0050] 2A-2B are schematic illustrations of an exemplary triangular prism array 200 in exploded perspective and exploded side views, respectively, and FIGs. 2C-2D are schematic illustrations of an exemplary triangular prism array 200 in assembled perspective and side views, respectively, according to certain embodiments described herein. The exemplary triangular prism array 200 includes a plurality of qubits 205 in a plurality of substantially linear regions including a central linear region 210 (e.g., a central trapping region including a central group or chain of qubits 212) having a central longitudinal axis 214. The exemplary triangular prism array 200 further includes three outer linear regions 220, 230, 240 (e.g., three outer trapping regions each including a corresponding outer group or chain of qubits 222, 232, 242, the three outer trapping regions adjacent the central linear region 210) having outer longitudinal axes 224, 234, 244 that are substantially parallel to each other and to the central longitudinal axis 214. Each of the substantially linear regions 210, 220, 230, 240 comprises two or more qubits 205 configured to interact with each other and with one or more qubits 205 of at least one other substantially linear region 210, 220, 230, 240. The qubits 205 are at least partially confined within the linear regions 210, 220, 230, 240 by potential wells created by three linear (e.g., 1D) traps 226, 236, 246 according to certain implementations described herein.

[0051] In the exemplary triangular prism array 200 of FIGS. 2A-2D, additional control and stability of the linear chain of qubits 205 along the central trapping region 210 is provided by overlapping the incident RF nulls from each of the three outer linear traps 226, 236, 246 such that they are approximately equidistant from each of the three outer linear traps 226, 236, 246. The interior angle (e.g., azimuthal angle) between any two outer linear traps 226, 236, 246 with the central trapping zone 210 as the apex is equal to approximately 60 degrees, forming a triangular prism (e.g., which may be substantially equilateral in cross section or substantially isosceles in cross section). In certain embodiments, the triangular prism array 200 has a C-shaped axial link connecting them along a lateral direction (e.g., substantially perpendicular to the central longitudinal axis 214). 6 C forming a NOT gate 3 A NOT gate is provided. A number of such gates can be formed and connected along the central longitudinal axis 214.

[0052] 2A-2D show schematic diagrams of an exemplary arrangement of substrates 228, 238, 248 and linear surface traps 226, 236, 246 (e.g., including RF and DC electrodes) along with data cable 250, optical fiber 260, optical detector 270, linear trapping zones 210, 220, 230, 240, groups (e.g., chains) of qubits 212, 222, 232, 242, light (e.g., laser light) exit port 280 and supporting outer structure 290, according to certain embodiments. In addition, FIGS. 2C-2D show an addressable laser output port 262 at the end of optical fiber 260 carrying multiple tuned wavelengths of laser light (e.g., from an acousto-optic modulator, not shown) for selective qubit addressing, emitting laser beam 264, and a C 3Schematically illustrates exemplary locations of four coupled (e.g., entangled) qubits 205a,b,c,d (e.g., one qubit from each of the four chains 212, 222, 234, 242) used to form a NOT gate. In certain embodiments, the four coupled qubits 205a,b,c,d also share a C qubit 205a (e.g., at the center) in accordance with certain embodiments described herein. 6 To form a NOT gate, it may be directly coupled (e.g., entangled) with three additional neighboring qubits 205e, f, g (e.g., nearby vertex qubits) along the triangular prism array 200, as shown diagrammatically in FIG. 2E. The alternating shading of the qubits indicates that there may be two interleaved species (e.g., two different ion species), where one ion may be co-cooled by a neighboring ion that is laser cooled. Because the co-cooled ions are not impinged by the cooling laser beam, the co-cooled ions may form a gate operation with less interference, noise, or timing issues. The dotted ovals in FIG. 2E indicate the two possible Cs of the shared target ion. 3 NOT gate to C 6 1 shows the lateral plane of two sets of apex ions that can be combined with shared target ions to create a NOT gate.

[0053] In certain embodiments, the three qubits 205b,c,d form a triangle (e.g., an equilateral triangle) of “control” qubits (e.g., the spacing between any two of the qubits can be in the range of 30 micrometers to 70 micrometers), where the triangle is substantially perpendicular to the longitudinal axes 214, 224, 234, 244 of the linear substrate regions 210, 220, 230, 240. The triangular three qubits 205b,c,d are examples of three qubits that are arranged within a substantially flat region and configured to simultaneously interact (e.g., entangle) with one another and collectively interact with or on the four central (e.g., target) qubits 205a to natively (e.g., geometrically, symmetrically) perform a multi-qubit gate operation in one effective gate operation, according to certain embodiments described herein.

[0054] In certain embodiments, as shown in Figures 2C-2D, the multi-qubit trap configuration has a substantially triangular cross-section in a plane substantially perpendicular to longitudinal axes 214, 224, 234, 244, while in certain other embodiments, the multi-qubit trap configuration has other shapes (e.g., circular, elliptical, geometric, non-geometric, symmetric, asymmetric, etc., square, rectangular, pentagonal, hexagonal, heptagonal, octagonal, etc.).

[0055] 3A and 3B-3C are schematic diagrams illustrating exploded and assembled perspective views, respectively, of an exemplary cubic (e.g., rectangular, square) prismatic array 300 according to certain embodiments described herein. The exemplary cubic prismatic array 300 includes a plurality of qubits 305 in a plurality of substantially linear regions including a central linear region 310 (e.g., a central trapping region including a central group or chain of qubits 312) having a central longitudinal axis 314. The exemplary cubic prismatic array 300 further includes four outer linear regions 320, 330, 340, 350 (e.g., four outer trapping regions each including a corresponding outer group or chain of qubits 322, 332, 342, 352, the four outer trapping regions adjacent the central linear region 310) having outer longitudinal axes 324, 334, 344, 354 that are substantially parallel to each other and to the central longitudinal axis 314. Each of the substantially linear regions 310, 320, 330, 340, 350 comprises two or more qubits 305 configured to interact with each other and with one or more qubits 305 of at least one other substantially linear region 310, 320, 330, 340, 350. The qubits 305 are at least partially confined within the linear regions 310, 320, 330, 340, 350 by potential wells created by four linear (e.g., 1D) trapping regions according to certain implementations described herein.

[0056] 3A-3C, additional control and stability of the linear chain of qubits 305 along the central trapping region 310 (e.g., additional as compared to the control that could be provided by a single accidental RF null) is provided by overlapping the accidental RF nulls from each of the four outer linear traps such that they are approximately equidistant from each of the four outer linear traps. The interior angle (e.g., azimuthal angle) between any two outer linear traps with the central trapping zone 310 as the apex is approximately equal to 90 degrees, forming a cubic prism that is substantially square in cross section.

[0057] 3A-3C show schematic diagrams of an exemplary arrangement of a substrate and linear surface traps (e.g., including RF and DC electrodes) along with data cables 250, optical fibers 260, optical detectors 270, linear regions (e.g., trapping zones) 310, 320, 330, 340, 350, groups (e.g., chains) of qubits 312, 322, 332, 342, 352, light (e.g., laser light) exit ports 280, and supporting outer structures 290, according to certain embodiments described herein. In addition, FIGS. 3B-3C show an addressable laser 262 emitting a laser beam 264, and a C 4 Schematically illustrates exemplary locations of five coupled (e.g., entangled) qubits 305a,b,c,d,e (e.g., one qubit from each of the five chains 312, 322, 332, 342, 352) used to form a NOT gate. In certain embodiments, the five coupled qubits 305a,b,c,d,e also share a C qubit 305a (e.g., at the center) in accordance with certain embodiments described herein. 8 Four additional adjacent qubits 305 (eg, nearby vertex qubits) along the cubic prismatic array 300 may be directly coupled (eg, entangled) to form a NOT gate.

[0058] 4A-4B are schematic illustrations of two perspective views of an exemplary hexagonal prism array 400 according to certain embodiments described herein. The exemplary hexagonal prism array 400 includes a plurality of qubits 405 in a plurality of substantially linear regions including a central linear region (e.g., a central trapping region including a central group or chain of qubits 412) having a central longitudinal axis. The exemplary hexagonal prism array 400 further includes six outer linear regions (e.g., six outer trapping regions each including a corresponding outer group or chain of qubits 422, 432, 442, 452, 462, 472, the six outer trapping regions adjacent the central linear region) having outer longitudinal axes that are substantially parallel to each other and to the central longitudinal axis. Each of the substantially linear regions includes two or more qubits 405 configured to interact with each other and with one or more qubits 405 in at least one other substantially linear region. Qubit 405 is at least partially confined within the linear region by a potential well created by six linear traps (eg, 1D surface traps) according to certain embodiments described herein.

[0059] In certain embodiments, the hexagonal prism array 400 includes C n For example, FIG. 4A illustrates a NOT gate according to certain embodiments described herein (e.g., "pyrochlore" C 124B shows a schematic of an exemplary arrangement of substrates and linear surface traps (e.g., including RF and DC electrodes) along with a depiction of the entanglement of thirteen qubits 405 at one end of the hexagonal prism array 400 (showing the formation of a NOT gate). FIG. 4B shows a schematic of an exemplary hexagonal prism array 400 including six linear traps (e.g., 1D surface traps) to form the illustrated hexagonal prism structure including an addressable laser output port 262 at the end of optical fiber 260 carrying multiple tuned wavelengths of laser light (e.g., from an acousto-optic modulator, not shown) that emits a laser beam 264, along with a data cable, optical fiber 260, optical detector 270, linear trapping zone, qubit groups (e.g., chains) 412, 422, 432, 442, 452, 462, 472, light (e.g., laser light) exit port, and supporting outer structure 290 (which may be omitted if other structures are sufficiently rigid). The seven example qubits 405 (e.g., ions) shown generally in FIGS. 4A-4B are, in accordance with certain embodiments described herein, 12 It is also possible to directly couple six adjacent vertex qubits in a substantially parallel lattice layer along the longitudinal axis of the hexagonal prism array 400 to form a NOT gate. 6 These gates can be entangled to form NOT gates, and these gates can be n NOT (which may be referred to as a "super-pyrochlore" gate cell, for example) 18 400 , may be further coupled directly to six other adjacent qubits 405 (e.g., vertex qubits) in a substantially parallel lattice layer along the hexagonal prism array 400 to form a quabit-like NOT (e.g., a vertex qubit).

[0060] 4C is a schematic cross-sectional view of an exemplary hexagonal prism array 400 having a plurality of single logical qubits 412, each of which comprises a single physical qubit (e.g., a single ion) in the central linear region, and a plurality of single logical qubits 422, 432, 442, 452, 462, 472, each of which comprises a single physical qubit (e.g., a single ion) in the outer linear region, according to certain implementations described herein. FIG. 4D is a schematic cross-sectional view of an exemplary hexagonal prism array 400 having a plurality of single logical qubits 412, each of which comprises a single physical qubit (e.g., a cluster 480 of 2, 3, 4, 5, 6 or more ions, as shown in FIG. 4D) in the central linear region, and a plurality of single logical qubits, each of which comprises a single physical qubit in the outer linear region, according to certain implementations described herein. The shaded regions in Figures 4C and 4D show diagrammatically six outer linear regions, each containing a primary trapping region generated by a corresponding surface trap, and a central linear region containing overlapping accidental trapping regions generated by the surface traps.

[0061] 5A-5D illustrate an exemplary system 500 comprising at least one hexagonal pillar array 400 (e.g., as shown diagrammatically in FIG. 4B) having an exemplary planar QC structure 600 comprising a multi-layer 2D qubit lattice according to certain embodiments described herein (see, e.g., U.S. Patent Application Publication No. 2021 / 0142204, which is incorporated herein by reference in its entirety). For example, the inter-qubit spacing, layout, and 3D geometric relationship at a corner of the pyrochlore chip can be aligned to a closely matching inter-qubit spacing and 3D geometry at one end of the super-pyrochlore cell to enable extension of direct coupling (e.g., entanglement) between pyrochlore and super-pyrochlore across the exemplary system 500. In this example, according to certain embodiments described herein, the direct coupling of closely packed multi-layer 2D pyrochlore gate cell (e.g., in a multi-layer 2D surface trap lattice) constituent segments to one or more super-pyrochlore cells advantageously enables ASIC implementations to customizable combinations of high throughput across specific segments of a chip combined with ultra-high processing power within specific other segments of the chip or substrate.

[0062] Other Exemplary Embodiments Embodiment 1: A quantum computing (QC) system comprising a plurality of logical qubits (e.g., each logical qubit comprises one or more physical qubits) arranged in a plurality of substantially linear regions having longitudinal axes that are substantially parallel to one another, where at least a portion of the substantially linear regions comprise two or more logical qubits, and where one or more qubits in each substantially linear region are configured to interact with one or more qubits in at least one other substantially linear region. Quantum logic gate operations are performed using the logical qubits, which may comprise at least one physical qubit (e.g., ions, neutral atoms, Rydberg atoms, electrons, electron holes, nitrogen defects, quantum dots, quantum particles with multiple possible states). For example, the logical qubits may comprise multiple physical qubits (e.g., ions) for redundancy as a means to improve logical qubit stability and / or improve fault tolerance in quantum computing systems where qubits are noisy, to reduce qubit decoherence time. As another example, a logical qubit can be accompanied by an auxiliary physical qubit for sympathetic cooling of the logical qubit (e.g., without affecting the quantum state). Unless otherwise specified, the term "qubit" as used herein generally refers to a logical qubit that includes a single physical qubit, but in certain implementations can include additional physical qubits (e.g., for fault tolerance, for cooling) without loss of generality.

[0063] Embodiment 2: The system described in embodiment 1, further comprising a first substrate and a second substrate, the first substrate and the second substrate being substantially parallel to each other, and the multiple qubits being arranged as a multi-qubit gate array comprising multiple multi-qubit gates positioned in a region between the first substrate and the second substrate, wherein the qubits at or near the surface of at least one of the first substrate and the second substrate are arranged in multiple substantially linear planar regions.

[0064] Embodiment 3: A system as described in embodiment 2, wherein, for each multi-qubit gate, each qubit is configured to be quantum mechanically entangled with at least one of the other qubits of the multi-qubit gate.

[0065] Embodiment 4: A system as described in embodiment 1, wherein two or more qubits and one or more qubits in each substantially linear region are configured to directly interact with one or more qubits in at least one other substantially linear region to form a three-dimensional (3D) array configured to undergo multi-qubit gate operations in which three or more qubits participate simultaneously.

[0066] Embodiment 5: A quantum computing (QC) system comprising a plurality of multi-qubit three-dimensional (3D) gates (e.g., arranged within a geometric prismatic 3D cell), each 3D gate including at least three qubits configured to be simultaneously fully connected to one another across three dimensions, and the plurality of multi-qubit 3D gates configured for gate operation of two or more of the multi-qubit 3D gates.

[0067] Embodiment 6: A system as described in embodiment 5, comprising an ion trap array configured to have optimal coherent connection or entanglement directly between nearest neighbor qubits or second nearest neighbor qubits, without the need for inefficient photonic interconnections between qubits that impart significant time delays and net fidelity loss in gate operation (e.g., without teleportation, without multiple transformations between atoms and photonic qubits).

[0068] Embodiment 7: A system as described in embodiment 5, wherein the multi-qubit 3D gate has a substantially geometrically symmetric arrangement to be natively performed in a single gate operation without relying on the concatenation of multiple 1- and 2-qubit gates.

[0069] Embodiment 8: The system described in embodiment 5, wherein the multiple multi-qubit 3D gates are configured to be operated as gates in at least one quantum FPGA (QFPGA) and / or ASIC (QASIC) chip.

[0070] Embodiment 9: A quantum computing (QC) system comprising a combination of 1D trapping regions to form quantum gates in a multi-layer lattice array involving three or more dimensions, using physical relationships (e.g., geometric arrangement, symmetric geometry, equilateral spatial separation) between logical qubits to natively involve three or more logical qubits (e.g., in a single gate operation, effectively in the same gate operation) without relying on concatenation of one and two qubit gates.

[0071] Embodiment 10: The system described in embodiment 9, wherein the quantum logical operation involving three or more logical qubits includes two or more control qubits (e.g., a multiply controlled NOT gate, a Toffoli gate, a super Toffoli gate, a multiply controlled phase gate) that natively acts on one or more target qubits.

[0072] Embodiment 11: A system as described in embodiment 9, wherein a quantum logical operation involving three or more logical qubits includes two or more target qubits (e.g., a singly controlled multi-NOT gate, a fan-out gate, etc.) that are natively acted upon by one or more control qubits.

[0073] Embodiment 12: The system described in embodiment 9, configured to enable integration of electrical and optical elements (e.g., electrical traces, optical beam configurations, detectors, optical exit ports, elements) for trapping, addressing (e.g., initializing, performing gate operations), and low-noise readout of quantum logic gate operations of three or more qubits that resemble 3D crystalline structures (e.g., pyrochlore, superpyrochlore, tetrahedrons, etc.) and participate simultaneously (e.g., in geometric prisms, 3D cells) in multilayer lattice gate configurations and are densely arranged to further enable an optimal number of simultaneous entanglement connections between nearest neighbor qubits, second nearest neighbor qubits, and possibly more qubits.

[0074] Embodiment 13: A system as described in embodiment 9, wherein opposing linear trapping zones comprise building blocks for forming a 3D configuration in which multiple linear trapping regions are aligned together, and the angle between the long axes of the linear traps is adjusted to form a geometric prism for additional control and stability of the central region of the overlapping RF null or accidental trapping zones, depending on the intended quantum gate operation to be implemented for the qubits between the multiple trapping zones (e.g., for multi-qubit gates).

[0075] Embodiment 14: The system of embodiment 9, comprising at least one triangular prism array comprising three 1D outer linear trapping regions including a central trapping zone according to certain embodiments described herein. The interior angle formed by any two outer linear trapping regions with the central trapping zone as a vertex is equal to about 60 degrees, forming a triangular prism that is substantially equilateral in cross section. The triangular prism may be formed by a plurality of C 3The NOT gates are formed along the transverse axis and connected axially to form C 6 It allows to form NOT.

[0076] Embodiment 15: The system of embodiment 9, comprising at least one cubic prism array comprising four 1D outer linear trapping regions including a central trapping zone according to certain embodiments described herein. The interior angle formed by any two outer linear trapping regions with the central trapping zone as a vertex is equal to about 90 degrees, forming a cubic prism that is substantially equilateral in cross section. The cubic prism may be a plurality of C 4 The NOT gates are formed along the transverse axis and connected axially to form C 8 It allows to form NOT.

[0077] Embodiment 16: The system of embodiment 9, comprising at least one pentagonal, hexagonal, heptagonal, octagonal, or other polygonal prism array comprising five, six, seven, eight, or more 1D outer linear trapping regions including a central trapping zone according to certain embodiments described herein. The interior angles formed by any two outer linear trapping regions with the central trapping zone as a vertex are approximately equal, forming a geometric prism that is substantially equilateral in cross section. The n-sided prism may be a plurality of C n The NOT gates are formed along the transverse axis and connected axially to form C 2n NOT, C 3n It allows to form NOT etc.

[0078] Embodiment 17: A quantum computing (QC) system comprising a planar multilayer quantum computing (QC) structure as disclosed by U.S. Patent Application Publication No. 2021 / 0142204 and at least one prismatic trapping lattice structure as shown in FIG. 4B.

[0079] The present invention has been described in several non-limiting embodiments. It is to be understood that the embodiments are not mutually exclusive and that elements described in connection with one embodiment may be combined with, rearranged, or excluded from other embodiments as appropriate to achieve desired design objectives. No single feature or group of features is essential or required for each embodiment.

[0080] For purposes of summarizing the invention, certain aspects, advantages, and novel features of the invention are described herein. It is to be understood, however, that not necessarily all such advantages may be achieved in accordance with any particular embodiment. Thus, for example, the invention may be embodied or performed to achieve one or more advantages without necessarily achieving other advantages as may be taught or suggested herein.

[0081] As used herein, any reference to "one embodiment" or "some embodiments" or "an embodiment" means that a particular element, feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment. In particular, conditional language used herein, such as "can," "could," "might," "may," "eg," and the like, is generally intended to convey that a particular embodiment includes certain features, elements, and / or steps, while other embodiments do not, unless specifically stated otherwise or understood otherwise within the context in which it is used. In addition, the articles "a" or "an" or "the" as used in this application and the appended claims shall be interpreted as meaning "one or more" or "at least one," unless otherwise specified.

[0082] For ease of description, spatial relative terms such as "upper", "lower", "up", "lower", "upper", "lower" and the like may be used herein to describe the relationship of an element or feature to another element or feature as depicted in the drawings. It will be understood that such spatial relative terms are intended to encompass different orientations of the components during use or operation in addition to the orientation depicted in the drawings. For example, if a device in the drawings is inverted, an element described as "upper" or "upper" of the other element or feature would be oriented "lower" or "lower" of the other element or feature. Thus, the exemplary term "upper" can encompass both an orientation of upper and lower. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relative descriptions used herein may be interpreted accordingly. Similarly, terms such as "upper", "lower", "vertical", "horizontal", and the like are used herein for illustrative purposes only, unless specifically indicated otherwise.

[0083] As used herein, degree words such as "approximately," "about," "generally," and "substantially" refer to a value, amount, or characteristic that is close to the stated value, amount, or characteristic that still performs a desired function or achieves a desired result. For example, the terms "approximately," "about," "generally," and "substantially" may refer to an amount that is within ±10%, ±5%, ±2%, ±1%, or ±0.1% of the stated amount. As another example, the terms "generally parallel" and "substantially parallel" refer to a value, amount, or characteristic that deviates from exact parallelism by ±10 degrees, ±5 degrees, ±2 degrees, ±1 degree, or ±0.1 degrees, and the terms "generally perpendicular" and "substantially perpendicular" refer to a value, amount, or characteristic that deviates from exact perpendicularity by ±10 degrees, ±5 degrees, ±2 degrees, ±1 degree, or ±0.1 degrees. The ranges disclosed herein also encompass any overlaps, subranges, and combinations thereof. Phrases such as "up to," "at least," "greater than," "less than," "between," and the like, are inclusive of the recited numbers. As used herein, the meanings of "a," "an," and "said" include plural references unless the context clearly dictates otherwise. Also, as used herein, the meaning of "in" includes "into" and "on," unless the context clearly dictates otherwise.

[0084] As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," or any other variations thereof, are open-ended terms and are intended to cover a non-exclusive inclusion. For example, a process, method, product, or apparatus that includes a list of elements is not necessarily limited to only those elements and may include other elements not expressly listed or inherent in such process, method, product, or apparatus. Furthermore, unless expressly stated to the contrary, "or" refers to an inclusive or, not an exclusive or. For example, a condition A or B is satisfied by any one of A being true (or present) and B being false (or absent), A being false (or absent) and B being true (or present), or both A and B being true (or present). As used herein, the phrase "at least one of" listed items refers to any combination of those items, including single members. As an example, "at least one of A, B, or C" is intended to cover A, B, C, A and B, A and C, B and C, and A, B, and C. Conjunction language such as "at least one of X, Y, and Z" should be otherwise understood by context as it is commonly used to convey that an item, term, etc., can be at least one of X, Y, or Z, unless specifically stated otherwise. Thus, such conjunctive language is generally not intended to imply that an embodiment requires that at least one of X, at least one of Y, and at least one of Z, each be present.

[0085] Thus, while only certain embodiments are specifically described herein, it will be apparent that numerous modifications can be made without departing from the spirit and scope of the present invention. Furthermore, acronyms are used only to improve the readability of the specification and claims. However, these acronyms are not intended to reduce the generality of the terms used, and they should not be interpreted as limiting the scope of the claims to the embodiments described therein.

Claims

1. 1. A quantum computing (QC) system comprising: a plurality of qubits arranged in a plurality of substantially linear regions having longitudinal axes that are substantially parallel to one another, at least some of the substantially linear regions comprising two or more qubits, one or more qubits in each substantially linear region configured to interact with one or more qubits in at least one other substantially linear region; Equipped with The plurality of substantially linear regions comprises: a central substantially linear region having a central longitudinal axis along which a central qubit of the central linear region is disposed; at least one outer substantially linear region having a corresponding outer longitudinal axis along which an outer qubit of the at least one outer substantially linear region is disposed; A quantum computing (QC) system comprising:

2. 2. The QC system of claim 1, wherein the at least one outer substantially linear region includes at least two outer substantially linear regions each having a corresponding outer longitudinal axis along which the outer qubits of the outer substantially linear regions are arranged, the central longitudinal axis being spaced apart from each of the outer longitudinal axes and substantially parallel to each of the outer longitudinal axes, and each of the outer longitudinal axes being at a different azimuthal position around the central longitudinal axis.

3. 3. The QC system of claim 2, wherein the at least two outer substantially linear regions include two outer substantially linear regions having two corresponding outer longitudinal axes at different azimuthal positions about the central longitudinal axis, the outer longitudinal axes being 180 degrees apart from one another.

4. 3. The QC system of claim 2, wherein the at least two outer substantially linear regions include three outer substantially linear regions having three corresponding outer longitudinal axes at different azimuthal positions about the central longitudinal axis, the outer longitudinal axes being 120 degrees apart from one another.

5. 3. The QC system of claim 2, wherein the at least two outer substantially linear regions include four outer substantially linear regions having four corresponding outer longitudinal axes at different azimuthal positions about the central longitudinal axis, the outer longitudinal axes being 90 degrees or 180 degrees apart from one another.

6. 3. The QC system of claim 2, wherein the at least two outer substantially linear regions include five outer substantially linear regions having five corresponding outer longitudinal axes at different azimuthal positions about the central longitudinal axis, the outer longitudinal axes being spaced apart from one another by 72 degrees or 144 degrees.

7. 3. The QC system of claim 2, wherein the at least two outer substantially linear regions include six outer substantially linear regions having six corresponding outer longitudinal axes at different azimuthal positions about the central longitudinal axis, the outer longitudinal axes being 60 degrees, 120 degrees, or 180 degrees apart from one another.

8. 2. The QC system of claim 1, further comprising a first substantially linear surface trap and a second substantially linear surface trap, wherein the qubit in one substantially linear region is in one trapping region including a primary potential trapping region created by the first substantially linear surface trap and an overlapping accidental potential trapping region created by the second substantially linear surface trap, and the qubit in the other substantially linear region is in another trapping region including a primary potential trapping region created by the second substantially linear surface trap and an overlapping accidental potential trapping region created by the first substantially linear surface trap.

9. The QC system of claim 1 , wherein the plurality of qubits includes a central substantially linear qubit chain and at least two outer substantially linear qubit chains.

10. 10. The QC system of claim 9, further comprising a first substantially linear surface trap, wherein one of the at least two outer substantially linear qubit chains is within a primary potential trapping region created by the first substantially linear surface trap, and the central substantially linear qubit chain is within an accidental potential trapping region created at least in part by the first substantially linear surface trap.

11. 11. The QC system of claim 10, further comprising a second substantially linear surface trap, wherein another of the at least two outer substantially linear qubit chains is within a primary potential trapping region created by the second substantially linear surface trap, and wherein the accidental potential trapping region is at least partially created by the second substantially linear surface trap.

12. 10. The QC system of claim 1, wherein the plurality of qubits comprises a chain of ions confined within a substantially linear potential well created by at least one substantially linear surface trap.

13. The ions are Ba ＋ , Be ＋ , Cd ＋ , Ca ＋ , Mg ＋ , Hg ＋ , Sr ＋ , Yb ＋ The QC system according to claim 12, comprising at least one of the following:

14. 2. The QC system of claim 1, further comprising three or more substantially linear surface traps configured to generate potential wells that are substantially parallel to one another and configured to contain the plurality of qubits within the plurality of substantially linear regions.

15. 2. The QC system of claim 1, wherein the plurality of substantially linear regions include a central trapping region including a central qubit chain along the central longitudinal axis and at least two outer trapping regions each including a corresponding outer qubit chain along the corresponding outer longitudinal axis, the central qubit chain including two or more qubits configured to interact with each other and with one or more qubits of at least one of the outer qubit chains, and each outer qubit chain including two or more qubits configured to interact with each other and with one or more qubits of the central qubit chain.

16. 16. The QC system of claim 15, wherein the at least two outer trapping regions include three, four, five, or six trapping regions adjacent to the central trapping region and having outer longitudinal axes that are substantially parallel to each other and to the central longitudinal axis of the central trapping region.

17. 16. The QC system of claim 15, wherein the plurality of qubits form a C6 NOT gate arranged along the central longitudinal axis.

18. 16. The QC system of claim 15, wherein the plurality of qubits form a C2nNOT gate arranged along the central longitudinal axis, where n is a positive integer greater than or equal to 2.

19. A quantum computing (QC) system comprising: a plurality of qubits arranged in a plurality of substantially linear regions having longitudinal axes that are substantially parallel to one another; at least a portion of the substantially linear region comprising two or more qubits; one or more qubits in each of the substantially linear regions entangled with (a) two or more qubits from one or more of the at least one other substantially linear regions, or (b) one or more qubits in an overlapping accidental potential trapping region created by each of the substantially linear regions and the at least one other substantially linear region to define a quantum gate; A QC system equipped with:

20. The plurality of substantially linear regions: a central substantially linear region having a central longitudinal axis along which a central qubit of the central substantially linear region is disposed; at least one outer substantially linear region having a corresponding outer longitudinal axis along which an outer qubit of the at least one outer substantially linear region is disposed; 20. The QC system of claim 19, comprising:

21. A QC system as described in claim 20, wherein the at least one outer substantially linear region includes at least two outer substantially linear regions each having a corresponding outer longitudinal axis, along which the outer qubits of the outer substantially linear regions are arranged, the central longitudinal axis is spaced from each of the outer longitudinal axes and is substantially parallel to each of the outer longitudinal axes, and each of the outer longitudinal axes is at a different azimuthal position around the central longitudinal axis.

22. The QC system of claim 21, wherein the at least two outer substantially linear regions comprise two outer substantially linear regions having two corresponding outer longitudinal axes, three outer substantially linear regions having three corresponding outer longitudinal axes, four outer substantially linear regions having four corresponding outer longitudinal axes, five outer substantially linear regions having five corresponding outer longitudinal axes, or six outer substantially linear regions having six corresponding outer longitudinal axes, wherein the outer longitudinal axes are arranged at different azimuthal positions around the central longitudinal axis, and the outer longitudinal axes are separated from each other by 60 degrees, 72 degrees, 90 degrees, 120 degrees, 144 degrees, or 180 degrees.

23. A QC system as described in claim 19, wherein the plurality of qubits comprises a chain of ions confined within a substantially linear potential well created by at least one substantially linear surface trap.

24. The QC system of claim 23, wherein the ions include Ba+, Be+, Cd+, Ca+, Mg+, Hg+, Sr+, or Yb+.

25. The QC system of claim 19, wherein the plurality of substantially linear regions include a central trapping region having a central qubit chain along a central longitudinal axis, and at least two outer trapping regions, each having a corresponding outer qubit chain along a corresponding outer longitudinal axis, the central qubit chains having two or more qubits configured to interact with each other and further with one or more qubits of at least one outer qubit chain, and each of the outer qubit chains having two or more qubits configured to interact with each other and further with one or more qubits of the central qubit chain.

26. The QC system of claim 25, wherein the plurality of qubits form a C 2n NOT gate arranged along the central longitudinal axis, where n is a positive integer greater than or equal to 2.

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