Package with channel interconnects disposed between solder interconnects - Patents.com

Abstract

A device comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects, the first package including a first substrate comprising at least a first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate, the second package including a second substrate comprising at least a second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate via the second plurality of solder interconnects, and a first plurality of channel interconnects coupled to the first surface of the second substrate, the first plurality of channel interconnects being located between solder interconnects from the second plurality of solder interconnects.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 532,754, filed in the United States Patent Office on November 22, 2021, the entire contents of which are incorporated by reference into this specification as if fully set forth below in their entirety, and for all applicable purposes.

[0002] Various aspects relate to packages having integrated devices. [Background technology]

[0003]

[0003] A package may include a substrate and an integrated device. These components are coupled together to provide a package capable of performing various electrical functions. There is a continuing need to provide better performing packages and to reduce the overall size of the package. Summary of the Invention

[0004] Various features relate to packages having integrated devices.

[0005]

[0005] One embodiment provides a device comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package includes a first substrate comprising at least a first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least a second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate via the second plurality of solder interconnects, and a first plurality of channel interconnects coupled to the first surface of the second substrate, the first plurality of channel interconnects being located between solder interconnects from the second plurality of solder interconnects.

[0006]

[0006] Another embodiment provides an apparatus comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package includes a first substrate comprising at least a first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least a second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate via the second plurality of solder interconnects, and a means for channel interconnection coupled to the first surface of the second substrate, the means for channel interconnection being located between solder interconnects from the second plurality of solder interconnects.

[0007]

[0007] Another example provides a method for making a package. The method includes preparing a first package including a first substrate having at least a first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The method includes coupling a second substrate having at least a second dielectric layer and a second plurality of interconnects to the first substrate via the first plurality of solder interconnects. The method includes preparing a first plurality of channel interconnects on a first surface of the second substrate. The method includes coupling a second integrated device to the first surface of the second substrate. The method includes coupling a third integrated device to the first surface of the second substrate via a second plurality of solder interconnects, the second plurality of solder interconnects being located between the solder interconnects of the second plurality of solder interconnects. [Brief description of the drawings]

[0008]

[0008] Various features, properties, and advantages may become apparent from reading the detailed description set forth below in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Figure 1]

[0009] 1 illustrates an exemplary cross-sectional profile view of a package including a channel interconnect; [Diagram 2]

[0010] 1 illustrates an exemplary cross-sectional plan view of a package including a channel interconnect; [Diagram 3]

[0011] 1 illustrates an exemplary electrical pathway within a package including a channel interconnect. [Figure 4]

[0012] 1 illustrates an exemplary cross-sectional profile view of a package including a channel interconnect; [Diagram 5]

[0013] 1 illustrates an exemplary cross-sectional plan view of a package including a channel interconnect; [Figure 6]

[0014] 1 illustrates an exemplary cross-sectional profile view of a package including a channel substrate having channel interconnects. [Figure 7]

[0015] 1 illustrates an exemplary cross-sectional plan view of a package including a channel substrate having channel interconnects. [Figure 8]

[0016] 1 illustrates an exemplary cross-sectional profile view of a package including a flexible cable with channel interconnects. [Figure 9]

[0017] 1 illustrates an exemplary cross-sectional plan view of a package including a flexible cable with channel interconnects. [Figure 10]

[0018] 1 illustrates an exemplary cross-sectional profile view of a package including several channel interconnects. [Figure 11A]

[0019] 1 illustrates an exemplary sequence for manufacturing a package with multiple channel interconnects. [Figure 11B] 1 illustrates an exemplary sequence for manufacturing a package with multiple channel interconnects. [Figure 11C] 1 illustrates an exemplary sequence for manufacturing a package with multiple channel interconnects. [Figure 12A]

[0020] 1 illustrates an exemplary sequence for manufacturing a package that includes a channel substrate that includes multiple channel interconnects. [Figure 12B] 1 illustrates an exemplary sequence for manufacturing a package that includes a channel substrate that includes multiple channel interconnects. [Figure 12C] 1 illustrates an exemplary sequence for manufacturing a package that includes a channel substrate that includes multiple channel interconnects. [Figure 13]

[0021] 1 illustrates an exemplary flow chart of a method for manufacturing a package with channel interconnects. [Figure 14A]

[0022] 1 illustrates an exemplary sequence for manufacturing a substrate. [Figure 14B] 1 illustrates an exemplary sequence for manufacturing a substrate. [Figure 15]

[0023] 1 shows an exemplary flow chart of a method for manufacturing a substrate. [Figure 16]

[0024] Various electronic devices are illustrated that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0025] In the following description, specific details are described to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0010]

[0026] The present disclosure describes a device comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package includes a first substrate comprising at least a first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least a second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate via the second plurality of solder interconnects, and a first plurality of channel interconnects coupled to the first surface of the second substrate, the first plurality of channel interconnects being located between solder interconnects from the second plurality of solder interconnects. As described further below, the use of the first plurality of channel interconnects between the solder interconnects helps to (i) improve signal isolation within the package, (ii) decongest signal paths, (iii) reduce package thickness, (iv) improve heat dissipation, and / or (v) improve manufacturing lead times.

[0011] Exemplary Package with Channel Interconnects

[0027] 1 shows a cross-sectional profile view of a package 100 including channel interconnects. The package 100 may be a package on package (PoP). The package 100 may include a first package 101 and a second package 103. The package 100 is coupled to a board 106 via a plurality of solder interconnects 110. The board 106 includes at least one board dielectric layer 160 and a plurality of board interconnects 162. The board 106 may include a printed circuit board (PCB).

[0012]

[0028] The first package 101 includes a first substrate 102 and a first integrated device 105. The first integrated device 105 is coupled to a first surface (e.g., a top surface) of the substrate 102 via a plurality of solder interconnects 150. The first substrate 102 includes at least a first dielectric layer 120 and a first plurality of interconnects 122. The first integrated device 105 is coupled to the first plurality of interconnects 122 of the first substrate 102 via the plurality of solder interconnects 150.

[0013]

[0029] The second package 103 includes a second substrate 104, a second integrated device 107, a third integrated device 109, and a plurality of channel interconnects 108. The second integrated device 107 is coupled to a first surface (e.g., a top surface) of the second substrate 104 via a plurality of solder interconnects 170. The third integrated device 109 is coupled to a first surface (e.g., a top surface) of the second substrate 104 via a plurality of solder interconnects 190. The second integrated device 107 is located between the second substrate 104 and the third integrated device 109. The second integrated device 107 is disposed below the third integrated device 109. The plurality of solder interconnects 190 can laterally surround the second integrated device 107.

[0014]

[0030] The plurality of channel interconnects 108 are disposed on a first surface (e.g., top surface) of the second substrate 104. It should be noted that the plurality of channel interconnects 108 shown in FIG. 1 represents a conceptual representation of possible channel interconnects. As further described below in at least FIGS. 4-9, the plurality of channel interconnects 108 may be implemented as and / or include a plurality of channel interconnects, a channel substrate (e.g., a fourth substrate, a patch substrate), and / or a flexible cable (e.g., a flexible substrate, a flexible board). The plurality of channel interconnects 108 may be a means for channel interconnection. At least one channel interconnect from the plurality of channel interconnects 108 is disposed between adjacent solder interconnects from the plurality of solder interconnects 190. The plurality of channel interconnects 108 may extend below the third integrated device 109.

[0015]

[0031] The multiple channel interconnects 108 between the solder interconnects help to (i) improve signal isolation within the package, (ii) untangle signal paths, (iii) reduce package thickness, (iv) improve heat dissipation, and / or (v) improve manufacturing lead times. For example, some signals can be configured to travel through electrical paths that include multiple channel interconnects 108 such that these signals do not interfere with other signals. In some implementations, signals to and / or from the integrated device 107 can be configured to travel through electrical paths that include multiple channel interconnects 108 such that these signals do not interfere with and / or are isolated from signals traveling between the integrated device 105 and the integrated device 109. This can improve the performance of the integrated device 105, the integrated device 107, the integrated device 109, and / or the package 100. Some electrical paths can include multiple channel interconnects 108 to reduce congestion and untangle paths within the second substrate 104. The use of multiple channel interconnects 108 can reduce the number of metal layers in the second substrate 104, which can help reduce the overall thickness of the second substrate 104 and / or the package 100. Using a substrate with fewer metal layers can help improve heat dissipation in the package 100, which can help improve the overall performance of the package 100.

[0016]

[0032] In some implementations, the total thickness of the second substrate 104, the plurality of solder interconnects 112, the first substrate 102, and the plurality of solder interconnects 110 may be about 510 micrometers or less. The second substrate 104 includes at least one second dielectric layer 140 and a second plurality of interconnects 142. The second substrate 104 may be an interposer. In some implementations, the second substrate 104 may have two or less metal layers. The third integrated device 109 is coupled to the second plurality of interconnects 142 of the second substrate 104 via a plurality of solder interconnects 190. The second integrated device 107 is coupled to the second plurality of interconnects 142 of the second substrate 104 via a plurality of solder interconnects 170. The second package 103 is coupled to the first package 101 via a plurality of solder interconnects 112. For example, the second substrate 104 is coupled to the first substrate 102 via a number of solder interconnects 112. The number of solder interconnects 112 may be considered part of the first package 101 and / or the second package 103.

[0017]

[0033] FIG. 2 shows a plan view of the package 100 along the line AA. FIG. 2 shows the second substrate 104, the second integrated device 107, the plurality of solder interconnects 190, and the plurality of channel interconnects 108. As shown in FIG. 2, at least one channel interconnect from the plurality of channel interconnects 108 is disposed between adjacent solder interconnects from the plurality of solder interconnects 190. The plurality of channel interconnects 108 is located on the second substrate 104. The plurality of channel interconnects 108 may conceptually represent an area in which the channel interconnects may be mounted and / or disposed within the package 100. FIG. 2 conceptually shows the plurality of channel interconnects 108 as one component. However, the plurality of channel interconnects 108 may be provided as one or more components. The plurality of channel interconnects 108 may laterally surround the second integrated device 107. The plurality of channel interconnects 108 may include one or more metal layers (e.g., one metal layer, two metal layers) to accommodate various interconnect needs and / or designs. The plurality of solder interconnects 190 may laterally surround the second integrated device 107.

[0018]

[0034] 3 illustrates possible electrical paths within the package 100. FIG. 3 illustrates electrical path 305, electrical path 306, and electrical path 307. Electrical path 305 may represent a possible electrical path for one or more signals to and / or from the second integrated device 107. Electrical path 306 may represent a possible electrical path for one or more signals to and / or from the second integrated device 107. Electrical path 307 may represent a possible electrical path for one or more signals to and / or from the first integrated device 105.

[0019]

[0035] The electrical path 305 (e.g., the first electrical path, the second electrical path, the third electrical path) may be an example of an electrical path for one or more signals between the second integrated device 107 and the first substrate 102. The electrical pathway 305 may include (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104; (ii) at least one first interconnect from the second plurality of interconnects 142 of the second substrate 104; (iii) at least one channel interconnect (e.g., a plurality of channel interconnects) from the plurality of channel interconnects 108; (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104; (v) at least one second solder interconnect from the first plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102; and (vi) at least one interconnect from the first plurality of interconnects 122 of the first substrate 102. At least one second solder interconnect from the first plurality of solder interconnects 112 that is part of the electrical path 305 may be a solder interconnect 112 disposed along the periphery of the substrate 102, substrate 104, and / or package 100. In some implementations, the solder interconnects 112 disposed along the periphery of the substrate 102 and / or substrate 104 include solder interconnects closest to one or more edges of the substrate 102 and / or substrate 104. In some implementations, the solder interconnects 112 disposed along the periphery of the substrate 102 and / or substrate 104 include a row of solder interconnects closest to one or more edges of the substrate 102 and / or substrate 104. In some implementations, the solder interconnects 112 disposed along the periphery of the substrate 102 and / or substrate 104 may include two rows of solder interconnects closest to one or more edges of the substrate 102 and / or substrate 104. The rows of solder interconnects may include rows along the X-direction and / or rows along the Y-direction of the substrate.

[0020]

[0036] The electrical pathway 305 may extend such that it is coupled to the board 106. For example, the electrical pathway 305 may also include at least one solder interconnect from the plurality of solder interconnects 110 and at least one board interconnect from the plurality of board interconnects 162. Thus, one or more signals between the board 106 and the second integrated device 107 may travel through the electrical pathway 305 as described above.

[0021]

[0037] The electrical path 306 (e.g., the first electrical path, the second electrical path, the third electrical path) may be an example of an electrical path for one or more signals between the second integrated device 107 and the first integrated device 105. The electrical pathway 306 may include (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from the second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect (e.g., multiple channel interconnects) from the plurality of channel interconnects 108, (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one solder interconnect from the plurality of solder interconnects 112, at least one interconnect from the first plurality of interconnects 122, and (vi) at least one solder interconnect from the plurality of solder interconnects 150.

[0022]

[0038] The electrical path 307 (e.g., the first electrical path, the second electrical path, the third electrical path) may be an example of an electrical path for one or more signals between the first integrated device 105 and the third integrated device 109. The electrical path 307 may include (i) at least one solder interconnect (e.g., 150) coupling the first integrated device 105 to the first substrate 102, (ii) at least one first interconnect from the first plurality of interconnects 122 of the first substrate 102, (iii) at least one solder interconnect from the plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, (iv) at least one interconnect from the second plurality of interconnects 142 of the second substrate 104, and (v) at least one solder interconnect from the plurality of solder interconnects 190 coupling the third integrated device 109 and the second substrate 104.

[0023]

[0039] FIG. 3 illustrates how electrical paths to and from channel interconnects can be implemented and configured within a package to help reduce path congestion, improve signal isolation, and untangle paths to help provide improved package performance. In one embodiment, integrated device 105 can include an application processor, integrated device 107 can include a modem, and integrated device 109 can include a memory. In some implementations, substrate 104 can include two metal layers (e.g., M1, M2). In some implementations, integrated device 107 can include one or more cores and / or one or more functions. In some implementations, different channel interconnects can be configured to be coupled to different cores and / or different functions of integrated device 107. In some implementations, multiple channel interconnects 108 are configured to be used for signals, currents, and / or grounds traveling to, from, and / or through integrated device 107.

[0024]

[0040] FIG. 4 shows a cross-sectional profile view of a package 400 including channel interconnects. The package 400 may be a package-on-package (PoP). The package 400 may be similar to the package 100 and may include similar components to the package 100. The package 400 may include a first package 101 and a second package 103. The package 400 is coupled to the board 106 via a plurality of solder interconnects 110. The package 400 includes a plurality of channel interconnects 408. The plurality of channel interconnects 408 may be an example of a plurality of interconnects 108. The plurality of channel interconnects 408 may be formed and / or disposed on the second substrate 104. The plurality of channel interconnects 408 may be coupled to the second plurality of interconnects 142. The plurality of channel interconnects 408 may be an example of a means for channel interconnection. The plurality of channel interconnects 408 may be printed (e.g., inkjet printed) on the second substrate 104. The plurality of channel interconnects 408 includes one metal layer. However, in some implementations, the plurality of channel interconnects 408 may include two or more metal layers. When there are two or more metal layers for the plurality of channel interconnects 408, a dielectric layer may be formed and disposed on a first metal layer of the plurality of channel interconnects 408, and a second metal layer may be formed on the dielectric layer and the first metal layer. The plurality of channel interconnects 408 may be defined by channel interconnects on the first metal layer and the second metal layer. In this example, the plurality of channel interconnects 408 on the first metal layer and the second metal layer on the substrate 104 may be disposed (e.g., laterally disposed) between adjacent solder interconnects from the plurality of solder interconnects 190. In some implementations, at least one dielectric layer (not shown) may be disposed on the plurality of interconnects 408. The at least one dielectric layer may include a polymer (e.g., a pure polymer). In some implementations, the dielectric layer overlying the plurality of interconnects 408 is different from the at least one dielectric layer 140 of the second substrate 104 .

[0025]

[0041] The electrical pathways 305, 306, and / or 307 described in FIG. For example, the electrical pathway 305 implemented in the package 400 may include (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from the second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect from the plurality of channel interconnects 408, (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one second solder interconnect from the first plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, and (vi) at least one interconnect from the first plurality of interconnects 122 of the first substrate 102. The electrical pathway 305 may be extended to be coupled to the board 106. For example, the electrical pathway 305 may also include at least one solder interconnect from the plurality of solder interconnects 110 and at least one board interconnect from the plurality of board interconnects 162. Thus, one or more signals between the board 106 and the second integrated device 107 may travel through the electrical pathway 305 as described above. The electrical pathway 305 may extend vertically through the substrate 102 and / or substrate 104 at the peripheral portion(s) of the substrate 102 and / or substrate 104. For example, the electrical pathway 305 may include interconnects (e.g., via interconnects) located at the peripheral portion(s) of the substrate 102 and / or substrate 104.

[0026]

[0042] The electrical path 306 implemented within the package 400 may include (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from the second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect from the plurality of channel interconnects 408, (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one solder interconnect from the plurality of solder interconnects 112 and at least one interconnect from the first plurality of interconnects 122, and (vi) at least one solder interconnect from the plurality of solder interconnects 150.

[0027]

[0043] The electrical pathways 307 implemented in the package 400 may include (i) at least one solder interconnect (e.g., 150) coupling the first integrated device 105 to the first substrate 102, (ii) at least one first interconnect from the first plurality of interconnects 122 of the first substrate 102, (iii) at least one solder interconnect from the plurality of solder interconnects 112 coupling the second substrate 104 to the first substrate 102, (iv) at least one interconnect from the second plurality of interconnects 142 of the second substrate 104, and (v) at least one solder interconnect from the plurality of solder interconnects 190 coupling the third integrated device 109 to the second substrate 104. The electrical pathways 307 may extend vertically through the substrate 102 and / or substrate 104 at a peripheral portion(s) of the substrate 102 and / or substrate 104. For example, the electrical pathway 307 may include interconnects (e.g., via interconnects) located at a peripheral portion(s) of the substrate 102 and / or substrate 104. The periphery of the substrate (e.g., 102, 104) may be defined differently. In some implementations, the peripheral portion of the substrate may include one or more portions of the substrate (e.g., including interconnects) between an edge(s) of the substrate (e.g., first edge, second edge, third edge, fourth edge) and an interior portion of the substrate that is above or below the outermost row(s) of solder interconnects relative to the center of the substrate. The rows of solder interconnects may be arranged along the X direction and / or along the Y direction. For example, the periphery of the substrate 102 may include one or more portions of the substrate 102 between the edge(s) of the substrate 102 and an interior portion located above or below the outermost row of solder interconnects 112 (e.g., the row(s) of solder interconnects closest to the edge(s) of the substrate, the row closest to the first edge, the row closest to the second edge, the row closest to the third edge, the row closest to the fourth edge).The periphery of the substrate 104 can include one or more portions of the substrate 104 between an edge or edges of the substrate 104 and an interior portion located above or below the outermost row of solder interconnects 112 (e.g., the row or rows of solder interconnects closest to the edge or edges of the substrate, the row closest to the first edge, the row closest to the second edge, the row closest to the third edge, the row closest to the fourth edge). In some implementations, the peripheral portion of the substrate can include one or more portions of the substrate between an edge or edges of the substrate and an interior portion located above or below the two outermost rows of solder interconnects 112 (e.g., the two rows of solder interconnects closest to the edge or edges of the substrate).

[0028]

[0044] FIG. 5 shows a plan view of the package 400 along the line AA. FIG. 5 shows the second substrate 104, the second integrated device 107, the plurality of solder interconnects 190, and the plurality of channel interconnects 408. As shown in FIG. 5, at least one channel interconnect from the plurality of channel interconnects 408 is disposed between adjacent solder interconnects from the plurality of solder interconnects 190. The plurality of channel interconnects 408 is located on the second substrate 104. The plurality of channel interconnects 408 can extend below the third integrated device 109. The plurality of channel interconnects 408 can include channel traces and / or channel pads. The plurality of channel interconnects 408 faces each of the four sides of the integrated device 107. For example, the first plurality of channel interconnects faces a first side of the integrated device 107, the second plurality of channel interconnects faces a second side of the integrated device 107, the third plurality of channel interconnects faces a third side of the integrated device 107, and the fourth plurality of channel interconnects faces a fourth side of the integrated device 107. However, it should be noted that the plurality of channel interconnects can face fewer than all four sides of the integrated device 107 (e.g., can face one or more sides of the integrated device). The plurality of channel interconnects 408 can laterally surround the second integrated device 107. The plurality of channel interconnects 408 can include one or more metal layers (e.g., one metal layer, two metal layers) to accommodate various interconnect needs and / or designs. The plurality of solder interconnects 190 can laterally surround the second integrated device 107.

[0029]

[0045] FIG. 6 shows a cross-sectional profile view of a package 600 including channel interconnects. The package 600 may be a package-on-package (PoP). The package 600 may be similar to the package 100 and may include similar components to the package 100. The package 600 may include a first package 101 and a second package 103. The package 600 is coupled to a board 106 via a plurality of solder interconnects 110. The package 600 includes a plurality of channel substrates 608 (e.g., a fourth substrate, a patch substrate). The plurality of channel substrates 608 may include at least one channel dielectric layer 602 and a plurality of channel interconnects 408. The plurality of channel substrates 608 may include a different number of metal layers. The plurality of channel substrates 608 may be an example of a plurality of channel interconnects 108. The plurality of channel substrates 608 may be provided on a second substrate 104. The plurality of channel substrates 608 can be coupled to the second plurality of interconnects 142 via a plurality of solder interconnects 610. For example, the plurality of channel interconnects 408 can be coupled to the second plurality of interconnects 142 via a plurality of solder interconnects 610. The plurality of channel substrates 608 can be an example of a means for channel interconnection. FIG. 6 shows the plurality of channel substrates 608 coupled to the second substrate 104 via a plurality of solder interconnects 610 (e.g., a ball grid array (BGA)). However, in some implementations, the plurality of channel substrates 608 can be coupled to the second substrate 104 via a land grid array (LGA). In some implementations, the plurality of channel interconnects 408 of the plurality of channel substrates 608 can be coupled to the second plurality of interconnects 142 without the need for solder interconnects. FIG. 6 shows the plurality of channel substrates 608 including one metal layer. However, in some implementations, a multiple channel substrate 608 may include multiple channel interconnects 408 on two or more metal layers.

[0030]

[0046] 3 may be implemented in a package 600. For example, the electrical pathway 305 implemented in the package 600 may include (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from the second plurality of interconnects 142 of the second substrate 104, and (iii) at least one channel interconnect from the plurality of channel interconnects 408 of the second substrate 104 (e.g., 170). 10), (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one second solder interconnect from the first plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, and (vi) at least one interconnect from the first plurality of interconnects 122 of the first substrate 102. The electrical pathway 305 may be extended to be coupled to the board 106. For example, the electrical pathway 305 may also include at least one solder interconnect from the plurality of solder interconnects 110 and at least one board interconnect from the plurality of board interconnects 162. Thus, one or more signals between the board 106 and the second integrated device 107 may travel through the electrical pathway 305 as described above.

[0031]

[0047] The electrical pathway 306 implemented within the package 600 may include (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104; (ii) at least one first interconnect from the second plurality of interconnects 142 of the second substrate 104; (iii) at least one channel interconnect from the plurality of channel interconnects 408 from the plurality of channel substrates 608 (which may also include (in and out) solder interconnects from the plurality of solder interconnects 610); (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104; (v) at least one solder interconnect from the plurality of solder interconnects 112 and at least one interconnect from the first plurality of interconnects 122; and (vi) at least one solder interconnect from the plurality of solder interconnects 150.

[0032]

[0048] The electrical path 307 implemented within the package 600 may include (i) at least one solder interconnect (e.g., 150) coupling the first integrated device 105 to the first substrate 102, (ii) at least one first interconnect from the first plurality of interconnects 122 of the first substrate 102, (iii) at least one solder interconnect from the plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, (iv) at least one interconnect from the second plurality of interconnects 142 of the second substrate 104, and (v) at least one solder interconnect from the plurality of solder interconnects 190 coupling the third integrated device 109 and the second substrate 104.

[0033]

[0049] FIG. 7 shows a plan view of the package 600 along the line AA. FIG. 7 shows the second substrate 104, the second integrated device 107, the solder interconnects 190, and the channel substrates 608. As shown in FIG. 7, at least some of the channel interconnects 408 from the channel substrates 608 are disposed between adjacent solder interconnects from the solder interconnects 190. The channel interconnects 408 from the channel substrates 608 and the channel substrates 608 are located on the second substrate 104. The channel interconnects 408 can extend below the third integrated device 109. The channel interconnects 408 can include channel traces and / or channel pads. The channel substrates 608 face each of the four sides of the integrated device 107. For example, a first multiple channel substrate faces a first side of the integrated device 107, a second multiple channel substrate faces a second side of the integrated device 107, a third multiple channel substrate faces a third side of the integrated device 107, and a fourth multiple channel substrate faces a fourth side of the integrated device 107. However, it should be noted that the multiple channel substrates can face fewer than all four sides of the integrated device 107 (e.g., can face one or more sides of the integrated device). A plurality of channel interconnects 408 faces each of the four sides of the integrated device 107. For example, the first plurality of channel interconnects faces a first side of the integrated device 107, the second plurality of channel interconnects faces a second side of the integrated device 107, the third plurality of channel interconnects faces a third side of the integrated device 107, and the fourth plurality of channel interconnects faces a fourth side of the integrated device 107. However, it should be noted that the plurality of channel interconnects can face fewer than all four sides of the integrated device 107 (e.g., can face one or more sides of the integrated device). The plurality of channel substrates 608 can laterally surround the second integrated device 107.The multiple channel substrates 608 can include one or multiple metal layers (e.g., one metal layer, two metal layers) to accommodate various interconnect needs and / or designs. The multiple solder interconnects 190 can laterally surround the second integrated device 107.

[0034]

[0050] FIG. 8 illustrates a cross-sectional profile view of a package 800 including channel interconnects. The package 800 may be a package-on-package (PoP). The package 800 may be similar to the package 100 and may include similar components to the package 100. The package 800 may include a first package 101 and a second package 103. The package 800 is coupled to a board 106 via a plurality of solder interconnects 110. The package 800 includes a plurality of flexible cables 808 (e.g., flexible substrates, flexible boards, flexible printed circuit boards). The plurality of flexible cables 808 may include at least one flexible dielectric layer 802 and a plurality of channel interconnects 408. The at least one flexible dielectric layer 802 may include polyimide. The plurality of flexible cables 808 may include a different number of metal layers. The plurality of flexible cables 808 may be an example of a plurality of channel interconnects 108. The plurality of flexible cables 808 may be provided on a second substrate 104. The plurality of flexible cables 808 can be coupled to the second plurality of interconnects 142 via a plurality of solder interconnects 810. For example, the plurality of channel interconnects 408 can be coupled to the second plurality of interconnects 142 via a plurality of solder interconnects 810. The plurality of flexible cables 808 can be one example of a means for channel interconnection. FIG. 8 illustrates the plurality of flexible cables 808 including one metal layer. However, in some implementations, the plurality of flexible cables 808 can include the plurality of channel interconnects 408 on two or more metal layers.

[0035]

[0051] 3 may be implemented in a package 800. For example, the electrical pathways 305 implemented in the package 800 may include (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from the second plurality of interconnects 142 of the second substrate 104, and (iii) at least one channel interconnect from the plurality of channel interconnects 408 from the plurality of flexible cables 808 (e.g., multiple solder interconnects 170). 810), (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one second solder interconnect from the first plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, and (vi) at least one interconnect from the first plurality of interconnects 122 of the first substrate 102. The electrical pathway 305 may be extended to be coupled to the board 106. For example, the electrical pathway 305 may also include at least one solder interconnect from the plurality of solder interconnects 110 and at least one board interconnect from the plurality of board interconnects 162. Thus, one or more signals between the board 106 and the second integrated device 107 may travel through the electrical pathway 305 as described above.

[0036]

[0052] The electrical pathway 306 implemented within the package 800 may include (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104; (ii) at least one first interconnect from the second plurality of interconnects 142 of the second substrate 104; (iii) at least one channel interconnect from the plurality of channel interconnects 408 from the plurality of flexible cables 808 (which may also include (inner and outer) solder interconnects from the plurality of solder interconnects 810); (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104; (v) at least one solder interconnect from the plurality of solder interconnects 112 and at least one interconnect from the first plurality of interconnects 122; and (vi) at least one solder interconnect from the plurality of solder interconnects 150.

[0037]

[0053] The electrical path 307 implemented within the package 800 may include (i) at least one solder interconnect (e.g., 150) coupling the first integrated device 105 to the first substrate 102, (ii) at least one first interconnect from the first plurality of interconnects 122 of the first substrate 102, (iii) at least one solder interconnect from the plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, (iv) at least one interconnect from the second plurality of interconnects 142 of the second substrate 104, and (v) at least one solder interconnect from the plurality of solder interconnects 190 coupling the third integrated device 109 and the second substrate 104.

[0038]

[0054] FIG. 9 shows a plan view of the package 800 along the line AA. FIG. 9 shows the second substrate 104, the second integrated device 107, the solder interconnects 190, and the flexible cables 808. As shown in FIG. 9, at least some of the channel interconnects 408 from the flexible cables 808 are disposed between adjacent solder interconnects from the solder interconnects 190. The channel interconnects 408 from the flexible cables 808 and the flexible cables 808 are located on the second substrate 104. The channel interconnects 408 can extend below the third integrated device 109. The channel interconnects 408 can include channel traces and / or channel pads. The flexible cables 808 face each of the four sides of the integrated device 107. For example, a first of the plurality of flexible cables faces a first side of the integrated device 107, a second of the plurality of flexible cables faces a second side of the integrated device 107, a third of the plurality of flexible cables faces a third side of the integrated device 107, and a fourth of the plurality of flexible cables faces a fourth side of the integrated device 107. However, it should be noted that the plurality of flexible cables may face fewer than all four sides of the integrated device 107 (e.g., may face one or more sides of the integrated device). A plurality of channel interconnects 408 faces each of the four sides of the integrated device 107. For example, a first plurality of channel interconnects faces a first side of the integrated device 107, a second plurality of channel interconnects faces a second side of the integrated device 107, a third plurality of channel interconnects faces a third side of the integrated device 107, and a fourth plurality of channel interconnects faces a fourth side of the integrated device 107. However, it should be noted that the plurality of channel interconnects can face fewer than all four sides of the integrated device 107 (e.g., can face one or more sides of the integrated device). The plurality of flexible cables 808 can laterally surround the second integrated device 107.The multiple flexible cables 808 can include one or multiple metal layers (e.g., one metal layer, two metal layers) to accommodate various interconnect needs and / or designs. The multiple solder interconnects 190 can laterally surround the second integrated device 107.

[0039]

[0055] 10 shows a cross-sectional profile view of a package 1000 including channel interconnects. The package 1000 may be a package-on-package (PoP). The package 1000 may be similar to the package 100 and may include similar components to the package 100. The package 1000 may include a first package 101 and a second package 103. The package 1000 is coupled to a board 106 via a plurality of solder interconnects 110.

[0040]

[0056] The package 1000 includes a plurality of channel interconnects 108, a plurality of channel interconnects 1008, and a plurality of channel interconnects 1009. The plurality of channel interconnects 1008 may be implemented as a plurality of channel interconnects 408, a plurality of channel substrates 608, and / or a plurality of flexible cables 808, as described in FIGS. 4-9. Similarly, the plurality of channel interconnects 1009 may be implemented as a plurality of channel interconnects 408, a plurality of channel substrates 608, and / or a plurality of flexible cables 808, as described in FIGS. 4-9. The plurality of channel interconnects 1008 are coupled to a first surface (e.g., a top surface) of the first substrate 102. The plurality of channel interconnects 1009 are coupled to a second surface (e.g., a bottom surface) of the second substrate 104.

[0041]

[0057] The electrical pathway 1005 (e.g., first electrical pathway, second electrical pathway) may include a plurality of channel interconnects 1008 (e.g., a plurality of channel interconnects 408). For example, at least one signal traveling through the electrical pathway 1005 may enter and exit the plurality of channel interconnects 1008 (e.g., a plurality of channel interconnects 408) through the first plurality of interconnects 122 of the first substrate 102 (e.g., enter and exit through a first surface of the first substrate 102). In some implementations, the electrical pathway 1005 may be implemented with the electrical pathway 305, the electrical pathway 306, and / or the electrical pathway 307. The electrical pathway 1005 may be part of an electrical pathway (e.g., 305, 306, 307) coupled to the first integrated device 105, the second integrated device 107, and / or the third integrated device 109.

[0042]

[0058] The electrical pathway 1006 (e.g., first electrical pathway, second electrical pathway) can include a plurality of channel interconnects 1009 (e.g., a plurality of channel interconnects 408). For example, at least one signal traveling through the electrical pathway 1006 can enter and exit the plurality of channel interconnects 1009 (e.g., a plurality of channel interconnects 408) through the second plurality of interconnects 142 of the second substrate 104 (e.g., enter and exit through the second surface of the second substrate 104). In some implementations, the electrical pathway 1005 can be implemented with the electrical pathway 305, the electrical pathway 306, and / or the electrical pathway 307. The electrical pathway 1006 can be part of an electrical pathway (e.g., 305, 306, 307) coupled to the first integrated device 105, the second integrated device 107, and / or the third integrated device 109.

[0043]

[0059] The multiple channel interconnects (e.g., 108, 1006, 1008) described in this disclosure can be implemented as part of a package that includes one substrate, two substrates, or three or more substrates. The substrate may include one or more channel interconnects on one surface (e.g., top, bottom) or both surfaces of the substrate. In some implementations, the package may include different designs and / or variations of the multiple channel interconnects. For example, a combination of substrate and flexible cable may be used with the substrate. The multiple channel interconnects can have different sizes and / or shapes. The multiple channel interconnects may have different numbers of channel interconnects.

[0044]

[0060] The integrated devices (e.g., 105, 107, 109) may include a die (e.g., a semiconductor bare die). The integrated devices may include a power management integrated circuit (PMIC). The integrated devices may include an application processor. The integrated devices may include a modem. The integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memories, power management processors, and / or combinations thereof. The integrated devices (e.g., 105, 107, 109) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated devices may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device.

[0045]

[0061] The packages (e.g., 100, 400, 600, 800) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The packages (e.g., 100, 400, 600, 800) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The packages (e.g., 100, 400, 600, 800) may be configured to support Global System for Mobile (GSM) communications, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The packages (e.g., 100, 400) may be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0046]

[0062] Having described the various packages, the sequence for manufacturing the packages will now be described below.

[0047] Exemplary sequence for manufacturing a package with channel interconnects

[0063] In some implementations, manufacturing the package includes several processes. Figures 11A-11C show an example sequence for providing or manufacturing a package including channel interconnects. In some implementations, the sequence of Figures 11A-11C can be used to provide or manufacture package 400. However, the process of Figures 11A-11C can be used to manufacture any of the packages described in this disclosure (e.g., 100, 1000).

[0048]

[0064] Note that the sequences in FIGS. 11A-11C can combine one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0049]

[0065] As shown in FIG. 11A, step 1 shows the state after substrate 102 is prepared. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 can include a first surface (e.g., the top surface) and a second surface (e.g., the bottom surface). Substrate 102 can be manufactured using the methods described in FIGS. 14A-14B. In some embodiments, a core substrate (e.g., a substrate including a core layer) is prepared.

[0050]

[0066] Step 2 shows the state after the first integrated device 105 is coupled to the first surface (e.g., the top surface) of substrate 102. The first integrated device 105 can be coupled to substrate 102 via a plurality of solder interconnects 150. A solder reflow process can be used to couple the first integrated device 105 to substrate 102.

[0051]

[0067] Step 3 shows the state after substrate 104 is coupled to substrate 102 via a plurality of solder interconnects 112. A solder reflow process can be used to couple substrate 104 to substrate 102. Substrate 104 is coupled to substrate 102 such that the first integrated device 105 is positioned between substrate 102 and substrate 104. Substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. Substrate 104 can be manufactured using the methods described in FIGS. 14A-14B. Substrate 104 can be an interposer.

[0052]

[0068] 11B, stage 4 shows the state after a plurality of channel interconnects 408 are formed on the first surface of the second substrate 104. The plurality of channel interconnects 408 may be bonded to the second plurality of interconnects 142. The plurality of channel interconnects 408 may be printed (e.g., inkjet printed) on the second substrate 104. An additional metal layer of the plurality of channel interconnects 408 may be formed on the substrate 104. One or more dielectric layers may be formed on the plurality of channel interconnects 408.

[0053]

[0069] Stage 5 shows the state after the second integrated device 107 has been bonded to a first surface (e.g., top surface) of the substrate 104. The second integrated device 107 may be bonded to the substrate 104 via a number of solder interconnects 170. A solder reflow process may be used to bond the second integrated device 107 to the substrate 104.

[0054]

[0070] As shown in FIG. 11C, stage 6 illustrates a state after the third integrated device 109 is coupled to a first surface (e.g., top surface) of the substrate 104. The third integrated device 109 can be coupled to the substrate 104 via a plurality of solder interconnects 190. A solder reflow process can be used to couple the third integrated device 109 to the substrate 104. The third integrated device 109 can be disposed on top of the second integrated device 107. The second integrated device 107 can be disposed between the third integrated device 109 and the substrate 104. At least one channel interconnect from the plurality of channel interconnects 408 can be disposed between solder interconnects from the plurality of solder interconnects 190. The plurality of solder interconnects 190 can laterally surround the second integrated device 107.

[0055]

[0071] Step 7 shows the state after a plurality of solder interconnects 110 are coupled to the second surface of the substrate 102. The plurality of solder interconnects 110 can be coupled to the substrate 102 using a solder reflow process. Step 7 can show a package 400 that includes a plurality of channel interconnects 408, at least as described in FIG. 4. The packages 400 may be manufactured one at a time, or may be manufactured partially or wholly together as part of one or more strips or panels and then assembled or singulated into individual packages.

[0056] Exemplary sequence for manufacturing a package with channel interconnects

[0072] In some implementations, manufacturing the package includes several processes. FIGS. 12A-12C show an exemplary sequence for providing or manufacturing a package that includes channel interconnects. In some implementations, the sequence of FIGS. 12A-12C can be used to provide or manufacture a package 600. However, the processes of FIGS. 12A-12C can be used to manufacture any of the packages described in this disclosure (e.g., 800, 1000).

[0057]

[0073] Note that the sequence of FIGS. 12A-12C can combine one or more steps to simplify and / or clarify the sequence for providing or manufacturing the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of this disclosure.

[0058]

[0074] As shown in FIG. 12A, stage 1 illustrates the state after a substrate 102 is prepared. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 102 may be manufactured using the methods described in FIGS. 14A-B. In some implementations, a core substrate (e.g., a substrate including a core layer) is prepared.

[0059]

[0075] Stage 2 shows the state after the first integrated device 105 has been bonded to a first surface (e.g., top surface) of the substrate 102. The first integrated device 105 may be bonded to the substrate 102 via a number of solder interconnects 150. A solder reflow process may be used to bond the first integrated device 105 to the substrate 102.

[0060]

[0076] Stage 3 shows the state after the substrate 104 is bonded to the substrate 102 via the plurality of solder interconnects 112. A solder reflow process can be used to bond the substrate 104 to the substrate 102. The substrate 104 is bonded to the substrate 102 such that the first integrated device 105 is located between the substrate 102 and the substrate 104. The substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The substrate 104 can be manufactured using the method described in Figures 14A-14B. The substrate 104 can be an interposer.

[0061]

[0077] 12B, stage 4 shows the state after the multiple channel substrate 608 is bonded to the first surface of the second substrate 104. The multiple channel substrate 608 can include multiple channel interconnects 408. The multiple channel interconnects 408 can be bonded to the second multiple interconnects 142 via multiple solder interconnects 610. In some implementations, the multiple channel interconnects 408 from the multiple channel substrate 608 can be bonded to the substrate 104 via a land grid array (LGA).

[0062]

[0078] In some implementations, instead of or in addition to the multiple channel substrate 608, the multiple flexible cables 808 can be coupled to the first surface of the second substrate 104. In some implementations, the multiple channel substrate 608 and / or the multiple flexible cables 808 can be coupled to the second surface of the second substrate 104 and / or the first surface of the substrate 102. The multiple channel substrate 608 and / or the multiple flexible cables 808 can be coupled to the second surface of the second substrate 104 and / or the first surface of the substrate 102 before the substrate 104 is coupled to the substrate 102.

[0063]

[0079] Stage 5 shows the state after the second integrated device 107 has been bonded to a first surface (e.g., top surface) of the substrate 104. The second integrated device 107 may be bonded to the substrate 104 via a number of solder interconnects 170. A solder reflow process may be used to bond the second integrated device 107 to the substrate 104.

[0064]

[0080] As shown in FIG. 12C, stage 6 illustrates a state after the third integrated device 109 is bonded to a first surface (e.g., top surface) of the substrate 104. The third integrated device 109 can be bonded to the substrate 104 via a plurality of solder interconnects 190. A solder reflow process can be used to bond the third integrated device 109 to the substrate 104. The third integrated device 109 can be disposed on top of the second integrated device 107. The second integrated device 107 can be disposed between the third integrated device 109 and the substrate 104. A plurality of channel interconnects 408 from the plurality of channel substrates 608 can be disposed between the solder interconnects from the plurality of solder interconnects 190. The plurality of solder interconnects 190 can laterally surround the second integrated device 107.

[0065]

[0081] Stage 7 shows the condition after the plurality of solder interconnects 110 have been bonded to the second surface of the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 110 to the substrate 102. Stage 7 may show a package 600 including a plurality of channel substrates 608 including a plurality of channel interconnects 408, at least as described in FIG. 6. The packages 600 may be manufactured one at a time, or may be manufactured partially or wholly together as part of one or more strips or panels and then assembled or singulated into individual packages.

[0066] 1 is an exemplary flow diagram of a method for manufacturing a package with channel interconnects;

[0082] In some implementations, manufacturing the package includes several processes. Figure 13 shows an example flow diagram of a method 1300 for providing or manufacturing a package with channel interconnects. In some implementations, the method 1300 of Figure 13 can be used to provide or manufacture the packages 100, 400, 600, 800, and / or 1000 described in this disclosure. The method 1300 can be used to provide or manufacture any of the packages described in this disclosure.

[0067]

[0083] It should be noted that the method of Figure 13 may combine one or more processes to simplify and / or clarify the method of providing or manufacturing the package. In some implementations, the order of the processes may be changed or modified.

[0068]

[0084] The method provides (at 1305) a first substrate (e.g., 102) and a first integrated device (e.g., 105) coupled to a first surface of the first substrate (e.g., 102). The first substrate 102 and the first integrated device 105 may be part of a first package 101. The first substrate 102 includes at least a first dielectric layer 120 and a first plurality of interconnects 122. Step 2 of FIG. 11A illustrates and describes an example of a first substrate having a first integrated device. Step 2 of FIG. 12A illustrates and describes an example of a first substrate having a first integrated device.

[0069]

[0085] The method includes (at 1310) bonding a second substrate (e.g., 104) to a first substrate (e.g., 102) via a plurality of solder interconnects (e.g., 112). The second substrate may include an interposer. The second substrate 104 includes at least one second dielectric layer 140 and a second plurality of interconnects 142. A solder reflow process may be used to bond the second substrate to the first substrate. Step 3 of FIG. 11A illustrates and describes an example of a second substrate bonded to a first substrate. Step 3 of FIG. 12A illustrates and describes an example of a second substrate bonded to a first substrate.

[0070]

[0086] The method prepares (at 1315) a plurality of channel interconnects on a first surface (e.g., a top surface) of the second substrate 104. Different implementations may prepare the plurality of channel interconnects differently. In some implementations, the plurality of channel interconnects 408 are formed on the second substrate 104 by a printing process (e.g., an inkjet printing process), as described in step 4 of FIG. 11B. In some implementations, the plurality of channel interconnects 408 are part of a plurality of channel substrates 608 coupled to the second substrate 104, as described in step 4 of FIG. 12B. In some implementations, the plurality of channel interconnects 408 are part of a plurality of flexible cables 808 coupled to the second substrate 104, as described in step 4 of FIG. 12B. It should be noted that the method may prepare the plurality of channel interconnects on and / or under different surfaces of the first substrate 102 and / or the second substrate 104.

[0071]

[0087] The method includes (at 1320) coupling a second integrated device (e.g., 107) to a first surface of a second substrate (e.g., 104) via a plurality of solder interconnects (e.g., 170). A solder reflow process may be used to couple the second integrated device to the first surface of the second substrate 104. Step 5 of FIG. 11B illustrates and describes one example of a second integrated device coupled to the second substrate. Step 5 of FIG. 12B illustrates and describes one example of a second integrated device coupled to the second substrate.

[0072]

[0088] The method couples (at 1325) a third integrated device (e.g., 109) to a first surface of a second substrate (e.g., 104) via a plurality of solder interconnects (e.g., 190). A solder reflow process can be used to couple the third integrated device to the first surface of the second substrate 104. The third integrated device 109 can be disposed on the second integrated device 107. The second integrated device 107 can be disposed between the third integrated device 109 and the substrate 104. The plurality of channel interconnects 408 can be disposed between the solder interconnects from the plurality of solder interconnects 190. The plurality of channel interconnects 408 from the plurality of channel substrates 608 can be disposed between the solder interconnects from the plurality of solder interconnects 190. The plurality of channel interconnects 408 from the plurality of flexible cables 808 can be disposed between the solder interconnects from the plurality of solder interconnects 190. A plurality of solder interconnects 190 may laterally surround the second integrated device 107 .

[0073]

[0089] In some implementations, several packages are manufactured simultaneously. In such cases, the method can singulate (at 1330) the packages (e.g., 100, 400, 600, 800, 1000). In other cases, singulation occurs before the substrates are bonded together.

[0074] Exemplary Sequence for Manufacturing a Substrate

[0090] In some implementations, manufacturing a substrate includes several processes. Figures 14A-14B show an example sequence for providing or manufacturing a substrate. In some implementations, the sequence of Figures 14A-14B can be used to provide or manufacture substrate 102. However, the process of Figures 14A-14B can be used to manufacture any of the substrates described in this disclosure, such as substrate 104 and / or channel substrate 608.

[0075]

[0091] Note that the sequences of FIGS. 14A - 14B can combine one or more steps to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the process can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0076]

[0092] Stage 1, as shown in FIG. 14A, shows the state after carrier 1400 is provided. Seed layer 1401 and interconnect 1402 can be disposed on carrier 1400. Interconnect 1402 can be disposed on seed layer 1401. An electroplating process and an etching process can be used to form interconnect 1402. In some implementations, carrier 1400 can be provided with seed layer 1401 and a metal layer patterned to form interconnect 1402. Interconnect 1402 can represent at least some of the interconnects from a plurality of interconnects 122.

[0077]

[0093] Stage 2 shows the state after dielectric layer 1420 is formed over first carrier 1400, seed layer 1401, and interconnect 1402. A deposition process and / or a lamination process can be used to form dielectric layer 1420. Dielectric layer 1420 can include a prepreg and / or polyimide. Dielectric layer 1420 can include a photoimageable dielectric. However, different implementations can use different materials for the dielectric layer.

[0078]

[0094] Stage 3 shows the state after a plurality of cavities 1410 are formed in dielectric layer 1420. The plurality of cavities 1410 can be formed using an etching process (e.g., a photolithography etching process) or a laser process.

[0079]

[0095] Stage 4 shows the state after interconnects 1412 have been formed in and on dielectric layer 1420, including in and over the plurality of cavities 1410. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0080]

[0096] Stage 5 shows the state after the dielectric layer 1422 is formed over the dielectric layer 1420 and the interconnects 1412. A deposition process and / or lamination process may be used to form the dielectric layer 1422. The dielectric layer 1422 may include prepreg and / or polyimide. The dielectric layer 1422 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0081]

[0097] 14B, stage 6 shows the state after a plurality of cavities 1430 are formed in the dielectric layer 1422. The plurality of cavities 1430 can be formed using an etching process (e.g., a photoetching process) or a laser process.

[0082]

[0098] Stage 7 shows the state after interconnects 1414 are formed in and on dielectric layer 1422, including in and over cavities 1430. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects. Interconnects 1402, 1412, and / or 1414 may be represented by interconnects 122. Dielectric layer 1420 and / or 1422 may be represented by at least one dielectric layer 120. At least one dielectric layer 120 may include a photoimageable dielectric. At least one dielectric layer 120 may include a prepreg and / or a polyimide.

[0083]

[0099] Stage 8 shows the state after the carrier 1400 has been separated (e.g., detached, removed, ground) from the at least one dielectric layer 120 and the seed layer 1401, and a portion of the seed layer 1401 has been removed (e.g., etched away), leaving behind the substrate 102 including at least one dielectric layer 120 and multiple interconnects 122.

[0084]

[0100] In some implementations, the substrate may include a solder resist layer(s). Stage 9 shows the state after solder resist layer 124 and solder resist layer 126 are formed on substrate 102. A deposition process may be used to form solder resist layer 124 and solder resist layer 126. In some implementations, zero or one solder resist layer may be formed on at least one dielectric layer 120.

[0085]

[0101] Different implementations may use different processes to form the metal layer(s) and / or the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0086] 1 is an exemplary flow diagram of a method for manufacturing a substrate;

[0102] In some implementations, manufacturing a substrate includes several processes. Figure 15 shows an example flow diagram of a method 1500 for providing or manufacturing a substrate. In some implementations, the method 1500 of Figure 15 can be used to provide or manufacture a substrate or substrates of the present disclosure. For example, the method 1500 of Figure 15 can be used to manufacture the substrate 102.

[0087]

[0103] It should be noted that the method 1500 of Figure 15 may combine one or more processes to simplify and / or clarify the method of providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0088]

[0104] The method includes (at 1505) preparing a carrier (e.g., 1400). Different implementations can use different materials for the carrier 1400. The carrier 1400 can include a seed layer (e.g., 1401). The seed layer 1401 can include a metal (e.g., copper). The carrier can include a substrate, glass, quartz, and / or a carrier tape. Step 1 of FIG. 14A illustrates and describes one example of a carrier with a prepared seed layer.

[0089]

[0105] The method forms and patterns (at 1510) interconnects on the carrier 1400 and the seed layer 1401. A metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer may include a metal layer. The metal layer is disposed on the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 402). Step 1 of FIG. 14A illustrates and describes an example of forming and patterning interconnects on a seed layer and a carrier.

[0090]

[0106] The method forms (at 1515) a dielectric layer 1420 over the seed layer 1401, the carrier 1400, and the interconnects 1402. A deposition process and / or a lamination process may be used to form the dielectric layer 1420. The dielectric layer 1420 may include prepreg and / or polyimide. The dielectric layer 1420 may include a photoimageable dielectric. Forming the dielectric layer 1420 may also include forming a plurality of cavities (e.g., 1410) in the dielectric layer 1420. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 2-3 of FIG. 14A illustrate and describe an example of forming a dielectric layer and cavities in the dielectric layer.

[0091]

[0107] The method forms (at 1520) interconnects in and on the dielectric layer. For example, interconnects 1412 can be formed in and on the dielectric layer 1420. A plating process can be used to form the interconnects. Forming the interconnects can include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnects can also include forming the interconnects in cavities in the dielectric layer. Step 4 of FIG. 14A illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0092]

[0108] The method forms (at 1525) a dielectric layer 1422 over the dielectric layer 1420 and the interconnects 1412. A deposition process and / or a lamination process may be used to form the dielectric layer 1422. The dielectric layer 1422 may include prepreg and / or polyimide. The dielectric layer 1422 may include a photoimageable dielectric. Forming the dielectric layer 1422 may also include forming a plurality of cavities (e.g., 1430) in the dielectric layer 1422. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 5-6 of Figures 14A-14B illustrate and describe an example of forming the dielectric layer and the cavities in the dielectric layer.

[0093]

[0109] The method forms (at 1530) interconnects in and on the dielectric layer. For example, interconnects 1414 can be formed in and on dielectric layer 1422. A plating process can be used to form the interconnects. Forming the interconnects can include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnects can also include forming the interconnects in cavities in the dielectric layer. Step 7 of FIG. 14B illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0094]

[0110] The method separates (at 1535) the carrier (e.g., 1400) from the seed layer (e.g., 1401). The carrier 1400 may be removed and / or ground. The method may also remove (at 1535) a portion of the seed layer (e.g., 1401). An etching process may be used to remove a portion of the seed layer 1401. Step 8 of Figure 14B illustrates and describes one example of carrier separation and seed layer removal.

[0095]

[0111] In some implementations, the method can form a solder resist layer(s) on the first surface and / or the second surface of the substrate. Step 9 of Figure 14B illustrates and describes one example of forming the solder resist layer(s).

[0096]

[0112] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0097] Exemplary Electronic Devices

[0113] FIG. 16 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1602, a laptop computer device 1604, a fixed location terminal device 1606, a wearable device 1608, or an autonomous vehicle 1610 may include a device 1600 as described herein. The device 1600 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1602, 1604, 1606, and 1608 and the vehicle 1610 illustrated in FIG. 16 are merely illustrative. Other electronic devices may also feature device 1600, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0098]

[0114] One or more of the components, processes, features, and / or functions shown in Figures 1-10, 11A-11C, 12A-12C, 13, 14A-14B, and 15-16 may be rearranged and / or combined into a single component, process, feature, or function, or may be combined into several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from the present disclosure. It is also noted that Figures 1-10, 11A-11C, 12A-12C, 13, 14A-14B, and 15-16 in this disclosure and corresponding descriptions thereof are not limited to dies and / or ICs. 1-10, 11A-11C, 12A-12C, 13, 14A-14B, and 15-16, and corresponding descriptions thereof, may be used to manufacture, fabricate, provide, and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0099]

[0115] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0100]

[0116] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even though they are not in direct physical contact with each other. Object A that is coupled to object B can be coupled to at least a portion of object B. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not propagate a current between the two objects. The use of the terms "first", "second", "third" and "fourth" (and / or anything more than fourth) is optional. Any of the components described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can also be a first component, a second component, a third component, or a fourth component. The terms "encapsulate", "encapsulating" and / or derivatives thereof mean that an object may partially encapsulate or completely encapsulate another object. As used in this disclosure, a first object surrounding a second object can mean that the first object partially surrounds the second object or completely surrounds the second object. The terms "top" and "bottom" are optional. A component located at the top may be located above a component located at the bottom.A top component may also be considered a bottom component, and vice versa. As described in this disclosure, a first component disposed "over" a second component may mean that the first component is disposed above or below the second component, depending on how bottom or top is arbitrarily defined. In another embodiment, a first component may be disposed above (e.g., above) a first surface of the second component, and a third component may be disposed above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being disposed above another component, the term "over" as used in this application may be used to mean a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but is not in direct contact with the second component, (2) that the first component is present on the second component (e.g., on a surface of the second component), and / or (3) that the first component is present within the second component (e.g., embedded within the second component). A first component that is disposed "in" a second component can be partially disposed within the second component or can be completely disposed within the second component. A value that is about X to XX can mean a value between and including X and XX. The value or values ​​between X and XX can be discrete or continuous. The term "about 'value X'" or "approximately value X" as used in this disclosure means within a range of 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0101]

[0117] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace (e.g., a trace interconnect), a via (e.g., a via interconnect), a pad (e.g., a pad interconnect), a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, the interconnects may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process.

[0102]

[0118] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. In addition, the order of steps may be rearranged. A process is terminated when its operations are completed.

[0103]

[0119] In the following, further examples are described to facilitate understanding of the invention.

[0104]

[0120] Aspect 1: A device comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package includes a first substrate comprising at least a first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least a second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate via the second plurality of solder interconnects, and a first plurality of channel interconnects coupled to the first surface of the second substrate, the first plurality of channel interconnects being located between solder interconnects from the second plurality of solder interconnects.

[0105]

[0121] Embodiment 2: The device of embodiment 1, wherein the second integrated device is located between the third integrated device and the second substrate.

[0106]

[0122] Example 3: The device of example 1 or 2, further comprising a fourth substrate bonded to the first surface of the second substrate, the first plurality of channel interconnects being part of the fourth substrate.

[0107]

[0123] Example 4: The device of any one of Examples 1 to 3, further comprising a flexible cable coupled to the first surface of the second substrate, the first plurality of channel interconnects being part of the flexible cable.

[0108]

[0124] Embodiment 5: A device according to any one of embodiments 1 to 4, wherein the first plurality of channel interconnects extends underneath the third integrated device.

[0109]

[0125] Embodiment 6: A device described in any one of embodiments 1 to 5, wherein the first electrical pathway between the second integrated device and the first substrate comprises a first plurality of channel interconnects.

[0110]

[0126] Aspect 7: The device of any one of aspects 1 to 6, wherein the first electrical pathway between the second integrated device and the first substrate includes at least one first solder interconnect coupling the second integrated device to the second substrate, at least one first interconnect from the second plurality of interconnects of the second substrate, at least one channel interconnect from the first plurality of channel interconnects, at least one second interconnect from the second plurality of interconnects of the second substrate, at least one second solder interconnect from the first plurality of solder interconnects coupling the second substrate and the first substrate, and at least one interconnect from the first plurality of interconnects of the first substrate.

[0111]

[0127] Example 8: The device of any one of Examples 1 to 7, further comprising a second plurality of channel interconnects coupled to the second surface of the second substrate.

[0112]

[0128] Example 9: The device of any one of Examples 1 to 8, further comprising a second plurality of channel interconnects coupled to the first surface of the first substrate.

[0113]

[0129] Example 10: The device of example 8 or 9, wherein the second plurality of channel interconnects is part of a fourth substrate and / or flexible cable.

[0114]

[0130] Aspect 11: An apparatus comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package comprises a first substrate comprising at least a first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package comprises a second substrate comprising at least a second dielectric layer and a second plurality of interconnects, a second integrated device coupled to the first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate via the second plurality of solder interconnects, and a means for channel interconnection coupled to the first surface of the second substrate, the means for channel interconnection being located between solder interconnects from the second plurality of solder interconnects.

[0115]

[0131] Example 12: An apparatus as described in example 11, wherein the second integrated device is located between the third integrated device and the second substrate.

[0116]

[0132] Embodiment 13: A device according to embodiment 11 or 12, wherein the means for channel interconnection comprises a fourth substrate.

[0117]

[0133] Embodiment 14: An apparatus according to any one of embodiments 11 to 13, wherein the means for channel interconnection comprises a flexible cable.

[0118]

[0134] Embodiment 15: An apparatus according to any one of embodiments 11 to 14, wherein the means for channel interconnection extends below the third integrated device.

[0119]

[0135] Embodiment 16: An apparatus described in any one of embodiments 11 to 15, wherein the first electrical pathway between the second integrated device and the first substrate comprises a means for channel interconnection.

[0120]

[0136] Example 17: An apparatus described in any one of Examples 11 to 16, wherein the first electrical pathway between the second integrated device and the first substrate includes at least one first solder interconnect coupling the second integrated device to the second substrate, at least one first interconnect from the second plurality of interconnects of the second substrate, means for channel interconnection, at least one second interconnect from the second plurality of interconnects of the second substrate, at least one second solder interconnect from the first plurality of solder interconnects coupling the second substrate and the first substrate, and at least one interconnect from the first plurality of interconnects of the first substrate.

[0121]

[0137] Embodiment 18: An apparatus according to any one of embodiments 11 to 17, further comprising a second means for channel interconnection coupled to the second surface of the second substrate.

[0122]

[0138] Embodiment 19: An apparatus according to any one of embodiments 11 to 18, further comprising a second means for channel interconnection coupled to the first surface of the first substrate.

[0123]

[0139] Aspect 20: The apparatus of any one of aspects 11 to 19, wherein the apparatus comprises a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an autonomous vehicle.

[0124]

[0140] Aspect 21: A method of preparing a first package including a first substrate having at least a first dielectric layer and a first plurality of interconnects and a first integrated device coupled to the first substrate. The method includes coupling a second substrate having at least a second dielectric layer and a second plurality of interconnects to the first substrate via the first plurality of solder interconnects. The method includes preparing a first plurality of channel interconnects on a first surface of the second substrate. The method includes coupling a second integrated device to the first surface of the second substrate. The method includes coupling a third integrated device to the first surface of the second substrate via a second plurality of solder interconnects, the second plurality of solder interconnects being located between the first plurality of channel interconnects from the second plurality of solder interconnects.

[0125]

[0141] Example 22: The method of example 21, wherein the second integrated device is located between the third integrated device and the second substrate.

[0126]

[0142] Example 23: A method as described in example 21 or 22, wherein preparing the first plurality of channel interconnects includes bonding a fourth substrate having the first plurality of channel interconnects to a first surface of the second substrate.

[0127]

[0143] Example 24: A method according to any one of examples 21 to 23, wherein preparing the first plurality of channel interconnects comprises bonding a flexible cable comprising the first plurality of channel interconnects to a first surface of the second substrate.

[0128]

[0144] Example 25: The method of any one of Examples 21 to 24, wherein the first plurality of channel interconnects extends below the third integrated device.

[0129]

[0145] A device comprising a package including a substrate comprising at least one dielectric layer and a plurality of interconnects, and an integrated device coupled to the substrate, the device including a first plurality of channel interconnects coupled to a first surface of the substrate.

[0130]

[0146] Example 27: The device of Example 26, further comprising another substrate bonded to the first surface of the substrate, the first plurality of channel interconnects being part of the another substrate.

[0131]

[0147] Example 28: The device of example 26 or 27, further comprising a flexible cable coupled to the first surface of the substrate, the first plurality of channel interconnects being part of the flexible cable.

[0132]

[0148] Embodiment 29: A device described in any one of embodiments 26 to 28, wherein the first electrical pathway to / from the integrated device comprises a first plurality of channel interconnects.

[0133]

[0149] Embodiment 30: A device described in any one of embodiments 26 to 29, wherein the first electrical path to / from the integrated device includes at least one first solder interconnect coupling the integrated device to a substrate, at least one first interconnect from the plurality of interconnects of the substrate, at least one channel interconnect from the first plurality of channel interconnects, and at least one second interconnect from the plurality of interconnects of the substrate.

[0134]

[0150] Embodiment 31: A device described in any one of embodiments 26 to 30, further comprising a second plurality of channel interconnects coupled to a second surface of the substrate.

[0135]

[0151] Example 32: The device of Example 31, wherein the second plurality of channel interconnects are part of a fourth substrate and / or flexible cable.

[0136]

[0152] Example 33: The device of any one of examples 1 to 32, further comprising another integrated device coupled to the first surface of the substrate via a second plurality of solder interconnects, the first plurality of channel interconnects being located between solder interconnects from the second plurality of solder interconnects, and the other integrated device being located above the integrated device.

[0137]

[0153] Various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A first package, a first substrate comprising at least one dielectric layer and a first plurality of interconnects; a first integrated device coupled to the first substrate; a first package comprising: a second package, a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, wherein the second substrate is coupled to the first substrate via a first plurality of solder interconnects; a second integrated device coupled to the first surface of the second substrate; a third integrated device coupled to the first surface of the second substrate via a second plurality of solder interconnects; a first plurality of channel interconnects coupled to the first surface of the second substrate, the first plurality of channel interconnects located laterally between solder interconnects from the second plurality of solder interconnects; a second package comprising: A device comprising:

2. The device of claim 1 , wherein the second integrated device is located between the third integrated device and the second substrate.

3. 10. The device of claim 1, further comprising a fourth substrate coupled to the first surface of the second substrate, the first plurality of channel interconnects being part of the fourth substrate.

4. The device of claim 1 , further comprising a flexible cable coupled to the first surface of the second substrate, the first plurality of channel interconnects being part of the flexible cable.

5. The device of claim 1 , wherein the first plurality of channel interconnects extend below the third integrated device.

6. The device of claim 1 , wherein a first electrical path between the second integrated device and the first substrate includes the first plurality of channel interconnects.

7. a first electrical path between the second integrated device and the first substrate; at least one first solder interconnect coupling the second integrated device to the second substrate; at least one first interconnect from the second plurality of interconnects of the second substrate; at least one channel interconnect from the first plurality of channel interconnects; at least one second interconnect from the second plurality of interconnects on the second substrate; and at least one second solder interconnect from the first plurality of solder interconnects coupling the second substrate and the first substrate; at least one interconnect from the first plurality of interconnects of the first substrate; Including, The device of claim 1 .

8. The device of claim 1 further comprising a second plurality of channel interconnects coupled to a second surface of the second substrate.

9. The device of claim 1 further comprising a second plurality of channel interconnects coupled to the first surface of the first substrate.

10. The device of claim 9 , wherein the second plurality of channel interconnects is part of a fourth substrate and / or a flexible cable.

11. An apparatus including a device according to any one of claims 1 to 10, wherein the apparatus is one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things device, and a device in an autonomous vehicle.

12. 1. A method comprising: A first package, a first substrate comprising at least one dielectric layer and a first plurality of interconnects; a first integrated device coupled to the first substrate; providing a first package comprising: coupling a second substrate, the second substrate comprising at least a second dielectric layer and a second plurality of interconnects, to the first substrate via a first plurality of solder interconnects; providing a first plurality of channel interconnects on a first surface of the second substrate; bonding a second integrated device to the first surface of the second substrate; coupling a third integrated device to the first surface of the second substrate via a second plurality of solder interconnects, wherein the first plurality of channel interconnects are located laterally between solder interconnects from the second plurality of solder interconnects; A method comprising:

13. The method of claim 12 , wherein the second integrated device is located between the third integrated device and the second substrate.

14. 13. The method of claim 12, wherein providing the first plurality of channel interconnects comprises bonding a fourth substrate comprising the first plurality of channel interconnects to the first surface of the second substrate.

15. 13. The method of claim 12, wherein providing the first plurality of channel interconnects comprises coupling a flexible cable comprising the first plurality of channel interconnects to the first surface of the second substrate.

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