Method for editing an integrated circuit (IC) design layout

Abstract

A method for manufacturing-ready edit of a circuit layout driven by predictions for a predicted manufactured wafer contour generated by a machine-trained network. The method enables fast edit loops in an interactive edit timeframe where a predicted manufactured wafer contour corresponding to a design edit is presented within seconds of the edit itself. In some embodiments, the wafer contour takes into account mask OPC / ILT and lithography effects, as determined by the machine-trained network.

Description

[Background technology]

[0001] In electronics engineering, design rules are geometric constraints imposed on circuit board, semiconductor device, and integrated circuit (IC) designers to ensure that their designs function properly, reliably, and can be produced with acceptable yields. Design rules for production are developed by process engineers based on the capability of the process to realize the design intent. Electronic Design Automation (EDA) is widely used to ensure that designers do not violate the design rules. This is a process called Design Rule Checking (DRC). DRC is a major step during physical verification sign-off on a design and also includes LVS (layout vs. schematic) checks, XOR checks, ERC (electrical rule checks), and antenna checks. The importance of design rules and DRC is greatest for ICs with nanoscale geometries and for advanced processes at smaller geometry process nodes.

[0002] Variations in new process geometries, edge placement errors, and various other issues force chipmakers and EDA vendors to face an increasing amount of increasingly complex and sometimes interconnected design rules to ensure that chips are manufacturable. Equally challenging is the way different circuit layout polygons affect each other, which has led to a significant increase in the number of rules. Especially for smaller geometry processes (e.g., currently 28 nm and below), many fabs also insist on using more restrictive rules to improve yields.

[0003] The number of rules has increased to the point where it is no longer possible to manually keep track of them all, resulting in extreme design rule bloat. This increases the number of checks required and makes debugging more difficult. Furthermore, some rules depend on other rules, which is a growing problem for some foundries in some processes.

[0004] General purpose IC design rules must be somewhat pessimistic / conservative in nature to accommodate a wide variety of designs since it is not known a priori which polygons will be adjacent to other polygons during IC layout, and therefore the rules must be able to accommodate nearly all possibilities.

[0005] On the other hand, standard cell designers (e.g., SRAM designers) have traditionally been able to take advantage of “DRC waivers” due to the extreme regularity of their designs (e.g., each SRAM cell is surrounded on all sides by identical or nearly identical dummy cells at the periphery of the memory array). This regularity means that it is known a priori which polygons are adjacent to other polygons, and therefore the rules can be somewhat “relaxed”, allowing for tighter packing of polygons compared to what is allowed by the restrictive rules. Packing cells tightly makes more sense when they are repeated many times, and therefore these waivers are often negotiated between the designer and the foundry / fab. Even a very small reduction in bitcell (or any other type of cell that is used highly repetitively, such as a cell in a standard cell library) area can result in exceptionally large improvements in chip density and area reduction at the chip level. Traditionally, efforts have been made in other design areas to use DRC waivers with regularly structured designs / fabrics to result in improved packaging density and / or improved manufacturing yields. Here, the regularity enforced by the design fabric has resulted in some relaxation of the design rule constraints, however this approach is somewhat inflexible as it requires significant regularity to be imposed on the design fabric, thus reducing options for the design and layout engineer.

[0006] An additional problem facing today's layout and yield engineers is that of lithography hot spots. Lithography hot spots (hereafter "hot spots") are locations in a design that are probabilistically susceptible to fatal pinching (open circuit) or bridging (short circuit) errors due to poor printability of certain patterns in the design layout. One way to find hot spots is to run lithography simulations on the layout. However, lithography simulations are computationally too expensive for full-chip designs. Furthermore, for smaller geometry processes, the layout must be colored and OPC corrected for multiple patterning before lithography simulations can be run, incurring additional computational costs.

[0007] Optical proximity correction is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects. The need for OPC is primarily seen in the manufacturing of semiconductor devices, due to the limitation of light to maintain the integrity of the edge placement of the original design after processing into an etched image on a silicon wafer. These projected images appear with irregularities such as line widths narrower or wider than designed, which can be compensated for by modifying the pattern on the photomask used for imaging. Other distortions, such as rounded corners, are caused by the resolution of the optical imaging tool and are more difficult to compensate. Such distortions, if not corrected, can significantly change the electrical properties of what is being manufactured. Optical proximity correction corrects these errors by moving edges or adding extra polygons to the pattern written on the photomask. This can be driven by pre-calculated lookup tables based on the widths and spacing between features (known as rule-based OPC), or by dynamically simulating the final pattern using a compact model, thereby driving the movement of the mask pattern, typically divided into sections, to find the best solution (this is known as model-based OPC). The goal is to reproduce as closely as possible on the semiconductor wafer the original layout drawn by the designer.

[0008] The most visible benefit of OPC is that it corrects for area differences found between contacts in areas of different environments, linewidth differences found between features in areas of different densities (e.g., center vs. edge of array, or nested vs. isolated lines), and line-end shortening (e.g., gate overlap on field oxide). These may be used in conjunction with feature size adjustments along with resolution enhancement techniques such as SRAF (Sub-Resolution Assist Features Placed Adjacent to Resolvable Lines). In addition, "dog-ear" (serif or hammerhead) features may be created at the line-ends in designs. OPC has a cost impact on photomask manufacturing, whereby for variable-shaped beam (VSB) mask writers, mask writing time is related to the complexity of the mask shape and data file, and similarly, mask inspection for defects takes longer as finer edge control requires smaller spot sizes. For multi-beam mask writers, writing time is independent of the complexity of the mask shape.

[0009] The state of the art requires advanced techniques such as ILT (Inverse Lithography Technology) for OPC correction, adding even more computational expense (ILT tools are notoriously CPU and GPU intensive). ILT may generate curvilinear or piecewise polygonal mask shapes, or ILT may be "Manhattanized" to generate axis-parallel orthogonal shapes specifically targeted for writing on VSB mask writers.

[0010] The mask is OPC corrected before lithography simulation is performed to investigate whether the candidate layout modifications will lead to the expected improvement. For the most critical layers and patterns, OPC is in the form of curvilinear ILT, which is more computationally expensive. Because turnaround time is a critical business enabler, more time-consuming techniques are often utilized for the worst performing areas of lithography. During the OPC or ILT process, these are commonly referred to as hot spots or lithography hot spots, but in this application, either term is used to refer to the problem areas that remain after the best that can be done by any OPC, including those corrected by ILT and even full-chip curvilinear ILT. The computational cost of any kind of OPC and lithography simulation for today's process nodes means that there is a large delay in getting feedback on the hot spot modification candidate solutions. These costs preclude the ability to perform such modifications in a truly interactive manner. Summary of the Invention

[0011] Some embodiments provide an EDA method that utilizes predicted manufacturing contours of design components during the design process to make design decisions. In some embodiments, the predicted manufacturing contours are generated by a machine trained (e.g., trained neural network) that generates multiple manufacturing wafer contours corresponding to the design edits within a short time (e.g., a few seconds) of the edits themselves. The use of the machine trained network in some embodiments enables fast editing loops in an interactive editing timeframe. In the following description, the machine trained network is referred to as a "digital twin" of the set of masks for the design, or of the manufacturing process that produces the wafer or IC die produced by using the set of masks. The predicted manufacturing wafer contours generated by the machine trained network are also referred to as a "digital twin" of the design produced by the set of masks, or on the IC die / wafer.

[0012] The methods of some embodiments predict manufacturing rule compliance by using pre-computation techniques, e.g., by using trained neural networks, to accelerate processing time. In some embodiments, the methods are used to implement compactors that allow designers to quickly see predicted wafer contours for automatic or manually driven compaction edits. Additionally or alternatively, the methods of some embodiments enable fast automatic detailed routing of layouts driven by manufacturing rules driven by predicted wafer contours. Also, the digital twin inferred wafer contour in some embodiments takes into account coloring, mask OPC / ILT, and lithography effects (e.g., by using trained neural networks). These methods accelerate the iterative optimization of EDA tools by quickly evaluating each iteration, providing greater insight into manufacturing considerations at each of their respective design stages.

[0013] Some embodiments provide an EDA architecture that leverages a high degree of concurrency to achieve an interactive, iterative timeframe by performing different tasks related to the problem of setting up data for pre-computed evaluation, possibly performed by a neural network, and post-processing the results using concurrent flows with GPU acceleration. Advanced applications of the interactive layout design method of some embodiments include bus route compaction and interactive lithography hotspot repair, to name a few. The method of some embodiments reduces design-level hotspots to a level that even the best curved ILT solutions cannot resolve during the manufacturing process.

[0014] The method of some embodiments is used in an interactive layout design process, where one or more EDA tools rapidly present the results of user-driven edits to a designer and receive additional edits or instructions from the designer. The interactive design architecture of some embodiments significantly minimizes the delay between the layout edits performed by the designer and the subsequent OPC / ILT-enabled visualization of the fabricated silicon water contour, enabling a tight interactive feedback loop and significantly improved productivity in the hot spot fixing process.

[0015] Also, for interactive custom IC design, some embodiments provide new EDA methodologies that extend the concept and application of DRC waivers to any design scenario (e.g., to any custom IC design) during design layout time. These methods effectively simplify the design rules for the layout designer and improve the resulting design yield and manufacturability. The EDA methodologies of some embodiments provide DRC waivers for custom IC designs without compromising layout flexibility, i.e., without forcing the layout designer to use a small number of predefined layout templates.

[0016] Some embodiments also use machine learning processes (such as the deep neural network processes disclosed in U.S. Patent Application Serial No. 16 / 949,270, incorporated herein by reference) to present a "What You See Is What You Get" (WYSIWYG) paradigm to the designer. These embodiments enable interactive design updates while visualizing the expected manufactured silicon results in real time. Some embodiments provide an architecture that minimizes the delay between layout edits performed by the designer and visualization of the manufactured silicon water contour, enabling a tight feedback loop in DRC-exempt design compaction. The methods of some embodiments are used in automated layout design and / or other forms of layout design, including synthesis.

[0017] The use of neural networks, possibly by neural networking techniques, for these embodiments described herein is useful because neural networking is a statistical technique. Neural networking may include some errors in the output, but some neural networking techniques include errors in such a way that the worst output is not too bad. In embodiments that use only neural networking methods for estimation purposes, the statistical nature of the outputs is sufficient for the task they perform.

[0018] The extremely fast run times of neural networking-based methods allow processes that may traditionally require weeks of computation to now be reasonably accurately approximated / estimated in a matter of seconds. These fast run times are in stark contrast to simulation-based analyses that often take weeks or days to complete, especially when chaining sequences of image-to-image transformations to perform particularly long chains of constructive and simulation-based processing, such as Monte Carlo analysis of various coloring possibilities, Monte Carlo analysis of various neighborhood possibilities, OPC / ILT, MPC, mask simulation, and wafer simulation. Neural networking-based methods further provide fast run times when considering various types of more complex analyses (such as Monte Carlo analysis) to improve their predictions. This is because the time required to account for the more complex analyses can be fully or nearly subsumed in the training time of the neural network, which allows these networks to continue their fast run-time operation. While some embodiments use neural networks, those skilled in the art will appreciate that other embodiments use other types of machine-trained networks or processes.

[0019] The above "Summary" is intended to serve as a brief introduction of some embodiments of the present invention. It is not intended to be an introduction or summary of all inventive subject matter disclosed herein. The following "Description of the Invention" and the "Drawings" referenced in the "Description of the Invention" further describe not only the embodiments described in the "Summary of the Invention" but also other embodiments. Therefore, in order to understand all embodiments described herein, the "Summary of the Invention", the "Description of the Invention", the "Drawings", and the "Claims" must be thoroughly considered. Furthermore, the claimed subject matter is not limited by the illustrative details in the "Summary of the Invention", the "Description of the Invention", and the "Drawings".

[0020] The novel features of the invention are set forth in the appended claims. However, for purposes of illustration, certain embodiments of the invention are set forth in the following drawings. [Brief description of the drawings]

[0021] [Figure 1] 1 shows an example of a user interface for an interactive IC layout editing tool. [Diagram 2] 1 conceptually illustrates an interactive editing process of some embodiments. [Diagram 3] 1 illustrates an interactive design process provided by an interactive design tool of some embodiments. [Figure 4] 1 illustrates an interactive design process provided by an interactive design tool of some embodiments. [Diagram 5] 1 illustrates an interactive design process provided by an interactive design tool of some embodiments. [Figure 6] 1 illustrates an interactive design process provided by an interactive design tool of some embodiments. [Figure 7]1 illustrates an interactive design process provided by an interactive design tool of some embodiments. [Figure 8] 1 illustrates an interactive design process provided by an interactive design tool of some embodiments. [Figure 9] 1 illustrates an interactive design process provided by an interactive design tool of some embodiments. [Figure 10] 1 illustrates an interactive design process provided by an interactive design tool of some embodiments. [Figure 11A] The use of neural networks to infer manufacturing shapes from CAD (computer-aided design) data input is demonstrated. [Figure 11B] An example of a U-Net model architecture is shown. [Figure 11C] 1 illustrates the use of the conceived U-Net model architecture in some embodiments to predict wafer aerial images produced from rasterized image tiles representing a user-drawn layout. [Figure 11D] 1 shows an example of a rasterized image corresponding to the desired printed metal for one of the metal layers in a D-type flip-flop (DFF) standard cell. [Figure 11E] An example of the corresponding manufacturing output (assembled set of tiles) is shown below. [Figure 11F] Shown are multiple networks trained to generate outputs for different process corners (PC), each corresponding to a different manufacturing parameter (MP). [Figure 11G] 13 shows an example of inferred output where the reassembled tiles represent an image that represents the manufactured shape of a DFF design under three different unique process conditions. [Figure 11H] 1 illustrates an overall simulation process that can generate output samples given received input design samples. [Figure 11I]An example of a data flow diagram in which these inputs are provided to the mask and wafer process simulation step is shown. [Figure 12] 3 shows a process that is a more detailed representation of the process of FIG. 2. [Figure 13] 13 provides further details regarding computational operations in some embodiments. [Figure 14] An example of a neural network is shown that receives image tiles representing biased-up mask shapes and generates image tiles representing corresponding silicon wafer contours in an operation known as inference. [Figure 15] An example of a global process incorporating all of the operations for generating contours by utilizing neural networks is shown. [Figure 16] 15 shows a process for splitting sub-operations somewhat differently than that of FIG. [Figure 17] We demonstrate the use of a novel software architecture that significantly improves the throughput time of the interactive editing process by improving the operation and communication of the layout editor, the manufacturing software server process, and the neural network software server process. [Figure 18] One such embodiment is shown in which multiple software servers run simultaneously, one dedicated to each combination of process conditions. [Figure 19] An embodiment is shown in which one layout editing server operates with multiple manufacturing software process servers and a single neural networking software server. [Figure 20] Another embodiment is shown in which one layout editing server operates with one manufacturing software process server and multiple neural networking software servers. [Figure 21]Another embodiment is shown in which one layout editing server operates with multiple manufacturing software process servers and one neural networking process server, where the neural network generates not one but multiple outputs, one for each process condition of interest, simultaneously. [Figure 22A] A neural networking software server is shown running a single neural network that generates multiple outputs at once, each output corresponding to a different process condition of interest. [Figure 22B] 1 shows a graphical user interface that allows a user to select which model to use. [Diagram 23] 1 illustrates a more detailed example of an interactive design implemented in accordance with some embodiments of the present invention. [Figure 24] 1 illustrates a more detailed example of an interactive design implemented in accordance with some embodiments of the present invention. [Diagram 25] 1 illustrates a more detailed example of an interactive design implemented in accordance with some embodiments of the present invention. [Figure 26] 1 illustrates a more detailed example of an interactive design implemented in accordance with some embodiments of the present invention. [Figure 27] 1 illustrates a more detailed example of an interactive design implemented in accordance with some embodiments of the present invention. [Figure 28] 1 illustrates a more detailed example of an interactive design implemented in accordance with some embodiments of the present invention. [Figure 29] 1 illustrates a graphical user interface of an interactive compaction tool in some embodiments. [Diagram 30] 29 illustrates the process performed by the layout editor when a user requests an interactive compaction operation via the user interface of FIG. [Diagram 31]FIG. 29 shows the compacted bus route design that results after several uses of the interactive compaction tool, followed by several inspections of the resulting contours. [Diagram 32] 1 shows a predicted manufacturing design with predicted contours for the final compacted design. [Diagram 33] 33 shows a close-up of the upper left corner of the design of FIG. 32. [Diagram 34] 1 illustrates a design being auto-compacted by an auto-compaction tool of a layout editor of some embodiments. [Diagram 35] 1 shows the manufacturing contour corresponding to the original design. [Diagram 36] 1 shows a compacted design generated through a naive attempt to manually compact the design by removing the 6 nanometer spaces between polygons in both the X and Y directions. [Figure 37] 36 shows a compacted design similar to the simply compacted design of FIG. 36, but showing the predicted manufactured silicon contour with the curvilinear DRC violations in the design of FIG. [Figure 38] 38 shows a close-up of the compacted design of FIG. 37. [Figure 39] 1 illustrates a UI for an auto compaction tool of some embodiments. [Diagram 40] 1 illustrates a process performed by an auto-compactor in some embodiments. [Diagram 41] 33 shows the fabricated silicon contours corresponding to the auto-compacted solutions generated by a single run of the SHGO optimizer to auto-compact the design of FIG. 34, along with a particular formulation of the cost function and a particular initial search space. [Diagram 42] A close-up of the DRC violation marker polygon is presented. [Diagram 43] 35 shows fabricated silicon contours corresponding to alternative auto-compacted solutions generated by a single run of the SHGO optimizer to auto-compact the design of FIG. 34 . [Diagram 44] 1 illustrates the interactive editing process used to manually correct yield-limiting portions of a design. [Diagram 45] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Diagram 46] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 47] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 48] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 49] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 50] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 51] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 52] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 53] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 54] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 55]We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 56] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 57] We present an example of using a neural network-enabled interactive layout editing system to manually correct yield-limiting parts. [Figure 58] Some embodiments illustrate a process used to generate training data for training one or more neural networks to generate multi-contour output shapes for input shapes of an IC design or portion of an IC design. [Figure 59] 1 conceptually illustrates a computer system upon which some embodiments of the present invention may be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] In the following detailed description of the invention, numerous details, examples, and embodiments of the invention are set forth and explained. However, it will be apparent to one of ordinary skill in the art that the invention is not limited to the described embodiments, and that the invention may be practiced without some of the specific details and examples described.

[0023] Some embodiments provide systems and methods for circuit layout edit driven by knowledge of the manufacturing wafer contour as specified by a digital twin generated for the circuit layout through a machine-trained process such as a neural network. Such systems and methods are hereinafter referred to as digital twin-guided circuit layout systems and methods. In some embodiments, these systems and methods are used in interactive editing tools to provide a fast edit loop in an interactive editing timeframe where a manufacturing wafer contour corresponding to a design edit is presented within seconds of the edit itself. In some embodiments, the wafer contour takes into account mask OPC / ILT and lithography effects (e.g., by using a neural network trained to account for these effects).

[0024] In some embodiments, the machine-trained network or process generates multiple predicted manufacturing contours of the design components to facilitate making design decisions. In some embodiments, the different manufacturing contours generated correspond to different manufacturing process variations, such as different dose amounts to account for mask variations, or different depth of focus and exposure intensities for wafer manufacturing variations. In the following description, the machine-trained network or process is referred to as a "digital twin" of the manufacturing process that produces the set of masks for the design, or the wafer or IC die produced by using the set of masks. The predicted manufacturing wafer contours generated by the machine-trained network are also referred to as a "digital twin" of the design produced by the set of masks, or produced on the IC die / wafer.

[0025] The design system architecture of some embodiments uses a high degree of concurrency to achieve interactive timeframes by using concurrent flows with GPU acceleration to execute different tasks related to the problem of setting up data for a neural network and post-processing the results. Advanced applications of the interactive layout design methodology of some embodiments include bus route compaction and interactive lithography hotspot repair, to name a few.

[0026] Some embodiments provide digital twin-guided interactive routing and / or compaction methods. In some embodiments, a digital twin of the manufacturing process is leveraged to provide information about the detailed silicon contour that will appear after manufacturing, which then guides various facets of the circuit design and layout. Although some examples are presented below in the context of interactive layout design, the systems and methods of some embodiments are equally applicable to other forms of layout design, including layout synthesis, auto-placement, routing, compaction, and the like.

[0027] Additionally, certain embodiments are described below with respect to deep learning-based implementations of manufacturing-enabled digital twin technology. However, those skilled in the art will appreciate that certain embodiments are not limited to deep learning-based digital twins, but rather encompass other forms of digital twins, such as those based on shallow learning, other computational techniques not limited to neural networks, and / or other forms of pre-computation.

[0028] FIG. 1 shows an example of a user interface 100 of an interactive IC layout editing tool. Commercial examples of such tools include Custom Compiler from Synopsys Inc. and Virtuoso from Cadence Design Systems Inc. A custom or full-custom IC design process uses unique building blocks that are created specifically for the functionality required. Many of the same tools are used in a custom IC design process that are used in a semi-custom or ASIC design process. The difference is that the building blocks that are assembled are often custom built to provide specific capabilities. An IC layout editor is a key tool for this type of design process.

[0029] The methods used to assemble these devices can also vary to suit the unique requirements of the IC or block being developed. Critical components of cutting edge designs are often designed using custom IC design processes and tools such as those mentioned above. Examples include SRAM bit cells, cells from standard cell libraries, and analog / RF design cells. One usage model is interactive design, where the designer places polygons or collections of polygons representing blocks, transistors, etc. in a layout and draws wires to connect them together.

[0030] In some embodiment interactive IC layout editing tools, automation is also present, for example, a local routing tool can aid in the completion of routing. Among other things, these tools present a canvas area in which the user design is edited, a layer selector window that allows various process layers to be selected for editing and / or viewing, and various menus, toolbars, and bind key actions for performing various layout design edits, typically in conjunction with mouse input for graphically specifying geometric coordinates. Such tools are also not limited to the editing of single cells, but also allow the editing and assembly of hierarchical layouts (cells placed within cells).

[0031] These tools are commonly used to edit a single cell at a time, without any context in which that cell will ultimately be used. It is also common to use these tools to edit a cell in the context of another, larger cell in which it is placed. These latter forms of editing actions are known as "editing in place," where the editor not only sees the contents of the cell being edited, but also the surrounding context (i.e., the context of the hierarchy "above" or next to the cell being edited). With an in-place editing context, the user and the tools are aware of the context surrounding the cell being edited, which can make certain actions much easier.

[0032] In some embodiments, a tool / user may edit a cell alone, without surrounding context, which is referred to in this document as "context-free" editing. In other embodiments, a tool / user may edit a cell using an in-place editing paradigm, where surrounding context may be available. Some embodiments support both context-free and in-place editing paradigms. When rasterizing a cell being edited, where context is already available through the use of an in-place editing paradigm, the rasterization process in some embodiments may be extended to include not only the cell being edited, but also some or all of the surrounding context. Rasterization is the process of taking an image described in a geometric / vector graphics format (shape) and converting it into a raster image (a series of pixels, dots, or lines that, when viewed together, create the image represented through the shape). The extension may only include areas of the surrounding context that affect the contour of the design cell being edited. In some embodiments, areas of the surrounding context that are too far away from the cell being edited (and therefore do not affect its manufacturing contour) are excluded from the extension. In some embodiments, the lithographic field dimensions can be set to a known fixed amount or can be specified by a user.

[0033] When a cell is being edited in an editing tool in a context-free paradigm, a context may be inferred for the cell, i.e., certain assumptions may be made about the surrounding context of the environment in which the cell will ultimately be placed. For example, in the case of a memory bit cell, the method may assume that the cell being edited is surrounded by similar cells, possibly with the same orientation or a different orientation (e.g., mirror image in X or Y). In the case of standard cells that form a standard cell library and are ultimately placed and routed in rows, the method may assume that the cell being edited is surrounded by other instances of itself, or instances of other cells in the standard cell library, in any of the possible valid orientations.

[0034] In this case, when a cell is rasterized, copies of the cell surrounded by their various contexts are also rasterized at the same time, effectively compositing the different neighborhoods for the cell being edited. Some embodiments also combine (effectively overlap) the predicted wafer contours across these different neighborhoods, i.e., effectively predicting and taking into account neighborhood-induced variations. The contours presented in some embodiments and used in the resulting calculations are either statistically determined or simply taken as the most extreme possibilities (largest possible "outer" contour and smallest possible "inner" contour). Inner / nominal / contour is also described in more detail below.

[0035] For ease of explanation, some examples described below and illustrated by the accompanying figures are presented as if the edited design were edited in a context-free manner, without inference of context as described above, however, those skilled in the art will appreciate that embodiments of the present invention extend to the edit-in-place paradigm, as these embodiments are equally applicable to the context-free paradigm and the edit-in-place paradigm.

[0036] FIG. 2 conceptually illustrates an interactive editing process 200 of some embodiments. This interactive process provides a designer with manufacturing-ready predictions of design element contours to enable the designer to evaluate the quality of a design viewed, generated, and / or edited via an interactive design tool. As shown, process 200 involves one or more iterations of three operations: (1) the designer performs manual editing operations (at 205); (2) the interactive tool provides a quick visualization of a representation of the wafer contour that will appear on silicon after fabrication (at 210); and (3) the designer evaluates (at 215) whether the designer is satisfied with the edits. If the designer is satisfied, the process ends. If not, the process returns to 205 for the designer to perform another manual edit, followed by another quick visualization of the predicted wafer contour once the integrated circuit is fabricated.

[0037] In some embodiments, the process 200 is used by an interactive design tool employing an interactive DRC exempt use model to enable a designer to perform various manual edits at 205. Also, in some embodiments, the manual edits are facilitated with some automated tool operations. Additionally, a quick visualization in some embodiments is generated within seconds of the manual edit operations, enabling a user to quickly assimilate the contour information and perform subsequent contour-driven edits in real time.

[0038] The visualization representation in some embodiments is intended to accurately represent silicon after it is fabricated by taking into account OPC / ILT mask corrections and lithography effects at small process geometries. Such visualization allows the user to visually inspect the contours and decide to perform the next editing action, such as moving some shapes closer or further away from each other, depending on the observed contours. If the silicon wafer contours are not determined and rendered quickly enough, the interactive use model paradigm will fail and throughput will decrease. The result is a reduced productivity and a less than optimal final layout.

[0039] 3-10 illustrate an interactive design process provided by an interactive design tool of some embodiments. The process is presented as various user interface stages that present various stages of a designer's interaction with the tool. FIG. 3 illustrates the user interface 100 of the interactive design tool as displaying several IC design components for a D-Flip-Flop (DFF) standard cell design 302 on metal layer 1. These components include several Manhattan routes (e.g., E-route 305, F-route 310, etc.) along with long horizontal power rails 315 at the top and bottom of the cell 302.

[0040] 4 shows the design 302 after it has been separated into two color masks using double patterning techniques (DPT): a red mask component 405 and a blue mask component 410. These color masks are shown in the figure in different shades of gray and use different stipple patterns, one with left-to-right cross-hatching for the red mask and the other with right-to-left cross-hatching for the blue mask.

[0041] This process of separating the wafer layer into multiple mask layers is commonly called "coloring". The various metal shapes are separated into two color masks to increase feature density, a process known as multiple patterning, a class of techniques for manufacturing ICs developed for photolithography to increase feature density. Today, multiple patterning is required for 10nm and 7nm node semiconductor processes and beyond. The premise is that a single lithography exposure may not be sufficient to provide sufficient resolution. Thus, additional exposures are required or else the etched feature sidewalls are used to position the pattern (using spacers).

[0042] Users trying to push design rules try to get shapes closer together while, among other things, maintaining the manufacturability of the shapes, their ability to connect to shapes on layers above and below. Without the benefit of some embodiments of the present invention, standard restrictive design rules typically constrain users to adopt pessimistic spacing rules. However, the DRC waiver feature of some embodiments allows users to remove some of the pessimism and compact the spacing below the minimum allowed by the restrictive design rules.

[0043] 5 illustrates the selection of a validation tool 500 of an interactive design tool of some embodiments. The tool allows a designer to select one or more semiconductor layers and instruct the tool to present a visualization of the contours of silicon features fabricated across process variations. In this example, the designer selects Metal 1 two color mask 520 and instructs the tool to present the visualization by selecting (e.g., clicking) a UI control 550 (e.g., a UI button).

[0044] FIG. 6 shows a predictive design 602 that represents a prediction of how the design 302 will look after it is manufactured. In the following, such a design is referred to as a predictive manufacturing design. The interactive design tool in some embodiments generates this design by using a machine trained network (e.g., a neural network) that is trained to take an EDA design as input and generate as output a predictive manufacturing design that represents the predicted shape of the input design. The machine trained network, in some embodiments, is trained through a learning process that uses a known input design (e.g., an input design after coloring) together with a known output design (e.g., an output design after mask making or mask simulation) to train the network's machine trainable parameters (e.g., neural network weight values).

[0045] As shown, the predicted design 602 includes a detailed image of the wafer contour (across process variations) for the layer geometries selected in FIG. 5. The interactive design tool presents this detailed image very quickly because it uses a machine trained network (e.g., a neural network) to generate this detailed image. In FIG. 6, the generated silicon wafer contour is overlaid on the design along with the original design layout components so that they can be seen in the full context of the design. It is highly advantageous to present this information to the user quickly (within seconds) to allow interactive editing to be performed quickly.

[0046] Several other examples shown in other figures described below also show machine-generated predicted contours superimposed on the design layout with their corresponding components in the design layout. Those skilled in the art will appreciate that other embodiments do not render the predicted contours superimposed on the design layout with their corresponding layout components, but rather render only the predicted contour shapes.

[0047] In FIG. 6 and other examples described below, the predicted manufacturing shape of each component is depicted with multiple contours (i.e., depicted as multiple shapes with multiple sets of curved segments). Each contour of each component represents the predicted shape of that component for a particular manufacturing process variation. As described above, the interactive design tool of some embodiments uses a machine trained network (e.g., a neural network) that is trained to generate a range of predicted shapes for each component of a selected portion of the design over a range of process variations. For example, in some embodiments, the interactive design tool presents the designer with not only the nominal manufacturing process wafer contour, but also corresponding outer (maximum) and inner (minimum) contours that reflect maximum and minimum manufacturing process variations.

[0048] In this example, the two rulers 605 and 610 indicate that the size of the initial design is approximately 1.7 microns (micrometers) in the X direction and 0.55 microns (micrometers) in the Y direction. Figure 7 shows a change in the zoom level of the UI 100 to insert measurement rulers that allow the designer to more closely inspect the contours of the predicted manufacturing design 602 and determine the width of the manufacturing contours and the spacing between the manufacturing contours.

[0049] 8 shows an example of the results of a ruler placement operation. Here, a user has quickly determined, via the ruler operation, the maximum possible spacing (after fabrication) between two particular metal 1 pieces. As shown by ruler 805, this spacing is identified as 0.037901629 microns (micrometers), or approximately 38 nm, between the inner wafer counters. A designer may also wish to determine the smallest possible spacing, for example, by placing a ruler between the outer fabrication contours as shown by arrow 810.

[0050] The designer may decide to perform some edits to exceed the design rules, for example in a DRC-waived design scenario, when the contours are accurate, fully reflect the OPC / ILT mask corrections and manufacturing (lithography) realities / non-idealities of today's small geometry process nodes, and ideally take into account the design context (adjacent features on the same layer). For example, the designer may decide to further reduce the spacing between linear metal features and recalculate / visualize the corresponding manufactured contours. As the features are pushed closer together, the impact on the resulting contours increases, significantly changing the contour shape and spacing, but these results can be easily determined and visualized by the manufacturing-ready design paradigm of some embodiments of the present invention.

[0051] To summarize the point, an extremely simple first attempt to compact a design could be to take the entire design and shrink the entire design by some factor. Figure 9 shows the result of a simple attempt to scale the design by a factor of 0.75. In this example, a second pair of rulers 905 and 910 has been placed (while also retaining the original rulers 605 and 610) to show the dimensions of the shrunken design. The new design has an X dimension of 1.29 microns (less than the 1.7 microns (micrometers) of the previous design) and a Y dimension of 0.4 microns (less than the 0.56 microns (micrometers) of the previous design).

[0052] 10 shows a zoom on a simple reduced design with four circled areas 1002-1008 showing pinching of a power rail at one process corner (inner contour). While the distance between the outer contours of pairs of adjacent features may be reasonable here, the circled areas show that this came at the cost of significant metal pinching on the power rail, which could lead to yield and / or long-term reliability issues.

[0053] If a designer can see such contours almost instantly after performing an edit, such as a global design shrink, the designer can quickly undo the shrink and look for other means to make the design more manufacturable. For example, a user may choose to add width to a power rail to provide extra margin. As another example, a choice may be made to expand the size of a cell to make its yield under all neighborhoods more manageable. Alternatively, after creative manipulation, it may be possible to shrink the design and further improve manufacturability. Such actions and decisions may be performed interactively only if the feedback loop for determining and presenting the predicted manufacturing contour is fast enough, e.g., within 5 seconds or less.

[0054] Some embodiments use neural network models described in U.S. Patent Application Serial No. 16 / 949,270, which is incorporated herein by reference. These models allow an image representing a user-edited layout design to be presented as input and the resulting silicon wafer contour to be generated as output. FIG. 11A illustrates the use of a neural network 1100 to infer a manufacturing shape from a CAD (Computer Aided Design) data input. This neural network is described in the previously incorporated patent application. When the neural network is run on modern GPU architectures, inference times can be reduced to interactive time frames (i.e., within a few seconds) even for relatively large designs. While some embodiments use neural networks, other embodiments use other machine learning processes to formulate predictions regarding the resulting final shape after the design is manufactured.

[0055] If an input image is too large to be processed at once, it can be split into a collection of (overlapping) image tiles. Each of the smaller tiles may then be processed by the network, and the output tiles may be collected and reassembled into a final output image. In some embodiments, a neural network architecture inspired by the original U-Net model architecture is used. FIG. 11B shows an example of a U-Net model architecture. In the U-Net model architecture 1102, each shaded box 1104 corresponds to a multi-channel feature map. The number of channels is indicated at the top of the box. The xy size is provided at the bottom left edge of the box. The white boxes 1106 represent the copied feature maps. The arrows indicate different operations. In the final layer, a 1×1 convolution is used to map each 64-component feature vector into the desired number of classes. In total, the original network has 23 convolution layers.

[0056] The architecture is essentially an encoder-decoder network, where the encoding side (on the left) and a bottleneck layer (below) guide the model to learn a low-dimensional encoding of the input image. The decoder network on the right then decodes that low-dimensional representation of the image back to the full output resolution, and both sides work together to learn the transformation from input images to output images during training. The copy and crop operations act as skip connections that provide additional information from the encoder side of the network to the decoder side, helping to localize information in x,y space.

[0057] In some embodiments, the input to the neural network represents the design intent, i.e., (tiles from) an input image that represents what is intended to be manufactured assuming an "ideal" (but not realistic) manufacturing process. In some embodiments, the output image represents what will actually be manufactured by a realistic manufacturing process, with sharp corners rounded, vias or metal shapes drawn as small squares manufactured as circles or ellipses, etc. After training the CNN with semiconductor manufacturing image data, the network model weights are adjusted to generate an output image that reflects the entire manufacturing process.

[0058] FIG. 11C illustrates the use of the conceived U-Net model architecture 1102 in some embodiments to predict a wafer aerial image produced from rasterized image tiles representing a user-drawn layout. FIG. 11D illustrates an example of a rasterized image corresponding to a desired printed metal for one of the metal layers in a D-type flip-flop (DFF) standard cell. White pixels indicate locations where metal is intended to be produced on the silicon substrate. Conversely, black pixels indicate locations where metal is not intended to be produced.

[0059] In some embodiments, several modifications to the original U-Net architecture were implemented to facilitate the creation of output images that reflect the semiconductor integrated circuit shapes being manufactured. One modification involves changing the final output layer of the U-Net from using a sigmoid activation function to using a linear activation function. This modification allows the U-Net to generate images with grayscale pixel values ​​that include floating-point values ​​that vary continuously from 0.0 to 1.0, which is more reflective of semiconductor wafer exposure images.

[0060] In some embodiments, for semiconductor manufacturing applications, the U-Net architecture is used as described above, but with the initial number of filters reduced from 64 to 32, and continuing the filter doubling after each max pooling operation. This has the effect of significantly reducing the overall number of trainable parameters for the network while maintaining a sufficient level of accuracy for semiconductor manufacturing applications. In some embodiments, different input and output tile sizes are used, for example, 256×256 (with an inner core tile of 128×128). In another embodiment, the network can be further modified by removing some of the layers (shorter “U” depth) or adding additional layers (deeper “U”), as needed for accuracy. In another embodiment, rather than doubling the number of filters after each downsampling (max pooling) or upsampling convolution, a different ratio can be used. In one embodiment, a fixed ratio (such as 2.0) can be used at each layer, and in an alternative embodiment, a different layer-specific ratio can be used at each layer. For example, the ratios may be lower at the bottom bottleneck layer of the "U" shape, gradually increase as one approaches the bottom bottleneck layer, and then correspondingly decrease again as one moves away from the bottleneck layer and up toward the output. These ratios and other network parameters may be tuned as part of a hyperparameter search during the training phase. In one embodiment, the tuning may be repeated for different manufacturing processes and / or for different layers in the manufacturing process.

[0061] In some embodiments, the network has a single input and a single output, representing a manufacturing output image corresponding to a single set of process conditions (i.e., a unique process corner). The input to the network consists of images corresponding to CAD data (tiles from a CAD image drawn by a circuit designer), and the output consists of images corresponding to silicon manufactured accordingly for that unique set of process conditions. An example of a reassembled set of tiles representing a desired DFF circuit metal layer is shown in FIG. 11D.

[0062] FIG. 11E shows an example of the corresponding fabrication output (assembled set of tiles). As shown, each white pixel represents an area where metal is present on the fabricated silicon wafer, and each black pixel represents an area where metal is not present. However, the pixel values ​​are actually grayscaled and real-valued, with some pixel values ​​at the "edges" of the polygons being between values ​​0 and 1.0. This image is produced by reassembling tiles that were generated by a single-input, single-output, fully trained deep convolutional neural network, as described above.

[0063] To address the case of process variations, i.e., multiple sets of process conditions, in some embodiments, multiple copies of the single-output network may be generated, i.e., one network for each unique set of process conditions (manufacturing parameter values), and each of these single-output networks may be trained in parallel. FIG. 11F shows multiple networks (1108) trained to generate outputs 1110 for different process corners (PCs), each corresponding to a different manufacturing parameter (MP). After training, each of these networks may be used to infer, for a given CAD data input image, the output for that unique set of process conditions, i.e., that particular process corner.

[0064] FIG. 11G shows an example of an inferred output where the reassembled tiles show images that represent the manufactured shape of the DFF design under three different unique process conditions. Though similar at first glance, upon closer inspection it is clear that the three images are different. For example, different amounts of "corner rounding" are evident in each. The shape in the top image 1112 is "closest" to the rectilinear CAD shape drawn from the previously shown images. The shape in the bottom image 1116 is perhaps the furthest away, with a greater degree of rounded corners and narrowed shapes. The middle image 1114 is somewhere between these extremes. While this example shows only three examples as representative of semiconductor manufacturing process conditions for simplicity, a more comprehensive set could include additional process parameters that represent different extremes in mask and wafer manufacturing.

[0065] In some embodiments, this per-process corner inference may be done serially (e.g., using a single GPU), while in other embodiments, this per-corner inference may be done in parallel (using multiple GPUs). In a preferred embodiment, outputs at different process corners may be inferred by a single multi-output GPU, as shown in FIG.

[0066] To enable a neural network to generate output images, the network must first be trained. Training is performed by exposing the network to a large set of input / output image samples, each sample including an input image (reflecting a portion of an IC design) and one or more output images (reflecting what would be manufactured in response given that input). To obtain the samples, several input designs may be selected or generated. Corresponding output images may be generated from the input designs through a process of detailed simulation involving numerical calculations. For each input sample, a single output sample may be generated that reflects nominal process conditions. Alternatively, multiple output samples may be generated that reflect different manufacturing process conditions. An exemplary process for generating input and output training data (i.e., generating training output data from training input data) is described below with reference to Figures 11H, 11I, and 58.

[0067] Different manufacturing conditions can result in substantially different manufactured wafer shapes. Possible different manufacturing parameters (MPs) include coloring tools and parameters, OPT / ILT tools and parameters, including source and wafer process model parameters, MPC tools and parameters, including mask process model parameters, fracturing tools and parameters, mask writing tools and parameters, mask processing parameters, and wafer process and parameters, including source and wafer processing parameters. These parameters are somewhat interdependent and collectively form a high-dimensional space, but it is common in the art of semiconductor manufacturing to attempt to reduce this to a lower dimensional space. The parameters related to mask manufacturing are collectively reduced to a single dimension represented by dose margin variation, which is reduced to the two main dimensions related to wafer manufacturing: dose margin variation and depth of focus variation. Thus, most of the total variance introduced by the original (large) set of parameters can be represented by the variation in this much smaller set of independent parameters.

[0068] 11H illustrates a simulation process 1120 that is used in some embodiments to generate output training samples for received input design training samples. In some embodiments, the input samples are the entire IC design, while in other embodiments, the input samples are a portion of the IC design in some embodiments.

[0069] As shown, process 1120 begins by performing (at 1122) a coloring operation that separates an input sample into multiple mask layers. In the coloring operation, each feature of the input sample on a reticle layer is colored to reflect the assignment of the feature to a particular mask layer. After the colorization operation, process 1120 performs (at 1124) an optical proximity correction (OPC) operation to generate one or more possible sets of mask designs, each set of mask designs corresponding to the input sample.

[0070] For the input samples, the generated mask design in some embodiments includes a nominal mask design with variations. In some embodiments, the possible mask designs generated in 1124 can be combined to create a nominal mask design with variations. Conventionally, a nominal mask design can be determined using a nominal dose amount, such as 1.0, and calculating a nominal contour of the mask design at a threshold value, such as 0.5. In some embodiments, the nominal contour of the mask design is calculated from several possible mask designs. In some embodiments, the OPC operation includes an ILT (inverse lithography technique) operation. The ILT operation in some embodiments generates an ideal curved ILT pattern, while in other embodiments, the ILT operation linearizes the curved pattern.

[0071] Process 1120 performs (at 1126) a mask simulation operation to generate Mask Data Preparation (MDP), which prepares a mask design for the mask writer. This operation in some embodiments includes "splitting" the data into trapezoids, rectangles, or triangles. This operation, in some embodiments, includes Mask Process Correction (MPC), which geometrically modifies shapes and / or assigns doses to shapes to make the resulting shapes on the mask closer to the desired shapes. MDP can use possible mask designs or the results of MPC as input. MPC can be performed as part of fracturing or other MDP operations.

[0072] After the mask simulation, the process 1120 performs (at 1128) a wafer simulation operation that calculates possible IC patterns that result from using the generated mask. In some embodiments, the wafer simulation operation (at 1128) includes a lithography simulation using the calculated mask image. The operation at 1128 calculates several possible patterns on the substrate from multiple mask images.

[0073] For an input sample, the generated IC pattern in some embodiments represents an output pattern or a range of output patterns (if the generated shape has multiple contours to account for process variations and manufacturing parameter variations). The input samples and generated output patterns in some embodiments represent known inputs with known outputs that are used to train a machine trained neural network. Once trained, the neural network can then be used during compaction to aid in the compaction operation in the manner described above.

[0074] Those skilled in the art will appreciate that process 1120 may be more or less than what is shown. Typically, the mask process simulation software may be parameterized, i.e., instructed to perform a mask process simulation under a set of mask process (e.g., exposure dose variation) parameter values. Similarly, the wafer simulation software may be parameterized, i.e., instructed to perform a wafer process simulation under a set of wafer process (e.g., exposure dose variation and depth of focus variation) parameter values.

[0075] Figure 11I shows an example of providing these process variations in manufacturing parameters (e.g., exposure dose variations and depth of focus variations) as inputs to a simulation process used to generate output training data from input training data. Process 1140 shown in Figure 11I is similar to process 1120 of Figure 11H, except that the exposure dose variations are provided to a mask process simulation 1126 and the exposure dose and depth of focus variations are provided to a wafer process simulation 1128.

[0076] In response, the mask process simulation operation 1126 in FIG. 11I can generate several image files representing the manufacturing of a mask under various mask process variations (exposure dose variations). In some embodiments, this is a mask produced at nominal values ​​(exposure dose parameters at nominal values) and several mask files representing some extreme corner conditions (exposure dose parameters at some "extreme" values, e.g., some percentages such as + / - 10% of the nominal values). Percentage values ​​representing the extremes of the true mask manufacturing process may be specified, or other limits, e.g., statistical limits such as 1 sigma, 2 sigma, or 3 sigma values, may be specified.

[0077] For each of the production mask images thus generated (as determined by simulation), the wafer process simulation operation 1128 of FIG. 11I can then be performed. For the mask process simulation operation, the wafer process simulation operation 1128 generates a number of wafer images representing the use of the mask to produce a silicon wafer layer under various wafer process variations (depth of focus variations plus exposure dose variations). In some embodiments, this is several wafer image files representing a wafer surface produced at nominal values ​​(depth of focus at nominal values ​​plus exposure dose parameters at nominal values) and several extreme corner conditions (exposure dose + depth of focus parameters at several "extreme" values, e.g., a percentage such as + / - 10% of nominal values). Percentage values ​​representing the extremes of the true wafer production process may be specified, or other limits, e.g., statistical limits such as 1 sigma, 2 sigma, or 3 sigma values, may be specified.

[0078] In some embodiments, the mask and wafer manufacturing parameter distributions may be taken as joint distributions and the percentage values ​​may be selected to reflect 1 sigma, 2 sigma or 3 sigma joint probability limits. (Given random variables X, Y, ... defined on a probability space, the joint probability distribution for X, Y, ... is a probability distribution that gives the probability that each of X, Y, ... falls within any particular range or discrete set of values ​​specified for that variable. In the case of only two random variables, this is called a bivariate distribution, but as is well known to those skilled in the art, the concept can be generalized to any number of random variables to give a multivariate distribution.) In some embodiments, a Monte Carlo simulation may be performed in which the independent parameters are randomly drawn from their distributions or joint probability distributions.

[0079] The set of wafer images thus generated thus reflects the manufacturing process variations at the extremes or + / -N sigma values. This set of images can then be further aggregated into a nominal image, a minimum image (in pixels), and a maximum image (in pixels) reflecting the process parameters at corresponding + / -N sigma values. The process may be repeated for different values ​​of N, e.g., N=1, 2, 3.

[0080] As a result of this process, given an arbitrary input design mask reflecting a portion of the design, the simulation process produces multiple images reflecting the entire manufacturing process at nominal process values ​​and at extreme values ​​reflecting absolute limits or statistical values ​​such as 1, 2 or 3 sigma. Each of these outputs is called a "set" of process conditions such as nominal, minimum or maximum.

[0081] Different statistical neural network models can then be trained by exposing the neural network to sets of images corresponding to the nominal, minimum, and maximum values ​​at various N Sigma levels. At the end of training, each of these neural networks can generate images that reflect the statistical N Sigma values, i.e., that reflect the variance in production at the corresponding N Sigma values.

[0082] FIG. 11G shows nominal, minimum, and maximum images generated for a tightly controlled process, where the variation is relatively small compared to the nominal condition. Although the variation is small, it is not zero. However, corresponding images for modern small geometry nanometer era processes exhibit much larger image variations than those shown in FIG. 11G, and these larger variations will be illustrated by additional figures in this disclosure in the context of various circuit design applications.

[0083] 11I may take a long time, but it only needs to be performed once for each manufacturing process for which the parameter variations are known. However, it does not need to be performed once for each design intended to be manufactured in the manufacturing process, and thus the computational costs of generating the data to train the model can be amortized over many designs.

[0084] Returning now to the discussion of design compaction, in order to accelerate the process of generating predicted shapes, some embodiments perform additional operations in addition to those previously described with respect to FIG. 11A. These additional operations are required because, even with a fast neural network inference process, the various overheads involved in setting up the problem, feeding the data to the neural network, and then post-processing the results generated by the neural network to make them presentable in a layout editor significantly lengthen the overall process. Some embodiments are geared towards eliminating or significantly reducing the setup costs, allowing neural networks such as those described in U.S. Patent Application No. 16 / 949,270 to be used in conjunction with interactive layout editors in a tight interactive (edit, visualize, edit, visualize...) loop in a truly interactive time frame (seconds or less). As a result, a circuit layout designer can enumerate and very quickly evaluate a variety of different potential layout modification solutions, allowing the best solution to be quickly determined and adopted.

[0085] Figure 12 shows a process 1200 that is a more detailed representation of process 200 of Figure 2. Process 1200 shows that visualization operation 210 is composed of two sub-operations: (1) a calculation operation 1202 that calculates a silicon contour for each component in the selected design portion, and (2) a presentation operation 1204 that displays a visualization of the calculated silicon contours.

[0086] In some embodiments, significant extra computational operations are required to compute the silicon wafer contour in a format that allows it to be presented within the layout editor. Figure 13 shows further details regarding computational operation 1202 in some embodiments. This figure shows that in order to compute the contour, the data from the layout editor must first be prepared in a format suitable for consumption by the neural network, the neural network must perform its processing, and then the output from the neural network must be post-processed into a format suitable for rendering within the interactive layer editor tool.

[0087] 13 illustrates that calculating the silicon contour further requires an additional (1) biasing operation 1302 that pre-processes the data into a form suitable for consumption by a neural network, followed by (2) a calculate operation 1304 that uses the neural network to generate a silicon contour for each component in the selected design portion, and then (3) an etch-down contour operation 1306 that post-processes the data into a form suitable for rendering in an interactive layer editor tool. In some embodiments, the biasing increases the size of component shapes in the design (e.g., to make the shapes easier to manufacture), while the etching operation reduces the size of component shapes in the design.

[0088] As part of semiconductor manufacturing in advanced small geometry process nodes, features in the IC layout database are pre-processed in a size-up or "bias-up" operation, along with corner rounding, to enlarge the features and generate a more realistic target wafer shape to manufacture (since 90 degree corners are practically impossible to manufacture) prior to mask creation. An example of a bias-up operation performed in the geometry domain is to calculate all edges of all polygons and then increase all edges by a certain length. Sizing is usually specified in the drawn dimensions (1X) before reticle scaling is applied. Sizing is usually applied "per side", which means the distance each edge of the polygon is moved towards the interior or exterior of the polygon. For example, a 1.25 μm per side square that is sized -0.125 μm per side will shrink the square to 1.00 μm per side, for a total shrinkage of -0.25 μm in both the X and Y dimensions.

[0089] Masks are generated for corner-rounded versions of the corresponding bias-up shapes and optimized to ensure best fidelity in printing onto silicon wafers using a process known as OPC (Optical Proximity Correction). At advanced process nodes, an advanced form of OPC known as ILT (Inverse Lithography) is often performed to achieve best printability. ILT sometimes produces Manhattanized shapes and sometimes produces curvilinear shapes. ILT is a very computationally demanding process that involves simulation or emulation to (1) predict how wafer fabrication, and possibly also mask fabrication, may systematically deviate from the desired target shape and (2) compensate for them. To determine the final silicon contour after these operations, some embodiments factor all of these steps into the calculations for each color mask when multiple patternings are performed. For example, in FIG. 4, two color masks are included.

[0090] Some embodiments employ simple models for the bias-up and etch processes that are evaluated within the layout editing tool itself; for example, the wafer etch process is modeled as a constant etch, which in some embodiments is a bias-down operation that complements the bias-up model. Where more complex models are required, some embodiments use manufacturing simulation software and associated hardware to perform the bias-up and / or etch modeling. Other embodiments are used in conjunction with extreme ultraviolet lithography (EUV) manufacturing. In these embodiments, the bias and etch steps are omitted or performed as pass-through operations.

[0091] After generating (at 1302) the biased-up mask shape, the process 1300 calculates (at 1304) the on-wafer contour. As previously mentioned, in some embodiments, manufacturing computational software is used to perform these steps, but such software is somewhat computationally expensive and has an operational timeline that is not ideal for an interactive use model, even with GPU support. Thus, some embodiments use a machine-trained process (e.g., a machine-trained neural network or other machine-trained network) instead of such computational software to perform the wafer contour determination step. As previously mentioned, a trained neural network, such as that described in U.S. Patent Application Serial No. 16 / 949,270, can be used to significantly improve the performance of the contour determination step when the neural network inference operations are performed on a GPU device.

[0092] To allow the neural network to perform its processing, the biased up mask data needs to be converted from its geometric form (edges and points array in the geometry domain) to the raster domain, i.e., converted to a pixel image format. Polygon rasterization is a basic technique of geometric data processing that is widely used in the Electronic Design Automation (EDA) industry in particular, and in many other industries in general. A set of polygons in EDA (e.g., shapes that define the physical design of an integrated circuit) is usually represented in GDSII or OASIS format as an array of vertices, and the rasterization process seeks to represent them by grayscale pixels on a grid. Some embodiments use a high-resolution curve format using techniques such as splines. Some formats represent pixel dose data in a compressed manner to minimize data size and transmission time. Different embodiments use different methods to represent shapes, but many of the embodiments use a transmission mechanism that is as compact as possible while having the least impact on accuracy.

[0093] Once the neural network receives the raster domain data, it processes the data and generates as output a raster image of the fabricated silicon contour. To allow the raster image to fit into the GPU memory along with the neural network model, the image needs to be divided into smaller image tiles as outlined in U.S. patent application Ser. No. 16 / 949,270. Figure 14 shows an example of a neural network 1400 that receives image tiles representing biased up mask shapes and generates image tiles representing corresponding silicon wafer contours in an operation known as inference.

[0094] Process 1300, in some embodiments, performs post-processing to stitch the output tiles generated (inferred) by the neural network into a final full-sized raster image of the manufactured design. In some embodiments, process 1300 also performs additional post-processing operations to convert the raster image into a geometric image suitable for rendering in layout editing tools that do not operate in the raster domain. This last form of post-processing is known as "contouring" and may be performed by manufacturing computer software and / or hardware, such as TrueMask® DS.

[0095] 15 illustrates an example of an overall process 1500 that incorporates all of the above operations to generate contours by leveraging neural networks. This process 1500 is performed by several different processes, which are identified by a text legend located next to each operation. These processes are a layout editing software process, a manufacturing software process, and a deep learning software process. As shown, the layout editing software first saves a copy of the design (1505).

[0096] Next, at 1510, a manufacturing software process launches, acquires licenses, biases up the design components for one of the colors, converts the design to a rasterized format, and tiles up the tiles. At 1515, a deep learning software process launches, loads its neural network with its weights, iteratively reads and processes tiles of inputs to generate predicted output designs, and then stitches together the outputs it generates for the processed tiles. In some embodiments, the neural network generates N (e.g., 3) different predicted output designs for N (e.g., 3) different process variations, each predicted output design being represented in terms of pixel values ​​that must be processed to derive the component contour for each process variation. Instead of one neural network, other embodiments use N neural networks, each neural network generating one of the N different predicted output designs for one of the N different process variations.

[0097] At 1520, the manufacturing software process (1) starts again, (2) analyzes the pixel values ​​in each predicted output design generated by the neural network to generate component contours (e.g., nominal contours, maximum contours, and minimum contours) of the predicted output design, and then (3) etches down the predicted contour designs. At 1525, the manufacturing software process determines whether it has processed design components for all colors. If so, it ends. If not, it returns to 1510 and repeats the operations for another set of components of another color.

[0098] Other embodiments divide the sub-operations of process 1500 differently. Figure 16 shows a process 1600 that divides these sub-operations somewhat differently than process 1500. In process 1600, the bias and etch sub-operations are performed by the layout editing software instead of by the manufacturing software processes. Specifically, the layout editing software performs the bias operation at 1505 and the etch operation at 1605.

[0099] The startup and license acquisition times of the manufacturing software processes, as well as the startup and network load-up times of the neural network processes, add delays to the overall speed of the process 1500. The inference work of a neural network (the time it takes for the model to be loaded and generate its output once its inputs are available) can be very short (often on the order of less than a second). However, there is a variety of overhead associated with starting the manufacturing software processes to prepare their inputs (obtaining licenses, performing rasterization and tiling steps), and converting the network-generated output into a format suitable for rendering in the layout tool (reconstructing the manufacturing contour image from the tiles, obtaining licenses and contouring from raster domains to geometry domains, and simulating the etch steps).

[0100] The time delays associated with these overheads may be unacceptable in some cases. Furthermore, the rasterization, tiling, neural network inference, reconstruction, and contour operation steps must be performed once for each color mask. Also, as described above, some embodiments present the user with not only the nominal manufacturing process wafer contour, but also the corresponding outer (maximum) and inner (minimum) contours that reflect the manufacturing process variations.

[0101] Furthermore, if two color masks are involved (double patterning) and three process conditions (nominal, maximum and minimum) are considered for each mask, a total of six sets of contour determination operations must be performed. If only the manufacturing software process takes 3 seconds to start up and obtain its license, this requires a minimum overhead of 18 seconds. If the neural network software takes another 20-40 seconds to start up and load its libraries, neural network model and neural network weights, this adds another 120-240 ((20-40)*6) seconds of overhead.

[0102] Thus, sequential data processing flows that launch the necessary processes when needed and wait for each to be completed in sequence by process 1500 or 1600 of Figure 15 or Figure 16 are not used in some embodiments. Instead, some embodiments use a novel software architecture 1700 of Figure 17 that significantly improves the throughput time of the interactive editing process by improving the operation and communication of the layout editor, the manufacturing software server process, and the neural network software server process.

[0103] In this example, the data flow is modified to allow for three parallel independent execution sequences (hereafter referred to as flows). In some embodiments, these may be mapped to multiple threads of execution, and in other embodiments, are mapped to multiple cooperating operating system processes. For example, in the example illustrated by FIG. 17, as well as other examples illustrated in FIGS. 18-21, the independent execution sequences are (1) separate threads of one process, (2) separate processes, and (3) separate one or more threads of two or more processes. To utilize multiple GPU resources, multiple operating system processes may be required.

[0104] In FIG. 17, a first execution flow 1702 represents the layout editor software where a user performs edits and visualizes the results. In some embodiments, the layout editing software process executes on a non-GPU enabled system. A second flow 1704 represents a manufacturing software process server. This server performs rasterization and tiling operations, as well as contour operations where raster images generated by the neural networking software server are converted back to the geometry domain for rendering in the layout editing software. In some embodiments, the manufacturing software process server is pre-launched by the layout editor software, for example, when the validation tool 500 shown in FIG. 5 is selected by the designer.

[0105] The third concurrent flow 1706 is the neural networking software itself, which contains the trained neural network, and is responsible for inferring the wafer contour from the rasterized and tiled images generated by the manufacturing software server. To achieve the required performance, this process runs on a GPU-enabled system. In some embodiments, the neural networking software process is launched by the layout editor software, for example, when a verification tool, as shown in FIG. 5, is selected by the designer.

[0106] As shown in Figure 17, the neural networking software server process takes the output tiles generated by the neural network and reassembles them to reconstruct the full size raster image. In an alternative embodiment, this reconstruction process is moved from the neural networking software server to the manufacturing software process server.

[0107] In some embodiments, the three processes 1702, 1704, and 1706 are launched simultaneously (e.g., by a wrapper script used to launch the layout editor). In further embodiments, the manufacturing software server process 1704 and the neural networking software server process 1706 act as servers and wait for instructions to arrive over a network socket (e.g., an Internet socket) once they have finished their initialization process. Thus, while the layout editor software is obtaining its license and loading the IC layout design, the manufacturing software server can also be launched and obtaining its license, and the neural networking software server can also be performing its initialization, which includes loading the neural network model and the relatively long step of setting the neural network weights. Because these three processes are performing their initialization simultaneously, rather than sequentially as shown in FIG. 15, these initialization times are removed from the inner loop time for processing the design and rendering contours after the user has performed interactive edits, thus significantly improving the turnaround time for each iteration of the editing, calculation, and visualization operations of the interactive editing tool of some embodiments. Thus, in the architecture of FIG. 17, the initialization time for the three main processes has been moved up front to before the interactive editing loop, and thus removed from the computation steps performed after each user edit in the edit-compute-visualize loop.

[0108] In FIG. 17 and other sequence diagrams described below, boxes are drawn around sub-processes that consume significant GPU time or GPU time. Dashed vertical arrowed lines represent periods of essentially idle time during which the corresponding software process waits for input from a user or one of the other processes involved. Horizontal arrowed lines represent data transfer from one process to another. The communication between processes in some embodiments is Internet / network socket communication. Also, in some embodiments, horizontal arrowed lines flowing from left to right represent client-side socket-based requests for a service to be performed, while horizontal arrowed lines flowing from right to left represent server-side socket-based responses indicating that the service has been performed and results are available. The results generated by the server may be stored, for example, in a networked disk file and then accessed by the client. After receiving the server response, the layout editor client may perform additional processing, prepare another set of files for consumption by the server process, initiate another service request, wait for a response, and / or consume the files representing the results of the server-side service.

[0109] In Figure 17, the manufacturing software server 1704 begins listening and accepting socket communications after it is initialized, obtains its license, etc. Similarly, the neural networking software server 1706 begins listening and accepting socket communications after it is initialized and loads the neural network model and weights. In some embodiments, the three processes 1702, 1704, and 1706 can run on the same machine or on separate networked machines. Ideally, the neural networking software process 1706 runs on a machine with GPU hardware support to allow maximum throughput during neural network inference.

[0110] After a user uses the layout editing software, performs layout edits, and requests to see the manufacturing contours, the layout software 1702 saves a copy of the design (reflecting the latest edits), ensures that the shapes are properly biased up to reflect manufacturing, and then sends a client request to the manufacturing software server 1704 to rasterize and tile the design to prepare the design for neural networking inference by the neural network. In other embodiments, the biasing up process is performed by the manufacturing process server 1704 rather than the layout editing software client 1702. Once the manufacturing process server indicates, via a socket response, that the data is ready for deep learning inference, the layout editor in some embodiments sends a socket-based client request to the neural networking software server, informing it of the location of the data tile files representing the rasterized and biased up design, and requesting that the contours be calculated.

[0111] In response, the neural networking software server 1706 loads the data in the image tiles and uses the trained neural network to quickly perform an inference operation that generates an output image tile that represents the silicon wafer shape in raster space. In some embodiments, the neural networking software server then reassembles these tiles to form a larger image of the silicon wafer shape in raster space before responding to the client with a message indicating that the data is available. In other embodiments, the neural networking software server 1706 does not reassemble the tiles and responds as soon as the tiles are computed. The image reconstruction in some of these embodiments is performed by the manufacturing software server 1704 via a separate client request (not shown) by the layout editing software 1702.

[0112] Once the reconstructed raster image of the silicon wafer shape is available, it needs to be converted from the raster domain to the geometry domain, i.e., converted back to a format suitable for rendering in the layout editor. In some embodiments, this operation is performed by the manufacturing software server 1704 in response to a request from the layout editor client 1702. This operation includes examining various pixel values ​​in the reconstructed raster domain image and generating a geometric database including contours, for example, by using a marching squares algorithm.

[0113] The sequence of operations described above must be performed for each process condition of interest (e.g., nominal process corners, max and min corners corresponding to outer and inner contours, respectively) and must be repeated for each color mask generated via the multiple pattern decomposition operation, which in some embodiments is performed by the layout editor prior to or in conjunction with user editing. In some embodiments, the sequence is simply repeated consecutively, once for each combination of color mask and process condition of interest. For example, if two color masks are included as shown in FIG. 4 and there are three contours of interest (nominal, max / outer, and min / inner) to be determined, the above sequence must be repeated six times.

[0114] As described above, a design can be edited in a context-free paradigm or in an in-place edit paradigm where the surrounding context is known. In an in-place edit paradigm, the contour generation operation can extend the design to include none, some, or all of the surrounding context. In a context-free paradigm (such as context-free standalone edit of standard cells or memory bit cells), the contour generation process can extend the design to infer the context.

[0115] For example, in a standard cell edit scenario, the inferred context may include the placement of other copies of the standard cell or other standard cells surrounding the cell being analyzed, in their various legal orientations. In a memory bit cell scenario, the inferred context is likely to include the placement of other copies of the cell being edited, and / or dummy cells, which are often placed around the periphery in various legal orientations. Corresponding operations may be performed after the calculated contours are etched, allowing the final contour of the cell being edited to be determined. Here, the inner and outer contours for each instance of the cell being edited (which vary due to different inferred neighborhoods) are aggregated to generate a final inner / outer contour that takes into account design neighborhood induced variations in addition to process variations. However, these inferred context steps are not shown in the figures for ease of explanation.

[0116] To further improve throughput, some embodiments use a different architecture where multiple manufacturing software servers are deployed along with multiple neural networking software servers. This increases concurrency / parallelism and reduces overall processing "wall clock" time. FIG. 18 shows one such embodiment where multiple software servers run simultaneously, one dedicated to each combination of process conditions. Under this approach, (1) a first neural networking server can be used to infer wafer contours for the combination "first color mask, nominal process conditions", (2) a second server can be used for the combination "second color mask, nominal process conditions", (3) a third server can be used for the combination "first color mask, maximum process conditions", and so on.

[0117] Some embodiments use as many neural networking software servers as there are unique combinations of color mask and process condition pairs to be evaluated. Each neural networking software is assigned a dedicated GPU. In some embodiments, the servers again operate simultaneously, with each server responsible for calculating the wafer contour for one color mask and process condition combination. In other embodiments, the number of servers is reduced to match the number of process corner conditions, so that each neural networking software server runs multiple inference cycles, one for each color mask. In yet other embodiments, the number of neural networking software servers matches the number of color masks (two in this example), and each is responsible for running multiple inferences, one for each process condition of interest.

[0118] In some embodiments, multiple manufacturing software servers operating simultaneously perform rasterization, tiling, and contouring operations for each of the color mask and process condition combinations. For example, in some embodiments, (1) a first manufacturing software server is used for the rasterization, tiling, and contouring operations for a first color mask and nominal process condition combination, (2) a second manufacturing software server is used for a second color mask, nominal process condition combination, (3) a third manufacturing software server is used for the first color mask, maximum process condition combination, and so on.

[0119] In some embodiments, there are as many manufacturing software servers as there are unique combinations of color mask and process condition pairs to be evaluated. The servers in some embodiments operate simultaneously, with each server responsible for the rasterization, tiling, and contouring operations for one color mask and process condition combination. In other embodiments, the number of servers is reduced to match the number of process corner conditions, such that each manufacturing software server performs multiple rasterization, tiling, and contouring operations, one for each color mask. In yet other embodiments, the number of manufacturing software servers matches the number of color masks (e.g., two), with each responsible for performing multiple rasterization, tiling, and contouring operations, one for each process condition of interest.

[0120] 19 illustrates an embodiment in which one layout editing server operates with multiple manufacturing software process servers and a single neural networking software server, which in turn generates outputs for each color mask and process condition combination.

[0121] 20 illustrates another embodiment in which one layout editing server operates with one manufacturing software process server and multiple neural networking software servers. The single manufacturing software process server performs multiple rasterization, tiling, and contouring operations in succession, one for each combination of color mask and process condition of interest. In this example, each neural networking software process performs an inference operation for one color mask and process condition, and different neural networking software processes perform different inference operations for different color masks and process conditions in parallel.

[0122] 21 illustrates another embodiment in which one layout editing server operates with multiple manufacturing software process servers and one neural networking process server, where the neural network generates multiple outputs instead of one, one for each process condition of interest simultaneously. This model is also used in some embodiments using multiple neural networking process servers, where each neural network generates multiple outputs instead of one, one for each process condition of interest simultaneously. In these embodiments, as well as the embodiment of FIG. 21, each neural networking software is assigned a dedicated GPU, as the extreme parallelism of GPU devices can be highly exploited to provide very fast inference times, e.g., essentially the same amount of time as a single output case.

[0123] 22A shows a neural networking software server running a single neural network that generates multiple outputs at a time, each output corresponding to a different process condition of interest. Here, the neural network is trained to calculate the inner (minimum), nominal, and outer (maximum) contours, i.e., the inner and outer contours relate to the extremes of the overall manufacturing process. These contours are generated by the neural network from a three-channel output image, given a single-channel input image representing a rasterized layout design for a particular layer / color mask combination.

[0124] In one embodiment, as described with respect to the discussion regarding FIG. 11H, the network may be trained to generate images that correspond to statistical limits, such as 1 sigma, 2 sigma, or 3 sigma process limits, where the inner / outer contours derived from the images generated by the network correspond to the corresponding sigma values. FIG. 22B shows a graphical user interface 2220 that allows the user to select which model to use. When the "Process Extremes" radio button 2222 is selected, the minimum / maximum values ​​correspond to the extremes of the manufacturing process. However, when the "Statistical Limits" radio button 2224 is selected, the user will select from the available models reflecting how much of the process variation (in terms of N sigma limits) should be reflected.

[0125] 23-28 show a more detailed example of an interactive design implemented according to some embodiments of the present invention. It will be understood by one skilled in the art that the contours shown in these images are for the extremes of the manufacturing process, and different contours corresponding to various N-sigma limits can instead be configured via the user interface of FIG. 22B. In this example, a 64-bit bus 2300 jogs left by one routing grid as the bus traverses from top to bottom as shown in the layout editor display shown in FIG. 23. FIG. 24 shows a close-up view of the top left portion of the initial design displayed in the layout editor. This view also shows several rulers 2405 drawn to show the design following the 40 nm minimum width and minimum spacing rules. It also shows two color masks (e.g., purple and cyan) with alternating diagonal stippling directions (e.g., top to bottom and left to right, or top to bottom and right to left) showing different color masks.

[0126] In this example, the designer wishes to compact the space between the routes while maintaining the width of the routing tracks themselves. In FIG. 23, the designer selects the dashed contour UI button 550 to instruct the layout editor to calculate the manufactured wafer contours across the process variations. In response, the layout editor works with one or more manufacturing software servers and one or more neural network software servers to calculate these contours, and then presents the designer with an elevated (zoomed out) view of the predicted bus 2500 design contours as they will be manufactured across the process variations, as shown in FIG. 25. FIG. 26 then shows the upper left corner of the bus after the designer performs a zoom operation to see three sets of generated contours showing the minimum, nominal and maximum contours of the predicted bus 2500.

[0127] Looking at the designs in Figures 25 and 26, the user determines that the manufacturing contours are well enough represented and that some extra reduction in design area is achievable by squeezing some of the space between the route shapes and "pushing beyond" the restrictive design rules. In particular, the routes can be moved closer to each other in both the horizontal (X) and vertical (Y) dimensions. For example, as shown in Figure 27, the designer may move the routes so that the horizontal spacing between the routes is reduced from 40 nm to 38 nm, effectively reducing the diagonal spacing from 52 nm to 48 nm. This can be accomplished by moving the shapes vertically and cutting off the tops so that they are all horizontally aligned. The new dimensions are indicated in this figure by rulers 2705 and 2710.

[0128] After performing the series of edits to obtain the design spacing shown in FIG. 27, the user can quickly determine whether the manufactured silicon wafer contour for this compacted design is acceptable by again selecting dashed contour button 550 to instruct the layout editor to initiate a series of operations (such as those described above with reference to FIGS. 12-22) to generate different predicted manufactured contours of the bus lines in the compacted design.

[0129] The resulting contours emerge quickly. FIG. 28 shows these contours in the upper left corner of the compacted design 2800. The designer zoomed in to this location to examine the spacing between the outer contours at several locations of interest. This spacing is indicated by rulers 2805, which in some embodiments are automatically displayed rulers, in other embodiments are user-selected rulers, and in still other embodiments are both automatically displayed and user-selected rulers. As indicated by these rulers, the spacing ranges from 29 nm to 33 nm depending on the location.

[0130] The user can continue to compact the design, pushing the design rules until the correspondingly placed rulers indicate that the wires are close together, yet have enough space between the outer contours as is comfortable from a yield standpoint. The user can also end the editing loop, for example, when the contours are determined to be equidistant both horizontally and diagonally. Additional tools and rulers not shown here may be deployed for the purpose of determining equidistance.

[0131] The interactive layout editor of some embodiments includes an interactive compaction tool that moves routes in the X and Y directions, compressing (or expanding) the horizontal and vertical space between routes if the user specifies delta X and delta Y space reduction values, negative values ​​expand the space. The tool can trim the resulting wires vertically as needed after each compact / expand operation to maintain the original alignment.

[0132] 29 illustrates a graphical user interface 2900 for this interactive compaction tool in some embodiments. As shown, the user interface includes (1) a set of dimension controls 2905 that allow the user to specify the amount of space reduction (in nanometers) in the X and Y directions, (2) a compaction button 2910 that allows the user to run the compaction operation, and (3) an auto contour checkbox 2915 that instructs the layout editor to calculate the contours resulting from the interactive compaction operation and display these contours superimposed on the layout.

[0133] Through this tool, the layout editor not only moves shapes the necessary amount in X and Y according to user-specified X and Y values ​​to compress / expand the space between them, but also trims or expands wires vertically to be as short or long as necessary while still accommodating diagonal jogs. When the Auto Contour checkbox is checked (as in FIG. 29), the compaction operation also quickly determines the contours resulting from the interactive compaction operation and displays them superimposed on the layout. Rapid display is now possible, as even for a design of a given size and complexity, the manufactured wafer contour across process variations can be determined and displayed in a matter of seconds.

[0134] FIG. 30 illustrates a process 3000 that the layout editor executes when a user requests an interactive compaction operation via the user interface 2900. As shown, the process 3000 executes one or more iterations of three operations: compacting the design (at 3005), generating a visualization of the silicon contour (at 3010), and then determining whether the design should be further compacted (at 3015). If the process determines (at 3015) that the design should not be further compacted, the process determines (at 3020) whether the design has been over-compacted. If so, the process reverses one or more previous compactions and selects one of the compaction solutions identified in that previous iteration from 3005 to 3015. If not, the process selects (at 3025) its last identified compaction solution and terminates.

[0135] Figure 31 shows a compacted bus route design 3100 that results after several uses of the interactive compaction tool of Figure 29, followed by several inspections of the resulting contours. In this design, the layout editor displays several rulers 3105 to contrast the size of the compacted design with the original design 2300.

[0136] FIG. 32 shows a predicted manufacturing design 3200 with predicted contours for the final compacted design. The contours shown are defined along with several process variations. As shown, the design area has been reduced by a significant amount (approximately 23%) compared to the original uncompacted design. FIG. 33 shows a close-up 3300 of the upper left corner of the design 3200. As shown, several measurements indicate reduced spacing between the outer contours of the final compacted shape. Also, as shown, there is no significant bridging evident between the shapes, nor any obvious pinching of the shapes even at this level of spacing.

[0137] In some embodiments, a user can interactively compact the design, visualize the resulting contours, measure the contours, etc., and instruct the interactive layout editor to repeat process 3000 of FIG. 30 until it is determined that the design is over-compacted. At this point, the design can be re-expanded (e.g., by specifying negative values ​​for the X and Y spatial contraction values ​​and a final click of the "Compact" button). Alternatively, an "Undo" editing operation can be used to achieve the same goal, resulting in a design that is as compact as possible.

[0138] Some embodiments provide an automated compaction tool that leverages a multi-goal optimizer to compact a design. In some of these embodiments, the goals of the optimizer include (1) minimizing the design area and (2) minimizing DRC violations. Some embodiments of the automated compactor minimize the design area without introducing DRC violations. Additionally or alternatively, some embodiments of the automated compactor minimize manufacturability violations between curvilinearly manufactured silicon features while optimizing or being constrained by parasitics, most notably resistance and capacitance, that affect circuit wiring delay.

[0139] In the bus route example above, the auto-compactor optimizer, in some embodiments, is configured to search the design space to identify X, Y values ​​that best compact the design without introducing manufacturability issues of the curves. The optimizer in some embodiments attempts to minimize a cost function by varying the input variables (in this example, the X and Y space reduction values) within the available search space (defined in some embodiments through a set of constraints) until the cost function value is minimized. In some embodiments, the cost function is a combination of both the area of ​​the compacted design and a value related to the manufacturability cleanliness of the curves of the compacted design.

[0140] Manufacturability cleanliness in some embodiments is expressed as DRC cleanliness, or curvilinear DRC of simulated or emulated curvilinear contours that represent manufacturing contours and their statistical variations, or any other measure that indicates a more manufacturable design than a less manufacturable design. In some embodiments, the manufacturability cleanliness value is a function of the area of ​​the curvilinear DRC marker polygons, with the larger the area of ​​the combined curvilinear DRC errors, the higher the cost. Meanwhile, the manufacturing cleanliness value in some embodiments is a function of the number of curvilinear DRC marker polygons. In other embodiments, the DRC cleanliness value is a function of both the number of curvilinear DRC marker polygons and the combined area of ​​the curvilinear DRC marker polygons. The curvilinear DRC marker polygons in some embodiments are not a function of the edges of the drawn layout (as in traditional DRC), but rather of the edges of the curvilinear polygons that correspond to the manufactured silicon shapes. DRC cleanliness in this context is a measure of how clean the curved manufacturing design contours are. These functions may be linear, square, or any other function. The less clean the contour (ie, the greater the amount of curve DRC violations), the larger the penalty that is added to the cost function.

[0141] FIG. 34 shows a design 3400 being auto-compacted by the auto-compaction tool of the layout editor of some embodiments. Rulers 3405 provide an indication of the Y dimension of this design. In this example, a slightly different manufacturing process is used, which results in a somewhat different contour than seen previously. The manufacturing contour corresponding to the original design is as shown in FIG. Several rulers 3505 are shown in this figure to provide an indication of the scale of the spacing between the outer contours at several target locations.

[0142] 36 shows a compacted design 3600 produced through a naive attempt to manually compact the design by removing the 6 nanometer spaces between polygons in both the X and Y directions. As shown, comparing the location of the bottom right corner of the compacted design with the ruler 3405 that was originally placed next to the original uncompacted design, the design has indeed been compacted by a certain amount.

[0143] FIG. 37 illustrates a compacted design 3600 similar to the simply compacted design 3700 of FIG. 36, but showing predicted manufactured silicon contours with curve DRC violations in design 3600. The contours and violations are shown in different colors, in some embodiments, e.g., red for contours and blue for violations. In FIG. 37, several colored locations (e.g., blue locations) circled in a black and white drawing identify DRC violations. In this example, the curve DRC rule check includes a curve minimum spacing check of 25 nm. Observed spacing between manufactured silicon contours that is less than this amount is flagged as a violation. A number of curve DRC violation polygons are shown in the figure.

[0144] FIG. 38 shows a close-up view of the compacted design 3700 of FIG. 37. The view of FIG. 38 shows a contour 3820 and DRC violation marker polygons 3825 corresponding to the upper left portion of the design 3700 of FIG. 37. Rulers 3805 are also shown to indicate scale. The violation marker polygons show the identified violations in more detail. These polygons indicate where the outer contour edges are within 25 nm of each other. One of the markers 3825a is shown with a ruler indicating a spacing of 23.3 nm (0.0233 μm). This ruler is displayed in some embodiments in response to a designer's input to further investigate the marker 3825a, but in other embodiments is displayed automatically by the tool. In still other embodiments, the tool automatically displays some or all of the rulers while also allowing the designer to invoke the display of the rulers to specify the dimensions of the violation marker polygons.

[0145] A goal of some embodiments is to be able to automatically compact a design as much as possible while minimizing curve DRC violations. To achieve this goal, some embodiments combine a black-box optimization process with a cost function that includes both (1) the area of ​​the compacted design and (2) the combined area of ​​the curve DRC marker violating polygons. This allows the optimizer to find a compaction solution that results in the smallest possible design area while, for example, keeping the spacing between manufactured silicon wafer contours greater than the design rule minimum.

[0146] Black-box optimization processes require only a cost function evaluation function, and optionally, in some cases, boundaries that define the search space. These processes run multiple cost function evaluations at various trial points in the search parameter space to attempt to determine the overall shape of the cost function in multidimensional space. The results are often combined with running a local optimizer near the lowest cost point to attempt to achieve a global minimum.

[0147] Some embodiments use the Simplex Homology Global Optimization (SHGO) algorithm, a promising recently published global optimization (GO) algorithm, e.g., https: / / stefan-endres.github.io / shgo / . Software implementations of the algorithm have been shown to be highly competitive when compared to state-of-the-art commercial open source optimization software. Other embodiments use other optimization processes (e.g., differential evolution optimization processes, e.g., https: / / en.wikipedia.org / wiki / Differential_evolution). 39 shows a UI for an auto compaction tool of some embodiments. Through this UI 3900, a designer can set search space parameters for exploring the solution space for auto compaction optimization. X min, X max fields 3902 and 3904 allow a user to specify a range of possible values ​​for the X space reduction parameter, and Y min, Y max fields 3906 and 3908 allow a user to specify a range of possible values ​​for the Y space reduction parameter. An auto compaction button 3910 allows a user to launch the optimizer on the current design being edited in the layout editor.

[0148] 40 illustrates a process 4000 performed by an auto-compactor of some embodiments. As shown, process 4000 identifies (at 4005) potential compaction solutions within user-specified search space boundaries. Process 4000 compacts (at 4010) the design by an appropriate amount using the identified compaction solutions, and then uses a neural network to generate a manufacturing wafer contour for the generated compacted design.

[0149] At 4015, a curvilinear DRC tool is also run on the curvilinear wafer contour shape, for example to determine spacing between manufactured features, and generates marker polygons whenever spacing is found to violate design rules. In some embodiments, the areas of both the compacted design and any DRC marker polygons are combined in a cost function that penalizes excess area or DRC violations, and the process runs its optimization sub-process to minimize this cost function value.

[0150] Next, at 4020, process 4000 determines whether to terminate upon finding a satisfactory solution to compaction in this or the previous iteration. In different embodiments, process 4000 uses different criteria to determine when to stop exploring the solution space. The criteria depend on the type of optimization sub-process that process 4000 uses.

[0151] Process 4000 ends when it determines (at 4020) that it has found a satisfactory solution and should terminate. Otherwise, if process 4000 determines (at 4020) that its search should not terminate, the process returns to 4005 to identify another potential compaction solution and then repeats its operations 4010 and 4015 for this solution. For each potential solution, the process generates a compaction based on the solution, generates a wafer contour for this compaction, applies curve DRC rules, and recalculates the cost function to evaluate the compaction resulting from the identified compaction solution.

[0152] After several such iterations, the optimizer may find a good solution to the problem, i.e., a set of input parameter values ​​(X and Y spatial reduction values ​​in this particular experiment) that correspond to low cost function values ​​with few or no DRC violations. At such point, it determines (4020) that the process should end, selects the best identified solution as a satisfactory solution, and terminates. In some embodiments, process 4000 terminates after reaching a specified maximum number of iterations or after reaching some other termination condition. Process 4000 in some embodiments performs 100-200 iterations, each taking only a few seconds thanks to the use of a neural network trained to generate production wafer contour values, completing the automated compaction of the design in the order of 10 minutes.

[0153] The auto-compaction tool of some embodiments has additional user interface controls to allow the user to further configure the optimizer, for example by specifying the maximum number of evaluation points, or the size of the initial search grid, etc. In some embodiments, the UI also provides one or more interfaces to additional suitable optimizers, as well as an interface that allows the user to select from a list of suitable optimizers.

[0154] Figure 41 illustrates a manufactured silicon contour corresponding to an auto-compacted solution generated by a single run of the SHGO optimizer to auto-compact the design of Figure 34, along with a particular formulation of the cost function and a particular initial search space. As shown, this auto-compacted result in a single DRC violation identified by a single small DRC violation marker polygon 4120, identified by a different color (e.g., blue) than the color used to indicate the contour (e.g., red). To illustrate the black and white diagram of Figure 41, a circle 4110 is used to highlight the location of the DRC violation polygon marker 4120.

[0155] 42 presents a close-up view of the DRC violation marker polygon 4120. As shown, the DRC polygon has a width of 24.169107 nm, as indicated by the ruler 4205. Applying a higher weighting to the DRC area term in the optimizer's cost function eliminates this DRC violation. Alternatively, the designer eliminates this violation through a manual adjustment operation or by providing an alternative value for an automatic compaction operation.

[0156] FIG. 43 shows the manufactured silicon contour corresponding to another auto-compacted solution generated by one run of the SHGO optimizer to auto-compact the design of FIG. 34. This other solution was identified using a different initial search space (e.g., X and Y space compaction values ​​were X=2.64 nm and Y=5.92 nm) and is free of DRC errors. In this example, the design was successfully compacted such that the overall Y dimension was reduced from 4.62 μm to 4.25 μm while the X dimension was correspondingly compacted (rulers not shown). Also, in this example, the auto-compacter did not generate any DRC violating polygons to identify any 25 nm curve spacing DRC errors.

[0157] In some embodiments, a neural network-enabled interactive layout editing system can be used to manually correct yield-limiting portions of a design (lithography hot spots). The process begins with inspecting the contours for known or suspected hot spot locations. The design is then iteratively modified and the resulting contours are visualized and inspected. Several potential candidate edits can be rapidly evaluated in this manner, along with their resulting impact on the manufacturing design contours.

[0158] FIG. 44 illustrates an interactive editing process 4400 used to manually modify yield-limiting portions of a design. As shown, the designer performs an editing operation (4405), i.e., instructs the tool to perform an editing operation. Examples of such operations include performing a flip or shift of cells, or modifying the yield-limiting portions of the design (via individual polygon edits). The process 4400 modifies (at 4410) the design based on the designer's input and provides a visualization of the resulting design with its associated predicted manufacturing contour. The designer reviews (at 4415) the design and determines whether the design should be further edited. If so, the process returns to 4405 as the designer performs another design. If not, the process ends.

[0159] 45-57 show an example of using a neural network enabled interactive layout editing system to manually correct a yield limiting portion. FIG. 45 shows a portion of a custom design including several placed standard cells for digital logic that have been determined to be associated with a yield issue. The central boxed area 4550 shows the contours associated with the yield limiting portion of the design (with inter-cell routing removed) as determined by the trained neural network. In this example, only the inner and outer contours are shown, with the nominal contours omitted for clarity.

[0160] FIG. 46 shows the corresponding portion of the design 4600 itself. The boxed area 4550 corresponds to area 4650 in FIG. 46. This area 4650 is at the abutment of two particular symmetrical cells 4605 and 4610 having back-to-back "E" shaped polygons. FIG. 47 shows a close-up of the problem area 4650 at the cell boundary to show the problem area in more detail. Here, it can be seen that the back-to-back "E" shaped polygons at the cell boundary are positioned close to each other. Such a positioning can occur, for example, due to color ring collisions.

[0161] 48 shows a corresponding close-up view of the manufactured wafer contour rapidly determined by the trained neural network, where three regions 4805, 4810, and 4815 are circled and approximately bridging the outer manufactured contour determined by the neural network.

[0162] Depending on the tools and methodologies used to create the original layout, as well as the nature of the layers and cells involved, various approaches may be chosen to repair such hot spots. If the original layout was created, for example, with a place-and-route tool, it may be possible to instruct the tool to gradually reroute parts of the design. However, this approach may result in sufficiently dramatic changes to alter circuit timing, and should therefore only be undertaken as a last resort. Even rerouting on designs with bad placement (such as the design shown in FIG. 46) may not be able to fix hot spots that are primarily placement dependent. Rerunning the placer may also be a way to solve the problem shown in FIG. 45, but again may lead to the need to reroute the newly re-placed design, again leading to timing challenges.

[0163] More localized forms of hotspot repair, such as flipping and shifting cells, or surgical changes to individual polygons as performed in an interactive editor, can yield better solutions, both in fixing the hotspots and in making minimal changes to timing and / or parasitics. The interactive editing tools of some embodiments are designed to support such localized repair solutions. The layout designer can perform manual / interactive localized edits to repair the hotspots. For example, the edits performed can include editing the problematic cells and / or their neighboring cell instances, such as interactively moving the problematic cell instances further apart, flipping cell instances, or performing other edits (such as cell remastering combined with manual polygon edits).

[0164] Following these edits, a predicted manufacturing contour is generated by the tool by re-running the contour extraction through the trained neural network, e.g., using the Contour button in the Verification Tool window described above with reference to Figures 5 and 6. An engineer tasked with fixing the hotspot can, for example, gradually increase the cell spacing and quickly re-run the contour extraction, continuing a tight edit-visual-edit-visual loop until the contours determined by the neural network are far enough apart that bridging is no longer an issue.

[0165] Alternatively, as shown in Figure 49, the designer may insert a predefined spacer cell 4905 from a cell library (e.g., a standard cell library typically includes one or more spacer cells for such purposes, among other things). Here, the spacer cell is a narrow cell that does not include anything other than well and power rail regions. This cell has been inserted by the user between the two cell instances in question, thus separating the two back-to-back "E" shaped polygons towards the center.

[0166] FIG. 50 shows the quick feedback the editing tool provides regarding the new contours determined by the editing tool's trained neural network. Thanks to the spacer cell, the contours of the two back-to-back "E" shaped polygons toward the center behave better from a manufacturability point of view. FIG. 51 shows a close-up of the spacer cell, and FIG. 52 shows a close-up of the manufactured wafer contours determined by the neural network in the vicinity of the spacer cell. Clearly, in this scenario, the outer contours are no longer able to short out to each other due to the large spacing between the corresponding design shapes.

[0167] The user can interactively rework the inter-cell routing connecting cell instances, thus re-establishing full connectivity with hotspots removed. As shown in Fig. 44, the entire interactive hotspot correction flow, together with the architecture described with reference to Figs. 17-21, is again made possible in a user interaction time frame (sub-second editing and visualization cycles) through the use of a trained neural network for contour prediction, one per process condition of interest and their accompanying description, allowing for amortization of maximum concurrency and startup overhead.

[0168] Given the design of Figure 46, a designer may wish to attempt a different hotspot fixing solution by simply interactively flipping the right edges of the two cell instances, as shown in Figure 53. Here, flipping the rightmost cell instance means that what were previously two back-to-back "E" shapes are effectively replaced with an "E" shape and a "C" shape, respectively (the "E" shape in the rightmost cell instance 4610 has been moved to the right edge of the diagram).

[0169] Figure 54 illustrates the immediate feedback on the resulting contours that an editing tool provides in some embodiments. This feedback indicates that a simple self-rip of such a rightmost cell instance may be sufficient to solve the problem without introducing extra space. The arrows in Figure 54 identify the space between the "E" shape 5405 and the "C" shape 5410, which is larger than the space that exists between the back-to-back "E" shapes in Figures 45 and 48.

[0170] FIG. 55 shows a close-up of the area between two cell instances in FIG. 53, and FIG. 56 shows a close-up of the corresponding contours in the area between the two cell instances. The arrows in FIG. 56 indicate a clear separation of the outer contours between the back "E" shape on the left-most cell and the "C" shape on the right-most cell. However, since the right-most cell has been flipped, it is conceivable that a new hotspot may have been introduced between that cell and its right-most neighbor. FIG. 57 shows how this can be quickly checked by zooming out the view to see the polygon of the right-most neighbor. As shown in FIG. 57, the cell boundary 5705 is fine in this example.

[0171] As mentioned above, different embodiments use different types of machine trained networks and train these networks differently. For example, as mentioned above, the machine trained network in some embodiments is a neural network. Some embodiments train the neural network to generate a predicted physical design layout from a current physical design layout by using many input data sets together with known output data sets to train the configurable parameters (e.g., weight values) of the neural network. In some embodiments, the input / output set is a portion of an IC design for a particular IC manufacturing process (e.g., Xnm design), the input portion is a portion of the physical design generated by a physical design tool, and the output portion is a corresponding wafer simulation portion or circuit portion generated for the physical design portion. Some examples of such approaches have been described above, for example, by reference to FIG. 11H and FIG. 11I. Another more detailed example of such an approach will be described below by reference to FIG. 58.

[0172] Some embodiments put a machine trained neural network through a learning process that accounts for (1) manufacturing variations in one or more manufacturing parameters (such as dose and depth of focus) and / or (2) neighborhood variations that account for different possible components adjacent to an input component pattern that is part of the input used for the learning process. To train the neural network, some embodiments feed each known input through the neural network to generate a predicted output, and then compare this predicted output to the known outputs for the input to identify a set of one or more error values. The error values ​​for the group of known inputs / outputs are then used to calculate a loss function, which is then back-propagated through the neural network to train configurable parameters (e.g., weight values) of the neural network. Once trained by processing a large number of known inputs / outputs, the neural network may then be used to facilitate a compaction operation, for example, according to any of the above-mentioned operations described with reference to the above-mentioned embodiments.

[0173] 58 illustrates a process 5800 that some embodiments use to generate training data for training one or more neural networks to generate multi-contour output shapes for input shapes of an IC design or portion of an IC design. The training data includes known input IC design portions and simulated output IC design portions generated by process 5800. This process is referred to as a digital twin process because it simulates the manufacturing process and generates a predicted manufactured wafer shape that is a digital twin of the actual manufactured wafer shape.

[0174] Process 5800 first selects (at 5805) a portion of a sample physical design of an integrated circuit as an input pattern for which one or more predicted output patterns need to be generated. In some embodiments, process 5800 uses multiple different sample physical designs from which it extracts a sample input pattern at 5805. The extracted input pattern is a portion of a previously defined physical design that may or may not have been used to manufacture an IC on a substrate (such as a silicon wafer). The pattern may include manufacturable shapes of circuit components (such as logic gates, transistors, metal layers, and other items that need to be found in the physical design of an IC). The physical design may be a straight line, a piecewise straight line, a partial curve, or a full curve. Curved patterns (each having at least one curve segment) are very computationally intensive, and therefore being able to optimize the pattern by calculating the cumulative effect of variations from multiple manufacturing stages is invaluable for curved patterns.

[0175] At 5810, if applicable to the selected physical design input pattern, process 5800 generates several possible neighborhood patterns adjacent to the physical design input pattern selected at 5805. In some embodiments, the physical design pattern selected at 5810 may be used in one or more subsequent IC designs and may end up with different neighborhood patterns in these subsequent IC designs. Some embodiments synthesize the neighborhood variations by using Monte Carlo techniques to enumerate several possible solutions.

[0176] In some embodiments, the physical design pattern selected in 5810, along with each of its synthesized neighborhood variations, represents a different input for which process 5800 generates a different output for the training process (also called a learning process) of the machine trained network. In other embodiments, the selected physical design input is the only input data, and its neighborhood variations are used only to identify contour variations during subsequent simulation runs of process 5800.

[0177] One example where it is useful to identify such neighborhood variations is when the input pattern is part of a standard cell design, and this standard cell design can be randomly placed in all possible neighborhoods that it may end up in, i.e., surrounded by various neighboring cells that are likely to be surrounded in the subsequent circuit design. In some embodiments, the selected portion of the physical design pattern is an instance of the physical design pattern, and the generated neighborhood pattern includes the possible neighborhoods of this instance. Thus, an instance of the target cell is placed in its various legal orientations alongside various orientations of various neighboring cells, and instances of those various neighboring cells are placed above / below, left or right, with various offsets in the placement. In some embodiments, the selected input pattern is the entire design of the standard cell design, which includes several standard cells, and the possible neighborhoods include all legal orientations of the standard cells.

[0178] At 5815, the process performs a coloring operation to separate the input pattern (e.g., the pattern selected at 5805 or the pattern generated at 5810 for the selected pattern) into multiple mask layers. In the coloring operation, each feature of the input pattern on a reticle layer is colored to reflect the assignment of the feature to a particular mask layer. After the colorization operation, process 5800 performs (at 5820) an optical proximity correction (OPC) operation to generate one or more possible sets of mask designs, each set of mask designs corresponding to the input pattern selected at 5805 or the possible neighborhoods generated at 5810.

[0179] For a selected input pattern, the generated mask design in some embodiments includes a nominal mask design with variations. In some embodiments, the possible mask designs generated in 5820 may be combined to create a nominal mask design with variations. Traditionally, a nominal mask design may be determined using a nominal dose, such as 1.0, and calculating a nominal contour of the mask design at a threshold, such as 0.5. In some embodiments, the nominal contour of the mask design is calculated from several possible mask designs. The variations may be calculated for all possible neighborhoods generated in 5810.

[0180] In some embodiments, the OPC operation includes an ILT (inverse lithography technique) operation. The ILT operation in some embodiments produces an ideal curved ILT pattern, while in other embodiments, the ILT operation straightens the curved pattern. The OPC features or ILT patterns for the same physical design pattern vary from neighborhood to neighborhood. Some embodiments calculate several possible sets of mask images from several possible mask designs in each of many possible neighborhoods. In some embodiments, a nominal mask design is calculated from the calculated OPC features or ILT patterns in many possible neighborhoods.

[0181] The process 5800 performs (at 5825) a mask simulation operation to generate mask data preparation (MDP), which prepares a mask design for the mask writer. This operation in some embodiments includes "splitting" the data into trapezoids, rectangles, or triangles. This operation in some embodiments includes mask process correction (MPC), which geometrically modifies shapes and / or assigns doses to shapes to make the resulting shapes on the mask closer to the desired shape. MDP can use possible mask designs or the results of MPC as input. MPC can be performed as part of a fracturing or other MDP operation. Other corrections may also be performed as part of a fracturing or other MDP operation, possible corrections include forward scattering, resist diffusion, Coulomb effect, etching, back scattering, fogging, loading, resist charging, and EUV mid-range scattering. Pixel level dose correction (PLDC) may be applied during the mask simulation operation. In other embodiments, a VSB (variable shaped beam) shot list or multi-beam exposure information can be generated to generate several possible mask images from the possible mask designs. In some embodiments, a set of VSB shots is generated for a calculated mask pattern in the plurality of calculated mask patterns. In some embodiments, MPC and / or MDP may be performed for the possible mask designs.

[0182] In some embodiments, the mask simulation operation calculates several possible mask images by using a charged particle beam simulation. Effects that may be simulated include forward scattering, back scattering, resist diffusion, Coulomb effect, fogging, loading, and resist charging. The mask simulation in some embodiments also includes a mask process simulation in which the effects of various post-exposure processes are calculated. These post-exposure processes may include resist baking, resist developing, and etching. When a charged particle beam simulation is performed for a mask on any given layer, the simulation may be performed over a range of process variations to establish a manufacturability contour for the mask itself. The contour may extend from a nominal contour, which may be based on a pattern generated at a particular resist threshold, e.g., a threshold of 0.5. In some embodiments, a mask image with variations is created for display in a viewport by calculating a given percentage difference in the exposure dose, e.g., + / - 10% dose variation. These variations include the upper and lower limits of a process variation band surrounding the nominal contour. In some embodiments, the positive and negative variations may be different from each other, e.g., +10% and -8%. The charged particle beam simulation and the mask process simulation are performed separately.

[0183] After mask simulation, process 5800 performs (at 5830) a wafer simulation operation that calculates possible IC patterns resulting from using the generated mask. For the input pattern selected in 5805, the generated IC pattern represents an output pattern or a range of output patterns (if the generated shape has multiple contours to account for process and manufacturing parameter variations). The selected input pattern and the generated output pattern represent known inputs with known outputs that are used in some embodiments to train a machine trained neural network. Once trained, the neural network can then be used during compaction to assist in the compaction operation in the manner described above.

[0184] In some embodiments, the wafer simulation operation (at 5830) includes a lithography simulation using the calculated mask images. The operation at 5830 calculates several possible patterns on the substrate from a plurality of mask images. Each pattern on the substrate in some embodiments corresponds to a set of manufacturing variation parameters. Calculating patterns from calculated mask images is described in U.S. Pat. No. 8,719,739, entitled "Method and System for Forming Patterns Using Charged Particle Beam Lithography," which is incorporated herein by reference.

[0185] Possible patterns on an IC can be combined to create a nominal IC pattern with variations. In some embodiments, the source of IC pattern variations will include some given variations in exposure (dose) combined with some given variations in depth of focus, e.g., + / -10% in exposure and + / -30 nm in depth of focus. In some embodiments, the plus and minus variations may be different from each other, e.g., +5% / -7% and 30 nm / -28 nm. Traditionally, statistical methods are used to generate 3 sigma variations from a nominal contour. The variations include a lower 3 sigma limit that is smaller than the nominal contour for a minimum value, and an upper 3 sigma limit that is larger than the nominal contour for a maximum value. Instead of calculating 3 sigma variations that extend from a nominal contour, some embodiments create a mask image with variations by combining several mask images that include process variation bands with lower and upper limits.

[0186] In some embodiments, the pattern can be formed on the wafer using an optical lithography process that uses a mask image with variations. The wafer simulation operation in some embodiments includes a wafer process simulation for the pattern. The wafer process simulation in some embodiments includes a simulation of resist baking, resist developing, and etching. Process 5800, in some embodiments, performs the lithography simulation and the wafer process simulation as separate steps, optionally with each step taking into account the process variations.

[0187] In some embodiments, process 5800 accounts for variations in different runs in a statistically cumulative manner, such that the process accounts for variations from previous runs in subsequent runs. In this way, the patterns in subsequent runs incorporate variations in mask processes and mask designs as well as variations in determining possible patterns on the substrate.

[0188] After the wafer simulation, the process 5800, in some embodiments, calculates process variation bands from possible patterns generated from the wafer simulation. To make the calculation of many possible combinations of variations more efficient, the variations can be accumulated using insight into how certain variations and pattern parameters may affect each other. For example, rather than simply feeding the minimum and maximum 3 sigma values ​​from one step to the next, the worst case variation fed to the next step can take into account the distance of one pattern from another. This is because features that are closer to each other affect each other more than features that are further apart. Because of the impact these variations have on design performance and manufacturing reliability, it may be desirable to allow designers to visualize the impact of different variations in the context of the actual circuit design. Visualizing the effect of the statistically accumulated variations predicted on the substrate can be shown after calculating the variation bands, or by visualizing the effect of different variations at each step.

[0189] At 5835, the process determines whether it has generated a sufficient number of known input and output patterns. If not, the process returns to 5805 to select another input pattern from the previously defined physical design and then repeats its operations 5810-5830 to generate a simulated output pattern for this input pattern. As discussed above, the selected input patterns and their corresponding generated output patterns represent known inputs with known outputs that, in some embodiments, are used to train the machine trained neural network.

[0190] Calculating the pattern to be manufactured on the substrate by calculating several wafer simulation patterns from several calculated mask images calculated from several mask designs can take a significant amount of time. Therefore, some embodiments use process 5800 of FIG. 58 to generate a large set of known input / output patterns, and then use these known input / output patterns to train (at 5840) a neural network so that the neural network can later be used to quickly generate predicted output patterns from input patterns examined during a compaction operation.

[0191] To train a neural network, some embodiments feed each known input through the neural network to generate a predicted output, and then compare the predicted output to the known outputs of the inputs to identify a set of one or more error values. The error values ​​for the group of known inputs / outputs are then used to calculate a loss function, which is then back-propagated through the neural network to train configurable parameters (e.g., weight values) of the neural network. Once trained by processing a large number of known inputs / outputs, the neural network can be used to facilitate compaction operations.

[0192] In some embodiments, compaction tools perform some or all of their operations and define their designs in the pixel domain rather than the contour domain. This is because pixel-based designs are ideal for analysis by machine-trained networks, as these networks are often optimized to process pixel-based data sets rather than contour-based descriptions. Pixel-based designs also make it easier to represent and process curvilinear shapes in a design. Thus, by representing the results of compaction operations in the pixel domain rather than the contour domain, some embodiments make it much easier for compaction tools to use machine-trained networks to quickly process curvilinear shapes in a design.

[0193] Similarly, to facilitate the creation of these masks, some embodiments use the pixel domain to perform the processing required to generate these masks, since a curvilinear mask operated in the pixel domain takes the same amount of time as any Manhattan design. This processing is also often performed on a GPU in the pixel domain. GPUs are excellent Single Instruction Multiple Data (SIMD) machines in the pixel domain, since a single instruction stream can be applied uniformly to many pixels, making the vast capabilities of GPU processing power ideal for this type of pixel manipulation. Relying on SIMD architectures can generate much higher computing throughput for processing physical designs and masks with curvilinear shapes.

[0194] Contours (also called geometry) are usually represented as piecewise linear polygons, but may also be represented in infinite resolution curve formats such as splines. Manipulating contours is the mathematical dual of manipulating pixel-based data, given the resolution limit. Mathematical duality means that functionally, anything that can be done on one side can be done on the other. However, when run-time performance or efficiency is considered, the computational behavior of one side may be quite different from the other, given a particular precision of the result as a target.

[0195] In general, manipulating shapes that are mostly large rectangles is faster in the contour domain (i.e., the geometry domain), and manipulating shapes that are mostly polygons or curves and have a higher vertex density is faster in the pixel domain. In the pixel domain, the pixel size is naturally defined from the resolution limit. Once the pixel size is defined, it does not matter whether the shapes being processed are curved or straight. Either computation is constant time. This is not the case for contour-based operations, since the computation time depends on the number of piecewise linear edge counts used to represent the contour. Also, given that many of these data processing operations are performed by high-powered GPUs, pixel-based analysis is preferred over contour-based analysis, since GPUs are SIMD machines that excel in the pixel domain.

[0196] Many of the features and applications described above are implemented as a software process specified as a set of instructions recorded on a computer-readable storage medium (also referred to as a computer-readable medium). When these instructions are executed by one or more processing units (e.g., one or more processors, processor cores, or other processing units), the instructions cause the processing units to perform the actions indicated in the instructions. Examples of computer-readable media include, but are not limited to, CD-ROMs, flash drives, RAM chips, hard drives, EPROMs, etc. Computer-readable media does not include carrier waves and electronic signals passing over wireless or wired connections.

[0197] As used herein, the term "software" is meant to include applications stored on magnetic storage devices or firmware resident in read-only memory that can be loaded into memory for processing by a processor. Also, in some embodiments, multiple software inventions may be implemented as subparts of a larger program while remaining separate software inventions. In some embodiments, multiple software inventions may also be implemented as separate programs. Finally, any combination of separate programs that together implement a software invention described herein is within the scope of the invention. In some embodiments, the software program, when installed to operate on one or more electronic systems, defines one or more specific machine implementations that execute and perform the operations of the software program.

[0198] 59 conceptually illustrates an electronic system 5900 in which some embodiments of the present invention are implemented. The electronic system 5900 may be a computer (e.g., a desktop computer, a personal computer, a tablet computer, a server computer, a mainframe, a blade computer, etc.), a phone, a PDA, or any other type of electronic device. As shown, the electronic system includes various types of computer-readable media and interfaces for various other types of computer-readable media. Specifically, the electronic system 5900 includes a bus 5905, a processing unit 5910, a system memory 5925, a read-only memory 5930, a permanent storage device 5935, input devices 5940, and output devices 5945.

[0199] The bus 5905 collectively represents all system, peripheral, and chipset buses that communicatively connect the various internal devices of the electronic system 5900. For example, the bus 5905 communicatively connects the processing unit 5910 to a read only memory (ROM) 5930, a system memory 5925, and a permanent storage device 5935. From these various memory units, the processing unit 5910 retrieves instructions to execute and data to process in order to perform the processes of the present invention. The processing unit may be a single processor or a multi-core processor in different embodiments.

[0200] The ROM 5930 stores static data and instructions required by the processing unit 5910 and other modules of the electronic system. The permanent storage device 5935, on the other hand, is a read-write memory device. This device is a non-volatile memory unit that stores instructions and data even when the electronic system 5900 is turned off. Some embodiments of the invention use mass storage devices (such as magnetic or optical disks and corresponding disk drives) as the permanent storage device 5935.

[0201] In other embodiments, a removable storage device (such as a floppy disk, flash drive, etc.) is used as the permanent storage device. Like the permanent storage device 5935, the system memory 5925 is a read-write memory device. However, unlike the storage device 5935, the system memory is a volatile read-write memory, such as a random access memory. The system memory stores some of the instructions and data that the processor needs at run time. In some embodiments, the processes of the present invention are stored in the system memory 5925, the permanent storage device 5935, and / or the read-only memory 5930. From these various memory units, the processing unit 5910 retrieves the instructions to execute and data to process in order to execute the processes of some embodiments.

[0202] The bus 5905 also connects to input devices 5940 and output devices 5945. The input devices allow a user to communicate information and select commands to the electronic system. The input devices 5940 include alphanumeric keyboards and pointing devices (also called "cursor control devices"). The output devices 5945 display images generated by the electronic system. Output devices include printers and display devices such as cathode ray tubes (CRT) or liquid crystal displays (LCD). Some embodiments include devices such as touch screens that function as both input and output devices.

[0203] Finally, as shown in Figure 59, the bus 5905 also couples the electronic system 5900 to a network 5965 via a network adapter (not shown). As such, the computer can be part of a network such as a network of computers (such as a local area network (LAN), a wide area network (WAN), or an intranet), or the Internet. Any or all of the components of the electronic system 5900 may be used in conjunction with the present invention.

[0204] Some embodiments include electronic components such as microprocessors, storage, and memory that store computer program instructions on a machine-readable medium or computer-readable medium (alternatively referred to as a computer-readable storage medium, machine-readable medium, or machine-readable storage medium). Some examples of such computer-readable media include RAM, ROM, read-only compact disks (CD-ROMs), recordable compact disks (CD-Rs), rewritable compact disks (CD-RWs), read-only digital versatile disks (e.g., DVD-ROMs, dual-layer DVD-ROMs), various recordable / rewritable DVDs (e.g., DVD-RAMs, DVD-RWs, DVD+RWs, etc.), flash memory (e.g., SD cards, mini SD cards, micro SD cards, etc.), magnetic and / or solid-state hard drives, read-only and recordable Blu-Ray® disks, extra-high density optical disks, any other optical or magnetic media, and floppy disks. The computer-readable medium can store a computer program that is executable by at least one processing unit and includes a set of instructions for performing various operations. Examples of computer programs or computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer, electronic component, or microprocessor using an interpreter.

[0205] While the above description primarily refers to microprocessors or multi-core processors executing software, some embodiments are performed by one or more integrated circuits, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In some embodiments, such integrated circuits execute instructions stored on the circuitry itself.

[0206] As used herein, the terms "computer," "server," "processor," and "memory" all refer to electronic or other technological devices. These terms exclude people or groups of people. For purposes of this specification, the terms display or display mean display on an electronic device. As used herein, the terms "computer-readable mediums," "computer-readable medium," and "machine-readable medium" are entirely limited to tangible, physical objects that store information in a form that is readable by a computer. These terms exclude any wireless signals, wired download signals, and any other ephemeral or transitory signals.

[0207] Although the present invention has been described with reference to numerous specific details, those skilled in the art will recognize that the present invention may be embodied in other specific forms without departing from the spirit of the present invention. For example, some of the figures conceptually illustrate processes. Certain operations of these processes may not be performed in the exact order shown and described. Certain operations may not be performed in one continuous sequence of operations, and different specific operations may be performed in different embodiments. Furthermore, processes may be implemented using several sub-processes or as part of a larger macro process. Thus, those skilled in the art will appreciate that the present invention should not be limited by the illustrative details set forth above, but should instead be defined by the appended claims.

Claims

1. A method for editing an integrated circuit (IC) design layout, receiving a design layout generated by a first set of design editing operations, the design layout including a plurality of components; generating, using a machine trained network, a plurality of contours for each component representing a plurality of predicted manufacturing shapes of the component, the plurality of contours for each component including a first contour representing a first predicted shape of the component for a first variation of a manufacturing process parameter and a second contour representing a second predicted shape of the component for a second variation of the manufacturing process parameter, the manufacturing process parameters being associated with a manufacturing process that will be used to manufacture an IC from the design layout; using the generated first and second contours representing the first and second predicted shapes of at least one particular component to perform a second set of design edit operations; The method includes:

2. 2. The method of claim 1 , wherein using the machine-trained network includes using the machine-trained network to generate a set of images representing the design layout after the manufacturing process has been performed by using the design layout, the manufacturing process portion of an overall process being used to manufacture a semiconductor die based on the design layout.

3. The method of claim 2 , further comprising performing image analysis on the set of images generated by the machine trained network to generate the plurality of contours.

4. The method of claim 1 , wherein the machine-trained network is a neural network.

5. 2. The method of claim 1 , wherein the machine-trained network serves as a digital twin of the manufacturing process used to manufacture a semiconductor die based on the design layout, and the manufacturing process parameters are parameters associated with the manufacturing process.

6. 6. The method of claim 5, wherein the design layout is a first design layout and the machine trained network generates a second design layout that is a digital twin of a design generated after performing the manufacturing process on the first design layout.

7. The method of claim 1 , wherein the manufacturing process is a mask making process and the manufacturing process parameter relates to a dose used during the mask making process.

8. 2. The method of claim 1, wherein the manufacturing process is a wafer simulation process, and the manufacturing process parameters relate to at least one of a depth of focus and an exposure intensity used during the wafer simulation process.

9. The method of claim 1, wherein the first contour is associated with a maximum variation of the manufacturing process parameter and the second contour is associated with a minimum variation of the manufacturing process parameter.

10. The method of claim 9 , wherein the plurality of contours for each component further comprises a third contour associated with a nominal variation of the manufacturing process parameter.

11. The method of claim 1, wherein the first contour is associated with a maximum variation of the manufacturing process parameter and the second contour is associated with a nominal variation of the manufacturing process parameter.

12. The method of claim 1 , further comprising generating a representation that overlays the plurality of contours for each component along with the components on the design layout.

13. The method of claim 1 , wherein the first and second set of design edit operations are compaction operations.

14. The method of claim 1 , wherein the first and second sets of design edit operations are routing operations.

15. The method of claim 1 , wherein the predicted shape comprises a shape of the component after a wafer simulation operation.

16. The method of claim 1 , wherein the predicted shape comprises a shape of the component after the IC is manufactured using the design layout.

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