Techniques for controlling vector processing operations - Patents.com

Abstract

A processing device is provided that includes a decoder circuit. The decoder circuit is configured to generate a control signal in response to an instruction. The processing device further includes a processing circuit that includes a plurality of processing lanes. The processing circuit is configured to perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing is valid for that processing lane in response to the control signal. The processing device further includes control circuitry that monitors each processing lane of the plurality of processing lanes for each instruction of the plurality of instructions performed in the plurality of processing lanes, and modifies the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane satisfying one or more predetermined conditions.

Description

[Technical field]

[0001] The present technique provides a processing device, a method for operating a processing device, and a non-transitory computer readable medium storing computer readable code for manufacturing a processing device. [Background technology]

[0002] Some data processing apparatuses include multiple processing lanes to allow vector processing operations to be performed. In some workflows that utilize vector processing operations, it may be desirable to perform the vector processing operations in only a subset of the multiple processing lanes. Summary of the Invention

[0003] In some configurations, a processing device is provided, the processing device comprising: a decoder circuit configured to generate control signals in response to the instructions; a processing circuit having a plurality of processing lanes, the processing circuit being configured to, in response to a control signal, perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing is valid for that processing lane; and a control circuit that monitors each processing lane of the multiple processing lanes for each instruction of the multiple instructions executed in the multiple processing lanes, and modifies a lane-specific mask for a processing lane of the multiple processing lanes in response to the processing state of the processing lane satisfying one or more predetermined conditions.

[0004] In some configurations, there is provided a method of operating a processing apparatus comprising a processing circuit comprising a plurality of processing lanes, the method comprising: generating a control signal in response to the command; in response to the control signal, performing vector processing operations using processing circuitry in each processing lane of the plurality of processing lanes for which the per-lane mask indicates that processing is valid for that processing lane; monitoring each processing lane of the plurality of processing lanes for each instruction of the plurality of instructions performed in the plurality of processing lanes, and modifying a per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane satisfying one or more predetermined conditions.

[0005] In some configurations, a non-transitory computer readable medium storing computer readable code for manufacturing a processing device is provided, the processing device comprising: a decoder circuit configured to generate control signals in response to the instructions; a processing circuit having a plurality of processing lanes, the processing circuit being configured to, in response to a control signal, perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing is valid for that processing lane; and control circuitry that monitors each processing lane of the plurality of processing lanes for each instruction of a plurality of instructions performed in the plurality of processing lanes, and modifies a per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane satisfying one or more predetermined conditions. [Brief description of the drawings]

[0006] The present technique will now be further described, by way of example only, with reference to arrangements thereof illustrated in the accompanying drawings, in which: [Figure 1] 1 illustrates a schematic representation of a processing apparatus according to various configurations of the present technique; [Diagram 2] 1 illustrates a schematic representation of a processing apparatus according to various configurations of the present technique; [Diagram 3] 1 illustrates a schematic representation of a processing apparatus according to various configurations of the present technique; [Figure 4] 1 illustrates, in schematic form, details of control circuitry for a processing device according to various configurations of the present technique; [Diagram 5] 1 shows a schematic representation of a spatial architecture with processing elements according to various configurations of the present technique; [Figure 6]1 illustrates a schematic representation of triggered processing elements according to various configurations of the present technique; [Figure 7a] 1 shows a schematic diagram of a sequence of processing steps according to various configurations of the present technique. [Figure 7b] 1 shows a schematic diagram of a sequence of processing steps according to various configurations of the present technique. [Figure 8] 1 illustrates generally the sequence of steps taken according to various configurations of the present technique; [Figure 9] 1 illustrates generally the sequence of steps taken according to various configurations of the present technique; [Figure 10] 1 illustrates, in a schematic manner, the manufacture of a processing apparatus according to various configurations of the present technique; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] At least some configurations provide a processing device comprising a decoder circuit, the decoder circuit configured to generate a control signal in response to an instruction. The processing device further comprises a processing circuit comprising a plurality of processing lanes. The processing circuit is configured to perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing is valid for that processing lane in response to the control signal. The processing device further comprises control circuitry for monitoring each processing lane of the plurality of processing lanes for each instruction of the plurality of instructions performed in the plurality of processing lanes, and for modifying the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane satisfying one or more predetermined conditions.

[0008] In some configurations, the processing circuitry, the decoder circuitry, and the control circuitry are each provided as separate (individual) functional circuits. However, in some configurations, two or more of the processing circuitry, the decoder circuitry, and the control circuitry are provided as the same block of circuitry arranged to function as two or more circuits. The decoder circuitry is provided to interpret a particular set of instructions forming an instruction set architecture. The instruction set architecture is a complete set of instructions available to a programmer to enable the programmer to control the processing circuitry. The decoder circuitry is provided to recognize each instruction of the instruction set architecture and generate the necessary control signals in response to the instruction to cause the processing circuitry to perform a particular operation. The processing device comprises a number of processing lanes to enable vector processing operations to be performed. Typically, in such processing devices, the same operation is performed in each of the processing lanes using different data provided in the vector processing registers. In this manner, the overall throughput of the processing device is increased. In some workflows, it may be desirable to perform processing in each of the processing lanes. However, in other workflows, it may be desirable to control which processing lanes perform a processing operation on a lane-by-lane basis. In other words, it may be desirable to control which processing lanes of the multiple processing lanes perform a particular operation and which processing lanes of the multiple processing lanes do not perform a particular operation.

[0009] Per-lane control of operations may be implemented, for example, by adding an additional operation to set a per-lane mask and explicitly providing that per-lane mask as an additional input to specifically designed instructions that will perform the operations only in those processing lanes of a plurality of processing lanes where the mask indicates that the operation should be performed. The inventors of the present technique have recognized that it is not always desirable to set and provide an explicit per-lane mask every time such control is needed, as such an approach may add significant control overhead resulting in performance degradation.

[0010] Instead, the technique provides a control circuit that monitors each processing lane of the multiple processing lanes for each of the multiple instructions performed in the multiple processing lanes. In other words, the control circuit is continuously monitoring the processing lane for at least the duration of the multiple (two or more) instructions. The control circuit is arranged to monitor the processing lane to determine whether the processing state of that processing lane satisfies one or more predetermined conditions. In other words, for each individual processing lane, the control circuit determines whether processing in that lane should be performed for each instruction of the multiple instructions based on whether the current processing state of the processing lane satisfies one or more predetermined conditions. In this manner, the processing device may be arranged to disable each processing lane when it satisfies one or more predetermined conditions and continue to perform processing operations only in the remaining lanes of the multiple processing lanes. Advantageously, the control circuit eliminates the need to explicitly set and provide per-lane masks for each instruction processed by the processing circuit, thus reducing the control overhead associated with such techniques.

[0011] The type of processing device to which the technique is applied is not particularly limited. In some configurations, the processing device is an in-order processing device that processes instructions in program counter order. In other configurations, the processing device is an out-of-order processing device in which processing operations are provided in the original program counter order defined by a programmer or compiler. However, the out-of-order processing device may deviate from the original program counter order based on the run-time availability of operands associated with the processing instructions. In some configurations, the instructions are triggered instructions, and the processing device is a triggered processing device that includes a front-end circuit that processes multiple fetched instructions and generates the triggered instruction in response to the execution state of the processing circuit satisfying a trigger condition associated with one of the fetched instructions. In such processing devices, there is no concept of a program counter. Instead, each instruction is triggered in response to a preceding instruction that sets the execution state of the processor such that the execution state satisfies the trigger condition associated with that instruction. In other words, rather than having a predetermined program order (which may change at run-time in the case of an out-of-order processing device), the execution order of instructions in the triggered processing device is not determined until run-time. The combination of a triggered processing unit and control circuitry monitoring each processing lane provides a particularly flexible processing unit, where the order in which instructions are processed and the lanes in which processing operations are performed are determined at run-time in response to the processing state of the processing circuit and the execution state of the processing circuit.

[0012] In some configurations, the front-end circuitry is configured to, in response to determining that two or more of the plurality of fetched instructions satisfy a trigger condition at a given time, determine a priority for the two or more fetched instructions based on a number of processing lanes that are active associated with each of the two or more fetched instructions. Because the triggered processing device does not have a predetermined execution order for the instructions, it is possible that multiple instructions are triggered in response to the same execution state. In such a situation, the triggered processing device is configured to determine a priority for the plurality of triggered instructions based on a number of processing lanes that are active for each of the plurality of triggered instructions. For example, in response to completion of a preceding instruction, the execution state of the triggered processing device may indicate that two instructions are ready for execution. However, the processing state associated with one triggered instruction may indicate that only a subset of the processing lanes are utilized, while the processing state associated with the other triggered instruction may indicate that all processing lanes are utilized. The front-end circuitry is configured to use this information to determine a priority associated with the instructions. In some configurations, the front-end circuitry is configured to prioritize triggered operations that utilize the fewest lanes first. This approach can result in reduced overall power consumption for situations where the results of the triggered operation reduce the number of lanes utilized by other processing operations. In some alternative configurations, the front-end circuit prioritizes processing operations that require the fewest changes to per-lane masks to minimize enabling / disabling of processing lanes. In other alternative configurations, the front-end circuit prioritizes triggered instructions whose execution state indicates that more of the multiple processing lanes are enabled to provide maximum utilization of the channel.

[0013] In addition to using the processing state to determine the order in which the triggered operations are performed, in some configurations, the front-end circuitry is configured to determine priority based on the length of time that the trigger conditions of two or more fetched instructions have been satisfied. This approach ensures that a balance is struck between meeting performance and / or power consumption requirements and ensuring fairness between different triggered instructions that may not best utilize the processing circuitry according to their performance and / or power consumption requirements.

[0014] The arrangement of the processing unit is not particularly limited. In some configurations, the processing unit may be a single-core processing unit or a multi-core processing unit. In some configurations, the processing unit comprises a plurality of processing elements arranged to form a spatial architecture, and the decoder circuit, the control circuit, and the processing circuit are arranged in one of the plurality of processing elements. In other words, each processing element of the plurality of processing elements is arranged to provide a decoder circuit, a processing circuit, and a control circuit dedicated to that processing element. The processing elements of the spatial architecture are distributed throughout a single chip to best utilize the circuit area and to ensure the locality of the processing elements with respect to the on-chip storage associated with the processing elements.

[0015] The arrangement of processing elements in a spatial architecture is not limited, and the network connecting the processing elements may be arranged to form an N-dimensional network, with each processing element connected to nearby processing elements along N different network paths. In some configurations, multiple processing elements are connected via a two-dimensional network arranged as a two-dimensional torus. The number of dimensions associated with the network is not limited by the number of dimensions associated with the physical arrangement of components on the chip. Rather, the number of dimensions of the network is defined by the layout of the connections between the processing elements. In a two-dimensional network, each processing element is connected to an element P i-1,j , P i+1,j , P i,j-1 , and P i,j+1 The processing element P connected between i,jare connected in the topological equivalent of the sequence of rows and columns having. By arranging the network connections to form a two-dimensional torus, an especially efficient configuration can be achieved that can route data between processing elements while avoiding network bottlenecks associated with the edge elements of the network. The two-dimensional torus layout is achieved by arranging an array of size R×S, resulting in processing elements P i,j (1 < i < R; 1 < j < S) being connected between elements P i-1,j , P i+1,j , P i,j-1 , and P i,j+1 , element P 1,j (1 < j < S) being connected between elements P R,j , P 2,j , P 1,j-1 , and P 1,j+1 , element P R,j (1 < j < S) being connected between elements P R-1,j , P 1,j , P R,j-1 , and P R,j+1 , element P i,1 (1 < i < R) being connected between elements P i-1,1 , P i+1,1 , element P i,S , and P i,2 , element P i,S (1 < i < R) being connected between P i-1,S , P i+1,S , P i,S-1 , and P i,1 , element P 1,1 being connected to P R,1 , P 2,1 , P 1,S , and P 1,2 , element P 1,S being connected to P R,S , P 2,S , P 1,S-1 , and P 1,1 , element P R,1 being connected to P R-1,1 , P 1,1 , P R,S , and P R,2 , element P R,S being connected to P R-1,S , P 1,S , P R,S-1 , and PR,1 The two-dimensional torus layout offers the advantage that processing elements are not located at the edges of the network, resulting in a more even distribution of network bandwidth.

[0016] The one or more predetermined conditions are not necessarily fixed, and in some configurations, the decoder circuitry is configured to generate an update condition control signal in response to an update condition instruction specifying a new condition, and the processing circuitry is configured to set the new condition as one of the one or more predetermined conditions in response to the update condition control signal. In some configurations, the decoder circuitry is responsive to a condition update instruction specifying whether the new condition should be added as an additional condition to the one or more predetermined conditions or should replace an existing one or more predetermined conditions. In some configurations, the control circuitry is configured to modify the per-lane mask in response to any of the one or more predetermined conditions being satisfied. In other configurations, the control circuitry is configured to modify the per-lane mask in response to a logical combination of the one or more predetermined conditions being satisfied.

[0017] The one or more predetermined conditions may be defined in various ways. However, in some configurations, the control circuitry is configured to modify the per-lane mask to meet the energy consumption target. In some configurations, there is a non-linear relationship between the performance gained by enabling more lanes and the power consumed by the additional lanes, which may be substantially more as the number of lanes increases. In such cases, and where performance is not paramount, the control circuitry may improve efficiency by reducing the number of lanes that are enabled. For example, rather than using all lanes of the multiple processing lanes to perform a single operation, the control circuitry may disable half of the lanes of the multiple processing lanes, resulting in a requirement that two operations be performed. However, due to the non-linear power requirements of the lanes, the amount of power used by each of the two operations is less than half of the amount of power that would have been used if all of the lanes were enabled. Thus, an overall energy reduction may be achieved.

[0018] In some configurations, the one or more predetermined conditions include a saturation condition, and the control circuitry is configured to modify the per-lane mask in response to the processing state of the processing lane indicating that a value in the processing lane is saturated. The control circuitry monitors values ​​in each lane of the processing device, and when a value in a processing lane saturates, the control circuitry is configured to disable that processing lane such that no further operations involving that processing element are performed. The value in the processing lane may be any value present in the processing lane. In some configurations, the value is a value of an input element in an input register in the processing lane. In other configurations, the value is a value of an output element in an output register of a preceding operation of the processing lane.

[0019] In some configurations, the one or more predetermined conditions include a negative condition, and the control circuitry is configured to modify the per-lane mask in response to the processing state of the processing lane indicating that the value in the processing lane is negative. The control circuitry monitors the values ​​in each lane of the processing device, and when a value in a processing lane becomes negative, the control circuitry is configured to disable that processing lane such that no further operations involving that processing element are performed. The value in the processing lane may be any value present in the processing lane. In some configurations, the value is the value of an input element in an input register in the processing lane. In other configurations, the value is the value of an output element in an output register of a preceding operation of the processing lane.

[0020] In some configurations, the one or more predetermined conditions include a divide-by-zero condition, and the control circuitry is configured to modify the per-lane mask in response to the processing state of the processing lane indicating that the value in the processing lane is a divide-by-zero condition. The control circuitry monitors values ​​in each lane of the processing device, and when a value in the processing lane indicates that a divide-by-zero operation has occurred, e.g., because the value in the processing lane indicates a NaN (Not a Number) value, the control circuitry is configured to disable that processing lane such that no further operations involving that processing element are performed. The value in the processing lane may be any value present in the processing lane. In some configurations, the value is the value of an input element in an input register in the processing lane. In other configurations, the value is the value of an output element in an output register of a preceding operation of the processing lane.

[0021] In some configurations, the one or more predetermined conditions include a numeric condition that specifies a number, and the control circuitry is configured to modify the per-lane mask in response to the processing state of the processing lane indicating that the value in the processing lane is equal to the number. The control circuitry is configured to monitor the value in each lane of the processing device, and when the value in the processing lane is equal to the number, the control circuitry is configured to disable that processing lane such that no further operations involving that processing element are performed. The value in the processing lane may be any value present in the processing lane. In some configurations, the value is a value of an input element of an input register in the processing lane. In other configurations, the value is a value of an output element of an output register of a prior operation of the processing lane. In some configurations, the control circuitry comprises a storage circuitry that stores the number. In other configurations, the storage circuitry is used to store a pointer to where the number is stored.

[0022] In some configurations, the processing device further comprises a plurality of data input channels configured to receive data associated with the data processing operation, the one or more predetermined conditions including a data condition that designates one data input channel of the plurality of data input channels, and the control circuitry configured to modify the per-lane mask in response to a processing state of a processing lane indicating that data in an input channel associated with the processing lane is marked as invalid. In this manner, the control circuitry may be arranged to control the processing circuitry to perform operations only in lanes of the plurality of processing lanes for which there is available data. In some configurations in which the processing device is arranged as a triggered processing device, the data condition may be used to prioritize among the triggered instructions such that priority is given to instructions for which the greatest amount of data is available, thereby resulting in a greater throughput of instructions.

[0023] The per-lane mask, on the other hand, is controlled by the control circuitry in response to the processing state of each of the processing lanes. In some configurations, the decode circuitry is configured to generate a set mask control signal in response to a set mask instruction specifying a new per-lane mask, and the processing circuitry is configured to set the new per-lane mask as the per-lane mask in response to the set mask control signal. The new per-lane mask may be specified as an immediate value or by specifying a register or a portion of a register that stores the new per-lane mask. In this manner, a programmer may specify the per-lane mask to provide the programmer with control over which lanes of the multiple processing lanes are enabled. For example, a programmer may select to enable all processing lanes of the multiple processing lanes. In some configurations, the decoder circuitry, in response to the set mask instruction, causes the control circuitry to pause monitoring of each processing lane of the multiple processing lanes. In other configurations, the set mask instruction sets an initial per-lane mask that is subsequently modified by the control circuitry based on the processing state of each processing lane.

[0024] In some configurations, the decode circuitry is configured to generate a reset condition control signal in response to the reset condition instruction, and the processing circuitry is configured to set the predetermined condition to a default predetermined condition in response to the reset condition control signal. The default predetermined condition may be any of the conditions described above. In some configurations, the default predetermined condition is a null condition, and when the default predetermined condition is set, the control circuitry is configured to maintain a current value of the per-lane mask independent of a processing state of each of the multiple processing lanes.

[0025] In some configurations, the per-lane mask is a single implicit predicate, and the processing circuitry is configured to reference the implicit predicate for all instructions of the multiple instructions performing processing in the multiple processing lanes. Thus, the single implicit predicate is used to determine, for each operation performed by the processing circuitry, which lanes of the multiple processing lanes are enabled and which lanes of the multiple processing lanes are disabled. In an alternative configuration, the per-lane mask is one of multiple implicit predicates, and the processing circuitry is configured to reference one of the multiple implicit predicates depending on the type of instruction. For each instruction executed by the processing circuitry, the processing circuitry accesses an implicit predicate of the multiple implicit predicates associated with that type of instruction. In this way, a programmer can use different predicates to control different types of instructions.

[0026] The concepts described herein may be embodied in computer readable code for the manufacture of devices embodying the concepts described. For example, the computer readable code may be used at one or more stages of a semiconductor design and manufacturing process, including an electronic design automation (EDA) stage, to manufacture integrated circuits comprising devices embodying the concepts. Such computer readable code may additionally or alternatively enable the definition, modeling, simulation, verification and / or testing of devices embodying the concepts described herein.

[0027] For example, computer readable code for producing a device embodying the concepts described herein can be embodied in code defining a hardware description language (HDL) representation of the concept. For example, the code can define a register-transfer-level (RTL) abstraction of one or more logic circuits to define a device embodying the concept. The code may define an HDL representation of one or more logic circuits embodying the device using intermediate representations such as Verilog, SystemVerilog, Chisel, or Very High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) and FIRRTL. The computer readable code can provide a definition embodying the concept using system level modeling languages ​​such as SystemC and SystemVerilog or other behavioral representations of the concept that can be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concept.

[0028] Additionally or alternatively, the computer readable code may define a low level description of integrated circuit elements embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer readable representations of the integrated circuit elements may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for use in manufacturing a device embodying the invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer readable code that is loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the concepts described. The FPGA may be deployed for concept validation and testing purposes prior to manufacture in an integrated circuit, or the FPGA may be deployed directly into a product.

[0029] The computer readable code may include a mixture of code representations for fabrication of a device, including, for example, a mixture of one or more of an RTL representation, a netlist representation, or another computer readable definition used in a semiconductor design and manufacturing process to fabricate a device embodying the invention. Alternatively or additionally, a concept may be defined in a combination of a computer readable definition used in a semiconductor design and manufacturing process to fabricate a device and computer readable code that defines instructions to be executed by the defined device once fabricated.

[0030] Such computer readable code may be disposed on any known transitory computer readable medium (such as wired or wireless transmission of code over a network) or on a non-transitory computer readable medium such as a semiconductor, magnetic disk, or optical disk. Integrated circuits manufactured using the computer readable code may include components such as one or more of a central processing unit, a graphic processing unit, a neural processing unit, a digital signal processor, or other components that individually or collectively embody the concepts.

[0031] Particular configurations of the present technique will now be described with reference to the figures.

[0032] FIG. 1 shows a schematic of a processing device 10 according to various configurations of the present technique. The processing device 10 comprises a decoder circuit 12, a control circuit 14, and a processing circuit 20. The decoder circuit 12 is provided to decode instructions from an instruction set architecture and generate control signals used to control the processing circuit 20. The processing circuit 20 comprises a number of processing lanes 24. In the configuration shown, four processing lanes 24 are provided, namely processing lane 00 24(A), processing lane 01 24(B), processing lane 10 24(C), and processing lane 11 24(D). The control signals provided by the decoder circuit 12 control each lane 24 of the processing circuit to perform a processing operation when that processing lane 24 is enabled. The control as to whether a processing lane is enabled is managed by the control circuit 14. The control circuit monitors the processing state of each of the processing lanes 24 and determines whether the lane satisfies one or more predetermined conditions 18. Depending on whether the processing state of each processing lane 24 satisfies a predetermined condition 18, the control circuitry 14 modifies the per-lane mask 16. In the example shown, the control circuitry 14 has determined that processing lane 10 24(C) satisfies the predetermined condition 18 and has set the corresponding bit of the per-lane mask 16 to 0 to indicate that processing lane 10 should be disabled. The per-lane mask 16 is fed back to the processing circuitry and the switches 22 are used to control whether the corresponding processing lane is enabled or disabled. In the configuration shown, the per-lane mask 16 is set to 1101, indicating that processing lane 00 24(A), processing lane 01 24(B) and processing lane 11 24(D) are enabled and processing lane 10 24(C) is disabled. Thus, in response to the most significant (left-most) bit of the per-lane mask 16 being set to logic 1, the switch 22(A) is in an enabled state and the control signal generated by the decoder circuitry 12 is used to control processing lane 00 24(A). In response to the next most significant bit (the second-leftmost bit) of the per-lane mask 16 being set to logic one, switch 22(B) is in an enabled state and the control signal generated by decoder circuit 12 is used to control processing lane 01 24(B).In response to the next most significant bit (the third bit from the left) of the per-lane mask 16 being set to logic 0, the switch 22 (C) is in a disabled state, the control signal generated by the decoder circuit 12 is withheld from the processing lane 10 24 (C), and the processing lane 10 24 (C) is disabled. Finally, in response to the least significant bit (the rightmost bit) of the per-lane mask 16 being set to logic 1, the switch 22 (D) is in an enabled state, and the control signal generated by the decoder circuit 12 is used to control the processing lane 11 24 (D). The control circuit 14 is arranged to continuously monitor the processing circuits and modify the per-lane mask 16 if, at any time, the processing state of a processing lane 24 changes such that a predetermined condition 18 is satisfied for that processing lane, the control circuit 14 being configured to modify the corresponding bit of the per-lane mask 16.

[0033] In some alternative configurations, the number of processing lanes 24 in processing device 10 is greater than four. For example, the number of processing lanes 24 may be eight, sixteen, thirty-two, or more. In such configurations, the per-lane mask comprises more bits, one for each of the processing lanes, and control of whether a processing lane is enabled or disabled is performed as described with respect to the indicated processing lane. In some configurations, control circuitry 14 forms part of the same circuit block as processing circuitry 20.

[0034] FIG. 2 illustrates a schematic of a processing device 10 according to various configurations of the present technique. The functional components illustrated in FIG. 2 are the same as those illustrated in FIG. 1, and for brevity, the description of these components will not be repeated. FIG. 2 illustrates the response of the processing device 10 to a set mask instruction specifying a new value for the per-lane mask 16 and an update condition instruction specifying a new condition. In response to the set mask instruction, the decoder circuit 12 generates a set mask control signal that is passed to the control circuit 14 via the processing circuit 20. In response to the set mask control signal, the control circuit 14 modifies the per-lane mask to the new per-lane mask specified in the set mask instruction. In response to the update condition instruction, the decoder circuit 12 generates an update condition control signal that is passed to the control circuit 14. In response to the control signal issued by the decoder circuit 14, the control circuit is configured to modify the predetermined condition 18, and in response to the processing state of the processing lane satisfying the new condition, the control circuit modifies the per-lane mask. In some alternative configurations, the set mask control signal and the update condition control signal are passed directly from the decoder circuit 12 to the control circuit 14 without passing through the processing circuit.

[0035] FIG. 3 illustrates a schematic of a processing device 30 arranged to operate as a triggered processing device according to various configurations of the present technique. The processing device 30 comprises a front-end circuit 36, a decoder circuit 38, a processing circuit 40, and a control circuit 46. The front-end circuit 36 ​​is arranged to store a plurality of fetched instructions, each associated with a trigger condition, and to generate a triggered instruction when the execution state of the processing circuit satisfies a trigger condition associated with one of the plurality of fetched instructions. The front-end circuit also comprises a plurality of input channels for fetching data associated with the fetched instructions. The triggered instruction is passed from the front-end circuit 36 ​​to a decoder circuit 38, which generates a control signal that is passed to the processing circuit 40. The processing circuit performs the operation defined by the control signal using a plurality of processing lanes 44 that are enabled / disabled based on a per-lane mask 32. The per-lane mask 32 is continuously updated by the control circuit 46 based on the processing state of the individual processing lanes 44 that satisfy the predetermined condition 32. Thus, the selection of the instruction to be executed is based on the execution state of the entire processing circuitry 40, and the per-lane execution of the operation is controlled by the per-lane mask 32 based on the processing state of each processing lane. The per-lane mask 32 is also fed back to the front-end circuitry 36. When the execution state of the processing circuitry 40 is such that multiple fetched instructions are eligible to be passed to the decoder circuitry 38 as triggered instructions, the front-end circuitry 36 is configured to select which of the eligible instructions should be used first (prioritized) to generate the triggered instruction. In some alternative configurations, the control circuitry is configured to determine whether the predetermined condition 34 is met based on whether the input data received by the front-end processing circuitry 36 is marked as valid or invalid per lane.

[0036] 4 shows in schematic detail a control circuit 50 of a processing device according to various configurations of the present technique. The control circuit 50 is configured to store a first per-lane mask 54 and a second per-lane mask 56 and is arranged to select which per-lane instruction mask should be used based on the type of instruction being processed by the processing circuit. The control circuit 50 receives an indication of an instruction type that controls a switch 52 to select between the first per-lane mask 54 and the second per-lane mask 56. The control circuit 50 is also configured to store a first predetermined condition 58 and a second predetermined condition 60. The processing state of each processing lane of the processing circuit is compared to the first predetermined condition 58 and the second predetermined condition 60. A bit of the first per-lane mask 54 is set when the processing state of the corresponding processing lane satisfies the first predetermined condition 58, and a bit of the second per-lane mask 56 is set when the processing state of the corresponding processing lane satisfies the second predetermined condition 60. In this manner, the processing state of a particular processing lane may be such that a first predetermined condition 58 is not satisfied (as indicated in the third least significant bit of first per-lane mask 54) and a second predetermined condition 60 is satisfied (as indicated in the third least significant bit of second per-lane mask 56). As a result, the third least significant processing lane is valid for instructions of the type associated with second per-lane mask 56 and invalid for instructions of the type associated with first per-lane mask 54.

[0037] FIG. 5 shows a schematic diagram of a data processing device 62 arranged as a spatial architecture according to various examples of the present technique. Spatial architectures can accelerate some applications by spreading out the computations that form the most time-consuming part of the program execution in space instead of in time. The computations are spread out in "space" by using multiple hardware units capable of concurrent operation. In addition to taking advantage of the concurrency opportunities offered by isolated applications that are distributed on the chip, spatial architectures such as the processing device 62 also take advantage of distributed on-chip memory. In this way, each processing element is associated with one or more memory blocks in close proximity to it. As a result, spatial architectures can avoid the von Neumann bottleneck that hampers the performance of many conventional architectures.

[0038] The processing unit 62 comprises an array of processing elements, also called interface tiles (IT), connected to a cache hierarchy or main memory via interface nodes, which are connected to a network via multiplexers (X). The processing elements within the processing unit 62 according to the configurations described herein comprise two different types of circuitry. Each processing element comprises a processing circuit, also called a compute tile (CT), and a memory control circuit, also called a memory tile (MT). The role of the CT is to perform the majority of the data processing operations and arithmetic calculations. Each of the compute tiles within the processing elements of the processing unit 62 may be arranged as described in connection with Figures 1-4.

[0039] The role of the MT is to perform data accesses to locally attached memory (local storage circuitry), data transfers to / from more distant areas of memory, and inter-processing element memory transfers between the processing element and other processing elements.

[0040] In some exemplary configurations, each of the processing elements of the processing unit 62 comprises a local storage circuit connected to a respective memory control circuit (MT), with each memory control circuit (MT) having a direct connection to one processing circuit (CT). Each MT-CT cluster is connected to a network on chip that is used to transfer data between the memory control circuits (MT) and between each memory control circuit (MT) and an interface node (IT). In an alternative configuration, local storage circuits are provided between multiple processing elements and are accessible by multiple memory control circuits (MT). The processing elements may be conventional processing elements. Alternatively, the processing elements may be trigger processing elements whose instructions are executed when one or more respective trigger conditions are met.

[0041] Each processing element of the data processing device 62 shown in Fig. 5 is connected via a set of input and output channels to a network-on-chip comprising switches and data links between the switches forming a two-dimensional torus topology layout. Data can be routed around the network-on-chip using any algorithm. However, a particularly efficient routing algorithm is the xy routing algorithm modified to take into account the torus layout. The xy algorithm prevents routing deadlocks in the network (cyclic dependencies between processing elements and / or network resources that make forward progress impossible) by prohibiting data routed along the y direction from subsequently being routed along the x direction.

[0042] 6 illustrates in schematic form further details of the operation of a processing device according to various configurations of the present technique when the processing device is arranged as a triggered architecture. The processing element comprises a current execution state latch 70 for latching the current execution state of the processing circuitry, and an instruction cache 72, 74 for storing a sequence of instruction opcodes 72 associated with each of a plurality of fetched instructions together with a corresponding trigger condition and next execution state information 74 indicative of the next execution state to be reached upon successful execution of the corresponding instruction by the processing element. The processing element further comprises a pre-decode circuit 76 for performing an initial pre-decode step to split the instructions stored in the instruction cache 72, 74 into micro-operations suitable for processing in the processing lanes 80 of the processing circuitry 66. The processing element further comprises a next execution state latch 84 for storing the next execution state to be entered into by the processing circuitry upon completion of the current instruction, and a completion latch 82 for latching an indication as to whether the instruction has completed. The processing element includes a switch (demultiplexer) 86 that updates the current execution state of the processing circuit stored in the current execution state latch 70 in response to the completion latch 82 indicating that the current instruction has completed. The current execution state latch 70, the instruction caches 72, 74, the pre-decode circuit 76, the completion latch, and the next execution state latch together form a front-end circuit responsible for generating triggered instructions based on the current execution state of the processing element. The processing element also includes a control circuit 64 arranged according to any of the configurations described herein. The control circuit monitors the processing state of the processing lanes 80 and determines whether each of the processing lanes satisfies one or more predetermined conditions. The control circuit 64 updates the per-lane mask in response to the processing lane processing state fed back to the processing circuit 80 such that each of the processing lanes is enabled or disabled. The control circuit 64 also feeds back the per-lane mask to the instruction caches 72, 74 of the front-end circuit which uses the per-lane mask to prioritize the fetched instructions when trigger conditions associated with two or more of the multiple fetched instructions are simultaneously satisfied.

[0043] During operation, the processing element determines an instruction stored in the instruction cache 72, 74 to be the next triggered instruction based on the current execution state latched in the current execution state latch 70. If the current execution state latched in the current execution state latch 70 matches a trigger condition associated with an instruction stored in the instruction cache 72, 74, then that instruction is passed to the pre-decode circuit 76 for decomposition into micro-operations, and the micro-operations are passed to the decode circuit 78 as triggered instructions. In addition, the instruction cache 72, 74 determines the corresponding next execution state 74 associated with the instruction for which the trigger condition has been met. The next execution state 74 is passed to the next execution state latch 84. At this point, the instruction has not completed, and therefore the completion latch stores an indication that this is the case. The current execution state latch 70 is not updated with the next execution state stored in the next execution state latch 84. Instead, the current execution state stored in the current execution state latch 70 is fed back to the input of the current execution state latch 70 via the switch 86, and in this manner, the current execution state latch is maintained at the current execution state. The triggered instruction is passed to decode circuitry 78, which generates control signals to cause those processing lanes 80 whose per-lane masks stored in the control circuit indicate that the corresponding processing lanes are enabled to perform processing operations based on the triggered instruction. When the processing operation is completed, an indication that the processing operation is completed is stored in a completion latch. Outputs from the processing lanes 80 may be used to update the next execution state based on operations performed during processing, the processing state of each of the processing lanes 80 being monitored by control circuitry 64. When a processing element latches in completion latch 82 that processing is complete, the current execution state latch is updated to contain the value previously latched in the next execution state latch. The new current execution state latched in current execution state latch 70 may then be used by the processing element to determine the next instruction used to generate the triggered instruction.

[0044] Figures 7a and 7b show schematic diagrams of the values ​​of the predefined conditions and masks per lane before and after executing instructions in response to a sequence of instructions, the instructions being listed in order from the first instruction at the top of each figure to the last instruction at the bottom of each figure.

[0045] Starting from FIG. 7a, the first instruction received is a "listener SAT" instruction. The "listener" instruction is a condition update instruction that causes the processing unit to update the predetermined condition to a saturation condition. In response to this instruction, the control circuitry sets the predetermined condition to a saturation condition. In the illustrated example, it is assumed that the per-lane mask before this instruction is received is [1,1,1,1], indicating that each lane of the multiple processing lanes is valid. In this case, the values ​​in the processing lanes after the instruction, indicating the values ​​of the vector vecJ determined by the preceding instruction, are [-124,2,2,-64]. The "listener SAT" instruction updates the predetermined condition but does not affect the values ​​in the processing lanes or the per-lane mask after the instruction is executed.

[0046] The next instruction to be executed is a saturating addition operation "qadd vecJ,vecJ,vecS", where vecS has already been defined (e.g., by a previous instruction) to be "vecS=[126,126,126,126]". This instruction adds the value of vecS to vecJ and stores the output in vecJ. Since qadd is a saturating addition, the output does not exceed the saturation value, but instead saturates to the maximum value that can be stored in vecJ. The per-lane mask after the "listener SAT" instruction was set to [1,1,1,1]. Thus, each processing lane of the multiple processing lanes is valid, and a saturating addition operation is performed for each lane. The values ​​in the processing lane are assumed to saturate at a value of 127. Thus, the values ​​in the processing lane after the instruction are vecJ=[2,127,127,62]. Because the second and third least significant elements of vecJ are saturated, the control circuit automatically sets the mask for each lane after the instruction to [1,0,0,1].

[0047] The next instruction to be executed is a second saturating addition operation "qadd vecJ,vecJ,vecS", where vecS has already been defined (e.g., by a previous instruction) to be "vecS=[126,126,126,126]". This instruction adds the value of vecS to vecJ and stores the output in vecJ. Since qadd is a saturating addition, the output does not exceed the saturation value, but instead saturates to the maximum value that can be stored in vecJ. The per-lane mask after the "listener SAT" instruction was set to [1,0,0,1]. Thus, the top and bottom processing lanes of the multiple processing lanes are enabled, and a saturating addition operation is performed on these lanes. The second and third bottom processing lanes are disabled, and therefore no processing is performed in these lanes. The values ​​in the processing lanes are assumed to saturate at a value of 127. Thus, the value of the processing lane after the instruction is vecJ=[127,127,127,127]. Since each of the elements of vecJ is saturated, the control circuit automatically sets the mask for each lane after the instruction to [0,0,0,0].

[0048] The next instructions issued are a “reset-condition” instruction which resets the predefined condition to the default predefined condition, and a “set per-lane mask[1,1,1,1]” instruction which sets the value of the per-lane mask to [1,1,1,1]. The value of vecJ is not changed in response to these instructions; instead, the predefined condition is reset and the per-lane mask is updated.

[0049] The next instruction is a "listener value,64" instruction that updates one or more predefined conditions such that the predefined conditions are met when the value of vecJ in the processing lane is set to 64. Because none of the values ​​in the processing lane are set to 64, the per-lane mask remains unmodified and has a value of [1,1,1,1] after the "listener value,64" instruction is executed.

[0050] The next instruction is another saturating addition operation "qadd vecJ,vecJ,vecS", where vecS has already been defined (e.g., by a previous instruction) to be "vecS=[-63,-64,-65,-66]". This instruction adds the value of vecS to vecJ and stores the output in vecJ. Because qadd is a saturating addition, the output does not exceed the saturation value, but instead saturates to the maximum value that can be stored in vecJ. The per-lane mask after the "listener value,64" instruction was set to [1,1,1,1]. Thus, each lane of the multiple processing lanes is valid, and a saturating addition operation is performed for all lanes. The value in the processing lane after the instruction is vecJ=[64,63,62,61]. Because the most significant element of vecJ is equal to 64, the control circuit automatically sets the per-lane mask after the instruction to [0,1,1,1].

[0051] The next instruction is another saturating addition operation "qadd vecJ,vecJ,vecS", where vecS has already been defined (e.g., by a previous instruction) to be "vecS=[1,1,1,1]". This instruction adds the value of vecS to vecJ and stores the output in vecJ. Because qadd is a saturating addition, the output does not exceed the saturation value, but instead saturates to the maximum value that can be stored in vecJ. The per-lane mask after the preceding "qadd vecJ,vecJ,vecS" instruction was set to [0,1,1,1]. Thus, the three lowest (rightmost) lanes of the multiple processing lanes are valid, and a saturating addition operation is performed on these lanes. The top (leftmost) lane of the multiple processing lanes is invalid, as the per-lane mask indicates that the predetermined condition has already been met for this lane. The value in the processing lane after the instruction is vecJ=[64,64,63,62]. Since the two most significant elements of vecJ are equal to 64, the control circuit automatically sets the per-lane mask after the instruction to [0,0,1,1].

[0052] The next instruction is another saturating addition operation "qadd vecJ,vecJ,vecS", where vecS has already been defined (e.g., by a previous instruction) to be "vecS=[1,1,1,1]". This instruction adds the value of vecS to vecJ and stores the output in vecJ. Because qadd is a saturating addition, the output does not exceed the saturation value, but instead saturates to the maximum value that can be stored in vecJ. The per-lane mask after the preceding "qadd vecJ,vecJ,vecS" instruction was set to [0,0,1,1]. Thus, the two bottom (rightmost) lanes of the multiple processing lanes are valid, and a saturating addition operation is performed on these lanes. The two top (leftmost) lanes of the multiple processing lanes are invalid, because the per-lane mask indicates that the predetermined condition has already been met for these lanes. The value in the processing lanes after the instruction is vecJ=[64,64,64,63]. Since the three most significant elements of vecJ are equal to 64, the control circuit automatically sets the per-lane mask after the instruction to [0,0,0,1].

[0053] The stream of instructions continues in FIG. 7b, where the first instruction is a "reset-condition" instruction that sets the predetermined condition to the default condition, and a "listener div0" instruction that sets the predetermined condition to the div0 condition. Thus, the control circuitry stops monitoring whether the value is equal to 64, and instead monitors for an indication that a divide-by-zero has occurred. The values ​​in the processing lanes are not modified by the "listener div0" operation. However, now, a per-lane mask is set based on whether the values ​​in the processing lanes after the instruction satisfy the divide-by-zero condition. The values ​​in the processing lanes after the instruction are [64,64,64,63], neither of which indicates that a divide-by-zero has occurred. Thus, the value of the per-lane mask after the instruction is [1,1,1,1].

[0054] The next instruction is an "sdiv vecJ,vecJ,vecS" instruction, where vecS has already been defined (e.g., by a previous instruction) to be "vecS=[4,2,1,0]". The sdiv instruction causes each element of vector vecJ to be divided by the corresponding element of vector vecS, and the result is stored in vector vecJ. The per-lane mask after the preceding "listener div0" instruction was set to [1,1,1,1]. Thus, all lanes of the multiple processing lanes are valid, and a division operation is performed on all lanes. The value in the processing lane after the instruction is vecJ=[16,32,64,NaN] (NaN is a value indicating that a division by zero has occurred and therefore the result is not a number). The control circuit is configured to set the per-lane mask after the instruction to [1,1,1,0] in response to the division by zero.

[0055] The next instruction is a "set per-lane mask [1,1,1,1]" instruction. The purpose of this instruction is to set the current value of the per-lane mask, in this case to [1,1,1,1]. However, the control circuitry still monitors for when a divide-by-zero error occurs, so the control circuitry sets the per-lane mask to [1,1,1,0] so that the "set per-lane mask" instruction does not affect the per-lane mask.

[0056] The next instruction is another "sdiv vecJ,vecJ,vecS" instruction, where vecS has already been defined (e.g., by a previous instruction) to be "vecS=[2,1,0,-1]". The sdiv instruction causes each element of vector vecJ to be divided by the corresponding element of vector vecS, and the result is stored in vector vecJ. The per-lane mask after the preceding "set per-lane mask [1,1,1,1]" instruction was set to [1,1,1,0]. Thus, the three topmost (leftmost) lanes of the multiple processing lanes are valid, and the division operation is performed on these lanes. The bottommost (rightmost) lane of the multiple processing lanes is invalid, and no division operation is performed on this lane. The value in the processing lane after the instruction is vecJ=[8,32,NaN,NaN] (NaN is a value indicating that the result is not a number because a division by zero occurred). The control circuit is configured to, in response to a divide by zero, set the mask for each lane after the instruction to [1,1,0,0].

[0057] The next instruction is a "listener negative" instruction that adds a new condition to the given conditions. In this case, the condition is a negative condition, which causes the control circuit to monitor for negative values ​​in the processing lanes in addition to monitoring for divide by zero operations. The "listener negative" instruction is not modifying any values ​​in the processing lanes, and since none of the processing lanes contain negative values, the mask per lane after the instruction remains [1,1,0,0].

[0058] The last instruction is a "qadd vecJ,vecJ,vecJ,vecS" instruction, where vecS has already been defined (e.g., by a previous instruction) to be "vecS=[-128,-128,-128,-128]". The per-lane mask after the preceding "listener negative" instruction was set to [1,1,0,0]. Thus, the two topmost (leftmost) lanes of the multiple processing lanes are enabled, and a division operation is performed on these lanes. The two bottommost (rightmost) lanes of the multiple processing lanes are disabled, and no division operation is performed on these lanes. The value in the processing lane after the instruction is vecJ=[-120,-96,NaN,NaN] (NaN is a value indicating that a division by zero occurred, so the result is not a number). The control circuitry is configured to set the mask for each lane after the instruction to [0,0,0,0] in response to a divide by zero in the two lowest (rightmost) lanes and a negative value in the two highest (leftmost) lanes.

[0059] The foregoing exemplary instructions are provided to generally illustrate the operation of the control circuitry to enable / disable a processing lane of a processing circuit in response to the processing state of that processing lane. It will be readily apparent to one skilled in the art that alternative instructions may be provided in a different order and that the control circuitry monitors the processing state of the processing lanes to determine which of a plurality of processing lanes should be enabled / disabled.

[0060] FIG. 8 shows a schematic sequence of steps performed by the control circuitry according to various configurations of the present technique. The flow starts at step S800, where the control circuitry waits for the next instruction cycle. At the next instruction cycle, the flow proceeds to step S802, where the control circuitry begins a process of determining whether a predetermined condition is met for each of the lanes. At step S802, a variable j is set equal to 0. The variable j is used as a counter to step through each of the lanes. The flow then proceeds to step S804, where it is determined whether a predetermined condition is met for lane j. If the predetermined condition is met for lane j, the flow proceeds to step S806, where the jth bit of the per-lane mask is set to indicate that the predetermined condition is met. The flow then proceeds to step S808. However, if at step S804 it is determined that the predetermined condition is not met for lane j, the flow proceeds to step S812, where the jth bit of the per-lane mask is set to indicate that the predetermined condition is not met. The flow then proceeds to step S808. In step S808, it is determined whether there are more lanes to test. If in step S808, it is determined that there are no more lanes to test, the flow returns to step S800. However, if in step S808, it is determined that there are more lanes to test, the variable j is incremented and the flow returns to step S804. The process of determining whether the predetermined condition is met is shown sequentially. However, the process of determining whether the predetermined condition is met may be performed in parallel for each of the lanes in an alternative configuration.

[0061] FIG. 9 shows a schematic sequence of steps performed by a processing device according to various configurations of the present technique. The flow starts at step S900, where it is determined whether an instruction has been received. If an instruction has not been received, the flow remains at step S900. If it is determined at step S900 that an instruction has been received, the flow proceeds to step S902. At step S902, the decoder circuit generates a control signal in response to the received instruction. The flow then proceeds to step S904, where the processing circuit performs processing operations in the plurality of processing lanes for which the per-lane mask indicates that processing is enabled. Processing operations are not performed in the processing lanes for which the per-lane mask indicates that processing is disabled. The flow then proceeds to step S906, where the control circuit monitors the processing status of the processing lanes. The flow then proceeds to step S908, where the control circuit updates the per-lane mask to indicate which processing lanes of the plurality of processing lanes satisfy one or more predetermined conditions. The flow then returns to step S900.

[0062] FIG. 10 illustrates in a schematic manner the manufacture of a processing device according to various configurations of the present technique. The manufacture is based on computer readable code 1002 stored on a non-transitory computer readable medium 1000. The computer readable code can be used in one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture an integrated circuit with a device embodying the concept. The manufacturing process includes applying the computer readable code 1002 directly to one or more programmable hardware units, such as field programmable gate arrays (FPGAs), to configure the FPGA to embody the configurations described above, or to facilitate the manufacture of a device implemented as one or more integrated circuits or a device embodying the configurations described above. The manufactured design 1004 is a processing device 10 comprising a decoder circuit 12, a processing circuit 20, and a control circuit 14 as described with reference to FIG. 1. In an alternative configuration, the computer readable code 1002 stored on the non-transitory computer readable medium 1000 can be configured to store information used to facilitate the manufacture of a processing device according to the configurations described.

[0063] In summary, there is a processing device including a decoder circuit. The decoder circuit is configured to generate a control signal in response to an instruction. The processing device further comprises a processing circuit comprising a plurality of processing lanes. The processing circuit is configured to perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing is valid for that processing lane in response to the control signal. The processing device further comprises control circuitry for monitoring each processing lane of the plurality of processing lanes for each instruction of the plurality of instructions performed in the plurality of processing lanes, and for modifying the per-lane mask for one processing lane of the plurality of processing lanes in response to a processing state of the processing lane satisfying one or more predetermined conditions.

[0064] In this application, the term "configured to..." is used to mean that an element of an apparatus has a configuration that is capable of performing a defined operation. In this context, "configuration" refers to a manner of arrangement or interconnection of hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that an apparatus element needs to be modified in any way to provide the defined operation.

[0065] Although exemplary configurations have been described in detail herein with reference to the accompanying drawings, it will be understood that the invention is not limited to exact configurations thereof, and various changes, additions, and modifications may be made by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims. For example, various combinations of the features of the following dependent claims may be made with the features of the independent claims without departing from the scope of the invention.

Claims

1. A processing device, a decoder circuit configured to generate control signals in response to the instructions; a processing circuit comprising a plurality of processing lanes, the processing circuit configured to, in response to the control signal, perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing is valid for that processing lane; and control circuitry that monitors each processing lane of the plurality of processing lanes for each instruction of a plurality of instructions performed in the plurality of processing lanes, and modifies the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane satisfying one or more predetermined conditions.

2. the command is a triggered command; 2. The processing device of claim 1, wherein the processing device is a triggered processing device comprising a front-end circuit that processes a plurality of fetched instructions and generates the triggered instruction in response to the execution state of the processing circuitry satisfying a trigger condition associated with one of the plurality of fetched instructions.

3. 3. The processing device of claim 2, wherein the front-end circuitry is configured to, in response to determining that two or more fetched instructions of the plurality of fetched instructions satisfy a trigger condition at a given time, determine a priority of the two or more fetched instructions based on a number of enabled processing lanes associated with each of the two or more fetched instructions.

4. 4. The processing device of claim 3, wherein the front-end circuitry is configured to determine the priority based on the length of time that the trigger condition of the two or more fetched instructions has been satisfied.

5. the processing unit comprises a plurality of processing elements arranged to form a spatial architecture; The processing device according to any one of claims 1 to 4, wherein the decoder circuit, the control circuit, and the processing circuit are arranged in one processing element of the plurality of processing elements.

6. The processing device of claim 5 , wherein the plurality of processing elements are connected via a two-dimensional network arranged as a two-dimensional torus.

7. the decoder circuit generates an update condition control signal in response to an update condition instruction specifying a new condition; 5. The processing device of claim 1, wherein the processing circuitry is configured to set the new condition as one of the one or more predetermined conditions in response to the update condition control signal.

8. The processing device of any one of claims 1 to 4, wherein the control circuitry is configured to modify the per-lane mask to meet an energy consumption target.

9. 5. The processing device of claim 1, wherein the one or more predetermined conditions include a saturation condition, and wherein the control circuitry is configured to modify the per-lane mask in response to the processing state of the processing lane indicating that a value in the processing lane is saturated.

10. 5. The processing device of claim 1, wherein the one or more predetermined conditions include a negative condition, and wherein the control circuitry is configured to modify the per-lane mask in response to the processing state of the processing lane indicating that the value in the processing lane is negative.

11. 5. The processing device of claim 1, wherein the one or more predetermined conditions include a divide-by-zero condition, and wherein the control circuitry is configured to modify the per-lane mask in response to the processing state of the processing lane indicating that a value in the processing lane is a divide-by-zero condition.

12. 5. The processing device of claim 1, wherein the one or more predetermined conditions include a numerical condition specifying a number, and the control circuitry is configured to modify the per-lane mask in response to the processing state of the processing lane indicating that a value in the processing lane is equal to the number.

13. a plurality of data input channels configured to receive data associated with the data processing operation; 5. The processing device of claim 1, wherein the one or more predetermined conditions include a data condition specifying one data input channel of the plurality of data input channels, and the control circuitry is configured to modify the per-lane mask in response to the processing state of the processing lane indicating that data in the one data input channel associated with the processing lane is marked as invalid.

14. the decoder circuit generates a mask setting control signal in response to a mask setting command specifying a new per-lane mask; The processing device of claim 1 , wherein the processing circuitry is configured to set the new per-lane mask as the per-lane mask in response to the mask setting control signal.

15. the decoder circuit generates a reset condition control signal in response to a reset condition command; The processing device according to any one of claims 1 to 4, wherein the processing circuit is configured to set the predetermined condition to a default predetermined condition in response to the reset condition control signal.

16. 5. The processing device of claim 1, wherein the per-lane mask is a single implicit predicate, and the processing circuitry is configured to reference the implicit predicate for all instructions among the plurality of instructions that perform processing in the plurality of processing lanes.

17. 5. The processing device of claim 1, wherein the per-lane mask is one of a plurality of implicit predicates, and the processing circuitry is configured to reference one of the plurality of implicit predicates depending on the type of the instruction.

18. 1. A method of operating a processing device comprising processing circuitry comprising a plurality of processing lanes, the method comprising: generating a control signal in response to the command; in response to the control signal, performing a vector processing operation using the processing circuitry in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing is valid for that processing lane; monitoring each processing lane of the plurality of processing lanes for each instruction of a plurality of instructions performed in the plurality of processing lanes, and modifying the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane satisfying one or more predetermined conditions.

19. 1. A non-transitory computer readable medium for storing computer readable code for manufacturing a processing device, comprising: a decoder circuit configured to generate control signals in response to the instructions; a processing circuit comprising a plurality of processing lanes, the processing circuit responsive to the control signal to perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing is valid for that processing lane; and control circuitry that monitors each processing lane of the plurality of processing lanes for each instruction of a plurality of instructions performed in the plurality of processing lanes, and that modifies the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane satisfying one or more predetermined conditions.

Images