Method for providing sinusoidal phase current with control and charging

Abstract

1. A method for supplying a rectifier with a sinusoidal phase current from a three-phase power supply network and its use, comprising the steps of detecting and evaluating a string voltage, rectifying the string voltage, connecting a capacitor to a positive or negative output of the rectifier via either a first or a second switching transistor, controlling control inputs of the first and second switching transistors by a control unit such that only the first switching transistor, only the second switching transistor, or both the first and second switching transistors are conductive, or neither is conductive, and charging the capacitor with a capacitor voltage in response to control of the control inputs such that the difference between the string voltage and the capacitor voltage dropped across the coil results in a sinusoidal flow of the average value of the coil current.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to Luxembourg patent application LU501001, filed on December 13, 2021, the entire contents of which are incorporated by reference herein in their entirety.

[0002] [Field of the Invention] The present invention relates to a method for modulating or clocking the string voltages of a network circuit from a three-phase power supply network, the method ensuring that the phase currents at the input of the rectifier are essentially sinusoidal, regardless of the load. [Background technology]

[0003] Network circuits are known from the prior art. EP 3068024 A1 discloses a three-phase pulse rectifier system with relatively low reverse voltage stress on the disconnectable power semiconductors, high power density and low system perturbation. Such three-phase three-point pulse rectifiers, also known as Wien rectifiers, are known to be characterized by extremely low harmonic content on the AC voltage side, in contrast to conventional six-pulse bridge circuits used for rectifying three-phase currents.

[0004] The Wien rectifier is a circuit that requires a large number of components, is very expensive, and requires very complex control. The lossy components also have a negative effect on the efficiency of the Wien rectifier.

[0005] Figure 1 shows a known network circuit of a three-phase DCM boost converter or boost converter according to the prior art. The network voltage present at the input of phases L1, L2, L3 is rectified and boosted to a value higher than the network voltage value. There are many variations of this circuit, all with a similar structure.

[0006] In the prior art, when the switching transistor T is turned on, the diode rectifier DGR is short-circuited. As a result, all three coils LL1, LL2, LL3 are charged in parallel depending on the string voltages u1, u2, u3 present at this time. When the switching transistor T is turned off, the coils LL1, LL2, LL3 are discharged. The current increase or current gradient in the coils LL1, LL2, LL3 is proportional to the voltage values ​​in the coils LL1, LL2, LL3 over the sinusoidal period when the switching transistor T is on. This means that in the known network circuit, the voltage drop in the coils LL1, LL2, LL3 and therefore the gradients of the coil currents and their final values ​​change during the period of the network sinusoid. Physically, this does not lead to a "clean" sinusoidal flow of the network current iNL, as shown in Figures 1 and 2. In particular, as can be seen in FIG. 2B, the phase current iNL1 has a dip in the range of about 30° of the zero crossing N towards the saddle L and a sinusoidal crest K towards the saddle L depending on the string voltages u1, u2, u3 applied at the input. Furthermore, the depth of the saddle K depends on the voltage difference between the string voltages u1, u2, u3 at the input and the intermediate circuit DC voltage UZK at the output. The higher the intermediate circuit DC voltage UZK at the output or the smaller the load at the output, the smaller the dip in the area of ​​the sinusoidal crest K. The same applies to the phase currents iNL2, iNL3.

[0007] Fig. 3 shows another known three-phase DCM boost converter with two switching transistors T+, T- according to the prior art. Due to the connection to the neutral point N, a first diode D+ and a second diode D- are required in this known circuit. This circuit is suitable for illustrating both conventional and hitherto common control systems, which correspond to the basic principle of pulse width modulation of the two switching transistors T+, T-.

[0008] Meanwhile, both switching transistors T+, T- are switched on in a staggered manner within a period by staggered control (push-pull). Thus, the first switching transistor T+ is conducting when the second switching transistor T- is not conducting and vice versa. Depending on the duty factor or duty cycle reaching 50%, both switching transistors are temporarily non-conducting. The duty cycle is the ratio between the switch-on period and the period of the pulse-width modulated signal. When the duty cycle exceeds 50%, both switching transistors are temporarily conducting. A system with such a duty cycle acts as two standard boost converters operating complementary in push-pull. In this known type of clocking, the connection between the midpoint MP and the neutral point N, as well as the first diode D+ in the positive branch and the second diode D- in the negative branch are absolutely necessary.

[0009] On the other hand, in synchronous / parallel control, both switching transistors T+, T- are turned on at the same time within a period. Thus, the first switching transistor T+ and the second switching transistor T- are simultaneously conductive or non-conductive. The switch-on period of both switching transistors T+, T- essentially depends on the duty cycle. The system with these known clockings functions as two complementary standard boost converters operating in common mode. In such known network circuits, only one switching transistor can be used for both boost converters (see Figure 1). The connection between the midpoint MP and the neutral point N, as well as one of the two diodes D+, D- can be omitted.

[0010] Depending on the duty cycle of the switching transistors, the level of the intermediate circuit DC voltage UZK at the output of the network circuit can be adjusted. These known clockings do not allow to extract an optimal sinusoidal current from the network (see Fig. 2A, 2B).

[0011] It is also known that many loads connected to the public power supply network draw pulsating network currents through simple bridge rectifiers, with large harmonic currents. These pulsating currents require the public power supply network to be oversized. Furthermore, short-term voltage dips and voltage peaks occur, which increase the possibility of problems for sensitive loads. For this reason, there are corresponding (PFC) standards (see, for example, DIN EN 61000-3-2 and DIN EN 61000-3-12), which require the use of power factor correction (PFC) above a certain power. Passive system components require larger installation space and the use of active circuit solutions, such as Vienna rectifiers, is required to supply currents with shapes that deviate from a sine wave.

[0012] In the known network circuits shown in Figures 1 and 3, as shown in Figures 2A and 2B, sinusoidal currents containing harmonics are drawn from the network, but the limit values ​​defined in the PFC standard are at best only met for low power or power classes.

[0013] Furthermore, an electric converter for converting between at least three-phase AC signals and DC signals is known from document WO 2021 / 219761 A1, which comprises at least three phase connections, a first DC connection and a second DC connection and a first converter stage and a second converter stage.

[0014] US Patent Document US7005759B2 discloses an integrated converter, which includes an AC / DC converter electrically connected to a three-phase power source and converts an alternating current into a first direct current to achieve the purpose of power factor correction.

[0015] European patent application EP 2 814 164 A2 discloses a power converter comprising a polyphase primary stage between a polyphase voltage source and a DC intermediate circuit, an input filter for the primary stage, a secondary stage between the DC intermediate circuit and a polyphase load with a bridge path for the neutral point of the load, and an input filter including an input filter star point connected to the midpoint of the DC intermediate circuit via a connection capacitance.

[0016] The object of the present invention is to provide sinusoidal phase currents at the input of the rectifier which meet the limits of the PFC standard for all power classes. Summary of the Invention

[0017] This document describes a method for supplying a rectifier with a sinusoidal phase current from a three-phase power supply network, comprising the steps of detecting and evaluating a string voltage, rectifying the string voltage, connecting a capacitor to a positive or negative output of the rectifier via either a first or a second switching transistor, controlling the control inputs of the first and second switching transistors by a control unit such that only the first switching transistor, only the second switching transistor, or both the first and second switching transistors are conductive, or neither is conductive, and charging the capacitor with a capacitor voltage in response to control of the control inputs such that a difference between the string voltage and the capacitor voltage dropped across the coil results in a sinusoidal flow of the average value of the coil current.

[0018] The control is either positive or negative, with positive control occurring during positive time intervals and negative control occurring during negative time intervals. A positive time interval is a time interval in which two of the three string voltages are positive. A negative time interval is a time interval in which two of the three string voltages are negative.

[0019] The control over time intervals is such that two of the three string voltages have the same polarity.

[0020] In a first aspect, the control is performed such that, in positive control, the first switching transistor is conductive / in a conductive state during a switch-on period from the first timing to the third timing, the second switching transistor is conductive / in a conductive state during a switch-on period from the second timing to the fourth timing, and the first and second switching transistors are conductive / in a conductive state during a short-circuit period from the second timing to the third timing.

[0021] According to the first aspect, the first switching transistor is first turned on when two of the three string voltages are positive, which allows the capacitor to be appropriately charged so as to draw a sinusoidal phase current from the power supply network that meets the PFC standard limits of the corresponding power class.

[0022] In a second aspect, the control is performed such that, in negative control, the second switching transistor is conductive / in a conductive state during a switch-on period from the first timing to the third timing, the first switching transistor is conductive / in a conductive state during a switch-on period from the second timing to the fourth timing, and the first and second switching transistors are conductive / in a conductive state during a short-circuit period from the second timing to the third timing.

[0023] According to the second aspect, the second switching transistor is first turned on when two of the three string voltages are negative, which allows the capacitor to be appropriately charged so as to draw a sinusoidal phase current from the power supply network that meets the PFC standard limits of the corresponding power class.

[0024] In a third embodiment, the control is performed such that the switch-on periods of the first and second switching transistors are the same.

[0025] According to the third aspect, the switch-on periods of the two switching transistors are equal, which promotes sinusoidal flow of the phase currents.

[0026] In a fourth aspect, the controlling is performed such that the switch-on periods of the first and second switching transistors are coordinated.

[0027] According to a fourth aspect, different switch-on durations can be realized during the switching period to allow a more flexible adaptation of the control to the detected value of the string voltage, thereby allowing appropriate charging of the capacitors to draw sinusoidal phase currents from the power supply network.

[0028] In the fifth aspect, the short-circuit period during control is a period during which the first switching transistor and the second switching transistor are conductive.

[0029] According to a fifth aspect, said control makes it possible to influence the length of the short circuit period so as to charge the capacitor in such a way as to draw a sinusoidal phase current from the power supply network.

[0030] In a sixth aspect, said control of the control inputs of the first and second switching transistors are clocked at a clock frequency higher than the network frequency.

[0031] According to the sixth aspect, it is ensured that harmonic currents caused by the clock frequency do not affect the sinusoidal flow of the phase current. Furthermore, according to the sixth aspect, the higher the clock frequency is selected, the smaller the size of components such as coils and capacitors, and therefore the component costs, can be reduced.

[0032] In a seventh embodiment, charging includes any of pre-charging, charging, recharging, and discharging.

[0033] According to a seventh aspect, the capacitors can be controlled to draw sinusoidal phase currents from the power supply network by pre-charging, charging, recharging or discharging depending on the detected string voltage.

[0034] In an eighth aspect, the method further includes providing a reference potential to a capacitor in a midpoint network on the coupling circuit.

[0035] According to an eighth aspect, the artificial neutral conductor of the coupling circuit provides a voltage reference for the capacitor voltage of the capacitor in the midpoint network.

[0036] In a ninth aspect, the method further comprises sensing at least one output variable of the intermediate circuit DC voltage, the intermediate circuit current, the positive and negative rectifier voltages, the capacitor voltage relative to a reference potential, and the capacitor current.

[0037] According to the ninth aspect, further variables can be detected to improve the control of the two switching transistors, which allows the capacitors to be appropriately charged to draw sinusoidal phase currents from the power supply network.

[0038] The use of the method is also described herein in at least one of a charging station, a power supply unit, an electric drive for a machine, and an energy conversion system on a power supply network, and thus the method can be used in various applications for providing sinusoidal phase currents that meet the PFC standard limits of the corresponding power class. [Brief description of the drawings]

[0039] The invention will now be described in more detail with reference to the following drawings.

[0040] [Figure 1] FIG. 1 shows a prior art boost converter.

[0041] [Figure 2A]FIG. 2A is a diagram showing current flow in the boost converter of FIG. [Figure 2B] FIG. 2B is a diagram showing the current flow of the boost converter of FIG.

[0042] [Diagram 3] FIG. 3 shows yet another prior art boost converter.

[0043] [Figure 4] FIG. 4 is a diagram showing a network circuit according to the first embodiment.

[0044] [Diagram 5] FIG. 5 is a diagram showing the flow of control signals in the positive control.

[0045] [Figure 6] FIG. 6 is a diagram showing different characteristic curves in the positive control.

[0046] [Figure 7] FIG. 7 is a diagram showing the flow of control signals in negative control.

[0047] [Figure 8] FIG. 8 is a diagram showing different characteristic curves in the negative control.

[0048] [Figure 9] FIG. 9 is a diagram showing the flow of network voltage in a three-phase power supply network in which positive and negative control is performed alternately and periodically.

[0049] [Figure 10A] FIG. 10A is a diagram showing a current flow based on positive / negative control in the network circuit of FIG. [Figure 10B] FIG. 10B is a diagram showing a current flow based on positive / negative control in the network circuit according to FIG.

[0050] [Figure 11]FIG. 11 shows a flow chart of the method according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0051] With reference to Fig. 4, the structure of a network circuit NS according to a first embodiment for supplying an intermediate circuit DC voltage UZK and a load-dependent intermediate circuit current IZK at an output from a three-phase power supply network VN is described. The network circuit NS comprises at least one switching transistor T+, T- and a midpoint network MPN and is configured as a boost converter. In particular, the network circuit NS is configured as a three-phase PFC boost converter. The absolute value of the output voltage at the output of the network circuit NS is always greater than the absolute value of the input voltage of the network circuit NS. The absolute value of the intermediate circuit DC voltage UZK at the output is therefore greater than the rectified value of the conductor voltages u12, u23, u31 at the input of the network circuit NS.

[0052] Compared to the circuit shown in Figure 3, the network circuit NS is expanded to a half bridge with a midpoint network MPN including a capacitor CS. In addition, the network circuit NS is connected to a neutral or reference potential SP.

[0053] The output capacitor CA of the network circuit NS is realized by one capacitor. In another example, the output capacitor CA can be realized as a series connection of two or more capacitors.

[0054] Preferably, the network circuit includes a first switching transistor T+ and a second switching transistor T−, but the network circuit NS is not limited to the first and second switching transistors T+, T−.

[0055] The network circuit NS also comprises other components connected to each other via phases or lines L1, L2, L3, the network circuit NS comprises an EMI filter or a filter for electromagnetic interference EMI, a network detector NE, a control unit SE, a rectifier GR, a coupling circuit KS to a reference potential SP, a first diode D+ and a second diode D- on the output lines of the network circuit NS and an output capacitor CA between the output lines.

[0056] At the input, the network circuit NS is connected to the power supply network VN via phases L1, L2, L3. The phases L1, L2, L3 include network variables. The network variables include at least one of the following: phase position, network voltages, including string voltages u1, u2, u3 and conductor voltages u12, u23, u31, phase currents iNL1, iNL2, iNL3. The input of the network circuit NS connects the three-phase power supply network VN to an EMI filter EMI via phases L1, L2, L3. The EMI filter EMI filters electromagnetic interference in a known manner. For this reason and for the sake of brevity, the EMI filter EMI will not be described in detail here.

[0057] The network detection unit NE detects, evaluates and passes on the network variables of the phases L1, L2, L3 to the control unit SE. The network detection unit NE may be an independent unit or may be integrated in the control unit SE. The control unit SE comprises an output detection unit AE for detecting voltage and current variables at various locations, in particular at the output of the network circuit NS. The output detection unit AE thus detects output variables including at least one of the intermediate circuit DC voltage UZK and the intermediate circuit current IZK, the positive and negative rectifier voltages uGR+, uGR-, the capacitor voltage uCS relative to the reference potential SP and the capacitor current iCS at the capacitor CS. The network detection unit NE and the output detection unit AE can include various options for detecting the network variables and the output variables. For example, the network variables can be detected by the network detection unit NE and the output detection unit AE using one or more sensors. However, the network variables can also be detected by the network detection unit NE and the output detection unit AE using a predefined detection method based on an ACTUAL / TARGET comparison.

[0058] The control unit SE uses information about the voltage and current variables or network variables obtained from the network detector NE and the output detector AE to control the first and second switching transistors T+, T- to provide a capacitor voltage uCS on the capacitor CS. The capacitor voltage uCS represents the voltage difference resulting from the difference between the string voltages u1, u2, u3 and the coil voltages uLL1, uLL2, uLL3 dropped across the coils LL1, LL2, LL3. The control results in a sine wave of the average value of the coil currents iLL1, iLL2, iLL3, which will be explained in more detail below.

[0059] The control unit SE comprises a microprocessor or microcontroller, or functionally similar components, for evaluating the network variables detected by the network detector NE and the output detector AE. The control unit SE is a known control unit from the prior art. For this reason, and for the sake of brevity, the control unit SE will not be described in detail here.

[0060] The rectifier GR is composed of rectifier diodes D1, D2, D3, D4, D5, D6 and inductors or coils LL1, LL2, LL3 as energy storage bodies. However, the rectifier GR is not limited to this embodiment example. The rectifier GR can be composed of passive components, active components and / or combinations thereof. The rectifier GR thus has the functions of both a rectifier and an inverter and allows feedback to the power supply network VN. The functions of the rectifier GR correspond to known functions and will not be described in more detail for the sake of brevity.

[0061] The coupling circuit KS is disposed between the midpoint network MPN and the rectifier GR. The coupling circuit KS is a capacitor star circuit including capacitors CYL1, CYL2, CYL3 and a reference potential SP. The reference potential SP is connected to the phases L1, L2, L3 via the capacitors CYL1, CYL2, CYL3. The coupling circuit KS is configured to create an artificial neutral conductor (neutral potential) to provide a voltage reference to the midpoint network MPN and thus to the capacitor CS. The midpoint network MPN (including the capacitor CS) is connected to the phases L1, L2, L3 via the reference potential SP of the coupling circuit KS.

[0062] The first switching transistor T+ and the second switching transistor T- each comprise a control input AN and a body diode (not shown) or a freewheeling diode (not shown) connected in parallel with the switching transistors T+, T-. The control input AN of the first switching transistor T+ is connected to the control unit SE. The control input AN of the second switching transistor T- is connected to the control unit SE. The control unit SE controls the first switching transistor T+ and the second switching transistor T- and will be described in more detail below.

[0063] The coupling circuit KS prevents high frequency currents resulting from the control of the first and second switching transistors T+, T- from appearing in the phase currents iNL1, iNL2, iNL3.

[0064] The midpoint network MPN of the network circuit NS performs the basic function of an adjustable voltage source and includes a capacitor CS. The capacitor CS of the midpoint network MPN is connected between a midpoint MP of the coupled circuit with the phases L1, L2, L3 at its input and a reference potential SP. The midpoint MP is provided between a first switching transistor T+ and a second switching transistor T- connected in series. The capacitor CS is electrically connected to the rectifier GR via the first switching transistor T+ with the positive output pG of the rectifier GR and via the second switching transistor T- with the negative output nG of the rectifier GR.

[0065] The first diode D+ and the second diode D- are arranged at the output of the network circuit NS in such a way that the intermediate circuit DC voltage UZK at the output is independent of the clocking of the first and second switching transistors T+, T-. To maintain the clocking independence, only the first diode D+, only the second diode D- or both diodes D+, D- can be provided.

[0066] The capacitor CS of the midpoint network MPN is charged by a special type of control of the control input AN of at least one of the first switching transistor T+ and the second switching transistor T- by the control unit SE. The charging of the capacitor CS corresponds to at least one of precharging, charging, recharging and discharging. The type of charging of the capacitor CS depends on the network variables detected by the network detection unit NE and the output detection unit AE.

[0067] The capacitor voltage uCS on the capacitor CS modulates the coil voltages uLL1, uLL2, uLL3 in such a way that sinusoidal phase currents iNL1, iNL2, iNL3 are drawn from the phases L1, L2, L3 of the power supply network VN. The level of the capacitor voltage uCS depends on the duty cycle TV, as explained below. As a result of the modulation, the phase currents iNL1, iNL2, iNL3 are essentially sinusoidal currents or have an essentially sinusoidal flow. The modulation corresponds to pulse width modulation, pulse frequency modulation or other known modulation methods. A sinusoidal current is drawn from the power supply network VN at the input of the network circuit NS.

[0068] By charging the capacitor CS according to a special type of control, the capacitor CS serves as an adjustable voltage source for generating a voltage difference between the coils LL1, LL2, LL3. The voltage difference between the coils LL1, LL2, LL3 can be influenced by the charging of the capacitor CS, so that in the corresponding time periods, larger coil voltages uLL1, uLL2, uLL3 are applied to the coils LL1, LL2, LL3 than are physically provided by the power supply network VN, as shown in Figures 5 to 8. As a result, essentially sinusoidal currents are drawn from the power supply network VN in all phases L1, L2, L3, complying with the limits of the PFC standard for the corresponding power class.

[0069] For this purpose, the first and second switching transistors T+, T- respectively receive control signals ST+, ST- from the control unit SE, by which the first and second switching transistors T+, T- are clocked. The clocking determines various time intervals, such as the switch-on period TE of the first switching transistor T+, the switch-on period TE of the second switching transistor T- and the short-circuit period TK, during which both switching transistors T+, T- are simultaneously on or conducting. Depending on the sequence of the time intervals, a distinction is made between positive and negative control. This special timing will be explained in more detail below with reference to figures 5 to 8. The control unit SE adjusts the modulation by the length of the time intervals. At the same time, the length of the time intervals and the short-circuit period TK are used to control the level of the intermediate circuit DC voltage UZK. During the time intervals, the capacitor CS of the midpoint network MPN is charged. The charging takes place in relation to an artificial neutral conductor provided by the coupling circuit KS.

[0070] FIG. 5 shows the flow of a first control signal ST+ for the first switching transistor T+ and the flow of a second control signal ST- for the second switching transistor T- over time based on positive control of the first switching transistor T+ and the second switching transistor T-.

[0071] In the case of positive control, the control inputs AN of the first and second switching transistors T+, T- are controlled by the control unit SE in such a way that the first switching transistor T+ is conductive / in a switch-on period TE between the first timing t1 and the third timing t3, and then the second switching transistor T- is conductive / in a switch-on period TE between the fourth timing t4 of the second timing t2. In the short-circuit period TK between the second timing t2 and the third timing t3, the first and second switching transistors T+, T- are simultaneously conductive. While the first control signal ST+ is zero, the first switching transistor T+ is non-conductive. The first switching transistor T+ is non-conductive during the switch-off period TA from the third timing t3 of the current control period TS to the first timing t1 of the next control period, during which the first switching transistor T+ is not controlled by the control unit SE. While the second control signal ST- is zero, the second switching transistor T- is non-conductive. The second switching transistor T- is non-conductive in a switch-off period TA from the fourth timing t4 of the current control cycle TS to the second timing t2 of the next control cycle, during which the second switching transistor T- is not controlled by the control unit SE.

[0072] The intermediate circuit DC voltage UZK can be arbitrarily controlled via the duty cycle TV from the switch-on period TE to the switch-off period TA or via the control period TS of the first and second switching transistors T+, T- and in combination with the short-circuit period TK. The switch-on period TE of the first switching transistor T+ and the switch-on period TE of the second switching transistor T- are selected to be of equal length in FIG. 5. The sum of the switch-on period TE and the switch-off period TA is the control period TS. However, the switch-on period TE of the first switching transistor T+ and the switch-on period TE of the second switching transistor T- can also be selected to be of different lengths. The switch-on period TE can also be adjusted via the control unit SE to be of different duration in each control period TS. The equally long switch-on periods TE of the first and second switching transistors T+, T- in FIG. 5 are therefore merely an example for illustrating positive control and are not intended to limit the positive control (and negative control) to this example.

[0073] The reciprocal of the control period TS is the clock frequency fs, at which the first switching transistor T+ and the second switching transistor T- are clocked under the control of the control unit SE. It should be noted that in order to minimize the costs of filtering harmonics generated by the clocking, the clocking needs to be performed at a clock frequency fs that is sufficiently high compared to the network frequency fN.

[0074] FIG. 6 shows the main characteristic curves of the positive control as a function of the timing of the first and second switching transistors T+, T- of the network circuit NS of FIG. 4 over time. An exemplary assumption is applied: the string voltages u2 and u3 in phases L2 and L3 are equal in absolute value and greater than 0 volts, while the string voltage u1 in phase L1 is less than 0 volts. Thus, the coils LL2 and LL3 are connected to the first switching transistor T+ via the positive output pG of the rectifier GR; whereas, the coil LL1 is connected to the second switching transistor T- via the negative output nG of the rectifier GR. These assumptions are exemplary and apply to the characteristic curves described below for the network voltages of the two phases greater than zero. The selected assumptions are not intended to limit the scope of the invention and can be made in other ways.

[0075] For better understanding, the control signals ST+, ST- for determining the timing of each time interval (t1 to t4') are also shown in Fig. 6. The flow of the first control signal ST+ and the second control signal ST- corresponds to that of Fig. 5 and will not be repeated here.

[0076] Also shown in Figure 6 over time are the flow of the output current IZK, the flow of the output capacitor current iCA in the output capacitor CA, the flow of the diode current iD+ through the first diode D+, the flow of the coil current iLL1 through the coil LL1, the flow of the coil current iLL23 corresponding to the sum of the coil currents iLL2 and iLL3, the flow of the capacitor voltage uCS, and the flow of the capacitor current iCS. The flow of the output current IZK remains constant and greater than zero throughout the entire control period TS.

[0077] At a first time t1, when the first switching transistor T+ is turned on, a positive capacitor current iCS is established in the capacitor CS by the controlled first switching transistor T+ and the upstream coils LL1, LL2, and LL3. The capacitor CS is discharged by the positively increasing capacitor current iCS to a capacitor voltage uCS = 0 V. The coil current iLL23, which is the sum of the coil currents iLL2 and iLL3 of the coils LL2 and LL3, increases positively along with the capacitor current iCS until a second time t2.

[0078] At the second time t2, the second switching transistor T- becomes conductive, and the first switching transistor T+ also becomes conductive. The second switching transistor T- is controlled by the control unit SE to become conductive when a set time has elapsed or when the capacitor voltage uCS is equal to zero volts. As a result, the rectifier GR is short-circuited during the short-circuit period TK. The capacitor CS is charged from a discharged state to a positive state from this second time t2, and the absolute value of the capacitor current iCS decreases from the second time t2. Meanwhile, the coil current iLL23 in the coils LL2 and LL3 continues to accumulate positively or to increase positively during the short-circuit period TK. From the second time t2, accumulation of a negative current begins in the coil LL1, and the coil current iLL1 increases in the negative direction. From the second time t2 to the third time t3, most of the electrical energy is absorbed by the components of the network circuit LV.

[0079] At a third time t3, the first switching transistor T+, which is conductive at the time t1, is switched off again by the control unit SE after a switch-on period TE. The second switching transistor T- remains conductive until a fourth time t4. From the third time t3, the coils LL2 and LL3, in which a positive coil current iLL23 has accumulated during the switch-on period TE of the first switching transistor T+, control this coil current iLL23 via the rectifier diodes D3, D5 of the rectifier GR on the input side and the first and second diodes D+, D- on the output side towards the load. This results in a diode current iD+ and an output capacitor current iCA, the absolute value of which decreases steadily from the third time t3. The coil current iLL23 in the coils LL2 and LL3 also decreases in absolute value again. From the third time t3, the capacitor current iCS decreases even more sharply and reaches zero ampere at the time t3'. Because the second switching transistor T− is still conductive, the coil current iLL23 flows through the first and second diodes D+, D− and is then split into the current through the coil LL1 and the current through the capacitor CS until the capacitor current iCS reaches zero amperes.

[0080] At time t3', the capacitor current iCS is equal to zero amperes and the capacitor voltage uCS reaches a maximum positive value. From time t3', a negative capacitor current iCS is established through the capacitor CS and increases negative over time until time t4. The capacitor CS is again continuously discharged. From time t3', the negative capacitor current iCS in the capacitor CS is added to the coil current iLL23 and continues to flow through the first diode D+, the load and the second diode D-. The sum of the two currents corresponds to the coil current iLL1 in the coil LL1.

[0081] At time t3L, the coil current iLL23 of the coils LL2 and LL3 is completely reduced. The coil current iLL23 becomes zero amperes at time t3L. Thus, the first and second diodes D+, D- are cut off, the diode current iD+ becomes equal to zero amperes, and the output capacitor current iCA takes over from the intermediate circuit current IZK and becomes negative. The entire negative capacitor current iCS of the capacitor CS continues to flow through the coil LL1 from time t3L, and the coil current iLL1 continues to increase negatively.

[0082] At the fourth time t4, the second switching transistor T-, which was previously in a conducting state, is controlled by the switching unit SE, and the second switching transistor T- is turned off. From the fourth time t4, the coil LL1 again continues to control the coil current iLL1 through the first and second diodes D+, D- and the load connected to the output of the network circuit NS. As a result, the diode current iD+ and the output capacitor current iCA immediately increase. From the fourth time t4, the capacitor current iCS flows through the only remaining current path in the form of the body diode included in the first switching transistor T+ or the freewheeling diode connected in parallel to the first switching transistor T+. From the fourth time t4 to the time t4', the capacitor current iCS decreases in absolute value again and approaches zero amperes. As a result, the capacitor CS is recharged to the original negative value that prevailed at the first time t1. At the same time, the positive coil current iLL23 again begins to accumulate in the two coils LL2 and LL3. The diode current iD+ and the output capacitor current iCA decrease steadily until timing t4'.

[0083] At time t4', the absolute value of the coil current iLL1 of the coil LL1 corresponds to the absolute value of the coil current iLL23 and thus corresponds to the sum of the absolute values ​​of the coil current iLL2 and the coil current iLL3. This results in a zero ampere capacitor current iCS. From time t4', no current flows from the capacitor CS through the body diode or the freewheeling diode of the first switching transistor T+. At time t4', the capacitor CS is fully charged to the negative initial value of the first time t1 and is available again for use in the next control period TS. The coils LL1, LL2, LL3 continue to control the current through the first and second diodes D+, D- and the load connected to the output of the network circuit NS, so that the remaining coil currents iLL1, iLL23 of the three coils LL1, LL2, LL3 decrease linearly over time. As the coil currents iLL1, iLL23 decrease from time t4', the diode current iD+ and the output capacitor current iCA also decrease in absolute value. The coil currents iLL1, iLL23 are equal to 0 A in the discontinuous conduction mode before the end of the control period TS or in the boundary conduction mode at the end of the control period TS.

[0084] In boundary conduction mode, one of the coil currents iLL1, iLL2, iLL3 goes exactly to zero at the end of the control period TS. In discontinuous conduction mode, a pause is inserted (the current is "interrupted" or discontinuous) between the current reduction and the start of the new control period TS. Discontinuous conduction mode and boundary conduction mode are the norm when using boost converters.

[0085] 7 shows the flow of the first control signal ST+ for the first switching transistor T+ and the flow of the second control signal ST- for the second switching transistor T- over time, based on the negative control of the first switching transistor T+ and the second switching transistor T-. In the case of negative control, the switch-on period TE, the switch-off period TA, the short-circuit period TK, and the switching period TS correspond to those of the positive control, but with the difference that the start and end timings are different. In other words, the same applies to the switch-on period TE, the switch-off period TA, the short-circuit period TK, and the switching period TS as in the case of positive control.

[0086] By negative control, the control inputs AN of the first and second switching transistors T+, T- are controlled by the control unit SE in such a way that the second switching transistor T- is conductive / in a conductive state during a switch-on period TE between the first time t1 and the third time t3, and then the first switching transistor T+ is conductive / in a conductive state during a switch-on period TE between the second time t2 and the fourth time t4. Between the second time t2 and the third time t3, during the short-circuit period TK, the first and second switching transistors T+, T- are simultaneously conductive. The first switching transistor T+ is non-conductive during a switch-off period TA from the fourth time t4 of the current control period TS to the second time t2 of the next control period, during which the first switching transistor T+ is not controlled by the control unit SE. The second switching transistor T- is non-conductive in a switch-off period TA from the third timing t3 of the current control cycle TS to the first timing t1 of the next control cycle, during which the second switching transistor T- is not controlled by the control unit SE.

[0087] In negative control, it is also important to ensure that the clock frequency fs is sufficiently high compared to the network frequency fN.

[0088] FIG. 8 shows the main characteristic curves of the positive control as a function of the timing of the first and second switching transistors T+, T- of the network circuit NS of FIG. 4 over time. The exemplary assumptions are applied: the string voltage u1 of the phase L1 is greater than zero volts, and the string voltages u2 and u3 of the phases L2 and L3 are equal in absolute value and less than zero volts. Thus, the coil LL1 is connected to the first switching transistor T+ via the positive output pG of the rectifier GR; whereas, the coils LL2 and LL3 are connected to the second switching transistor T- via the negative output nG of the rectifier GR. These assumptions are exemplary and apply to the characteristic curves described below, where the network voltages of the two phases are less than zero. The selected assumptions are not intended to limit the scope of the invention and can be made in other ways.

[0089] For better understanding, the control signals ST+, ST- for determining the timing of each time interval (t1 to t4') are also shown in Fig. 8. The flow of the first control signal ST+ and the second control signal ST- corresponds to that in Fig. 7 and will not be repeated here.

[0090] Also shown over time in Figure 8 are the flow of the output current IZK, the flow of the output capacitor current iCA, the flow of the diode current iD+, the flow of the inductor current iLL1, the flow of the inductor current iLL23 corresponding to the sum of the inductor currents iLL2 and iLL3, the flow of the capacitor voltage uCS, and the flow of the capacitor current iCS. The flow of the output current IZK remains constant, greater than zero, throughout the entire control period TS.

[0091] At the first timing t1, when the second switching transistor T- is turned on, a negative capacitor current iCS is generated in the capacitor CS by the controlled second switching transistor T- and the upstream coils LL1, LL2, and LL3. The capacitor CS is discharged to the capacitor voltage uCS = 0 V by the negatively increasing capacitor current iCS. The coil current iLL23, which is the sum of the coil currents iLL2 and iLL3 of the coils LL2 and LL3, increases negatively along with the capacitor current iCS until the second timing t2.

[0092] At the second time t2, the first switching transistor T+ becomes conductive, and the second switching transistor T- also becomes conductive. The first switching transistor T+ is controlled by the control unit SE to become conductive when a set time has elapsed or when the capacitor voltage uCS becomes zero volts. As a result, the rectifier GR is short-circuited in the short-circuit period TK. From this second time t2, the capacitor CS is charged negatively from a discharged state, and the absolute value of the capacitor current iCS decreases from the second time t2. Meanwhile, the coil current iLL23 in the coils LL2 and LL3 continues to accumulate negatively. In the coil LL1, a positive current accumulation starts from the second time t2, and the absolute value of the coil current iLL1 increases in the positive direction. From the second time t2 to the third time t3, most of the electrical energy is absorbed by the components of the network circuit LV.

[0093] At a third time t3, the second switching transistor T-, which was conductive at the first time t1, is switched off again by the control unit SE after a switch-on period TE. The first switching transistor T+ remains conductive until a fourth time t4. From the third time t3, the coils LL2 and LL3, in which a negative coil current iLL23 was accumulated during the switch-on period TE of the second switching transistor T-, control this coil current iLL23 via the rectifier diodes D4, D6 of the rectifier GR on the input side and the first and second diodes D+, D- on the output side towards the load.

[0094] The diode current iD+ and the output capacitor current iCA are set and their absolute values ​​decrease steadily from the third time t3. The coil current iLL23 in the coils LL2 and LL3 also decreases again. From the third time t3, the absolute value of the capacitor current iCS decreases more rapidly and becomes zero amperes at time t3'. Because the first switching transistor T+ is still conducting, the current through the capacitor CS is added to the coil current iLL1 through the coil LL1 until the capacitor current iCS reaches zero amperes.

[0095] At time t3', the capacitor current iCS is equal to zero amperes and the capacitor voltage uCS reaches a maximum negative value. From time t3', a positive capacitor current iCS is established through capacitor CS and increases positive over time until time t4. Capacitor CS is discharged again. From time t3', the positive capacitor current iCS in capacitor CS is subtracted from the coil current iLL1 in coil LL1 and continues to flow through D+, D- and the load. The difference between the two currents corresponds to the coil current iLL23 in coils LL2 and LL3.

[0096] At time t3L, the coil current iLL23 of the coils LL2 and LL3 decreases completely. The coil current iLL23 becomes zero amperes at time t3L. Therefore, the first and second diodes D+, D- are cut off, the diode current iD+ becomes equal to zero amperes, and the output capacitor current iCA takes over from the intermediate circuit current IZK and becomes negative. The entire positive capacitor current iCS of the capacitor CS continues to flow through the coil LL1 from time t3L, and the coil current iLL1 continues to increase positive.

[0097] At the fourth time t4, the first switching transistor T+, which was previously in a conducting state, is controlled by the switching unit SE, so that the first switching transistor T+ is in a non-conducting state. From the fourth time t4, the coil LL1 again controls the coil current iLL1 through the first and second diodes D+, D- and the load connected to the output of the network circuit NS. As a result, the diode current iD+ and the output capacitor current iCA immediately increase. From the fourth time t4, the capacitor current iCS flows through the only remaining current path in the form of the body diode included in the second switching transistor T- or the freewheeling diode connected in parallel to the second switching transistor T-. From the fourth time t4 to the time t4', the capacitor current iCS decreases in absolute value again and approaches zero amperes. As a result, the capacitor CS is recharged to its original positive value, as in the first time t1. At the same time, the negative coil current iLL23 again begins to accumulate in the two coils LL2 and LL3. The diode current iD+ and the output capacitor current iCA decrease steadily until timing t4'.

[0098] At time t4', the absolute value of the coil current iLL1 of the coil LL1 corresponds to the absolute value of the coil current iLL23 and thus to the sum of the absolute values ​​of the coil current iLL2 and the coil current iLL3. This results in a zero ampere capacitor current iCS. From time t4', no current flows from the capacitor CS through the body diode or the freewheeling diode of the second switching transistor T-. At time t4', the capacitor CS is fully charged to the positive initial value of the first time t1 and is available again for the next control period TS. The coils LL1, LL2, LL3 continue to control the current through the first and second diodes D+, D- and the load connected to the output of the network circuit NS, so that the remaining coil currents iLL1, iLL23 of the three coils LL1, LL2, LL3 decrease linearly over time. As the coil currents iLL1, iLL23 decrease from time t4', the diode current iD+ and the output capacitor current iCA also decrease in absolute value. The coil currents iLL1, iLL23 are equal to 0 A in the discontinuous conduction mode before the end of the control period TS or in the boundary conduction mode at the end of the control period TS.

[0099] In order for the network circuit NS to function as expected and to be able to draw sinusoidal phase currents iNL1, iNL2, iNL3 from the power supply network VN while complying with the limit values ​​of the PFC standard for the corresponding power class, not only is only positive or only negative control performed, but both alternate cyclically during operation. The time at which positive or negative control is used depends on the network variables detected and evaluated on the phases L1, L2, L3.

[0100] Figure 9 shows the power network VN as a three-phase system with string voltages u1, u2, u3 and time intervals A and B. Looking at the flow of string voltages u1, u2, u3 in the three-phase system, there is a positive time interval A where two string voltages are greater than zero and one phase voltage is less than zero, and a negative time interval B where one string voltage is greater than zero and two string voltages are less than zero.

[0101] If two of the string voltages u1, u2, u3 are greater than zero, then positive control (see Figures 5, 6) is used in this positive time interval A. If two of the string voltages u1, u2, u3 are less than zero, then negative control (see Figures 7, 8) is used in this negative time interval B. Over time, an approximately triangular voltage curve SK (dashed line) is obtained, made up of sinusoidal sections, which is bounded by the time intervals A and B and moves around the zero line.

[0102] During time intervals A and B, i.e., when the positive or negative control is active, the string voltages u1, u2, and u3 are always in the same state, i.e., greater than or less than zero. Therefore, for time intervals A and B, we can define time interval A = time interval B based on a symmetrical three-phase system.

[0103] At each zero point of the approximate triangular voltage curve SK, there is a change from positive control to negative control or from negative control to positive control. The control changes from negative control to positive control when the approximate triangular voltage curve SK moves from a negative time interval B (i.e., value less than zero) to a positive time interval A (i.e., value greater than zero). The transition from positive / negative control to negative / positive control may occur abruptly, for example, as shown in Figure 9. However, the transition can also be smooth (not shown).

[0104] The duration of the time intervals A, B depends on the network frequency fN. In a European power supply network with a network frequency fN = 50 Hz, a zero point occurs every 3.33 ms in a three-phase system. This means that the system switches between positive and negative control every 3.33 ms. However, the network circuit NS is not limited to the European power supply network. On the contrary, the network circuit NS can be operated at all international network voltages and frequencies.

[0105] By charging the capacitor voltage uCS, depending on the control of the first and second switching transistors T+, T- by the control unit SE, it is possible to affect the voltage difference between the string voltage u1, u2, u3 and the capacitor voltage uCS of the coils LL1, LL2, LL3, so that there is a larger coil voltage uLL1, uLL2, uLL3 at the coils LL1, LL2, LL3 than is physically available from the power supply network VN. In other words, the phase currents iNL1, iNL2, iNL3 are modulated by the coil voltages uLL1, uLL2, uLL3, which are influenced by the adjustable voltage applied to the capacitor CS. As a result, sinusoidal network currents iNL1, iNL2, iNL3 are supplied to the inputs of the rectifiers in order to meet the limit values ​​of the PFC standard of the corresponding power class, as shown in Figures 10A and 10B.

[0106] As can be seen from Figures 10A and 10B, the dips both in the region of the zero crossings N1 and in the region of the sinusoidal crests K1 can be corrected with the help of the control and the capacitor CS, compared to the zero crossings N and the sinusoidal crests K in the flows of Figures 2A and 2B. As a result, sinusoidal phase currents iNL1, iNL2, iNL3 with minimized harmonic content are obtained, which meet the limits of the PFC standards for the corresponding power classes.

[0107] 11 shows the steps of the method according to the invention. In step S1, the string voltages u1, u2, u3 of at least phases L1, L2, L3 are detected and evaluated by the network detection unit NE and the output detection unit AE. In step S2, the string voltages u1, u2, u3 are rectified by the rectifier GR. In step S3, the capacitor CS is electrically connected to the positive output pG or the negative output nG of the rectifier GR via the first switching transistor T+ and the second switching transistor T-. In step S4, the control inputs AN of the first switching transistor T+ and the second switching transistor T- are controlled by the control unit SE according to the time intervals A, B, such that only the first switching transistor T+, only the second switching transistor T-, or both are conductive, or neither the first nor the second switching transistor T+, T- is conductive. In step S5, the capacitor CS of the midpoint network MPN is charged according to the control of the control input AN (step S4) so ​​that the voltage difference between the string voltage u1, u2, u3 and the capacitor voltage uCS dropped across the coils LL1, LL2, LL3 results in a sinusoidal flow of the average value of the coil currents iLL1, iLL2, iLL3. In this way, with the help of the capacitor voltage uCS, steep coil currents iLL1, iLL2, iLL3 are generated in the coils LL1, LL2, LL3.

[0108] The method can be used, for example, in charging stations, in circuits of electric drives for machines, in power supply units and in energy conversion systems on the power supply network VN. [Explanation of symbols]

[0109] A,B Time Interval AE output detector AN control input section KS coupling circuit CA Output Capacitor CS Capacitor CYL1, CYL2, CYL3 capacitors D1-D6 Rectifier diode D+ First Diode D- Second Diode EMI Electromagnetic Filters (Filters for Electromagnetic Interference) fN Network frequency GR rectifier iNL1,iNL2,iNL3 phase current IZK intermediate circuit DC current KS coupling circuit L1, L2, L3 phase LL1, LL2, LL3 coils MPN Midpoint Network NS Network Circuit NE Network Detector SE control unit SK Triangular Voltage Curve SP reference potential T+ First switching transistor T- Second switching transistor TE Switch-On Period TK Short circuit period u1,u2,u3 string voltage u12,u23,u31 Conductor voltage UZK Intermediate circuit DC voltage VN Power supply network

Claims

1. 1. A method for supplying sinusoidal phase currents to a rectifier, comprising: Detecting and evaluating the string voltage; rectifying the string voltage; connecting a capacitor to either the positive output or the negative output of the rectifier via either the first switching transistor or the second switching transistor; controlling the control inputs of the first switching transistor and the second switching transistor by a control unit so that only the first switching transistor, only the second switching transistor, or both the first and second switching transistors are conductive, or neither is conductive; a step of applying a difference between the string voltage and the capacitor voltage to a coil arranged on a main power supply side in a subsequent stage of an input phase of the rectifier, and charging the capacitor with a capacitor voltage in accordance with the control of the control input unit so that an average value of a coil current flows in a sinusoidal waveform; The control is either a positive control or a negative control, the positive control is performed during a positive time interval when two of the three string voltages are positive; The method of claim 1, wherein the negative control is performed during a negative time interval in which two of the three string voltages are negative.

2. 10. The method of claim 1, The control is performed such that, in the positive control, the first switching transistor is conductive / in a conductive state during a switch-on period from a first timing to a third timing, the second switching transistor is conductive / in a conductive state during a switch-on period from a second timing to a fourth timing, and the first and second switching transistors are conductive / in a conductive state during a short-circuit period from the second timing to the third timing.

3. 3. The method of claim 2, The control is performed such that, in the negative control, the second switching transistor is conductive / in a conductive state during a switch-on period from a first timing to a third timing, the first switching transistor is conductive / in a conductive state during a switch-on period from a second timing to a fourth timing, and the first and second switching transistors are conductive / in a conductive state during a short-circuit period from the second timing to the third timing.

4. In the method according to claim 2 or claim 3, The method is characterized in that the controlling is performed so that the switch-on periods of the first and second switching transistors are the same.

5. In the method according to claim 2 or claim 3, The method, wherein the controlling is performed such that the switch-on periods of the first and second switching transistors are adjusted.

6. 3. The method of claim 2, The method, wherein the short-circuit period during the control is a period during which the first switching transistor and the second switching transistor are conductive.

7. 10. The method of claim 1, The method of claim 1, wherein the control is clocked at a clock frequency higher than the network frequency.

8. 10. The method of claim 1, The method, wherein the charging includes any one of pre-charging, charging, recharging, and discharging.

9. 10. The method of claim 1, The method further comprising providing a reference potential to a capacitor in a midpoint network on the coupling circuit.

10. 10. The method of claim 1, The method further comprising the step of detecting at least one output variable of the intermediate circuit DC voltage, the intermediate circuit current, the positive and negative rectifier voltages, the capacitor voltage relative to a reference potential, and the capacitor current.

11. 10. The method according to claim 1, wherein the method is used for at least one of a charging station, an electric drive for a machine, a power supply unit, and an energy conversion system on a power supply network.

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