Display device and manufacturing method thereof

Abstract

A display device according to various embodiments includes a substrate, a pixel circuit layer located on the substrate, a first connecting electrode and a second connecting electrode located on the pixel circuit layer, a first bump located on the first connecting electrode and a second bump located on the second connecting electrode, and a light-emitting element including a first electrode electrically connected to the first connecting electrode and a second electrode electrically connected to the second connecting electrode, wherein the first bump and the second bump include materials having different elastic modulus.

Description

[Technical Field]

[0001] The present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] The growing interest in information display and the increasing demand for portable information media has led to a major demand and commercialization of display devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 10-2021-0064238 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of strengthening the bonding strength between a light emitting element and a substrate, and a method for manufacturing the same. [Means for solving the problem]

[0005] A display device according to one embodiment of the present invention includes a substrate, a pixel circuit layer located on the substrate, first and second connecting electrodes located on the pixel circuit layer, first bumps located on the first connecting electrodes and second bumps located on the second connecting electrodes, and a light emitting element including a first electrode electrically connected to the first connecting electrode and a second electrode electrically connected to the second connecting electrode, wherein the first bumps and the second bumps include materials having different elastic moduli.

[0006] The first bump may have a greater modulus of elasticity than the second bump.

[0007] The first bump and the second bump may include an organic material or a metallic material.

[0008] The first bump may include a positive photoresist material, and the second bump may include a negative photoresist material.

[0009] The height of the second bump may be smaller than the height of the first bump, and the diameter of the second bump may be larger than the diameter of the first bump.

[0010] The light emitting device may include a semiconductor structure having a surface with a different height and emitting light, a first electrode located on the surface of the semiconductor structure, and a second electrode located on the surface of the semiconductor structure and different from the first electrode.

[0011] The first electrode may be located at a lower height on one surface of the semiconductor structure, and the second electrode may be located at a higher height on one surface of the semiconductor structure.

[0012] The semiconductor structure may include a first semiconductor layer, an active layer disposed on one side of the first semiconductor layer, and a second semiconductor layer disposed on one side of the active layer and of a different type than the first semiconductor layer.

[0013] The pixel circuit layer may include a transistor located on the substrate, the transistor including a semiconductor pattern, a first source electrode, a first drain electrode, and a gate electrode, and a plurality of via layers located on the transistor, and a first drain electrode of the transistor may be electrically connected to the first connecting electrode through contact holes of the plurality of via layers.

[0014] The semiconductor device may further include a third linking electrode covering the first bump and at least partially overlapping the first linking electrode, and a fourth linking electrode covering the second bump and at least partially overlapping the second linking electrode.

[0015] The light emitting device may further include an insulating film disposed between the light emitting device and the third and fourth connecting electrodes.

[0016] A display device according to one embodiment includes a substrate, a pixel circuit layer located on the substrate, a via layer located on the pixel circuit layer, a first connecting electrode and a second connecting electrode located on the pixel circuit layer, a first bump located on the first connecting electrode and a second bump located on the second connecting electrode, and a light-emitting element including a first electrode electrically connected to the first connecting electrode and a second electrode electrically connected to the second connecting electrode, wherein the first bump and the second bump include materials having different elastic moduli, and the second bump and the via layer include the same material.

[0017] The first bump may have a greater modulus of elasticity than the second bump.

[0018] The via layer, the first bump, and the second bump may include an organic material.

[0019] The height of the second bump may be smaller than the height of the first bump, and the diameter of the second bump may be larger than the diameter of the first bump.

[0020] The light emitting device may include a semiconductor structure having a surface with a different height and emitting light, a first electrode located on the surface of the semiconductor structure, and a second electrode located on the surface of the semiconductor structure and different from the first electrode.

[0021] The first electrode may be located at a lower height on one surface of the semiconductor structure, and the second electrode may be located at a higher height on one surface of the semiconductor structure.

[0022] A method for manufacturing a display device according to one embodiment includes the steps of providing a pixel circuit layer including a transistor on a substrate, a first connecting electrode, a second connecting electrode, a first bump, a second bump, and a via layer on the pixel circuit layer, disposing a light-emitting element including a first electrode and a second electrode on the substrate, and bonding the light-emitting element to the substrate so that the first electrode of the light-emitting element overlaps the first bump and the second electrode of the light-emitting element overlaps the second bump, wherein the first bump and the second bump include materials having different elastic moduli.

[0023] Before the light emitting device and the substrate are bonded together, the height of the first bump and the height of the second bump may be the same.

[0024] After the light emitting device and the substrate are bonded, the height may be higher than the height of the first bump and the height of the second bump. [Effects of the Invention]

[0025] According to one embodiment, the first bump and the second bump have different elastic moduli, so that the bonding strength between the substrate and the light emitting element including the first electrode and the second electrode located at different heights can be strengthened.

[0026] The effects of one embodiment are not limited to the contents described above, and various other effects are included in this specification. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a plan view schematically illustrating a display device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view schematically showing the display device of FIG. [Figure 3] 1 is a plan view illustrating a multi-screen display device that can be implemented as a display device according to an embodiment; [Figure 4] 2 is a circuit diagram illustrating an electrical connection relationship of one pixel included in a display device according to an embodiment; [Figure 5]1 is a cross-sectional view showing a light emitting device included in a display device according to an embodiment; [Figure 6] 1 is a cross-sectional view schematically illustrating a pixel included in a display device according to an embodiment. [Figure 7] 1 is a cross-sectional view schematically illustrating a pixel included in a display device according to an embodiment. [Figure 8] 10 is a diagram for experimenting with the characteristics of materials forming the first bump and the second bump of a pixel according to an embodiment; [Figure 9] 9 is a graph for explaining the results of the experiment in FIG. 8. [Figure 10] 9 is a table for explaining the results of the experiment in FIG. 8. [Figure 11] 10 is a diagram for experimenting with the characteristics of materials forming the first bump and the second bump of a pixel according to an embodiment; [Figure 12] 12 is a graph for explaining the results of the experiment in FIG. 11. [Figure 13] 12 is a table for explaining the results of the experiment in FIG. 11. [Figure 14] 10 is a diagram for experimenting with the characteristics of materials forming the first bump and the second bump of a pixel according to an embodiment; [Figure 15] 15 is a graph for explaining the results of the experiment in FIG. 14. [Figure 16] 15 is a table for explaining the results of the experiment in FIG. 14. [Figure 17] 10 is a graph showing the relationship between the indentation depth and the load depending on the material forming the first bump and the second bump of the pixel according to an embodiment. [Figure 18] 1A to 1C are cross-sectional views sequentially illustrating a part of a method for manufacturing a display device according to an embodiment. [Figure 19] 1A to 1C are cross-sectional views sequentially illustrating a part of a method for manufacturing a display device according to an embodiment. [Figure 20] 1A to 1C are cross-sectional views sequentially illustrating a part of a method for manufacturing a display device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0028] Although the present invention is susceptible to various modifications and can be embodied in various forms, only specific embodiments are illustrated in the drawings and the present disclosure will be described based on these. However, the present invention is not limited to the specific disclosed embodiments, and it should be understood that all modifications, equivalents, and alternatives within the spirit and technical scope of the present invention are included in the present invention.

[0029] Terms such as "first" and "second" are used to describe various components, but the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component can be called a second component, and similarly, a second component can be called a first component, without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0030] When an element or layer is referred to as being "on," "coupled," or "coupled" to another element or layer, it can be directly coupled to the other element or layer, or there can be an element or layer or one or more intermediate elements or layers present. When an element or layer is referred to as being "directly on," "directly coupled," or "directly bonded" to another element or layer, there are no intermediate elements or layers present. For example, when a first element is described as being "bonded" or "coupled" to a second element, the first element can be directly bonded or coupled to the second element, or the first element can be indirectly bonded or coupled to the second element via one or more intermediate elements.

[0031] In the drawings, dimensions of various elements, layers, etc. may be exaggerated for clarity of illustration. Like reference numerals refer to like elements. As used herein, the term "and / or" includes all combinations of one or more of the associated listed items. Also, the use of "may" in describing embodiments of the present invention refers to "one or more embodiments of the present invention." A phrase such as "at least one" preceding a list of elements modifies the entire list of elements, not individual elements of the list. As used herein, the terms "use," "using," and "used" can be considered synonymous with the terms "utilize," "utilize," and "utilize," respectively. As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than degree, and such terms are intended to account for obvious variations in measured or calculated values ​​that are recognized by those of ordinary skill in the art.

[0032] The terms used in this specification are used to describe embodiments of the present invention and are not intended to limit the present invention. As used in this specification, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly dictates otherwise. In this application, the terms "comprise" or "have" and the like are intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0033] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0034] FIG. 1 is a plan view schematically showing a display device according to an embodiment, and FIG. 2 is a cross-sectional view schematically showing the display device of FIG.

[0035] 1, a display device DD according to one embodiment may include a display area DA that displays an image and a non-display area NDA that does not display an image. The non-display area NDA may be provided on at least one side of the display area DA and may be provided to surround the display area DA (e.g., to surround or extend the periphery when viewed on a plane). Depending on the embodiment, the shape of the display area DA and the position of the non-display area NDA may be designed relatively.

[0036] The display device DD may be provided in the form of a rectangular plate having sharp corners, or in some embodiments, the display device DD may be embodied in the form of a rectangular plate having rounded corners. However, the present invention is not limited thereto, and the display device DD may be embodied in various shapes.

[0037] The display device DD according to one embodiment can be applied to electronic devices having a display surface on at least one side, such as a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, PDA, PMP (portable multimedia player), MP3 player, medical equipment, camera, or wearable display device.

[0038] In addition, the display device DD according to one embodiment may include a self-luminous display panel such as a nano-scale or micro-scale LED display panel, a quantum dot organic light emitting display panel (QD OLED panel), etc.

[0039] The display device DD may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB.

[0040] The substrate SUB may constitute a base member of the display device DD. Depending on the embodiment, the substrate SUB may be a rigid or flexible substrate or film, and its material and physical properties are not particularly limited. For example, the substrate SUB may be a rigid substrate including (or consisting of) glass or tempered glass, a flexible substrate (or thin film) including (or consisting of) plastic or metal, or at least one insulating layer, and its material and / or physical properties are not particularly limited.

[0041] A plurality of pixels PXL may be located in the display area DA, and wiring, pads, driving circuits, etc. connected to the pixels PXL of the display area DA may be selectively located in the non-display area NDA.

[0042] 1 shows only one pixel PXL, a plurality of pixels PXL may be distributed in the display area DA. For example, the pixels PXL may be arranged in the display area DA in an array structure such as a matrix or stripe. However, the present invention is not limited to this.

[0043] Referring to FIG. 2, the display device DD may include a pixel circuit layer PCR, a display element layer DPL, and a cover layer CVL, which are sequentially disposed on a substrate SUB.

[0044] The pixel circuit layer PCL is located on the substrate SUB and may include a plurality of transistors, a capacitor, and signal lines connected to the plurality of transistors. For example, each transistor may have a structure in which a semiconductor pattern, a gate electrode, a source electrode, and a drain electrode are stacked in this order with an insulating layer sandwiched therebetween.

[0045] The display element layer DPL is located on the pixel circuit layer PCL and may include a light emitting element, which may be, for example, an inorganic light emitting element or a light emitting element that emits light by changing the wavelength of the emitted light using quantum dots.

[0046] The cover layer CVL may be positioned on the display element layer DPL. The cover layer CVL may be in the form of a sealing substrate or a sealing film made of a multilayer film. When the cover layer CVL is in the form of a sealing film, it may be in the form of an inorganic film, an organic film, and an inorganic film stacked in order. The cover layer CVL may prevent or substantially prevent external air and moisture from penetrating into the display element layer DPL and the pixel circuit layer PCL.

[0047] According to an embodiment, the cover layer CVL may be coated on the substrate SUB in a liquid form including (or consisting of) a heat- and / or light-curable resin, and then cured by a curing process using heat and / or light. In this case, the cover layer CVL may protect the light emitting device and stably fix the light emitting device.

[0048] The cover layer CVL may also include an anti-reflective film (AR).

[0049] FIG. 3 is a plan view showing a multi-screen display device that can be implemented as a display device according to an embodiment.

[0050] Referring to FIG. 3, a display device according to an embodiment may be a multi-screen display device TDD including multiple display devices.

[0051] A multi-screen display device TDD (also called a tiled display) may include a plurality of display devices DD1, DD2, DD3, and DD4 arranged in a matrix form along a first direction DR1 and a second direction DR2, where one display device DD1 may be the display device DD shown in FIGS.

[0052] The display devices DD1, DD2, DD3, and DD4 may display individual images or divide one image into segments. The display devices DD1, DD2, DD3, and DD4 may include display panels of the same type, structure, size, or format, but the present invention is not limited thereto.

[0053] The multiple display devices DD1, DD2, DD3, DD4 can be physically coupled together by a housing (not shown) that can be positioned underneath the multiple display devices DD1, DD2, DD3, DD4 so as to form one multi-screen display device TDD.

[0054] The plurality of display devices DD1, DD2, DD3, and DD4 may be embodied in various shapes. In FIG. 3, the plurality of display devices DD1, DD2, DD3, and DD4 are shown as having rectangular plate shapes, but the present invention is not limited thereto, and the plurality of display devices DD1, DD2, DD3, and DD4 may each have a circular or elliptical shape, etc.

[0055] Hereinafter, a pixel included in a display device according to an embodiment will be described with reference to FIG.

[0056] FIG. 4 is a circuit diagram showing an electrical connection relationship of one pixel included in a display device according to an embodiment.

[0057] Referring to FIG. 4, one pixel PXL according to an embodiment may include a light emitting unit EMU that generates light with a brightness corresponding to a data signal and a pixel circuit PXC for driving the light emitting unit EMU.

[0058] The light emitting unit EMU may include a light emitting element LD connected between a first power supply wiring PL1 to which a voltage of a first driving power supply VDD is applied and a second power supply wiring PL2 to which a voltage of a second driving power supply VSS is applied.

[0059] The light emitting element LD may include a second electrode EL2 connected to a first driving power supply VDD via a first power supply wiring PL1 and a first electrode EL1 connected to a second driving power supply VSS via a second power supply wiring PL2. In one embodiment, the first electrode EL1 may be a cathode, and the second electrode EL2 may be an anode.

[0060] The light emitting element LD can emit light at a brightness corresponding to a driving current supplied via a pixel circuit PXC (described later). For example, during each frame period, the pixel circuit PXC can supply a driving current corresponding to a gray scale value of the corresponding frame data to the light emitting unit EMU. The driving current supplied to the light emitting unit EMU can flow to the light emitting element LD, and the light emitting element LD can emit light at a brightness corresponding to the driving current.

[0061] The pixel circuit PXC can be connected to a scan line Si and a data line Dj. If the pixel PXL is arranged in the i-th row (i is a natural number) and j-th column (j is a natural number) of the display area DA (see FIG. 1), the pixel circuit PXC can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0062] The pixel circuit PXC may also include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0063] The first transistor T1 is a driving transistor for controlling the driving current applied to the light emitting unit EMU and may be connected between the light emitting unit EMU and the second driving power supply VSS. Specifically, a first terminal of the first transistor T1 may be connected to the light emitting unit EMU, a second terminal of the first transistor T1 may be connected to the second driving power supply VSS via the second power supply wiring PL2, and a gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the amount of driving current flowing from the first driving power supply VDD to the light emitting unit EMU in accordance with the voltage applied to the first node N1. In one embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode.

[0064] The second transistor T2 is a switching transistor that selects and activates the pixel PXL in response to a scan signal applied to the scan line Si, and may be connected between the data line Dj and the first node N1. A first terminal of the second transistor T2 may be connected to the data line Dj, a second terminal of the second transistor T2 may be connected to the first node N1, and a gate electrode of the second transistor T2 may be connected to the scan line Si.

[0065] When a scan signal of a gate-on voltage (e.g., a high-level voltage) is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the data line Dj to the first node N1. The first node N1 is a point where the second terminal of the second transistor T2 is connected to the gate electrode of the first transistor T1, and the second transistor T2 can transmit a data signal to the gate electrode of the first transistor T1.

[0066] One electrode STE1 (or a first storage electrode) of the storage capacitor Cst may be connected to the second driving power supply VSS, and the other electrode STE2 (or a second storage electrode) may be connected to the first node N1. The storage capacitor Cst may charge a voltage corresponding to the data signal supplied to the first node N1 and maintain the charged voltage until the data signal of the next frame is supplied.

[0067] The present invention is not limited to the structure shown in Fig. 4, and the structure of the pixel circuit PXC can be modified in various ways. Depending on the embodiment, the pixel circuit PXC may further include a sensing transistor, a light-emitting control transistor, a parasitic capacitor, etc. in addition to the transistors shown in Fig. 4.

[0068] The light emitting element described in FIG. 4 will be described in detail below with reference to FIG.

[0069] FIG. 5 is a cross-sectional view showing a light emitting device included in a display device according to an embodiment.

[0070] Referring to FIG. 5, a light emitting device LD according to an embodiment may include a semiconductor structure 10, a first electrode EL1, and a second electrode EL2.

[0071] The semiconductor structure 10 can emit light by recombination of electrons and holes due to a current flowing between the first electrode EL1 and the second electrode EL2. By utilizing this principle, the light emitting element LD can be used as a light source (or a light emitting source) for various display devices (or light emitting devices) by controlling the light emission of the semiconductor structure 10.

[0072] For example, the first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may be an n-type semiconductor layer including any one of semiconductor materials selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant (or n-type dopant) such as Si, Ge, or Sn. However, the material constituting the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be made of various other materials. In one embodiment of the present invention, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant).

[0073] The active layer 12 is disposed on one side of the first semiconductor layer 11 and may have a single or multiple quantum well structure. For example, if the active layer 12 has a multiple quantum well structure, the active layer 12 may have a barrier layer, a strain reinforcing layer, and a well layer periodically stacked as a single unit. The strain reinforcing layer has a smaller lattice constant than the barrier layer, thereby further reinforcing the compressive strain applied to the well layer. However, the structure of the active layer 12 is not limited to the above embodiment and may be variously modified depending on the embodiment.

[0074] The active layer 12 can emit light having a wavelength of about 400 nm to about 900 nm and can have a double heterostructure. In one embodiment, a clad layer doped with a conductive dopant can be formed on the upper and / or lower parts of the active layer 12. In one example, the clad layer can be formed of an AlGaN layer or an InAlGaN layer. Depending on the embodiment, materials such as AlGaN and InAlGaN can be used to form the active layer 12, but various other materials can also be used to form the active layer 12. The active layer 12 can include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0075] The second semiconductor layer 13 may include a semiconductor layer of a different type from the first semiconductor layer 11. As an example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a dopant of a second conductivity type (or a p-type dopant) such as Mg. However, the material constituting the second semiconductor layer 13 is not limited thereto, and various other materials may be used to constitute the second semiconductor layer 13. In one embodiment, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a dopant of a second conductivity type (or a p-type dopant).

[0076] The second semiconductor layer 13 is disposed on one side of the active layer 12 and may include a lower surface in contact with the upper surface of the active layer 12 and an upper surface in contact with the second electrode EL2. The second semiconductor layer 13 may provide holes to the active layer 12.

[0077] To form the semiconductor structure 10, the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may each be provided as a structure in which they are sequentially stacked on a semiconductor substrate. Here, the semiconductor substrate may include a semiconductor material such as a sapphire substrate or a silicon substrate. Such a semiconductor substrate may be used as a growth substrate for growing the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and then separated from the first semiconductor layer 11 by a substrate separation process. Here, the substrate separation process may be performed by laser lift-off or chemical lift-off. As a result, the growth semiconductor substrate is removed from the semiconductor structure 10, allowing the semiconductor structure 10 to have a thin thickness. In one embodiment, the semiconductor structure 10 may have a small size on the order of a microscale, but the present invention is not limited thereto.

[0078] In one embodiment, the semiconductor structure 10 may include a mesa interface formed by a surface having different heights and a slope extending from the surface. The mesa interface may be formed by performing an etching process to remove portions of the second semiconductor layer 13, the active layer 12, and the first semiconductor layer 11. This may expose the side surfaces of the active layer 12 and / or the second semiconductor layer 13 to the outside. Here, the etching process may be, for example, a dry etching process.

[0079] The first electrode EL1 may be located on one surface of the semiconductor structure 10. The first electrode EL1 may be located in a low-height portion on one surface of the semiconductor structure 10. Specifically, the first electrode EL1 may be located on the first semiconductor layer 11 so as to be electrically isolated from the active layer 12 and the second semiconductor layer 13. In FIG. 5 , the first electrode EL1 is shown as being located on a portion of the top surface of the first semiconductor layer 11, but the size of the first electrode EL1 may be modified in various ways. Depending on the embodiment, the edge of the first electrode EL1 may be located on the same line as the edge of the first semiconductor layer 11.

[0080] In one embodiment, the first electrode EL1 can overlap a first bump (see FIG. 7) for bonding the light emitting element LD.

[0081] The second electrode EL2 may be located on one surface of the semiconductor structure 10. The second electrode EL2 may be located at a higher portion on one surface of the semiconductor structure 10. Specifically, the second electrode EL2 may be located on the second semiconductor layer 13. In FIG. 5, the second electrode EL2 is shown as being located on a portion of the top surface of the second semiconductor layer 13, but the size of the second electrode EL2 may be modified in various ways. Depending on the embodiment, the second electrode EL2 may be located so as to completely overlap the top surface of the second semiconductor layer 13.

[0082] In one embodiment, the second electrode EL2 can overlap with a second bump (see FIG. 7) for bonding the light emitting element LD.

[0083] The first electrode EL1 may be a contact electrode making ohmic contact with the first semiconductor layer 11, and the second electrode EL2 may be a contact electrode making ohmic contact with the second semiconductor layer 13. Depending on the embodiment, the first and second electrodes EL1 and EL2 may be Schottky contact electrodes.

[0084] The first electrode EL1 and the second electrode EL2 may include a conductive material. For example, the first electrode EL1 and the second electrode EL2 may include an opaque metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), or an oxide or alloy thereof, either alone or in combination, but the present invention is not limited thereto. According to an embodiment, the first electrode EL1 and the second electrode EL2 may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO).

[0085] Hereinafter, a specific configuration of a display device according to an embodiment will be described with reference to FIGS.

[0086] 6 and 7 are cross-sectional views each showing a pixel included in a display device according to an embodiment.

[0087] Referring to FIGS. 6 and 7, one pixel PXL included in a display device according to an embodiment may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

[0088] The substrate SUB may be a rigid or flexible base layer. For example, if the substrate SUB is rigid, it may be implemented as a glass substrate, a quartz substrate, a glass ceramic substrate, a crystalline glass substrate, etc. If the substrate SUB is flexible, it may be implemented as a polymer organic substrate including polyimide, polyamide, etc., a plastic substrate, etc.

[0089] The pixel circuit layer PCL is located on the substrate SUB.

[0090] The pixel circuit layer PCL may include a plurality of wirings connected to at least one transistor, and may include a buffer layer BFL, a plurality of insulating layers GI1, GI2, ILD, INS1, INS2, INS3, and a plurality of via layers VIA1, VIA2, VIA3, which are sequentially stacked on one surface of the substrate SUB.

[0091] The buffer layer BFL is located on the substrate SUB so as to cover the substrate SUB. The buffer layer BFL can prevent impurities from diffusing from the outside into the pixel circuit layer PCL. The buffer layer BFL is made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x The buffer layer BFL may include at least one of a metal oxide such as a metal oxide (e.g., a SiO 2 layer, a SiO 3 layer, a SiO 4 layer, a SiO 5 layer, a SiO 6 layer, a SiO 7 layer, a SiO 8 layer, a SiO 9 layer, a SiO 2 layer, a SiO 2 layer, a SiO 3 layer, a SiO 4 layer, a SiO 5 layer, a SiO 6 layer, a SiO 7 layer, a SiO 8 layer, a SiO 9 ...

[0092] The transistor TR may include a semiconductor pattern ACT, a gate electrode GAT, a first source electrode TE1, and a first drain electrode TE2.

[0093] The semiconductor pattern ACT is located on the buffer layer BFL. The semiconductor pattern ACT may include a channel region and source and drain regions located on both sides (e.g., opposite sides) of the channel region. The source region of the semiconductor pattern ACT may be electrically connected to a first source electrode TE1, and the drain region may be electrically connected to a first drain electrode TE2. That is, the source and drain regions may be extended and electrically connected to electrodes of other layers through contact openings (e.g., contact holes), respectively.

[0094] The semiconductor pattern ACT may include at least one of polycrystalline silicon, amorphous silicon, and oxide semiconductor.

[0095] Among the insulating layers GI1, GI2, ILD, INS1, INS2, and INS3, the first gate insulating layer GI1 is located on the semiconductor pattern ACT and the buffer layer BFL. The first gate insulating layer GI1 covers the semiconductor pattern ACT and the buffer layer BFL.

[0096] The first gate insulating layer GI1 may include an inorganic material. For example, the first gate insulating layer GI1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ) According to an embodiment, the first gate insulating layer GI1 may include an organic material.

[0097] The gate electrode GAT is located on the first gate insulating layer GI1 and may be located to overlap a channel region of the semiconductor pattern ACT.

[0098] A first capacitor electrode CE1 may be located on the first gate insulating layer GI1. The first capacitor electrode CE1 may form a capacitor C together with a second capacitor electrode CE2, which will be described later.

[0099] The second gate insulating layer GI2 of the multiple insulating layers GI1, GI2, ILD, INS1, INS2, and INS3 is located on the gate electrode GAT and the first gate insulating layer GI1. The second gate insulating layer GI2 covers the gate electrode GAT and the first gate insulating layer GI1.

[0100] The second gate insulating layer GI2 may include the same material as the first gate insulating layer GI1, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ) may include at least one of:

[0101] A second capacitor electrode CE2 may be located on the second gate insulating layer GI2.

[0102] Among the insulating layers GI1, GI2, ILD, INS1, INS2, and INS3, the interlayer insulating layer ILD is located on the second gate insulating layer GI2. The interlayer insulating layer ILD covers the second gate insulating layer GI2 and the second capacitor electrode CE2. The interlayer insulating layer ILD may contain the same material as the second gate insulating layer GI2, and may contain an inorganic or organic material.

[0103] The first source electrode TE1 and the first drain electrode TE2 are located on the interlayer insulating layer ILD, where the first source electrode TE1 may have the same configuration as the second terminal of the first transistor T1 in FIG.

[0104] The first drain electrode TE2 may be electrically connected to the first electrode EL1 of the light emitting element LD via a first contact opening (e.g., a first contact hole) CH1 of a first via layer VIA1, a first bridge electrode BRD1, a second contact opening (e.g., a second contact hole) CH2 of a second via layer VIA2, a second bridge electrode BRD2, a third contact opening (e.g., a third contact hole) CH3 of a third via layer VIA3, a first connecting electrode CNE1, and a third connecting electrode CEL3, which will be described later. As a result, the transistor TR may transmit the voltage of the second driving power supply VSS (see FIG. 4) to the first electrode EL1.

[0105] The first via layer VIA1 of the multiple via layers VIA1, VIA2, and VIA3 is located on the first source electrode TE1, the first drain electrode TE2, and the interlayer insulating layer ILD, and covers the first source electrode TE1, the first drain electrode TE2, and the interlayer insulating layer ILD.

[0106] The first via layer VIA1 may include at least one organic insulating layer. The first via layer VIA1 may be composed of a single layer or multiple layers and may include an inorganic insulating material or an organic insulating material. For example, the first via layer VIA1 may include at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0107] The first contact hole CH1 of the first via layer VIA1 may physically and / or electrically connect the first drain electrode TE2 and the first bridge electrode BRD1.

[0108] The first insulating layer INS1 of the plurality of insulating layers GI1, GI2, ILD, INS1, INS2, and INS3 is located on the first via layer VIA1. The first insulating layer INS1 may include an inorganic material. For example, the first insulating layer INS1 may be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ) Depending on the embodiment, the first insulating layer INS1 may include an organic material.

[0109] The first contact hole CH1 in the first insulating layer INS1 may physically and / or electrically connect the first drain electrode TE2 and the first bridge electrode BRD1.

[0110] The first bridge electrode BRD1 is located on the first insulating layer INS1.

[0111] The second via layer VIA2 of the multiple via layers VIA1, VIA2, and VIA3 is located on the first insulating layer INS1 and the first bridge electrode BRD1. The second via layer VIA2 may include the same material as the first via layer VIA1. For example, the second via layer VIA2 may include at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0112] The second contact hole CH2 of the second via layer VIA2 may physically and / or electrically connect the first bridge electrode BRD1 and the second bridge electrode BRD2.

[0113] The second insulating layer INS2 of the plurality of insulating layers GI1, GI2, ILD, INS1, INS2, and INS3 is located on the second via layer VIA2. The second insulating layer INS2 may include the same material as the first insulating layer INS1. For example, the second insulating layer INS2 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ) Depending on the embodiment, the second insulating layer INS2 may include an organic material.

[0114] The second contact hole CH2 in the second insulating layer INS2 may physically and / or electrically connect the first bridge electrode BRD1 and the second bridge electrode BRD2.

[0115] The second bridge electrode BRD2 is located on the second insulating layer INS2. The drive voltage line DVL is also located on the second insulating layer INS2.

[0116] The third via layer VIA3 of the multiple via layers VIA1, VIA2, and VIA3 is located on the second insulating layer INS2, the second bridge electrode BRD2, and the drive voltage wiring DVL. The third via layer VIA3 may include the same material as the second via layer VIA2. For example, the third via layer VIA3 may include at least one of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0117] The third contact hole CH3 of the third via layer VIA3 may physically and / or electrically connect the second bridge electrode BRD2 to a first connecting electrode CNE1 (described later), and the fourth contact opening (e.g., fourth contact hole) CH4 of the third via layer VIA3 may physically and / or electrically connect the driving voltage line DVL to a second connecting electrode CNE2 (described later).

[0118] The third insulating layer INS3 of the plurality of insulating layers GI1, GI2, ILD, INS1, INS2, and INS3 is located on the third via layer VIA3. The third insulating layer INS3 may include the same material as the second insulating layer INS2. For example, the third insulating layer INS3 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ) Depending on the embodiment, the third insulating layer INS3 may include an organic material.

[0119] The display element layer DPL may include connecting electrodes CNE1, CNE2, CNE3, and CNE4, a fourth via layer VIA4, a fourth insulating layer INS4, a first bump BUM1, a second bump BUM2, a light emitting element LD, and an insulating film FIL.

[0120] The connecting electrodes CNE1, CNE2, CNE3, and CNE4 may include a first connecting electrode CNE1, a second connecting electrode CNE2, a third connecting electrode CE3, and a fourth connecting electrode CNE4.

[0121] The first connecting electrode CNE1 may be located on the pixel circuit layer PCL and may be physically and / or electrically connected to the second bridge electrode BRD2 through the third insulating layer INS3 and the third contact hole CH3 of the third via layer VIA3.

[0122] The second connecting electrode CNE2 may be located on the pixel circuit layer PCL, and may be located in the same layer as the first connecting electrode CNE1. The second connecting electrode CNE2 may be physically and / or electrically connected to the driving voltage line DVL through the third insulating layer INS3 and the fourth contact hole CH4 of the third via layer VIA3. The driving voltage line DVL may correspond to a portion of the first power line PL1 described with reference to FIG. 4.

[0123] The first connecting electrode CNE1 and the second connecting electrode CNE2 may form a single layer of a material selected from the group consisting of copper (Cu), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), and alloys thereof, or a mixture thereof, or may have a double-layer or multi-layer structure of copper (Cu), titanium (Ti), aluminum (Al), silver (Ag), or gold (Au) to reduce wiring resistance. For example, the first connecting electrode CNE1 and the second connecting electrode CNE2 may have a triple-layer structure in which titanium (Ti), aluminum (Al), and titanium (Ti) are stacked in this order.

[0124] The third connecting electrode CNE3 may be positioned on the first connecting electrode CNE1 and the first bump BUM1. The third connecting electrode CNE3 may at least partially overlap the first connecting electrode CNE1 and may be positioned to cover the first bump BUM1. The third connecting electrode CNE3 may be in direct contact with the first electrode EL1 of the light emitting element LD and may be physically and / or electrically connected to the first electrode EL1 of the light emitting element LD. As a result, the third connecting electrode CNE3 may electrically connect the first electrode EL1 and the first connecting electrode CNE1, and the first electrode EL1 may receive a driving current from the second driving power source VSS (see FIG. 4) from the driving transistor of the pixel circuit layer PCL.

[0125] The fourth connecting electrode CNE4 may be located on the second connecting electrode CNE2 and the second bump BUM2. The fourth connecting electrode CNE4 may at least partially overlap the second connecting electrode CNE2 and may be located to cover the second bump BUM2. The fourth connecting electrode CNE4 may be in direct contact with the second electrode EL2 of the light emitting element LD and may be physically and / or electrically connected to the second electrode EL2 of the light emitting element LD. As a result, the fourth connecting electrode CNE4 may electrically connect the second electrode EL2 and the second connecting electrode CNE2, and the second electrode EL2 may receive the first driving power supply VDD (see FIG. 4) from the driving voltage wiring DVL of the pixel circuit layer PCL.

[0126] The third connecting electrode CNE3 and the fourth connecting electrode CNE4 may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. The present invention is not limited thereto, and according to an embodiment, the third connecting electrode CNE3 and the fourth connecting electrode CNE4 may include an opaque metal such as magnesium (Mg), aluminum (Al), silver (Ag), gold (Au), copper (Cu), tin (Sn), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and oxides or alloys thereof, either alone or in combination.

[0127] The fourth via layer VIA4 (or via layer) can be located on the pixel circuit layer PCL.

[0128] The fourth via layer VIA4 may be an organic insulating film containing an organic material. For example, the fourth via layer VIA4 may include at least one of a polyacrylate resin (e.g., a polyacrylate resin), an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin. However, the present invention is not limited thereto, and the fourth via layer VIA4 may include an inorganic material.

[0129] In addition, in one embodiment, the fourth via layer VIA4 may include a negative photoresist material or may be a black pixel define layer made of the negative photoresist material. In one embodiment, the fourth via layer VIA4 may include the same organic material as the second bump BUM2 described below.

[0130] The fourth insulating layer INS4 may be located on the fourth via layer VIA4 to cover the fourth via layer VIA4. The fourth insulating layer INS4 may include an inorganic material. For example, the fourth insulating layer INS4 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x However, the present invention is not limited thereto, and the fourth insulating layer INS4 may include an organic material.

[0131] The first bump BUM1 may be located on the first connecting electrode CNE1.

[0132] The second bump BUM2 may be located on the second connecting electrode CNE2.

[0133] The first bump BUM1 may have a semicircular ellipse shape that is elongated in the third direction DR3 in a cross-sectional view. Therefore, the shape of the third connecting electrode CNE3 covering the first bump BUM1 may correspond to the shape of the first bump BUM1. That is, in one embodiment, the third connecting electrode CNE3 may have a semicircular ellipse shape that is elongated in a cross-sectional view. However, the present invention is not limited thereto, and the shape of the first bump BUM1 may be modified in various ways. In one embodiment, the height hh1 of the first bump BUM1 may correspond to about 1.5 μm to about 3 μm, and the diameter dd1 of the first bump BUM1 may correspond to about 3 μm to about 6 μm.

[0134] The second bump BUM2 may have a semicircular ellipse shape that is elongated in the third direction DR3 in a cross-sectional view. Therefore, the shape of the fourth connecting electrode CNE4 covering the second bump BUM2 may correspond to the shape of the second bump BUM2. That is, in one embodiment, the fourth connecting electrode CNE4 may have a semicircular ellipse shape that is elongated in a cross-sectional view. However, the present invention is not limited thereto, and the shape of the second bump BUM2 may be variously modified. In one embodiment, the height hh2 of the second bump BUM2 coupled to the light emitting element LD may be smaller than the height hh1 of the first bump BUM1, and the diameter dd2 of the second bump BUM2 may be larger than the diameter dd1 of the first bump BUM1. In one embodiment, the height hh2 of the second bump BUM2 may correspond to approximately 1.5 μm to approximately 3 μm, and the diameter dd2 of the second bump BUM2 may correspond to approximately 3 μm to approximately 6 μm.

[0135] The first bump BUM1 may include an organic material. For example, the first bump BUM1 may include a positive photoresist material. The present invention is not limited thereto, and according to an embodiment, the first bump BUM1 may include a metal material.

[0136] The second bump BUM2 may include a different organic material from the first bump BUM1. For example, the second bump BUM2 may include a negative photoresist material. The present invention is not limited to this, and according to an embodiment, the second bump BUM2 may include a metal material having a lower modulus of elasticity than the first bump BUM1. The second bump BUM2 may also include various organic materials having a lower modulus of elasticity than the first bump BUM1.

[0137] In one embodiment, the second bump BUM2 may contain the same material as the fourth via layer VIA4. The present invention is not limited to this, and the second bump BUM2 may contain a different material from the fourth via layer VIA4. Hereinafter, the material (or materials) forming the first bump BUM1 and the second bump BUM2 will be described in detail with reference to FIGS. 8 to 17.

[0138] In one embodiment, the first bump BUM1 may include a material having a greater modulus of elasticity than the second bump BUM2. Therefore, even if the same pressure is applied to the first bump BUM1 and the second bump BUM2, the second bump BUM2 may deform more than the first bump BUM1. That is, the amount of deformation of the second bump BUM2 may be greater than the amount of deformation of the first bump BUM1 under the same load and pressure. Therefore, when the light emitting element LD is coupled to the substrate SUB with the first electrode EL1 and the second electrode EL2 facing downward in the third direction DR3, the second bump BUM2 in contact with the second electrode EL2 deforms more than the first bump BUM1. This reduces the contact resistance between the light emitting element LD and the pixel circuit layer PCL (or the circuit board or substrate) despite the height difference (or step) between the first electrode EL1 and the second electrode EL2. This strengthens the bonding strength between the light emitting element LD and the substrate.

[0139] The light emitting element LD may be located on the third linking electrode CNE3 and the fourth linking electrode CNE4. In one embodiment, the light emitting element LD may be located such that the first electrode EL1 and the second electrode EL2 face the third linking electrode CNE3 and the fourth linking electrode CNE4, respectively, in the third direction DR3. Since the semiconductor structure 10 of the light emitting element LD includes a mesa interface, the heights of the first electrode EL1 and the second electrode EL2 may be different.

[0140] The first electrode EL1 of the light emitting element LD can be in direct contact with the third connecting electrode CNE3 and can overlap the first bump BUM1.

[0141] The second electrode EL2 of the light emitting element LD can be in direct contact with the fourth linking electrode CNE4 and can overlap the second bump BUM2.

[0142] The insulating film FIL may be located on the fourth insulating layer INS4, the third connecting electrode CNE3, and the fourth connecting electrode CNE4.

[0143] The insulating film FIL can be located between the light emitting element LD and a circuit board, where the circuit board can collectively refer to the substrate SUB, the pixel circuit layer PCL, and a part of the display element layer DPL.

[0144] Specifically, the insulating film FIL may be located between the light emitting element LD and the third and fourth connecting electrodes CNE3 and CNE4. That is, the insulating film FIL may be located between the light emitting element LD and the third connecting electrode CNE3 to couple the light emitting element LD to a circuit board, or may be located between the light emitting element LD and the fourth connecting electrode CNE4 to couple the light emitting element LD to a circuit board.

[0145] In one embodiment, the insulating film FIL may correspond to a non-conductive film (NCF), but the present invention is not limited thereto, and the insulating film FIL may correspond to various materials made of insulating materials and having cohesive properties.

[0146] In the display device according to the embodiment, the light emitting element LD can be stably coupled to the circuit board by the first bump BUM1, the second bump BUM2, the third connecting electrode CNE3, the fourth connecting electrode CNE4, and the insulating film FIL.

[0147] The materials forming the first bump and the second bump described with reference to FIG. 7 will be described below with reference to FIGS. 8 to 17. FIG.

[0148] FIG. 8 is a diagram for testing the properties of materials constituting the first and second bumps of a pixel according to an embodiment, FIG. 9 is a graph illustrating the results of the experiment of FIG. 8, and FIG. 10 is a table illustrating the results of the experiment of FIG. 8. FIG. 11 is a diagram for testing the properties of materials constituting the first and second bumps of a pixel according to an embodiment, FIG. 12 is a graph illustrating the results of the experiment of FIG. 11, and FIG. 13 is a table illustrating the results of the experiment of FIG. 11. FIG. 14 is a diagram for testing the properties of materials constituting the first and second bumps of a pixel according to an embodiment, FIG. 15 is a graph illustrating the results of the experiment of FIG. 14, and FIG. 16 is a table illustrating the results of the experiment of FIG. 14. FIG. 17 is a graph illustrating the relationship between indentation depth and load for materials constituting the first and second bumps of a pixel according to an embodiment.

[0149] First, referring to FIGS. 8 to 16, materials constituting the first and second bumps of a pixel according to an embodiment can be divided into a first embodiment, a second embodiment, and a third embodiment. The material of each embodiment can be positioned on the base layer BSL of FIGS. 8, 11, and 14 as a bump layer BUML. For example, in a first experiment, the bump layer BUML can be configured as the first embodiment and positioned on the base layer BSL. In a second experiment, the bump layer BUML can be configured as the second embodiment and positioned on the base layer BSL. In a third experiment, the bump layer BUML can be configured as the third embodiment and positioned on the base layer BSL. Here, the base layer BSL can be glass, and the bump layer BUML can be a single layer.

[0150] 8, an object 810 having an inverted triangular shape in cross section is positioned on the bump layer BUML. Then, a predetermined reference pressure (e.g., a previously determined pressure) is applied to the object 810 having an inverted triangular shape in cross section (or having a cross-sectional shape of an inverted triangle), and the indentation depth of the bump layer BUML due to the load can be measured.

[0151] 11, an object 1110 having a circular cross section is placed on the bump layer BUML, and then a predetermined pressure is applied to the object 1110 having a circular cross section, so that the pressing depth of the bump layer BUML due to the load can be measured.

[0152] 14, a cylindrical object 1410 is placed on the bump layer BUML, and then a predetermined pressure is applied to the cylindrical object 1410, so that the indentation depth of the bump layer BUML due to the load can be measured.

[0153] An object 810 having an inverted triangular shape in cross section may have a smaller area of ​​contact with the upper surface of the bump layer BUML than an object 1110 having a circular shape in cross section, and an object 1110 having a circular shape in cross section may have a smaller area of ​​contact with the upper surface of the bump layer BUML than an object 1410 having a cylindrical shape.

[0154] The first embodiment may correspond to a material forming the first bump BUM1. For example, the first embodiment may correspond to a material using polyimide as a binder among positive photoresist materials.

[0155] The second and third embodiments may correspond to a material forming the second bump BUM2. For example, the second and third embodiments may correspond to a negative photoresist material using cardo acrylate as a binder. Specifically, the second and third embodiments may correspond to a black pixel defining layer and may correspond to a material that transmits different wavelengths (e.g., different wavelengths of light) depending on the initiator. Here, the black pixel defining layer refers to a black organic layer. When the organic layer corresponds to a pixel defining layer included in a display element layer, the display element layer can be said to include a black pixel defining layer.

[0156] The second embodiment is capable of transmitting short wavelengths (eg, about 365 nm), and the third embodiment is capable of transmitting short and long wavelengths (eg, about 400 nm).

[0157] In the present invention, the materials of the first, second, and third embodiments are not limited to the above examples. Depending on the embodiment, if the material of the first embodiment is an organic material having a larger elastic modulus than the materials of the second and third embodiments, it may correspond to the material of the first bump BUM1 and the second bump BUM2.

[0158] Therefore, referring to FIG. 9, when the bump layer BUML includes the first embodiment, the indentation depth can be shallower than those of the second and third embodiments even when the same load (or pressure) is applied. For example, referring to FIG. 10, the first embodiment can have a higher hardness and elastic modulus than the second embodiment, and the second embodiment can have a higher hardness and elastic modulus than the third embodiment. Furthermore, the first embodiment can have an indentation depth of about 0.14 μm when a load of 0.2 mN is applied, and the second and third embodiments can have an indentation depth of about 0.16 μm when a load of 0.2 mN is applied. In the experiment shown in FIG. 8, the results of the second and third embodiments can be similar. In one embodiment, when the bump layer BUML includes the first embodiment, the second bump BUM2 has a smaller elastic deformation rate (i.e., a larger elastic modulus) than the second and third embodiments even when the same load is applied, and therefore the second bump BUM2 can deform more than the first bump BUM1 for the same pressure. As a result, the second bump BUM2 in contact with the second electrode EL2 deforms more than the first bump BUM1, and therefore the contact resistance between the light emitting element LD and the pixel circuit layer PCL (or the circuit board or substrate) can be reduced despite the difference in height (or step) between the first electrode EL1 and the second electrode EL2. This can strengthen the bonding force between the light emitting element LD and the substrate.

[0159] 12, when the bump layer BUML includes the first embodiment, the indentation depth can be shallower than that of the second and third embodiments when the same load (or pressure) is applied. For example, referring to FIG. 13, when a load of 0.2 mN is applied, the first embodiment can have an indentation depth of about 0.11 μm, and when a load of 0.2 mN is applied, the second and third embodiments can have an indentation depth of about 0.13 μm. In the experiment shown in FIG. 11, the results of the second and third embodiments can be similar. In one embodiment, when the bump layer BUML includes the first embodiment, the elastic deformation rate is smaller than that of the second and third embodiments when the same load is applied (i.e., the elastic modulus is larger), so the second bump BUM2 can have a larger deformation amount for the same pressure than the first bump BUM1. As a result, the second bump BUM2 in contact with the second electrode EL2 deforms more than the first bump BUM1, so that the contact resistance between the light emitting element LD and the pixel circuit layer PCL (or the circuit board, the substrate) can be reduced despite the difference in height (or the step) between the first electrode EL1 and the second electrode EL2, thereby strengthening the bonding force between the light emitting element LD and the substrate.

[0160] 15, when the bump layer BUML includes the first embodiment, the press-in depth can be shallower than those of the second and third embodiments even when the same load (or pressure) is applied. Also, when the bump layer BUML includes the second embodiment, the press-in depth can be shallower than those of the third embodiment even when the same load (or pressure) is applied. For example, with reference to FIG. 16, the first embodiment can have an press-in depth of about 0.03 μm when a load of 1 mN is applied, the second embodiment can have an press-in depth of about 0.06 μm when a load of 1 mN is applied, and the third embodiment can have an press-in depth of about 0.08 μm when a load of 1 mN is applied. In one embodiment, when the bump layer BUML includes the first embodiment, the second bump BUM2 has a smaller elastic deformation rate (i.e., a larger elastic modulus) than the second and third embodiments even when the same load is applied, and therefore the second bump BUM2 can deform more than the first bump BUM1 for the same pressure. As a result, the second bump BUM2 in contact with the second electrode EL2 deforms more than the first bump BUM1, and therefore the contact resistance between the light emitting element LD and the pixel circuit layer PCL (or the circuit board or substrate) can be reduced despite the difference in height (or step) between the first electrode EL1 and the second electrode EL2. This can strengthen the bonding force between the light emitting element LD and the substrate.

[0161] 17, materials forming the first and second bumps of a pixel according to an embodiment can be divided into Examples 1, 2, 3, and 4. Here, Examples 1, 2, and 3 may be the same as Examples 1, 2, and 3 described with reference to FIGS.

[0162] The fourth embodiment may correspond to a material forming the second bump BUM2. For example, the fourth embodiment may correspond to a negative photoresist material using cardo acrylate and epoxy as a binder. Specifically, the fourth embodiment may correspond to a black pixel defining layer (BPDL) and may correspond to a material that transmits different wavelengths depending on the initiator. Here, the fourth embodiment may transmit short wavelengths (e.g., about 350 nm).

[0163] When the first bump BUM1 includes the first embodiment, the press-fit depth can be shallower than when the second bump BUM2 includes the fourth embodiment even when the same load is applied. For example, when a load of 2 mN or less is applied to the first bump BUM1 and the second bump BUM2, it can be seen that the press-fit depth of the first embodiment (first bump BUM1) is shallower than that of the fourth embodiment (second bump BUM2). Thus, in one embodiment, when the bump layer BUML includes the first embodiment, it has a smaller elastic deformation rate than the fourth embodiment even when the same load is applied (i.e., it has a larger elastic modulus), so the second bump BUM2 can have a larger deformation amount for the same pressure than the first bump BUM1. As a result, the second bump BUM2 in contact with the second electrode EL2 deforms more than the first bump BUM1, so it is possible to reduce the contact resistance between the light emitting element LD and the pixel circuit layer PCL (or circuit board, substrate) despite the difference in height (or step) between the first electrode EL1 and the second electrode EL2. This makes it possible to strengthen the bonding force between the light emitting element LD and the substrate.

[0164] A method for manufacturing a display device according to one embodiment will be described below with reference to FIGS.

[0165] 18 to 20 are cross-sectional views sequentially showing a part of a method for manufacturing a display device according to one embodiment.

[0166] Referring to FIG. 18, a display device according to one embodiment may include a pixel in which a pixel circuit layer PCL including a transistor TR is formed on a substrate SUB, and first to fourth connecting electrodes CNE1, CNE2, CNE3, CNE4, a first bump BUM1, a second bump BUM2, a fourth via layer VIA4 (or via layer), and a fourth insulating layer INS4 are provided on the pixel circuit layer PCL.

[0167] The first bump BUM1 may be provided on the first connecting electrode CNE1, and the third connecting electrode CNE3 may be provided to cover the first bump BUM1 and at least partially overlap the first connecting electrode CNE1.

[0168] The second bump BUM2 may be provided on the second connecting electrode CNE2, and the fourth connecting electrode CNE4 may be provided to cover the second bump BUM2 and at least partially overlap the fourth connecting electrode CNE4.

[0169] The first bump BUM1 and the second bump BUM2 may include materials with different elastic moduli. For example, the elastic modulus of the first bump BUM1 may be greater than the elastic modulus of the second bump BUM2. In this case, the height hh1 of the first bump BUM1 may be the same as or similar to the height hh2 of the second bump BUM2, and the diameter dd1 of the first bump BUM1 may be the same as or similar to the diameter dd2 of the second bump BUM2. That is, before bonding the light emitting element LD on the substrate SUB, the sizes and / or shapes of the first bump BUM1 and the second bump BUM2 may be the same as or similar to each other.

[0170] In one embodiment, the first bump BUM1 and the second bump BUM2 may include an organic material or a metallic material. The details regarding the materials constituting the first bump BUM1 and the second bump BUM2 are the same as those described in detail above with reference to FIGS. 7 to 17, and therefore will not be repeated below.

[0171] In one embodiment, the second bump BUM2 and the fourth via layer VIA4 may include the same material. For example, the second bump BUM2 and the fourth via layer VIA4 may include a negative photoresist material. Here, the second bump BUM2 and the fourth via layer VIA4 may include the same material and be manufactured using the same process. This may reduce the time and cost required to manufacture the display device in one embodiment.

[0172] Referring to FIG. 19, a display device according to an embodiment may have a light emitting element LD including a first electrode EL1 and a second electrode EL2 disposed on a substrate SUB.

[0173] The light emitting element LD may be disposed such that the first electrode EL1 faces the first bump BUM1 and the third linking electrode CNE3, and the second electrode EL2 faces the second bump BUM2 and the fourth linking electrode CNE4, based on the third direction DR3.

[0174] 20, in the display device according to an embodiment, a predetermined standard (or predetermined) pressure is applied in the third direction DR3 to couple the light emitting element LD and the substrate SUB, thereby allowing the first electrode EL1 to directly contact the third connecting electrode CNE3 and the second electrode EL2 to directly contact the fourth connecting electrode CNE4.

[0175] Because the first bump BUM1 has a larger elastic modulus than the second bump BUM2, the second bump BUM2 can deform more than the first bump BUM1. As a result, the second bump BUM2 overlapping the second electrode EL2 deforms more than the first bump BUM1, allowing the light emitting element LD to be stably coupled to the substrate SUB despite the difference in height (or step) between the first electrode EL1 and the second electrode EL2. In this case, the height hh1 of the first bump BUM1 may be larger than the height hh2 of the second bump BUM2, and the diameter dd1 of the first bump BUM1 may be smaller than the diameter dd2 of the second bump BUM2. In other words, the size and / or shape of the first bump BUM1 and the second bump BUM2 may be deformed after the light emitting element LD is coupled to the substrate SUB.

[0176] Thereafter, an insulating film FIL including an insulating material may be formed between the light emitting device LD and the third and fourth connecting electrodes CNE3 and CNE4. The insulating film FIL may be positioned between the light emitting device LD and the third connecting electrode CNE3 to couple the light emitting device LD to a circuit board, and may be positioned between the light emitting device LD and the fourth connecting electrode CNE4 to couple the light emitting device LD to a circuit board.

[0177] Although the present invention has been described above with reference to preferred embodiments, it will be understood that those skilled in the art or those with ordinary knowledge in the art can make various modifications and changes to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below.

[0178] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims

1. A substrate; a pixel circuit layer located on the substrate; a first connecting electrode and a second connecting electrode located on the pixel circuit layer; a first bump located on the first connecting electrode and a second bump located on the second connecting electrode; a light emitting device including a first electrode electrically connected to the first connecting electrode and a second electrode electrically connected to the second connecting electrode, The display device, wherein the first bump and the second bump include materials having different elastic moduli.

2. The display device according to claim 1 , wherein the elastic modulus of the first bump is greater than the elastic modulus of the second bump.

3. The display device of claim 2 , wherein the first bump and the second bump include an organic material or a metallic material.

4. The first bump includes a positive photoresist material; 2. The display device of claim 1, wherein the second bump comprises a negative photoresist material.

5. The height of the second bump is lower than the height of the first bump, 2. The display device according to claim 1, wherein the diameter of the second bump is larger than the diameter of the first bump.

6. The light-emitting element is a semiconductor structure that emits light and includes a surface having a different height; a first electrode located on one side of the semiconductor structure; 2. The display device of claim 1, further comprising: a second electrode located on one surface of the semiconductor structure and different from the first electrode.

7. The first electrode is located at a low height on one surface of the semiconductor structure, The display device according to claim 6 , wherein the second electrode is located at a high portion on one surface of the semiconductor structure.

8. The semiconductor structure comprises: A first semiconductor layer; an active layer disposed on one side of the first semiconductor layer; The display device of claim 7 , further comprising: a second semiconductor layer disposed on one side of the active layer and having a type different from that of the first semiconductor layer.

9. The pixel circuit layer includes: a transistor located on the substrate and a plurality of via layers located on the transistor; the transistor includes a semiconductor pattern, a first source electrode, a first drain electrode, and a gate electrode; 2. The display device of claim 1, wherein a first drain electrode of the transistor is electrically connected to the first connecting electrode through contact holes of the plurality of via layers.

10. a third connecting electrode covering the first bump and at least partially overlapping the first connecting electrode; The display device of claim 9 , further comprising a fourth connecting electrode covering the second bump and at least partially overlapping the second connecting electrode.

11. The display device of claim 10 , further comprising an insulating film disposed between the light emitting device and the third and fourth connecting electrodes.

12. A substrate; a pixel circuit layer located on the substrate; a via layer located on the pixel circuit layer; a first connecting electrode and a second connecting electrode located on the pixel circuit layer; a first bump located on the first connecting electrode and a second bump located on the second connecting electrode; a light emitting device including a first electrode electrically connected to the first connecting electrode and a second electrode electrically connected to the second connecting electrode, The display device, wherein the first bump and the second bump include materials having different elastic moduli, and the second bump and the via layer include the same material.

13. The display device according to claim 12 , wherein the elastic modulus of the first bump is greater than the elastic modulus of the second bump.

14. The display device of claim 13 , wherein the via layer, the first bump, and the second bump include an organic material.

15. The height of the second bump is lower than the height of the first bump, The display device according to claim 12 , wherein the diameter of the second bump is larger than the diameter of the first bump.

16. The light-emitting element is a semiconductor structure that emits light and includes a surface having a different height; a first electrode located on one side of the semiconductor structure; 13. The display device of claim 12, further comprising: a second electrode located on one surface of the semiconductor structure and different from the first electrode.

17. The first electrode is located at a low height on one surface of the semiconductor structure, The display device of claim 16, wherein the second electrode is located at a high portion on one surface of the semiconductor structure.

18. Providing a pixel circuit layer including a transistor on a substrate, a first connecting electrode, a second connecting electrode, a first bump, a second bump and a via layer on the pixel circuit layer; disposing a light emitting element including a first electrode and a second electrode on the substrate; bonding the light emitting element to the substrate such that a first electrode of the light emitting element overlaps the first bump and a second electrode of the light emitting element overlaps the second bump; A method for manufacturing a display device, wherein the first bump and the second bump include materials having different elastic moduli.

19. 20. The method of claim 18, wherein the height of the first bumps and the height of the second bumps are the same before the light emitting device and the substrate are bonded together.

20. 20. The method of claim 19, wherein the height of the first bump is greater than the height of the second bump after the light emitting device and the substrate are bonded together.

21. a plurality of display devices and a seam disposed between the plurality of display devices; A first display device among the plurality of display devices is A substrate; a pixel circuit layer located on the substrate; a first connecting electrode and a second connecting electrode located on the pixel circuit layer; a first bump located on the first connecting electrode and a second bump located on the second connecting electrode; a light emitting device including a first electrode electrically connected to the first connecting electrode and a second electrode electrically connected to the second connecting electrode, The first bump and the second bump include materials having different elastic moduli.

22. The tiled display device according to claim 21, wherein each of the light emitting elements is a flip-chip type micro light emitting diode element.

23. The tile-type display device according to claim 21 , wherein the substrate is made of glass.

24. The first display device is a pad disposed on a first surface of the substrate; 22. The tiled display device of claim 21, further comprising side wiring disposed on a first surface of the substrate, a second surface opposite to the first surface, and one side surface between the first surface and the second surface, and connected to the pad.

25. The first display device is a connecting wire disposed on a second surface of the substrate; a flexible film connected to the connecting wire via a conductive adhesive member, The tiled display device of claim 24, wherein the side wiring is connected to the connecting wiring.

26. The tiled display device of claim 21, wherein the plurality of display devices are arranged in a matrix shape with M rows and N columns.

27. The tiled display device of claim 21 , wherein the elastic modulus of the first bumps is greater than the elastic modulus of the second bumps.

28. The display device of claim 27, wherein the first bump and the second bump include an organic material or a metallic material.

29. The first bump includes a positive photoresist material; The tiled display device of claim 21, wherein the second bumps include a negative photoresist material.

30. The height of the second bump is lower than the height of the first bump, The tiled display device of claim 21 , wherein the diameter of the second bump is larger than the diameter of the first bump.

31. The light-emitting element is a semiconductor structure that emits light and includes a surface having a different height; a first electrode located on one side of the semiconductor structure; 22. The display device of claim 21, further comprising: a second electrode located on one surface of the semiconductor structure and different from the first electrode.

32. The first electrode is located at a low height on one surface of the semiconductor structure, The device of claim 31, wherein the second electrode is located at a high portion on one surface of the semiconductor structure.

33. The semiconductor structure comprises: A first semiconductor layer; an active layer disposed on one side of the first semiconductor layer; The tiled display device of claim 32 , further comprising: a second semiconductor layer disposed on one side of the active layer and having a type different from that of the first semiconductor layer.

34. The pixel circuit layer includes: a transistor located on the substrate, the transistor including a semiconductor pattern, a first source electrode, a first drain electrode, and a gate electrode; a plurality of via layers located over the transistor; The device of claim 21, wherein a first drain electrode of the transistor is electrically connected to the first connecting electrode through a contact hole of the plurality of via layers.

35. a third connecting electrode covering the first bump and at least partially overlapping the first connecting electrode; The device of claim 34, further comprising a fourth connecting electrode covering the second bump and at least partially overlapping the second connecting electrode.

36. The tiled display device of claim 35, further comprising an insulating film disposed between the light emitting device and the third and fourth connecting electrodes.

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