Atomicity maintenance method, processor and electronic device

Abstract

The present application provides a method, a processor, and an electronic device for maintaining atomicity, the method including the steps of: generating N access store operations, where N is a positive integer greater than or equal to 1, according to a vector access store instruction; checking whether an event exists during processing of the N access store operations that causes the vector access store instruction to not be atomic; processing the N access store operations; and if the event exists, processing any of the N access store operations does not produce any processing effect, or the N access store operations produce all processing effects. The present application can achieve the maintenance of atomicity of vector instructions.

Description

[Technical field]

[0001] The present application relates to the field of computer technology, and in particular to a method for maintaining atomicity, a processor, and an electronic device. [Background technology]

[0002] The atomicity of an instruction refers to the property that the process from the start of execution to the end of execution is not interrupted. For example, if instruction A has atomicity, once the execution of instruction A begins, it is not affected by events such as interrupt events or exception events, and the execution of instruction A is not paused until the execution of instruction A is completed.

[0003] During the execution of an instruction, it is often the case that the execution of the instruction is temporarily suspended due to the influence of events such as interrupt events and exception events. For example, if instruction B is taken as an example, if instruction B does not have atomicity, when the CPU detects an interrupt event while executing instruction B, it will temporarily suspend the execution of instruction B, give priority to the execution of the interrupt event, and resume the execution of instruction B when the execution of the interrupt event is completed. The atomicity of the instruction can no longer be maintained due to the influence of interrupt events, exception events, etc.

[0004] In the prior art, in the processing of any one vector instruction, there are multiple identical or similar operations in a single instruction inside the processor, but from the software developer's point of view, a single vector instruction is the smallest operation unit of the CPU, that is, a single vector instruction should have atomicity. Therefore, the processor design needs to ensure the atomicity of the execution of vector instructions.

[0005] In practical applications, multiple operations obtained by a processor dividing a vector instruction are executed in parallel at the same time, and the parallel execution mechanism designed to improve the execution efficiency of instructions brings challenges to maintaining the atomicity of vector instructions. In addition, the instruction system further includes a barrier instruction, which is used to isolate the access memory operations before and after the barrier instruction. Meanwhile, inside the processor, multiple operations obtained by dividing the barrier instruction from other vector instructions are also executed in parallel at the same time. The above various factors bring further difficulties to ensuring the atomicity of vector instructions. Summary of the Invention [Problem to be solved by the invention]

[0006] The present application provides an atomicity maintaining method, a processor, and an electronic device to solve a problem in the prior art in which the atomicity of a vector instruction cannot be ensured due to a mechanism for parallel execution of multiple operations after a vector instruction is divided, and a mechanism for parallel execution of a barrier instruction and a vector instruction. [Means for solving the problem]

[0007] In order to solve the above problems, the present application discloses a method for maintaining atomicity, the method comprising: Dividing the vector access store instruction into N access store operations, N being a positive integer greater than or equal to 1; determining whether an event exists during processing of the N access store operations that causes the vector access store instruction to be non-atomic; If the event exists, then either none of the N access storage operations produces any processing effect, or the N access storage operations produce all of the processing effects.

[0008] In order to solve the above problem, the present application further discloses a processor, the processor comprising: a decoding unit adapted to receive a vector access store instruction and generate N access store operations according to the vector access store instruction, N being a positive integer greater than or equal to 1; determining whether an event exists during processing of the N access store operations that causes the vector access store instruction to be non-atomic, and if the event exists, a processing unit is used whereby either none of the N access store operations produces any processing effect or all of the N access store operations produce all of the processing effects.

[0009] To solve the above problems, the present application further discloses an electronic device, the electronic device including a memory and one or more programs, the one or more programs being stored in the memory and configured to process one or more atomicity maintaining methods of the present application by one or more processors. Effect of the Invention

[0010] The present invention has the following advantages over the conventional techniques:

[0011] The atomicity maintaining method, processor, and electronic device provided by the embodiments of the present application generate N access store operations according to a vector access store instruction, and check whether an event exists during the processing of the N access store operations that causes the vector access store instruction to not be atomic, and if an event exists, the processing of any of the N access store operations does not produce any processing effect, or the N access store operations produce all processing effects, thereby realizing the maintenance of the atomicity of the vector instruction. [Brief description of the drawings]

[0012] [Figure 1] 1 is a step flowchart of an atomicity maintaining method according to a first embodiment of the present application; [Diagram 2]1 is a step flowchart of an atomicity maintaining method according to Example 2 of the present application. [Diagram 3] 11 is a step flowchart of an atomicity maintaining method according to Example 3 of the present application. [Figure 4] 11 is a step flowchart of an atomicity maintaining method according to Example 4 of the present application. [Diagram 5] 11 is a step flowchart of an atomicity maintaining method according to Example 5 of the present application. [Figure 6-A] FIG. 11 is a structural block diagram of one processor according to a fifth embodiment of the present invention. [Figure 6-B] FIG. 11 is a structural block diagram of another processor according to a fifth embodiment of the present invention. [Figure 7] FIG. 13 is a structural block diagram of an electronic device according to a sixth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In order to make the above objects, features and advantages of the present application more clear and understandable, the present application will be described in more detail below with reference to the drawings and specific embodiments.

[0014] Example 1 Referring to FIG. 1, FIG. 1 shows a step flow chart of one atomicity maintaining method according to the first embodiment of the present application.

[0015] The method for maintaining atomicity provided by the embodiment of the present application may be executed by a CPU (Central Processing Unit), and includes the following steps.

[0016] In step 101, generate N access store operations according to a vector access store instruction, where N is a positive integer equal to or greater than 1.

[0017] The embodiments of the present application can be applied to a scene in which, during processing of a vector access store operation instruction, it is confirmed whether an event exists that causes the vector access store instruction to not be atomic, and according to the confirmation result, it is determined whether to execute the vector access store instruction, or the execution result of the vector access store instruction is submitted to realize the atomicity of the instruction.

[0018] The vector access store instruction can simultaneously realize the same processing on a set of data. In practical applications, after receiving the vector access store instruction, the vector access store instruction can be decoded and divided into N access store operations, where N is a positive integer greater than or equal to 1.

[0019] In this example, the vector access storage instruction may be a Load instruction or a Store instruction.

[0020] After generating the N access store operations according to the vector access store instruction, step 102 is performed.

[0021] Step 102 determines whether there is an event during processing of the N access store operations that causes the vector access store instruction to be non-atomic.

[0022] In the prior art, the pipeline of vector access store instruction processing includes the following steps: 1. instruction acquisition and decoding step, i.e., acquiring a vector access store instruction and decoding the vector access store instruction; 2. dispatch step, i.e., sending the instruction in the operation queue to the reserve station according to the operation type, and reading the register values ​​and result status fields during dispatch; and 3. execution step, when all the required operands are ready, Order Step 4: Execute; Step 5: Write back. That is,4. A step of transmitting the execution result to a result bus and releasing the reserve station; and 5. a step of submitting, i.e., a step of writing back the execution result of the instruction to a register or memory if the instruction execution result in the queue has been written back and no exception has occurred.

[0023] Based on this, in the embodiments of the present application, processing a vector access store instruction means performing any one or a combination of operations of instruction fetch, decode, dispatch, execution, writeback, and submission on the vector access store instruction, and processing an access store operation includes performing any one or a combination of operations of dispatch, execution, and submission on the access store operation.

[0024] The events referred to in this example refer to events that cause the vector access store instruction to be non-atomic, and in this example the events may include at least one of an interrupt event, an exception event, the detection of a barrier instruction, etc.

[0025] An interrupt event (also called an external interrupt) is an event that occurs outside the CPU execution instructions.

[0026] An exception event refers to an event that occurs within the CPU execution instructions.

[0027] A barrier instruction is an instruction for ensuring synchronization between different operations. For example, a barrier instruction can complete the synchronization function between load / store access memory operations and specify the synchronization target and degree of synchronization of the load / store access memory operations.

[0028] The atomicity of a vector access store instruction refers to the property that one vector access store instruction is not interrupted from the start of execution to the end of execution and submission completion.

[0029] Thus, in this example, after splitting the vector access store instruction into N access store operations, during the processing of the N access store operations, the N access store operations can be checked, i.e., whether there is an event that causes the vector access store instruction to be non-atomic during the processing of the N access store operations. Optionally, processing the access store operations can include issuing, executing, and submission In the case where the vector access store instruction includes performing any one of the operations or a combination of a plurality of operations, a check is performed for the N access store operations for an event that causes the vector access store instruction to be non-atomic, i.e., the N access store operations are checked in the process of issuing the N access store operations, or the N access store operations are checked in the process of executing the N access store operations, or the N access store operations are checked in the process of submitting the N access store operations. Specifically, the stage at which the N access store operations are checked is determined according to the type of the event that causes the vector access store instruction to be non-atomic (i.e., an interrupt event, an exception event, a barrier instruction, etc.).

[0030] Step 103 is executed after determining whether there is an event that causes the vector access store instruction to be non-atomic during the processing of the N access store operations.

[0031] In step 103, if the event exists, then either none of the N access storage operations produces any processing effect, or all of the N access storage operations produce all processing effects.

[0032] In the embodiment of the present application, an access store operation having no processing effect refers to either an access store operation being executed but not yet submitted, or an access store operation not being executed, or an access store operation not being submitted, while an access store operation having all processing effects refers to all N access store operations obtained by dividing a vector access store instruction being executed, and all execution results of the N access store operations being submitted.

[0033] In the embodiment of the present application, when there is no event that makes the vector access store instruction non-atomic, N access store operations can be executed according to the processing order of the above instruction pipeline to submit the execution results of the N access store operations, specifically, when the vector access store instruction is a Load instruction, an operation can be executed to read the operand at the address designated by the vector access store instruction from the memory to the designated general-purpose register, while when the vector access store instruction is a Store instruction, an operation can be executed to write the operand at the address designated by the vector access store instruction from the designated general-purpose register to the memory.

[0034] In the embodiment of the present application, when it is confirmed that an event exists during the processing of the N access store operations that makes the vector access store instruction not atomic, the vector access store instruction is not processed, i.e., the current processing of the vector access store instruction may be discarded, or the execution result of the vector access store instruction may not be submitted and the vector access store instruction may be executed. Specifically, first, when it is confirmed that the interrupt flag is marked on the N access store operations, it indicates that an interrupt event exists during the processing of the N access store operations, in this case, the current execution of the vector access store instruction is discarded, i.e., all of the N access store operations are not executed or the N access store operations are not sent. Second, when an exception event exists during the processing of the N access store operations, the vector access store instruction is executed but the execution result is not submitted. Third, for the barrier instruction, the barrier instruction may be executed first, and all of the access store operations are not executed or not sent, and when the processing of the barrier instruction is completed, the access store operation is executed and the execution result is submitted. This process will be described in detail from three dimensions, namely, interrupt events, exception events, and barrier instructions, with reference to Examples 2, 3, and 4, respectively, so a detailed description of this embodiment will be omitted here.

[0035] In addition, in the embodiment of the present application, when it is confirmed that an event that makes the vector access store instruction not atomic exists during the processing of the N access store operations, all the vector access store instructions are executed, the execution results of the vector access store instructions are submitted, and the above event that makes the vector access store instruction not atomic is processed. Specifically, first, when it is confirmed that the interrupt flag is marked in the N access store operations, it indicates that an interrupt event exists during the processing of the N access store operations, in this case, the N access store operations are sent and executed, and then the execution results of the N access store operations are submitted, and when all the execution results are submitted, the interrupt event is responded to. Secondly, for the barrier instruction, first, all the access store operations are sent and executed, and when the execution results of all the access store operations are submitted, the barrier instruction may be processed. Since the exception event is an event inside the processing pending instruction, when an exception event is encountered during the processing of an instruction, all the execution of the instruction is stopped. result The submission of the interrupt event command does not occur. The process will be described in detail from two dimensions, namely, the interrupt event command and the barrier command, with reference to the second, third and fourth embodiments, and therefore the detailed description of the process will be omitted here.

[0036] The method for maintaining atomicity provided by the embodiment of the present application generates N access store operations according to a vector access store instruction, and checks whether there is an event that causes the vector access store instruction to be non-atomic during the processing of the N access store operations. If there is an event that causes the vector access store instruction to be non-atomic, the processing of any of the N access store operations will not produce any processing effect, or the N access store operations will produce all processing effects, thereby realizing the maintenance of the atomicity of the vector instruction. By adopting the above technical solution, the processing of the vector instruction in the prior art can be realized. Multiple operationsWhen an event is encountered that causes the vector access store instruction to not be atomic for the parallel execution mechanism or the simultaneous parallel execution mechanism of multiple operations obtained by dividing a barrier instruction from other vector instructions, by not executing all the access store operations and not submitting all the execution results of the access store operations, or by submitting all the execution results of the access store operations, a phenomenon does not occur in which part of the access store operations obtained by dividing the vector access store instruction has an execution effect while the other part of the access store operation has no execution effect, and the atomicity of the vector instruction is reliably ensured.

[0037] Example 2 Referring to FIG. 2, FIG. 2 shows a step flow chart of one atomicity maintaining method according to the second embodiment of the present application.

[0038] The method for maintaining atomicity provided by an embodiment of the present application may be executed by a CPU, and is based on the fact that an event that causes a vector access store instruction to not be atomic is an interrupt event, and the method for maintaining atomicity includes the following steps:

[0039] In step 201, generate N access store operations according to a vector access store instruction, where N is a positive integer equal to or greater than 1.

[0040] In the embodiment of the present application, the vector access store instruction can simultaneously realize the same processing on a set of data. In practical application, after receiving the vector access store instruction, the vector access store instruction can be divided into N access store operations, where N is a positive integer greater than or equal to 1.

[0041] In this example, the vector access storage instruction may be a Load instruction or a Store instruction.

[0042] After generating the N access store operations according to the vector access store instruction, step 202 is performed.

[0043] In step 202, upon determining that an event exists during the processing of the N access store operations that causes the vector access store instruction to be non-atomic and that the event is an interrupt event, a corresponding flag may be added to the N access store operations to indicate that an interrupt event exists during the processing of the N access store operations.

[0044] In an embodiment of the present application, the step of checking whether an interrupt event exists during the processing of the N access storage operations may be performed during the submission phase of the N access storage operations or during the execution phase of the N access storage operations.

[0045] In one particular implementation of the present application, a method for marking an interruption graph may include step A1.

[0046] In step A1, during the processing of the vector access store instruction, an interrupt event In response to the occurrence of an interrupt flag is added to one or more of the N access storage operations.

[0047] In actual application, the number of vector access store instructions is huge. Once one vector access store instruction is obtained, the vector access store instruction will be added to the cache for dispatch and execution. During the processing of the vector access store instruction, an interrupt event check is performed for the vector access store instruction, and during the processing of the vector access store instruction, it can be checked whether an interrupt event exists that makes the vector access store instruction non-atomic. In specific implementation, since the interrupt event is an external event, during the processing of the vector access store instruction, the CPU can check in real time whether an interrupt request is received, and determine whether an interrupt event exists during the processing of the vector access store instruction according to the checking result. That is, when the CPU receives an interrupt request, it determines the checking result that an interrupt event exists during the processing of the vector access store instruction.

[0048] Of course, other methods may be used to check whether an interrupt event exists during processing of a vector access store instruction that would cause the vector access store instruction to be non-atomic. Specifically, the method of checking for an interrupt event may be determined according to business needs, and this embodiment is not limited thereto.

[0049] In the present embodiment, the interrupt flag indicates the presence of an interrupt event during the processing of the N access storage operations. It can be used for Specifically, the display form of the interrupt flag may be determined according to business needs, and this embodiment is not limited thereto.

[0050] Furthermore, if during the processing of the N access store operations, an event exists that causes the vector access store instruction to be non-atomic, and it is determined that the event is an interrupt event, an interrupt flag can be added to the access store operations.

[0051] In concrete terms, there are two cases where an interrupt flag is added to an access memory operation:

[0052] 1. A scene where an interrupt flag is added to any one of N access store operations. Specifically, an interrupt flag may be added to the first access store operation, an interrupt flag may be added to the last access store operation, or an interrupt flag may be added to any one of the access store operations between the first access store operation and the last access store operation (it should be understood that the above descriptions of first and last are limited according to the execution order of the N access store operations). For example, a vector access store instruction can be divided into five access store operations, and when these five access store operations are rearranged in order of their execution order, the order is access store operation 1, access store operation 2, access store operation 3, access store operation 4, and access store operation 5. When an interrupt flag is added, an interrupt flag may be added to the first access store operation (i.e., access store operation 1), or to the last access store operation (i.e., access store operation 5). interrupt A flag may be added, or an interrupt flag may be added to the access storage operations that are between the first access storage operation and the last access storage operation (ie, access storage operation 2 or access storage operation 3 or access storage operation 4).

[0053] It is preferable to add an interrupt flag to the first access store operation of the N access store operations.

[0054] The above examples are merely examples for better understanding of the technical solutions according to the embodiments of the present application. Limited It should be understood that this does not define the

[0055] 2. A situation in which an interrupt flag is added to all access store operations of the N access store operations, i.e., an interrupt flag is added to each of the N access store operations. For example, continuing the above example, after dividing the vector access store instruction into five access store operations, an interrupt flag may be added to each of these five access store operations, i.e., an interrupt flag may be added to each of access store operation 1, access store operation 2, access store operation 3, access store operation 4, and access store operation 5.

[0056] In the embodiment of the present application, by adding an interrupt flag to the N access store operations to indicate an interrupt event, during subsequent processing of the vector access store instruction, the interrupt flag can intuitively determine whether the vector access store instruction has atomicity and determine how to process the vector access store instruction.

[0057] In step 203, it is determined whether an interrupt flag exists in the N access storage operations.

[0058] In an embodiment of the present application, the above method can be used to add an interrupt flag to N access storage operations, and then sequentially check whether the interrupt flag is marked on the N access storage operations to determine whether an interrupt event exists during the processing of the N access storage operations.

[0059] After adding an interrupt flag to the N access storage operations, the method of checking the interrupt flag can be divided into the following two types:

[0060] First, it checks sequentially whether the N access storage operations have the interrupt flag marked or not.

[0061] Second, it is checked whether the first access store operation of the N access store operations has an interrupt flag marked.

[0062] After checking that the interrupt flag exists for the N access storage operations, step 204 is executed.

[0063] After confirming that the interrupt flag is not marked in any of the N access storage operations, step 205 is executed.

[0064] In step 204, if the interrupt flag is present, then either none of the N access store operations produces any processing effect or all of the N access store operations produce all processing effects.

[0065] After confirming that the N access storage operations are marked with interrupt flags, either any of the N access storage operations does not produce any processing effect, or the N access storage operations produce all processing effects, which can be specifically described with reference to the following four situations:

[0066] In the first type of situation, when it is confirmed that an interrupt flag is marked in any of the N access storage operations, none of the N access storage operations is sent or executed, and in this case, none of the N access storage operations produces any execution processing effect, i.e., when the response to the interrupt event is terminated, the sending or execution of the N access storage operations and the submission of the execution results of the N access storage operations are resumed.

[0067] Alternatively, if it is confirmed during the transmission stage of the N access storage operations that an interrupt flag is marked in any of the N access storage operations, none of the N access storage operations is transmitted, or N access storage operations are transmitted but none of the N access storage operations is executed, but if it is confirmed during the execution stage of the N access storage operations that an interrupt flag is marked in any of the N access storage operations, none of the execution results of any of the N access storage operations is submitted.

[0068] In the second situation, when it is confirmed that an interrupt flag is marked in any of the N access storage operations, each of the N access storage operations is Call and submitting all the execution results of the N access storage operations, that is, responding to the interrupt event after all the N access storage operations have been completed and the corresponding execution results have been submitted.

[0069] In a third situation, when it is confirmed that the first access storage operation among the N access storage operations has an interrupt flag marked, none of the N access storage operations is sent or executed, and in this case, none of the N access storage operations produces any processing effect, i.e., when the response to the interrupt event is terminated, the sending or execution of the N access storage operations and the submission of the execution results of the N access storage operations are resumed.

[0070] Alternatively, when it is confirmed during the transmission stage of the N access storage operations that the first access storage operation among the N access storage operations has an interrupt flag marked, none of the access storage operations among the N access storage operations is transmitted, or N access storage operations are transmitted but none of the access storage operations among the N access storage operations is executed, and when it is confirmed during the execution stage of the N access storage operations that the first access storage operation among the N access storage operations has an interrupt flag marked, none of the execution results of any of the N access storage operations is submitted.

[0071] In a fourth situation, when it is determined that the first access storage operation among the N access storage operations has an interrupt flag marked, each access storage operation of the N access storage operations is executed, and all the execution results of the N access storage operations are submitted, that is, after all the N access storage operations have been executed and the corresponding execution results have been submitted, the interrupt event is responded to.

[0072] In step 205, if the interrupt flag is not marked for any of the N access store operations, execute the N access store operations and submit the execution results of the N access store operations.

[0073] If it is confirmed that the interrupt flag is not marked in any of the N access storage operations, the N access storage operations can be executed to obtain the execution results of the N access storage operations, and further the execution results of the N access storage operations can be submitted.

[0074] The atomicity maintaining method provided by the embodiment of the present application generates N access store operations according to a vector access store instruction, and checks whether the N access store operations are marked with an interrupt flag. If the interrupt flag is checked, the processing of any of the N access store operations will not produce any processing effect, or the N access store operations will produce all processing effects. By adopting the technical solution of the present application, when an interrupt event occurs during the processing of the vector access store operation, the interrupt event will be responded to after the vector access store instruction is all processed, or the vector access store instruction will be processed after the response to the interrupt event is finished, so that the vector access store instruction will not be affected by the interrupt event and only a part of the execution result of the access store operation will be submitted, and the atomicity of the vector instruction can be maintained.

[0075] Example 3 Referring to FIG. 3, FIG. 3 shows a step flowchart of a method for maintaining atomicity according to a third embodiment of the present application.

[0076] The method for maintaining atomicity provided by an embodiment of the present application may be executed by a CPU, and is based on the fact that an event that causes a vector access store instruction to not be atomic is an exception event, and the method for maintaining atomicity includes the following steps:

[0077] In step 301, generate N access store operations according to a vector access store instruction, where N is a positive integer equal to or greater than 1.

[0078] In the embodiment of the present application, the vector access store instruction can simultaneously realize the same processing on a set of data. In practical application, after receiving the vector access store instruction, the vector access store instruction can be divided into N access store operations, where N is a positive integer greater than or equal to 1.

[0079] In this example, the vector access storage instruction may be a Load instruction or a Store instruction.

[0080] After generating the N access store operations according to the vector access store instruction, step 302 is performed.

[0081] In step 302, it is confirmed whether or not there is any access storage operation that generates an exception event during processing among the N access storage operations, and a confirmation result is obtained.

[0082] After generating the N access store operations according to the vector access store instruction, check whether there is any access store operation that generates an exception event during processing among the N access store operations, and obtain a checking result. The checking process of the exception event can be described in detail with reference to the following specific implementation.

[0083] In an embodiment of the present application, the step of checking whether an exception event exists during the processing of the N access storage operations may be performed during the execution phase of the N access storage operations.

[0084] In one particular implementation of the present application, the above step 302 includes: Substep S1 and Substep S2 may include.

[0085] In sub-step S1, an access storage address of each of the N access storage operations is obtained.

[0086] In the embodiment of the present application, after generating N access store operations according to the vector access store instruction, an access store address of each access store operation of the N access store operations can be obtained.

[0087] After obtaining the access storage address of each of the N access storage operations, sub-step S2 is performed.

[0088] In sub-step S2, it is determined whether or not a situation that satisfies an exception event trigger exists for each of the access storage addresses. If so, the N pcs It is determined as a confirmation result that there is an access storage operation that generates an exception event during processing among the access storage operations, and if not, it is determined as a confirmation result that there is no access storage operation that generates an exception event during processing among the N access storage operations.

[0089] After obtaining the access memory address of each of the N access memory operations, it is checked whether there exists a situation that satisfies the exception event trigger for each access memory address. If there exists, pcs It is determined as a confirmation result that there is any access storage operation that generates an exception event during processing among the access storage operations, but if not, it is determined as a confirmation result that there is no access storage operation that generates an exception event during processing among the N access storage operations.

[0090] The circumstances that satisfy the exception event trigger include at least one of the following circumstances:

[0091] 1. The permission of any access memory operation has an attribute permission violation, where the attribute permission violation includes a segment attribute permission violation and a page attribute permission violation, and the attribute permission mainly refers to read permission, write permission, execute permission, privilege level permission, etc., and the attribute permission violation is mainly used to indicate whether the operation of any access memory operation / vector access memory instruction is consistent with the permission corresponding to the address accessed by the access memory operation / vector access memory instruction, and if not consistent, it is determined that the permission of any access memory operation / vector access memory instruction has an attribute permission violation.

[0092] 2. The address translation table contains Any of the N access storage operations Any access storage address is not included.

[0093] 3. The access memory address of the vector access memory instruction is an out-of-bounds address.

[0094] In step 303, the N access storage operations are executed.

[0095] After generating the N access store operations according to the vector access store instruction, the N access store operations can be executed to obtain the execution result of the N access store operations.

[0096] In step 304, if the confirmation result indicates that there is an access storage operation among the N access storage operations that generates an exception event during processing, the execution result of any of the access storage operations among the N access storage operations is not submitted and the exception event is reported.

[0097] If the confirmation result of the exception event indicates that there is an access storage operation among the N access storage operations that generates an exception event during processing, the execution result of any of the N access storage operations is not submitted and the exception event is reported.

[0098] In step 305, if the checking result indicates that none of the N access storage operations generates an exception event during processing, submit the execution results of the N access storage operations.

[0099] If the confirmation result of the exception event indicates that none of the N access storage operations generates an exception event during processing, the execution result of the N access storage operations may be submitted.

[0100] The method for maintaining atomicity provided by the embodiment of the present application generates N access store operations according to a vector access store instruction, and checks whether there is any access store operation among the N access store operations that will generate an exception event during processing. If there is, the execution result of any of the access store operations among the N access store operations will not be submitted, and the exception event will be reported. By adopting the technical solution of the present application, when an exception event occurs during the processing of the vector access store operation, the exception event will be responded to, but the vector access store instruction will not produce any processing effect, so that the vector access store instruction will not be affected by the exception event and only a part of the processing result of the access store operation will be submitted, thereby realizing the maintenance of the atomicity of the vector instruction.

[0101] Example 4 Referring to FIG. 4, FIG. 4 shows a step flowchart of a method for maintaining atomicity according to a fourth embodiment of the present application.

[0102] The method for maintaining atomicity provided by an embodiment of the present application may be executed by a CPU, and is based on the fact that an event that causes a vector access store instruction to not be atomic is a barrier instruction event, and the method for maintaining atomicity includes the following steps:

[0103] In step 401, generate N access store operations according to a vector access store instruction, where N is a positive integer equal to or greater than 1.

[0104] In the embodiment of the present application, the vector access store instruction can simultaneously realize the same processing on a set of data. In practical application, after receiving the vector access store instruction, the vector access store instruction can be divided into N access store operations, where N is a positive integer greater than or equal to 1.

[0105] In this example, the vector access storage instruction may be a Load instruction or a Store instruction.

[0106] After generating the N access store operations according to the vector access store instruction, step 402 is performed.

[0107] Step 402 checks whether a barrier instruction exists during the processing of the N access storage operations.

[0108] After generating the N access store operations according to the vector access store instruction, it can be checked whether a barrier instruction exists during the processing of the N access store operations.

[0109] In an embodiment of the present application, the step of checking whether a barrier instruction that affects atomicity is present during processing of the N access storage operations may be performed at the dispatch phase or execution phase of the N access storage operations.

[0110] In step 403, in response to obtaining the barrier instruction, if it is determined that all of the N number of access storage operations being executed have been completed, processing the barrier instruction; or In step 404, in response to obtaining the vector access store instruction, if there is a barrier instruction that has not yet been processed, the N access store operations generated by the vector access store instruction are cached without being processed, and the N access store operations are processed after the barrier instruction that has not yet been processed is processed.

[0111] If it is determined that a barrier instruction exists during the processing of the N access storage operations, in response to the obtained barrier instruction, after determining that all the N access storage operations being executed have been executed and that all the execution results of the N access storage operations have been submitted, process the barrier instruction; or In response to obtaining the vector access store instruction, if there is a barrier instruction that has not yet been processed, the N access store operations generated by the vector access store instruction are cached without being dispatched or executed, and the N access store operations are executed after the barrier instruction that has not yet been processed is processed.

[0112] Here, the above steps 403 and 404 are parallel options after step 402 is executed, that is, after step 402 is executed, either step 403 or step 404 can be selected and executed, and step 403 and step 404 can be prevented from being executed simultaneously.

[0113] The method for maintaining atomicity provided by the embodiment of the present application is, after confirming that a barrier instruction is received, responsive to obtaining the barrier instruction, and processing the barrier instruction when it is confirmed that all of the N access memory operations being processed have been processed to completion; or, responsive to obtaining a vector access memory instruction, if there is an unprocessed barrier instruction, cache the N access memory operations generated by the vector access memory instruction without processing them, and process the N access memory operations after the unprocessed barrier instruction is processed to completion. By adopting the technical solution of the present application, first, process the barrier instruction, and process the N access memory operations after the barrier instruction is processed to completion, or first, process the N access memory operations, and process the barrier instruction after the N access memory operations are executed to completion and all execution results are submitted, the vector access memory instruction is not affected by the barrier instruction and only a part of the execution results of the access memory operations are submitted, thereby realizing the maintenance of the atomicity of the vector instruction.

[0114] Example 5 Referring to FIG. 5, FIG. 5 shows a step flowchart of a method for maintaining atomicity according to a fifth embodiment of the present application.

[0115] The embodiment of the present application provides another atomicity maintaining method that simultaneously covers three events that affect the atomicity of a vector access store instruction, as described in embodiment 2 to embodiment 4. On this basis, the atomicity maintaining method includes the following steps:

[0116] In step 501, generate N access store operations according to a vector access store instruction, where N is a positive integer equal to or greater than 1.

[0117] In the embodiment of the present application, the definition and decoding method of the vector access store instruction are consistent with those in the second to fourth embodiments, and therefore will not be repeated here.

[0118] In step 502, in the dispatch stage of the N access storage operations, it is checked whether an interrupt event exists during the processing of the N access storage operations, and if so, step 504 is executed, but if not, step 503 is executed. At the same time, in the dispatch stage of the N access storage operations, it is checked whether a barrier instruction exists during the processing of the N access storage operations, and if so, step 505 is executed, but if not, step 503 is executed.

[0119] In step 503, N access storage operations are sent, and during the execution stage of the N access storage operations, it is confirmed whether or not there is any access storage operation among the N access storage operations that generates an exception event during processing. If there is, step 506 is executed, but if not, step 507 is executed.

[0120] In step 504, none of the N access storage operations is processed and the interrupt event is responded to.

[0121] In an embodiment of the present application, not processing any of the N access storage operations includes not submitting any of the N access storage operations or not executing any of the N access storage operations.

[0122] Furthermore, after completing the response to the interrupt event, the N access storage operations are processed, and if none of the N access storage operations is issued, step 503 is executed after completing the response to the interrupt event, and if none of the N access storage operations is executed, after completing the response to the interrupt event, in the execution phase of the N access storage operations in step 503, a step is executed to check whether there is any access storage operation among the N access storage operations that generates an exception event during processing.

[0123] In step 505, the N access storage operations are cached without being processed, and after the barrier instructions that have not yet been processed are processed, the N access storage operations are processed.

[0124] In the embodiment of the present application, after the barrier instruction that has not yet been processed is processed, the N access storage operations are processed, i.e., after the barrier instruction that has not yet been processed is processed, step 503 is executed.

[0125] Furthermore, in steps 502 and 504, if an interrupt event / barrier command exists, step 503 may be executed first, and the execution results of the N access storage operations / exception event reports may be submitted before responding to the interrupt event / barrier command.

[0126] In step 506, the access storage operation of any one of the N access storage operations is Execution result Report an exception event without submitting a

[0127] In step 507, the N access storage operations are executed, and the execution results of the N access storage operations are submitted.

[0128] Example 6 Referring to FIG. 6, FIG. 6 shows a structural block diagram of a processor according to a sixth embodiment of the present application.

[0129] As shown in FIG. 6-A, the processor according to the embodiment of the present application includes: a decoding unit 61, which is used for obtaining a vector access store instruction and generating N access store operations according to the vector access store instruction, where N is a positive integer greater than or equal to 1; a processing unit 62 that is used to check whether an event exists during processing of the N access store operations that causes the vector access store instruction to be non-atomic, and if the event exists, either none of the N access store operations produces any processing effect, or all of the N access store operations produce all of the processing effects.

[0130] Specifically, the processing unit 62 is used for checking whether at least one of an interrupt event, an exception event, and a barrier instruction exists during the processing of the N access store operations, and, if so, determining that an event that causes the vector access store instruction to not be atomic exists during the processing of the N access store operations.

[0131] As shown in FIG. 6-B, the processor includes an instruction memory 63, and the vector access store instructions of the decode unit may come from the instruction memory.

[0132] Optionally, the processing unit 62 includes an originating unit 621 , an executing unit 622 , and a submitting unit 623 .

[0133] The signaling unit 621 is used for adding an interrupt flag to one or more of the N access store operations in response to an interrupt event occurring during processing of the vector access store instruction, before checking whether an event exists that causes the vector access store instruction to be non-atomic during processing of the N access store operations, the interrupt flag being for indicating that an interrupt event has occurred during processing of the vector access store instruction.

[0134] Optionally, the sending unit 621 is specifically used for adding the interrupt flag to any one of the access storage operations among the N access storage operations.

[0135] Optionally, the sending unit 621 is specifically used for adding the interrupt flag to all the access storage operations of the N access storage operations.

[0136] Optionally, the sending unit 621 is used for sequentially checking whether the N access storage operations have the interrupt flag marked or not, and if any of the access storage operations among the N access storage operations has the interrupt flag marked, not sending any of the access storage operations among the N access storage operations.

[0137] Optionally, the sending unit 621 is used for sequentially checking whether the N access storage operations are marked with the interrupt flag, and when determining that any of the N access storage operations is marked with the interrupt flag, sending the N access storage operations; The execution unit 622 is used to cache the N access store operations generated by the vector access store instruction, not execute any of the N access store operations, and execute the N access store operations after the interrupt event has been processed.

[0138] Optionally, the sending unit 621 is used for sequentially checking whether the N access storage operations are marked with the interrupt flag, and when determining that any of the N access storage operations is marked with the interrupt flag, sending the N access storage operations; The execution unit 622 is used to execute each access storage operation of the N access storage operations; The submit unit 623 is used for submitting the execution results of the N access storage operations; When the processor confirms that the execution results of the N access storage operations have been submitted, it processes the interrupt event.

[0139] Alternatively, the sending unit 621 checks whether a first access storage operation among the N access storage operations has the interrupt flag marked, and if the first access storage operation has the interrupt flag marked, does not send any of the N access storage operations.

[0140] Optionally, the sending unit 621 is used for checking whether the first access storage operation of the N access storage operations is marked with the interrupt flag, and when determining that the first access storage operation is marked with the interrupt flag, sending the N access storage operations; The execution unit 622 is used to cache the N access store operations generated by the vector access store instruction, not execute any of the N access store operations, and execute the N access store operations after the interrupt event has been processed.

[0141] Optionally, the sending unit 621 is used for checking whether the first access storage operation of the N access storage operations is marked with the interrupt flag, and when determining that the first access storage operation is marked with the interrupt flag, sending the N access storage operations; The execution unit 622 is used to execute each access storage operation of the N access storage operations; The submit unit 623 is used for submitting the execution results of the N access storage operations.

[0142] Alternatively, the sending unit 621 is used to send the N access storage operations when the interrupt flag is not marked in any of the N access storage operations; the execution unit 622 is used to execute the N access storage operations; The submit unit 623 is used for submitting the execution results of the N access storage operations.

[0143] Optionally, the sending unit 621 is used for determining whether there is any access storage operation that generates an exception event during processing among the N access storage operations, obtaining a determination result, and sending the N access storage operations; the execution unit 622 is used to execute the N access storage operations; When the confirmation result indicates that there is an access storage operation among the N access storage operations that generates an exception event during processing, the submission unit 623 is used to report the exception event without submitting the execution result of any of the access storage operations among the N access storage operations.

[0144] Optionally, the sending unit 621 is used to send the N access storage operations; The execution unit 622 is used for executing the N access storage operations, and checking whether there is any access storage operation that generates an exception event during processing among the N access storage operations, and obtaining a checking result; When the confirmation result indicates that there is an access storage operation among the N access storage operations that generates an exception event during processing, the submission unit 623 is used to submit all execution results of each access storage operation of the N access storage operations and report the exception event.

[0145] Optionally, the sending unit 621 may obtain an access storage address of each of the N access storage operations, and for each of the access storage addresses, check whether a situation that satisfies an exception event trigger exists; if so, send the N pcs is used to determine as a confirmation result that there is any access storage operation that generates an exception event during processing among the access storage operations, and if not, determine as a confirmation result that there is no access storage operation that generates an exception event during processing among the N access storage operations; Here, the situation that satisfies the exception event trigger is: Any of the above N The situation where the access storage operation permission has an attribute permission violation, The address translation table Any of the access storage operations among the N access storage operations Either No.A The access memory address is not included. the access store address of the vector access store instruction is an out-of-bounds address.

[0146] Optionally, the submission unit 623 If the checking result indicates that none of the N access storage operations generates an exception event during processing, the checking result is used to submit an execution result of the N access storage operations.

[0147] Alternatively, the processing unit 62 responds to the barrier command when it is determined that a barrier command has been received, and processes the barrier command when it is confirmed that all the N access storage operations being processed have been completed and submitted; or In response to obtaining the vector access store instruction, if there is a barrier instruction that has not yet been processed, the N access store operations generated by the vector access store instruction are cached without being executed, and are used to execute the N access store operations after the barrier instruction that has not yet been processed is processed.

[0148] Alternatively, the vector access store instruction is a Load instruction or a Store instruction, the processing unit further includes an execution unit, and the processor further includes a general purpose register 64; When the vector access store instruction is a Load instruction, the execution unit 622 is specifically used to execute the operation of reading the operand at the address indicated by the vector access store instruction from memory, and the submission unit 623 is used to read the operand into the designated general-purpose register 64; When the vector access store instruction is a store instruction, the execution unit 622 is specifically used to execute reading an operand at an address indicated in the vector access store instruction from a specified general-purpose register 64, and the submission unit is used to write the operand to memory.

[0149] The processor in the embodiments of the present application is used to realize the corresponding atomicity maintaining method in the above-mentioned method embodiments, and has beneficial effects according to the method embodiments, so it will not be described repeatedly here.

[0150] Example 7 Referring to FIG. 7, FIG. 7 shows a structural schematic diagram of an electronic device for maintaining atomicity according to a seventh embodiment of the present application.

[0151] As shown in FIG. 7, the electronic device may include one or more of a processing assembly 702, a memory 704, a power supply assembly 706, a multimedia assembly 708, an audio assembly 710, an input / output (I / O) interface 712, a sensor assembly 714, and a communication assembly 716.

[0152] The processing assembly 702 generally controls the overall operation of the electronic device, such as operations related to display, data communication, camera operation, and recording operations. assembly The processing assembly 702 may include one or more processors 720 for processing instructions to complete all or some of the steps of the methods described above. The processing assembly 702 may also include one or more modules for facilitating interaction between the processing assembly 702 and other assemblies. For example, the processing assembly 702 may include one or more processors 720 for processing instructions to complete all or some of the steps of the methods described above. assembly 702 may include a multimedia module to facilitate interaction between the multimedia assembly 708 and the processing assembly 702 .

[0153] The memory 704 is configured to store various types of data to support operation on the electronic device. Examples of such data include instructions for any application or method operated on the electronic device, contact data, phone book data, messages, images, videos, etc. The memory 704 may be implemented by any type of volatile or non-volatile storage device, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk, or an optical disk, or a combination thereof.

[0154] The power supply assembly 706 provides power to the various assemblies of the electronic device. The power supply assembly 706 includes a power management system, one or more power sources, and electronic equipment 700 may include other assemblies related to the generation, management, and distribution of electrical power.

[0155] The multimedia assembly 708 includes a screen that provides an output interface between the electronic device and a user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen for receiving input signals from a user. The touch panel includes one or more touch sensors for sensing touches, swipes, and gestures on the touch panel. The touch sensors can sense the boundaries of a touch or swipe operation as well as detect the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia assembly 708 includes one front camera and / or a rear camera. The front camera and / or the rear camera can receive external multimedia data when the electronic device is in an operating mode, such as a photo mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or may have a focal length and optical zoom capability.

[0156] The audio assembly 710 is configured to output and / or input audio signals. For example, the audio assembly 710 includes a microphone (MIC) configured to receive an external audio signal when the terminal is in an operation mode such as a call mode, a recording mode, a voice recognition mode, etc. The received audio signal may be further stored in the memory 704 or may be transmitted to the communication assembly 706. 716 In some embodiments, the audio assembly 710 further includes a speaker for outputting the audio signal.

[0157] The I / O interface 712 provides an interface between the processing assembly 702 and a peripheral interface module, which may be a keypad, a click wheel, buttons, etc. These buttons may include, but are not limited to, a home button, volume buttons, a start button, and a lock button.

[0158] The sensor assembly 714 includes one or more sensors for providing an assessment of various aspects of the state of the electronic device 700. For example, the sensor assembly 714 can detect the open / closed state of the electronic device 700, the relative positioning of an assembly, such as the display and keypad of a terminal, and can also detect changes in the position of the terminal or an assembly of the terminal, the presence or absence of a user's contact with the electronic device, the orientation or acceleration / deceleration of the electronic device, and changes in the temperature of the electronic device. The sensor assembly 714 can include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 714 can also include an optical sensor, such as a CMOS or CCD image sensor for use in imaging applications. In some embodiments, the sensor assembly 714 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0159] The communication assembly 716 is configured to facilitate wired or wireless communication between the electronic device and other devices. The electronic device can access a wireless network based on a communication standard such as WiFi, 2G, or 3G, or a combination thereof. In one exemplary embodiment, the communication component 716 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 716 further comprises a Near Field Communication (NFC) module for facilitating short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0160] In an exemplary embodiment, the electronics may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements to process the atomicity maintaining methods described in Examples 1 to 5 above.

[0161] The electronic device of the present application is for implementing the corresponding atomicity maintaining methods in the embodiments of the methods described above, and has beneficial effects of implementing the corresponding methods, so they will not be described again here.

[0162] Each embodiment in this specification will be described step by step, and each embodiment will focus on the differences with other embodiments, and the same or similar parts between each embodiment can be referred to each other. The device embodiment is basically similar to the method embodiment, so the description will be relatively simple, and the relevant parts can be described with reference to the method embodiment.

[0163] The above describes the atomicity maintaining method, processor, and electronic device provided by the present application in detail. In this specification, the principle and embodiment of the present invention are described by applying specific examples, but the above examples are merely described to help understand the method of the present invention and its main concept, and at the same time, those skilled in the art can make changes to the specific embodiment and its application scope based on the concept of the present invention. As described above, the description in this specification should not be understood as limiting the present invention.

[0164] The algorithms and displays provided herein are not inherently related to any particular computer, electronic system, or other device. Various general-purpose systems may also be used in conjunction with the teachings herein. The necessary structure for building such a system will be apparent in light of the above description. Furthermore, this application is not directed to any particular programming language. It should be understood that a variety of programming languages ​​can be used to implement the contents of the application as described herein, and the above description of a particular language is provided to disclose the best mode of carrying out the application.

[0165] In the specification provided by the present application, a large amount of specific details are described. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0166] Similarly, in the above description of exemplary embodiments of the present application, it should be understood that various features of the present application may be grouped together in a single embodiment, drawing, or description thereof in order to simplify the disclosure and aid in the understanding of one or more aspects of the various inventions. However, this method of disclosure should not be interpreted as reflecting an intention that the present application requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, aspects of the present invention include fewer than all features of each of the embodiments disclosed above. Thus, any claims according to a particular embodiment are hereby expressly incorporated into that particular embodiment, with each claim serving as a separate embodiment of the present application in its own right.

[0167] Those skilled in the art can understand that the modules in the devices in the embodiments can be adaptively modified and arranged in one or more devices different from the embodiments. The modules, units or assemblies in the embodiments can be combined into a single module, unit or assembly, and further divided into multiple sub-modules, sub-units or sub-assemblies. All features disclosed in this specification (including the appended claims, abstract and accompanying drawings) and all processes or units of the methods or devices thus disclosed can be combined in any combination, except where at least some of such features and / or processes or units are mutually exclusive. Each feature disclosed in this specification (including the appended claims, abstract and accompanying drawings) may be replaced by an alternative feature serving the same, equivalent or similar purpose, unless otherwise specified.

[0168] In addition, those skilled in the art will appreciate that some embodiments described herein include some features but not other features included in other embodiments, but that combinations of features from different embodiments are within the scope of the present application and are meant to form different embodiments. For example, in the following claims, any one of the claimed embodiments may be used in any combination.

[0169] The embodiments of the various components of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or digital signal processor (DSP) may actually be used to implement some or all of the functions of some or all of the components in a browser client device according to the embodiments of the present application. The present application may also be implemented as a device or apparatus program (e.g., computer program and computer program product) for performing some or all of the methods described herein. Such programs implementing the present application may be stored on a computer readable medium or may have the form of one or more signals. Such signals may be downloadable from an Internet site, provided on a carrier signal, or provided in any other form.

[0170] It should be noted that the above examples are illustrative of the present application, but do not limit it, and that a person skilled in the art may design alternative examples without departing from the scope of the appended claims. In the claims, reference signs placed between parentheses shall not be interpreted as limiting the scope of the claims. The term "comprises" does not exclude the presence of an element or step not stated in the claim. The term "a" or "one" preceding an element does not exclude the presence of a plurality of such elements. The present application may be implemented by hardware comprising several different elements, and by a suitably programmed computer. In individual claims enumerating several devices, several of these devices may be embodied by the same hardware. The use of the terms first, second, third, etc. does not indicate any order. These terms may be interpreted as names.

[0171] This application claims priority to a Chinese patent application filed with the China National Intellectual Property Office on December 10, 2021, bearing application number 202111507703.X and entitled "Method for maintaining atomicity, processor and electronic device," the entire contents of which are incorporated by reference into this application.

Claims

1. generating N access store operations, N being a positive integer greater than or equal to 1, according to a vector access store instruction; determining whether an event exists during processing of the N access store operations that causes the vector access store instruction to be non-atomic; if the event exists, then either none of the N access storage operations produces any processing effect or the N access storage operations produce all of the processing effects; The access storage operation not producing any processing effect refers to the access storage operation being executed but the execution effect of the access storage operation not being submitted, or the access storage operation not being executed, or the access storage operation not being sent; the access storage operation producing all processing effects refers to all of the N access storage operations being executed and all of the execution results of the N access storage operations being submitted; determining whether there is an event during processing of the N access store operations that causes the vector access store instruction to be non-atomic, comprising: determining whether at least one of an interrupt event, an exception event, and a barrier instruction exists during processing of the N access store operations; if so, determining that an event exists during processing of the N access store operations that causes the vector access store instruction to not be atomic.

2. prior to the step of determining whether there is an event during processing of the N access store operations that causes the vector access store instruction to be non-atomic, responsive to an interrupt event occurring during processing of the vector access store instruction, adding an interrupt flag to one or more of the N access store operations; 2. The method of claim 1, wherein the interrupt flag is for indicating that an interrupt event has occurred during processing of the vector access store instruction.

3. adding an interrupt flag to one or more of the N access store operations 3. The method for maintaining atomicity according to claim 2, further comprising the step of adding the interrupt flag to any one of the N access storage operations.

4. adding an interrupt flag to one or more of the N access store operations 3. The method for maintaining atomicity according to claim 2, further comprising the step of adding said interrupt flag to all access store operations of said N access store operations.

5. determining whether there is an event during processing of the N access store operations that causes the vector access store instruction to be non-atomic, comprising: sequentially checking whether the interrupt flag is marked for the N access storage operations; The step of causing no access storage operation among the N number of access storage operations to produce any processing effect when the event exists comprises: The method for maintaining atomicity according to any one of claims 2 to 4, further comprising the steps of: caching the N access store operations generated by the vector access store instruction if the interrupt flag is marked in any of the N access store operations; not executing any of the N access store operations; and executing the N access store operations after the interrupt event has been processed.

6. determining whether there is an event during processing of the N access store operations that causes the vector access store instruction to be non-atomic, comprising: sequentially checking whether the interrupt flag is marked for the N access storage operations; The step of causing all of the N access storage operations to have a processing effect if the event exists comprises: executing each and every access storage operation of the N access storage operations if the interrupt flag is marked for any of the access storage operations of the N access storage operations; submitting execution results of the N access storage operations; The method for maintaining atomicity according to any one of claims 2 to 4, further comprising a step of processing the interrupt event when it is confirmed that the execution results of all of the N access storage operations have been submitted.

7. determining whether there is an event during processing of the N access store operations that causes the vector access store instruction to be non-atomic, comprising: determining whether the interrupt flag is marked in a first access store operation of the N access store operations; The step of causing no access storage operation among the N number of access storage operations to produce any processing effect when the event exists comprises: The method for maintaining atomicity according to any one of claims 2 to 4, further comprising the steps of: caching the N access store operations generated by the vector access store instruction if the first access store operation is marked with the interrupt flag; not executing any of the N access store operations; and executing the N access store operations after the interrupt event has been processed.

8. determining whether there is an event during processing of the N access store operations that causes the vector access store instruction to be non-atomic, comprising: determining whether the interrupt flag is marked in a first access store operation of the N access store operations; The step of causing all of the N access storage operations to have a processing effect if the event exists comprises: executing each and every access store operation of the N access store operations if the first access store operation has the interrupt flag marked; submitting execution results of the N access storage operations; The method for maintaining atomicity according to any one of claims 2 to 4, further comprising a step of processing the interrupt event when it is confirmed that the execution results of the N access storage operations have been submitted.

9. The method for maintaining atomicity comprises: if none of the N access store operations has the interrupt flag marked, executing the N access store operations; 5. The method for maintaining atomicity according to claim 2, further comprising the step of: submitting execution results of the N access storage operations.

10. determining whether there is an event during processing of the N access store operations that causes the vector access store instruction to be non-atomic, comprising: determining whether any of the N access storage operations generates an exception event during processing, and obtaining a determination result; performing said N access storage operations; The step of causing no access storage operation among the N number of access storage operations to produce any processing effect when the event exists comprises: A method for maintaining atomicity as described in any one of claims 1 to 4, characterized in that if the confirmation result indicates that there is an access storage operation among the N access storage operations that generates an exception event during processing, the method includes a step of reporting the exception event without submitting the execution result of any of the access storage operations among the N access storage operations.

11. The step of checking whether any of the access storage operations that generates an exception event during processing exists among the N access storage operations and obtaining a checking result includes: obtaining an access storage address for each of the N access storage operations; confirming whether or not a situation that satisfies an exception event trigger exists for each of the access storage addresses, and if so, determining as a confirmation result that there is any access storage operation among the N access storage operations that will cause an exception event during processing, and if not, determining as a confirmation result that there is no access storage operation among the N access storage operations that will cause an exception event during processing, The circumstances that satisfy the exception event trigger are: A situation in which the permission of any of the N access storage operations has an attribute permission violation; A situation in which the address translation table does not include any access storage address of any access storage operation among the N access storage operations; 11. The method of claim 10, further comprising at least one of: a situation in which an access store address of the vector access store instruction is an out-of-bounds address.

12. After the step of performing the N access storage operations, 11. The method for maintaining atomicity according to claim 10, further comprising the step of submitting execution results of the N access storage operations if the confirmation result indicates that none of the N access storage operations generates an exception event during processing.

13. determining whether there is an event during processing of the N access store operations that causes the vector access store instruction to be non-atomic, comprising: determining whether a barrier command has been received; The step of causing none of the N access storage operations to produce any processing effect or causing all of the N access storage operations to produce processing effects when the event exists comprises: in response to receiving the barrier instruction, processing the barrier instruction when it is confirmed that all the N access storage operations being processed have been completed and execution results have been submitted; or The method for maintaining atomicity according to any one of claims 1 to 4, further comprising the step of: in response to obtaining the vector access store instruction, if there is a barrier instruction that has not yet been processed, caching the N access store operations generated by the vector access store instruction without executing them, and executing the N access store operations after the barrier instruction that has not yet been processed has been processed.

14. The vector access storage instruction is a Load instruction or a Store instruction, When the vector access store instruction is a Load instruction, performing the N access store operations includes: performing an operation of reading an operand at an address designated by the vector access store instruction from a memory into a designated general-purpose register; When the vector access store instruction is a Store instruction, performing the N access store operations comprises: The method for maintaining atomicity according to any one of claims 1 to 4, further comprising a step of executing an operation of writing an operand at an address indicated by the vector access store instruction from a specified general-purpose register to a memory.

15. a decode unit adapted to obtain a vector access store instruction and generate N access store operations according to the vector access store instruction, N being a positive integer greater than or equal to 1; determining whether an event exists during processing of the N access store operations that causes the vector access store instruction to be non-atomic, and if the event exists, a processing unit is used to either not cause any access store operation of the N access store operations to produce any processing effect or to cause all of the N access store operations to produce processing effects; The access storage operation not producing any processing effect refers to the access storage operation being executed but the execution effect of the access storage operation not being submitted, or the access storage operation not being executed, or the access storage operation not being sent; the access storage operation producing all processing effects refers to all of the N access storage operations being executed and all of the execution results of the N access storage operations being submitted; Specifically, the processing unit includes:

1. A processor for use in: ascertaining whether at least one of an interrupt event, an exception event, and a barrier instruction is present during processing of the N access store operations; and, if so, determining that an event is present during processing of the N access store operations that causes the vector access store instruction to be non-atomic.

16. The processing unit includes a sending unit; 16. The processor of claim 15, wherein the dispatch unit is adapted to, prior to determining whether an event exists that causes the vector access store instruction to be non-atomic during processing of the N access store operations, add an interrupt flag to one or more of the N access store operations in response to an interrupt event occurring during processing of the vector access store instruction, the interrupt flag being for indicating that an interrupt event occurred during processing of the vector access store instruction.

17. 17. The processor according to claim 16, wherein the issuing unit is specifically used for adding the interrupt flag to any one of the N access storage operations.

18. 17. The processor of claim 16, wherein the issuing unit is specifically used for adding the interrupt flag to all access storage operations of the N access storage operations.

19. The processor according to any one of claims 16 to 18, characterized in that the sending unit is used for sequentially checking whether the N access storage operations have the interrupt flag marked or not, and when the interrupt flag is marked for any of the N access storage operations, not sending any of the N access storage operations.

20. the processing unit further comprises an execution unit; The sending unit is used for sequentially checking whether the N access storage operations are marked with the interrupt flag, and when determining that any of the N access storage operations is marked with the interrupt flag, sending the N access storage operations; The processor of any one of claims 16 to 18, characterized in that the execution unit is used to cache the N access store operations generated by the vector access store instruction, not execute any of the N access store operations, and execute the N access store operations after the interrupt event has been processed.

21. The processing unit further includes an execution unit and a submission unit; The sending unit is used for sequentially checking whether the N access storage operations are marked with the interrupt flag, and when determining that any of the N access storage operations is marked with the interrupt flag, sending the N access storage operations; the execution unit is used to execute each and every access storage operation of the N access storage operations; The processor according to any one of claims 16 to 18, wherein the submission unit is used for submitting execution results of the N access storage operations.

22. The processor according to any one of claims 16 to 18, characterized in that the sending unit is used to check whether a first access storage operation among the N access storage operations has the interrupt flag marked, and if the first access storage operation has the interrupt flag marked, not to send any of the N access storage operations.

23. the processing unit further comprises an execution unit; The sending unit is used for checking whether a first access storage operation among the N access storage operations is marked with the interrupt flag, and when determining that the first access storage operation is marked with the interrupt flag, sending the N access storage operations; The processor of any one of claims 16 to 18, characterized in that the execution unit is used to cache the N access store operations generated by the vector access store instruction, not execute any of the N access store operations, and execute the N access store operations after the interrupt event has been processed.

24. The processing unit further includes an execution unit and a submission unit; The sending unit is used for checking whether a first access storage operation among the N access storage operations is marked with the interrupt flag, and when determining that the first access storage operation is marked with the interrupt flag, sending the N access storage operations; the execution unit is used to execute each and every access storage operation of the N access storage operations; The processor according to any one of claims 16 to 18, wherein the submission unit is used for submitting execution results of the N access storage operations.

25. The processing unit further includes an execution unit and a submission unit; the sending unit is used to send the N access store operations when the interrupt flag is not marked in any of the N access store operations; the execution unit is used to execute the N access storage operations; The processor according to any one of claims 16 to 18, wherein the submission unit is used for submitting execution results of the N access storage operations.

26. The processing unit includes an originating unit, an executing unit, and a submitting unit; the sending unit is used for sending the N access storage operations; The execution unit is used for executing the N access storage operations, and for checking whether any access storage operation that generates an exception event during processing exists among the N access storage operations, and obtaining a checking result; 16. The processor of claim 15, wherein the submission unit is used to report an exception event without submitting an execution result of any of the N access storage operations when the confirmation result indicates that there is an access storage operation among the N access storage operations that generates an exception event during processing.

27. The execution unit is used for obtaining an access storage address of each of the N access storage operations, and for each of the access storage addresses, checking whether a situation that satisfies an exception event trigger exists, and if so, determining as a confirmation result that there is any access storage operation among the N access storage operations that generates an exception event during processing, and otherwise determining as a confirmation result that there is no access storage operation among the N access storage operations that generates an exception event during processing; The circumstances that satisfy the exception event trigger are: A situation in which the permission of any of the N access storage operations has an attribute permission violation; A situation in which the address translation table does not include any access storage address of any access storage operation among the N access storage operations; and a situation in which an access store address of the vector access store instruction is an out of bounds address.

28. 28. The processor of claim 27, wherein the submission unit is used to submit execution results of the N access storage operations if the confirmation result indicates that none of the N access storage operations generates an exception event during processing.

29. The processing unit includes: Responding to the barrier command when it is determined that a barrier command has been received, and processing the barrier command when it is determined that all the N access storage operations being processed have been completed and execution results have been submitted; or 16. The processor of claim 15, wherein, in response to obtaining the vector access store instruction, if there is a barrier instruction that has not yet been processed, the N access store operations generated by the vector access store instruction are cached without being executed, and are used to execute the N access store operations after the barrier instruction that has not yet been processed is processed.

30. 5. An electronic device comprising a memory and one or more programs, the one or more programs being stored in the memory and configured to be executed by one or more processors according to the method for maintaining atomicity according to one or more of claims 1 to 4.

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