Communication method and device, chip system and electronic equipment

Abstract

The embodiment of the invention relates to a communication method and device, a chip system and electronic equipment, and relates to the technical field of electronics. The method executes a plurality of tasks based on a first chip, the first chip comprises a first scheduler, a first AI accelerator and a first memory reader, and the method comprises the following steps: the first scheduler outputs a first trigger signal to the first AI accelerator based on a first scheduling subtask; the first AI accelerator responds to the first trigger signal based on the first calculation sub-task, performs AI calculation to obtain first data, and outputs a first completion signal to the first scheduler to indicate that the first calculation sub-task is completed, and the first data is data required by the second chip for performing AI calculation; the first scheduler outputs a second trigger signal to the first memory reader according to the first completion signal based on the first scheduling sub-task; and the first memory reader transmits the first data to the second chip in response to the second trigger signal based on the first transmission subtask. Therefore, the problem of relatively high time overhead can be solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic technology, and in particular, to a communication method, device, chip system and electronic device. Background Art

[0002] The business scenario of intelligent driving has a high demand for the artificial intelligence (AI) computing power of chips. When the computing power of a single chip is insufficient, the AI ​​computing power can be expanded by combining multiple chips, and AI calculations and data interaction can be performed through multiple chips to complete the overall AI calculation. Each of the multiple chips includes devices such as a processor, an AI accelerator, and a memory reader, where the AI ​​accelerator is used to perform AI calculations, and the memory reader is used to transmit data obtained by performing AI calculations. In the scenario where multiple chips perform AI calculations and data interaction, the time overhead is relatively large. Summary of the invention

[0003] The embodiments of the present application provide a communication method, device, chip system and electronic device, which solve the problem of large time overhead in the prior art.

[0004] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0005] In a first aspect, a communication method is provided. The method performs multiple tasks based on a first chip, the multiple tasks include a first scheduling subtask, a first computing subtask, and a first transmission subtask. The first chip includes a first scheduler, a first AI accelerator, and a first memory reader. The method includes: the first scheduler outputs a first trigger signal to the first AI accelerator based on the first scheduling subtask. The first AI accelerator performs AI calculation based on the first computing subtask and responds to the first trigger signal to obtain first data, and outputs a first completion signal to the first scheduler, wherein the first data is the required data for the second chip to perform AI calculation; the first completion signal is used to indicate that the first computing subtask has been completed. The first scheduler outputs a second trigger signal to the first memory reader based on the first scheduling subtask according to the first completion signal. The first memory reader transmits the first data to the second chip based on the first transmission subtask in response to the second trigger signal.

[0006] In the above technical solution, compared with the software scheduling AI calculation and data transmission process run by the first processor, the AI ​​calculation and data transmission process of the embodiment of the present application is scheduled by the first scheduler of the hardware unit. The first scheduler outputs a first trigger signal to the first AI accelerator based on the first scheduling subtask, so that the first AI accelerator performs the first calculation subtask. In response to the first trigger signal, the first AI accelerator starts to execute the first calculation subtask, performs AI calculation to obtain the first data, and outputs a first completion signal to the first scheduler, so that the first scheduler knows that the first calculation subtask has been completed. Based on the first scheduling subtask, the first scheduler outputs a second trigger signal to the first memory reader according to the first completion signal, so that the first memory reader performs the first transmission subtask. In response to the second trigger signal, the first memory reader starts to execute the first transmission subtask and transmits the first data to the second chip. By setting the first scheduler, the AI ​​calculation in the chip and the data transmission between chips are scheduled in a hardware manner, so that the inter-chip communication no longer depends on the processor software scheduling. In addition to the AI ​​calculation overhead of the first AI accelerator and the data transmission overhead of the first memory reader, the scheduling overhead and communication overhead of the first scheduler are small, which can be ignored compared to the delay of software scheduling. Therefore, the delay and jitter caused by the scheduling and calculation of the first processor can be eliminated, and the problem of large time overhead can be improved.

[0007] In a possible implementation of the first aspect, the first scheduler outputs a second trigger signal to the first memory reader based on the first scheduling subtask according to the first completion signal, including: the first scheduler outputs a second trigger signal to the first memory reader based on the first scheduling subtask in response to the first indication signal according to the first completion signal, the first indication signal is used to indicate that the second chip has processed the second data, and the second data is the data obtained by the previous AI calculation of the first AI accelerator. In the above possible implementation, the first scheduler can know that the second chip has processed the second data sent last time according to the first indication signal, and the accelerator of the second chip is in an idle state. At this time, the first scheduler can output a second trigger signal to the first memory reader to schedule the first memory reader to transmit the first data to the second chip. In this way, the first chip and the second chip can be guaranteed to be processed serially, avoiding the first chip sending the first data to be processed this time to the second chip before the second chip has processed the second data sent last time, causing data trampling. In addition, compared with the method of transmitting data to the second chip at a fixed time, the time for transmitting the first data to the second chip can be flexibly set according to the first indication signal, which can further reduce the time overhead.

[0008] In a possible implementation of the first aspect, the first chip also includes a first notification circuit, and the multiple tasks also include a first notification subtask. The method also includes: the first notification circuit receives a first notification signal from the second chip based on the first notification subtask, and outputs a first indication signal obtained according to the first notification signal to the first scheduler, and the first notification signal is used to indicate that the second chip has processed the second data. In the above possible implementation, the first chip also includes a first notification circuit, and the first notification circuit receives a first notification signal from the second chip based on the first notification subtask, and then obtains a first indication signal according to the first notification signal, and outputs the first indication signal to the first scheduler. In this way, the first scheduler does not have to actively and regularly check whether the first indication signal is received, but passively receives the first indication signal from the first notification circuit, which can reduce the occupancy of the first scheduler, speed up the scheduling speed, and further reduce time overhead.

[0009] In a possible implementation of the first aspect, the method further includes: after the first memory reader transmits the first data to the second chip, the first scheduler outputs a third trigger signal to the first notification circuit based on the first scheduling subtask. The first notification circuit sends a second notification signal to the second chip based on the first notification subtask in response to the third trigger signal, and the second notification signal is used to instruct the second chip to perform AI calculations based on the first data. In the above possible implementation, after the first memory reader transmits the first data to the second chip, the first scheduler outputs a third trigger signal to the first notification circuit, and schedules the first notification circuit to send a second notification signal to the second chip, so that the second chip knows that the first data has been transmitted to the second chip, so that the second chip can perform AI calculations based on the first data. In this way, it can be ensured that the first chip and the second chip are processed serially to avoid the second chip being unable to determine the time to execute the third calculation subtask (performing AI calculations based on the first data).

[0010] In a possible implementation of the first aspect, the first chip also includes a first memory. The first AI accelerator performs AI calculation based on the first computing subtask and in response to the first trigger signal to obtain the first data, including: the first AI accelerator performs AI calculation based on the first computing subtask and in response to the first trigger signal to obtain the first data, and writes the first data into the first storage space of the first memory. The first memory reader transmits the first data to the second chip based on the first transmission subtask and in response to the second trigger signal, including: the first memory reader reads the first data from the first storage space based on the first transmission subtask and in response to the second trigger signal, and transmits the first data to the second chip. In the above possible implementation, the storage space where the first AI accelerator outputs the first data and the storage space accessed by the first memory reader when acquiring the first data are both the first storage space in the first memory, and there is no need to copy data, which further reduces time overhead and can reduce storage space bandwidth requirements.

[0011] In a possible implementation of the first aspect, the multiple tasks also include a second computing subtask, and the method also includes: after the first chip receives the third data from the second chip, the first scheduler outputs a fourth trigger signal to the first AI accelerator based on the first scheduling subtask, and the third data is the data obtained by the second chip performing AI calculation based on the first data. The first AI accelerator performs AI calculation based on the third data in response to the fourth trigger signal based on the second computing subtask. In the above possible implementation, the first chip can also receive the third data from the second chip, and the first scheduler outputs a fourth trigger signal to the first AI accelerator based on the first scheduling subtask to schedule the first AI accelerator to perform AI calculation based on the third computing subtask and the third data. In this way, the communication method provided in the embodiment of the present application can be applied to a variety of data interaction scenarios.

[0012] In a possible implementation of the first aspect, the first chip also includes a first processor, and the method further includes: the first processor outputs the execution order of multiple tasks to the first scheduler based on the request of the first application run by the first processor. In the above possible implementation, the first processor only needs to send the execution order of multiple tasks executed by the first chip to the first scheduler. Since the execution order of sending multiple tasks is not included in the AI ​​computing time and communication time, the time for the first processor to send the execution order of multiple tasks does not affect the AI ​​computing time and communication time, and the first processor is less occupied.

[0013] In a second aspect, a communication method is provided, wherein the method executes multiple tasks based on a second chip, the multiple tasks include a second scheduling subtask and a third computing subtask, the second chip includes a second scheduler and a second AI accelerator, and the method includes: after the second chip receives first data from the first chip, the second scheduler outputs a fifth trigger signal to the second AI accelerator based on the second scheduling subtask. The second AI accelerator performs AI computing based on the first data in response to the fifth trigger signal based on the third computing subtask.

[0014] In the above technical solution, compared with the software scheduling AI calculation and data transmission process run by the second processor, the AI ​​calculation and data transmission process of the embodiment of the present application is scheduled by the second scheduler of the hardware unit. The second scheduler can actively or passively know whether the second chip receives the first data from the first chip, and then the second scheduler outputs a fifth trigger signal to the second AI accelerator based on the second scheduling subtask, so that the second AI accelerator performs the third calculation subtask based on the first data. In response to the fifth trigger signal, the second AI accelerator starts to execute the third calculation subtask and performs AI calculation based on the first data. The second AI accelerator can only execute the third calculation subtask when the second scheduler confirms that the first data has arrived. By setting the second scheduler, the inter-chip data transmission and the intra-chip AI calculation are scheduled in a hardware manner, so that the inter-chip communication no longer depends on the processor software scheduling. In addition to the AI ​​calculation overhead of the second AI accelerator, the scheduling overhead and communication overhead of the second scheduler are small, which can be ignored compared to the delay of software scheduling. In this way, the delay and jitter caused by the scheduling and operation of the second processor can be removed, and the problem of large time overhead can be improved.

[0015] In a possible implementation of the second aspect, the second AI accelerator performs AI calculation based on the first data based on the third calculation subtask in response to the fifth trigger signal, including: the second AI accelerator performs AI calculation based on the first data based on the third calculation subtask in response to the fifth trigger signal, and outputs a second completion signal to the second scheduler, the second completion signal is used to indicate that the AI ​​calculation based on the first data is completed. The method also includes: the second scheduler sends a third notification signal to the first chip based on the second scheduling subtask according to the second completion signal, the third notification signal is used to indicate that the second chip has processed the first data. In the above possible implementation, the second scheduler learns that the second AI accelerator has completed the AI ​​calculation based on the first data according to the second completion signal from the second AI accelerator, and the second scheduler can send a third notification signal to the first chip to indicate that the second chip has processed the first data, and the first chip can send the data that needs to be AI calculated next time. In this way, the first chip and the second chip can perform data interaction and AI calculations in a loop for multiple times, and can ensure that the first chip and the second chip are processed in series, so as to avoid data trampling when the first chip sends the next data to be processed to the second chip before the second chip has finished processing the first data sent last time. In addition, compared with the method of transmitting data to the second chip at a fixed time, the time required for transmitting the next AI calculation to the second chip can be flexibly set according to the third notification signal, which can further reduce time overhead.

[0016] In a possible implementation of the second aspect, the second chip also includes a second notification circuit, and the multiple tasks also include a second notification subtask. The second scheduler sends a third notification signal to the first chip based on the second scheduling subtask and according to the second completion signal, including: the second scheduler outputs a sixth trigger signal to the second notification circuit based on the second scheduling subtask and according to the second completion signal. The second notification circuit sends a third notification signal to the first chip in response to the sixth trigger signal based on the second notification subtask. In the above possible implementation, the second chip also includes a second notification circuit, and the second scheduler schedules the second notification circuit to send the third notification signal to the first chip by outputting the sixth trigger signal to the second notification circuit. In this way, the second scheduler does not need to write the information carried by the third notification signal into the first chip, but only needs to output the sixth trigger signal to the second notification circuit inside the second chip. Since the operation of outputting the sixth trigger signal is relatively simple, the occupancy of the second scheduler can be reduced, the scheduling speed can be accelerated, and the time overhead can be further reduced.

[0017] In a possible implementation of the second aspect, the method further includes: the second notification circuit receives a second notification signal from the first chip based on the second notification subtask, and outputs a second indication signal obtained according to the second notification signal to the second scheduler, wherein the second notification signal is used to instruct the second chip to perform AI calculation based on the first data, and the second indication signal is used to instruct the second scheduler to output a fifth trigger signal to the second AI accelerator. In the above possible implementation, the second notification circuit receives a second notification signal from the first chip based on the second notification subtask, obtains a second indication signal according to the second notification signal, and outputs a second indication signal to the second scheduler. In this way, the second chip can be informed that the first data has been transmitted to the second chip, ensuring that the first chip and the second chip are processed serially, and avoiding the second chip from being unable to determine the time to execute the third calculation subtask (performing AI calculation based on the first data). In addition, the second scheduler does not need to actively check whether the second indication signal is received at regular intervals, but passively receives the second indication signal from the second notification circuit, which can reduce the occupancy of the second scheduler, speed up the scheduling speed, and further reduce the time overhead.

[0018] In a possible implementation of the second aspect, the second chip further includes a second memory, and the second storage space of the second memory is used to store the first data, and the second storage space is the storage space registered (MR) by the second chip for the first chip. The second AI accelerator performs AI calculations based on the first data in response to the fifth trigger signal based on the third computing subtask, including: the second AI accelerator reads the first data from the second storage space in response to the fifth trigger signal based on the third computing subtask, and performs AI calculations based on the first data. In the above possible implementation, the second storage space in the second memory is the storage space registered (MR) by the second chip for the first chip. The storage space in which the first memory reader writes the first data in the second chip and the storage space accessed when the second AI accelerator obtains the first data are both the second storage space in the second memory, and there is no need to copy data, which further reduces time overhead and can reduce storage space bandwidth requirements.

[0019] In a possible implementation of the second aspect, the second chip also includes a second memory reader, and the multiple tasks also include a second transmission subtask. The method also includes: after the second AI accelerator completes the AI ​​calculation based on the first data, the second scheduler outputs a seventh trigger signal to the second memory reader based on the second scheduling subtask. The second memory reader transmits third data to the first chip in response to the seventh trigger signal based on the second transmission subtask, and the third data is the data obtained by the second AI accelerator performing AI calculation based on the first data. In the above possible implementation, the second scheduler can also output the seventh trigger signal to the second memory reader based on the second scheduling subtask to schedule the second memory reader to transmit the third data to the first chip based on the second transmission subtask. In this way, the communication method provided in the embodiment of the present application can be applied to a variety of data interaction scenarios.

[0020] In a possible implementation of the second aspect, the second chip also includes a second processor, and the method further includes: the second processor outputs the execution order of multiple tasks to the second scheduler based on the request of the second application run by the second processor. In the above possible implementation, the second processor only needs to send the execution order of multiple tasks executed by the second chip to the second scheduler. Since the execution order of sending multiple tasks is not included in the AI ​​computing time and communication time, the time for the second processor to send the execution order of multiple tasks does not affect the AI ​​computing time and communication time, and the second processor is less occupied.

[0021] In a third aspect, a communication device is provided, which is applied to a first chip, and the device is configured to perform multiple tasks, including a first scheduling subtask, a first computing subtask, and a first transmission subtask. The device includes a first scheduler, a first AI accelerator, and a first memory reader. The first scheduler is used to output a first trigger signal to the first AI accelerator based on the first scheduling subtask. The first AI accelerator is used to perform AI calculation based on the first computing subtask and in response to the first trigger signal to obtain first data, and output a first completion signal to the first scheduler, wherein the first data is the required data for the second chip to perform AI calculation; the first completion signal is used to indicate that the first computing subtask has been completed. The first scheduler is used to output a second trigger signal to the first memory reader based on the first scheduling subtask according to the first completion signal. The first memory reader is used to transmit the first data to the second chip in response to the second trigger signal based on the first transmission subtask.

[0022] In a possible implementation of the third aspect, the first scheduler is specifically used to, based on the first scheduling subtask, respond to the first indication signal, and output a second trigger signal to the first memory reader according to the first completion signal, wherein the first indication signal is used to indicate that the second chip has processed the second data, and the second data is the data obtained by the previous AI calculation of the first AI accelerator.

[0023] In a possible implementation of the third aspect, the device further includes a first notification circuit, and the plurality of tasks further include a first notification subtask. The first notification circuit is configured to receive a first notification signal from the second chip based on the first notification subtask, and output a first indication signal obtained according to the first notification signal to the first scheduler, wherein the first notification signal is used to indicate that the second chip has processed the second data.

[0024] In a possible implementation of the third aspect, after the first memory reader transmits the first data to the second chip, the first scheduler is further configured to, based on the first scheduling subtask, output a third trigger signal to the first notification circuit;

[0025] The first notification circuit is further used to send a second notification signal to the second chip based on the first notification subtask and in response to the third trigger signal, wherein the second notification signal is used to instruct the second chip to perform AI calculation based on the first data.

[0026] In a possible implementation of the third aspect, the device further includes a first memory. A first AI accelerator is specifically configured to perform AI calculation based on the first computing subtask and in response to a first trigger signal to obtain first data, and write the first data into a first storage space of the first memory. A first memory reader is specifically configured to read the first data from the first storage space and transmit the first data to the second chip in response to a second trigger signal based on the first transmission subtask.

[0027] In a possible implementation of the third aspect, the multiple tasks further include a second computing subtask. After the first chip receives the third data from the second chip, the first scheduler is further configured to, based on the first scheduling subtask, output a fourth trigger signal to the first AI accelerator, where the third data is data obtained by the second chip performing AI computing based on the first data. The first AI accelerator is further configured to, based on the second computing subtask, perform AI computing based on the third data in response to the fourth trigger signal.

[0028] In a possible implementation manner of the third aspect, the first chip further includes a first processor. The first processor is configured to output an execution order of the multiple tasks to the first scheduler based on a request of a first application run by the first processor.

[0029] In a fourth aspect, a communication device is provided, which is applied to a second chip, and the device is configured to perform multiple tasks, the multiple tasks include a second scheduling subtask and a third computing subtask, and the device includes a second scheduler and a second AI accelerator. After the second chip receives the first data from the first chip, the second scheduler is used to output a fifth trigger signal to the second AI accelerator based on the second scheduling subtask. The second AI accelerator is used to perform AI calculation based on the first data in response to the fifth trigger signal based on the third computing subtask.

[0030] In a possible implementation of the fourth aspect, the second AI accelerator is specifically configured to perform AI calculation based on the first data in response to the fifth trigger signal based on the third computing subtask, and output a second completion signal to the second scheduler, where the second completion signal is used to indicate that the AI ​​calculation based on the first data is completed. The second scheduler is further configured to send a third notification signal to the first chip based on the second scheduling subtask and according to the second completion signal, where the third notification signal is used to indicate that the second chip has processed the first data.

[0031] In a possible implementation of the fourth aspect, the second chip further includes a second notification circuit, and the plurality of tasks further include a second notification subtask. The second scheduler is specifically configured to output a sixth trigger signal to the second notification circuit based on the second scheduling subtask and according to the second completion signal. The second notification circuit is specifically configured to send a third notification signal to the first chip in response to the sixth trigger signal based on the second notification subtask.

[0032] In a possible implementation of the fourth aspect, the second notification circuit is further used to receive a second notification signal from the first chip based on the second notification subtask, and output a second indication signal obtained according to the second notification signal to the second scheduler, wherein the second notification signal is used to instruct the second chip to perform AI calculation based on the first data, and the second indication signal is used to instruct the second scheduler to output a fifth trigger signal to the second AI accelerator.

[0033] In a possible implementation of the fourth aspect, the second chip further includes a second memory, a second storage space of the second memory is used to store the first data, and the second storage space is a storage space registered (MR) by the second chip for the first chip. The second AI accelerator is specifically configured to read the first data from the second storage space based on the third computing subtask and respond to the fifth trigger signal, and perform AI computing based on the first data.

[0034] In a possible implementation of the fourth aspect, the second chip further includes a second memory reader, and the plurality of tasks further include a second transmission subtask. After the second AI accelerator completes the AI ​​calculation based on the first data, the second scheduler is further configured to output a seventh trigger signal to the second memory reader based on the second scheduling subtask. The second memory reader is further configured to transmit third data to the first chip in response to the seventh trigger signal based on the second transmission subtask, the third data being data obtained by the second AI accelerator performing the AI ​​calculation based on the first data.

[0035] In a possible implementation of the fourth aspect, the second chip further includes a second processor. The second processor is further configured to output the execution order of the multiple tasks to the second scheduler based on a request of a second application run by the second processor.

[0036] In a fifth aspect, a chip system is provided, the system comprising a first chip and a second chip, the first chip comprising a communication device provided by the third aspect or any possible implementation of the third aspect, and the second chip comprising a communication device provided by the fourth aspect or any possible implementation of the fourth aspect.

[0037] In a sixth aspect, an electronic device is provided, which includes an interface circuit and the chip system provided in the fifth aspect, wherein the interface circuit is coupled to the chip system.

[0038] It can be understood that any of the communication devices, chip systems and electronic devices provided above are used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application Figure 1 ;

[0040] Figure 2 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application Figure 2 ;

[0041] Figure 3 A communication method according to an embodiment of the present invention is provided. Figure 1 ;

[0042] Figure 4 A communication method according to an embodiment of the present invention is provided. Figure 2 ;

[0043] Figure 5 A communication method according to an embodiment of the present invention is provided. Figure 3 ;

[0044] Figure 6 A schematic diagram of a scheduling task provided in an embodiment of the present application;

[0045] Figure 7 A schematic diagram of a control flow and a data flow of a first chip provided in an embodiment of the present application;

[0046] Figure 8 A schematic diagram of a control flow and a data flow of a second chip provided in an embodiment of the present application;

[0047] Fig. 9 A schematic diagram of a communication device provided in an embodiment of the present application Figure 1 ;

[0048] Fig.10 A schematic diagram of a communication device provided in an embodiment of the present application Figure 2 ;

[0049] Fig.11 A schematic diagram of a chip system provided in an embodiment of the present application;

[0050] Fig.12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application Figure 3 . DETAILED DESCRIPTION

[0051] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b and c can be single or multiple. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, in the embodiments of the present application, the words "first", "second" and the like do not limit the quantity and execution order.

[0052] In the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0053] In the embodiments of the present application, the numbers of the steps are only for distinguishing the different steps, but do not limit the sequence of the steps.

[0054] Before introducing the specific contents of the embodiments of the present application, the technical terms of the embodiments of the present application are first introduced.

[0055] Processor: The processor is the control center of the chip, which uses various interfaces and lines to connect the various parts of the entire chip, and performs various functions and processes data by running or executing software programs and / or software modules stored in the memory, and calling data stored in the memory. In some examples, the processor can be a single processor structure, a multi-processor structure, a single-threaded processor, and a multi-threaded processor. In some examples, the processor may include a central processing unit (CPU), a general-purpose processor, a microcontroller, or a microprocessor. In addition, the processor may further include other hardware circuits or accelerators, such as application-specific integrated circuits, field programmable gate arrays or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the contents of the embodiments of the present application. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like.

[0056] AI accelerator: AI accelerator is a hardware unit that uses logical language to implement artificial intelligence (AI) computing functions.

[0057] Hardware Scheduler: The hardware scheduler is a hardware unit that performs scheduling tasks.

[0058] Next, the application scenarios of the embodiments of the present application are introduced. The embodiments of the present application are applicable to electronic devices, which can be used to perform artificial intelligence AI calculations. The electronic devices include, but are not limited to: mobile phones, computers, tablet computers, laptops, PDAs, wearable devices (such as smart watches, smart bracelets, pedometers, etc.), vehicle-mounted devices (for example, cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed railways, etc.), virtual reality (VR) devices, augmented reality (AR) devices, communication equipment (such as connectors, switches, routers, etc.), etc. Taking the application of the electronic device in the intelligent driving scenario as an example, the electronic device needs to perform a large amount of AI calculations to realize the perception function, prediction function and planning control function. For scenarios such as high-speed assisted driving and urban assisted driving, in order to improve the user experience, it is necessary to improve the AI ​​computing power. When the computing power of a single chip is insufficient, the AI ​​computing power can be expanded by combining multiple chips.

[0059] Next, combine Figure 1 The structure of the electronic device 100 is introduced. For example, the electronic device 100 includes an image acquisition device 110 (such as a camera, radar, etc.), a chip 120, a chip 130 and a control system 140. The chip 120 and the chip 130 can both be coupled to the image acquisition device 110, and the chip 120 and the chip 130 can be set on the control system 140. The image acquisition device 110 may include a camera and / or a radar, and the control system 140 may be used to control the speed and direction of the electronic device 100. When the electronic device 100 is a car, the control system 140 may be a car chassis, which can be used to control the speed and direction of the car, and can also be used to place batteries or motors. The chip 120 includes a processor 121 and an AI accelerator 122, and the chip 130 includes a processor 131 and an AI accelerator 132.

[0060] Exemplarily, the processor 121 runs a perception process 150, and the processor 131 runs a perception process 161, a prediction process 162, and a planning control process 163. The perception process 150 and the perception process 161 are both used to implement the perception function, the prediction process 162 is used to implement the prediction function, and the planning control process 163 is used to implement the planning control function. The perception process 150 calls the AI ​​accelerator 122 to calculate and obtain data A, and the chip 120 transmits data A to the chip 130 through inter-chip communication. The perception process 161 calls the AI ​​accelerator 132 to calculate data B based on data A, the prediction process 162 calls the AI ​​accelerator 132 to calculate data C based on data B, and the planning control process 163 operates the control system 140 based on data C.

[0061] Among them, a communication module with a built-in direct memory access (DMA) controller can be used between the chip 120 and the chip 130 for inter-chip communication. The communication module can be a peripheral component interconnect express (PCIE) device or a hardware unit such as a network port. Taking the PCIE device as an example, PCIE is a high-speed serial computer expansion bus standard that can provide point-to-point interconnection between the PCIE root complex device (RC) and the terminal device (EP), or a RC connects multiple EPs. The characteristics of the PCIE device are high data transmission rate and low transmission delay. For example, the bandwidth of a single transmission channel can reach 8Gbps. The PCIE device can use DMA technology to reduce the occupancy of the processor by data transmission. The DMA controller can control the data transmission between the RC and the EP without passing through the processor.

[0062] Next, combine Figure 2 The process of calculating by the electronic device 200 is introduced. The electronic device 200 includes a chip 210 and a chip 220. The chip 210 includes a processor 211, an AI accelerator 212, a cache 213, a memory reader 214, and a cache 215. The memory reader 214 may be a communication module with a built-in DMA controller. The cache 213 and the cache 215 are both storage spaces in the memory of the chip 210. The cache 213 is a storage space accessible to the AI ​​accelerator 212, and the AI ​​accelerator 212 can write the data obtained by performing AI calculations into the cache 213. The cache 215 is a storage space accessible to the memory reader 214, and the memory reader 214 can read data from the cache 215. The chip 220 includes a processor 221, an AI accelerator 222, a cache 223, a memory reader 224, and a cache 225. The memory reader 224 may be a communication module with a built-in DMA controller. The cache 223 and the cache 225 are both storage spaces in the memory of the chip 220. Cache 223 is a storage space accessible to AI accelerator 222, and AI accelerator 222 can read data from cache 223 to perform AI calculations. Cache 225 is a storage space registered by chip 220 for chip 210, and memory reader 214 can write data into cache 225. The process of electronic device 200 performing calculations may include the following steps:

[0063] S101: The processor 211 sends instruction 1 to the AI ​​accelerator 212, where the instruction 1 is used to instruct the AI ​​accelerator 212 to perform AI calculations. The processor 211 switches from user mode to kernel mode to drive the AI ​​accelerator 212 to perform AI calculations.

[0064] S102: The AI ​​accelerator 212 performs AI calculation according to the instruction 1 to obtain data 1, writes the data 1 into the cache 213, and sends a response 1 to the processor 211, where the response 1 is used to indicate that the AI ​​calculation has been completed. The AI ​​accelerator 212 notifies the driver of the AI ​​accelerator 212 through a hardware interrupt. After the driver of the AI ​​accelerator 212 performs interrupt processing, it sends a response 1 to the process A running on the processor 211 to indicate that the AI ​​calculation is completed, and the processor 211 switches from the kernel state to the user state according to the response 1.

[0065] S103 : processor 211 copies data 1 in cache 213 to cache 215 according to response 1 .

[0066] S104: The processor 211 sends instruction 2 to the memory reader 214, and the instruction 2 is used to instruct to transfer data 1 to the chip 220. The processor 211 switches from the user state to the kernel state, and the process A running on the processor 211 calls the interface of the memory reader 214 to perform memory reading and data transmission operations.

[0067] S105: The memory reader 214 reads data 1 from the cache 215 according to instruction 2, writes data 1 into the cache 225 in the chip 220, and sends notification 1 to the memory reader 224 in the chip 220, where notification 1 is used to indicate that the transmission of data 1 is completed.

[0068] S106: When the memory reader 224 receives the notification 1, it outputs the notification 2 obtained according to the notification 1 to the processor 221. The memory reader 224 receives the notification 1 and notifies the driver of the memory reader 224 through a hardware interrupt. After the driver of the memory reader 224 performs interrupt processing, it sends the notification 2 to the process A running on the processor 221 to indicate that the data 1 transmission is completed, and the processor 221 switches from the kernel state to the user state according to the notification 2.

[0069] S107 : The processor 221 copies the data 1 in the cache 225 to the cache 223 according to the notification 2 .

[0070] S108: The processor 221 sends a data instruction 3 to the AI ​​accelerator 222, where the instruction 3 is used to instruct to perform AI calculation based on the data 1. The processor 221 switches from the user state to the kernel state to drive the AI ​​accelerator 222 to perform AI calculation.

[0071] S109 : The AI ​​accelerator 222 reads data 1 from the cache 223 according to instruction 3 , and performs AI calculation based on data 1 .

[0072] The process of AI calculation by the above-mentioned electronic device 200 has the following problems: First, since in the chip 210, the cache 213 accessible to the AI ​​accelerator 212 is different from the cache 215 accessible to the memory reader 214, from the output of data 1 by the AI ​​accelerator 212 to the reading of data 1 by the memory reader 214, data 1 needs to be copied from cache 213 to cache 215, occupying the processor 211 and increasing the latency. Second, since in the chip 220, the cache 223 accessible to the AI ​​accelerator 222 is different from the cache 225 accessible to the memory reader 224, from the writing of data 1 to the reading of data 1 by the AI ​​accelerator 222, data 1 needs to be copied from cache 225 to cache 223, occupying the processor 221 and increasing the latency. Third, since both the AI ​​accelerator and the memory reader are hardware devices, they need to perform corresponding operations under the scheduling of the processor, which will increase the scheduling overhead and increase the latency.

[0073] Specifically, S101 requires one switching overhead from user state to kernel state; S102 requires one interrupt scheduling overhead, one interrupt processing overhead, and one switching overhead from kernel state to user state; S103 requires one memory copy overhead; S104 requires one switching overhead from user state to kernel state; S106 requires one interrupt scheduling overhead, one interrupt processing overhead, and one switching overhead from kernel state to user state; S107 requires one memory copy overhead; S108 requires one switching overhead from user state to kernel state. All of the above steps require the participation of the processor, which will increase the processor's latency. In particular, interrupt scheduling and switching between user state and kernel state depend on the scheduling of the operating system. When the processor is busy, it will cause uncontrollable latency jitter, and the jitter time may exceed the execution time of the AI ​​calculation. Therefore, the time overhead is large.

[0074] The communication method provided in the embodiment of the present application can be used to improve the problem of large time overhead. Figure 3 A possible flow chart of a communication method provided in an embodiment of the present application. Figure 3 The communication method shown is based on the first chip performing multiple tasks and the second chip performing multiple tasks. The multiple tasks performed by the first chip include a first scheduling subtask, a first computing subtask, and a first transmission subtask. The multiple tasks performed by the second chip include a second scheduling subtask and a third computing subtask. The first chip can be coupled to the second chip, the first chip includes a first processor, a first scheduler, a first AI accelerator, and a first memory reader, and the second chip includes a second processor, a second scheduler, and a second AI accelerator.

[0075] Among them, the first chip and the second chip can both be system on chip (system on chip, SOC). The first AI accelerator, the second AI accelerator, the first scheduler and the second scheduler can all be hardware units. The first AI accelerator and the second AI accelerator can both be independent acceleration computing units, which can efficiently perform AI computing tasks. The first memory reader can be a communication module with a built-in DMA controller, and the communication module can be a hardware unit such as a PCIE device or a network port. The communication module can implement DMA technology, and the processor does not need to be involved in data transmission.

[0076] The communication method provided in the embodiment of the present application may include the following steps:

[0077] S210: The first processor outputs, to the first scheduler, an execution order of multiple tasks executed by the first chip based on a request of a first application executed by the first processor.

[0078] S220: The first scheduler outputs a first trigger signal to the first AI accelerator based on the first scheduling subtask.

[0079] S230: The first AI accelerator performs AI calculation based on the first computing subtask and in response to the first trigger signal to obtain first data, and outputs a first completion signal to the first scheduler, where the first data is the data required for the second chip to perform AI calculation; the first completion signal is used to indicate that the first computing subtask has been completed.

[0080] S240: The first scheduler outputs a second trigger signal to the first memory reader based on the first scheduling subtask and the first completion signal.

[0081] S250: The first memory reader transmits the first data to the second chip based on the first transmission subtask and in response to the second trigger signal.

[0082] In some embodiments, the execution order of each of the multiple tasks executed by the first chip is fixed to complete fixed AI computing and inter-chip communication functions. The request of the first application can be used to instruct the first processor to control each hardware unit to perform fixed AI computing and inter-chip communication functions.

[0083] In other embodiments, the execution order of each of the multiple tasks performed by the first chip is customized by the user / first application to perform corresponding AI calculations and inter-chip communication functions according to the needs of the user / first application. The request of the first application can be used to generate the execution order of each task and instruct the hardware units of the first processor to execute each task according to the execution order of each task. Furthermore, the execution order of each of the multiple tasks performed by the first chip can be changed, for example, based on the update instruction sent by the first application.

[0084] Exemplarily, the structure between each of the multiple tasks executed by the first chip can be at least one of a sequential structure, a branch structure, or a loop structure. Among them, the sequential structure means that the execution order of each of the multiple tasks is from top to bottom or from left to right, and is executed in sequence. The branch structure means that tasks of different branches are selectively executed through specified judgment conditions. The branch structure can be divided into single branch, double branch, and multiple branches. The loop structure means that part or all of the tasks in the multiple tasks are repeatedly executed. The structure between tasks can be one of a sequential structure, a branch structure, or a loop structure. Optionally, the structure between each of the multiple tasks executed by the first chip can also be other structures, and the embodiments of the present application are not limited to this.

[0085] In the communication method provided in the embodiment of the present application, the first processor only needs to send the execution order of multiple tasks executed by the first chip to the first scheduler. Since sending the execution order of multiple tasks is not included in the AI ​​computing time and communication time, the time when the first processor sends the execution order of multiple tasks does not affect the AI ​​computing time and communication time, and the first processor is less occupied.

[0086] Moreover, compared with the software-scheduled AI computing and data transmission process run by the first processor, the AI ​​computing and data transmission process of the embodiment of the present application is scheduled by the first scheduler of the hardware unit. The first scheduler outputs a first trigger signal to the first AI accelerator based on the first scheduling subtask, so that the first AI accelerator performs the first computing subtask. In response to the first trigger signal, the first AI accelerator starts to execute the first computing subtask, performs AI computing to obtain the first data, and outputs a first completion signal to the first scheduler, so that the first scheduler knows that the first computing subtask has been completed. Based on the first scheduling subtask, the first scheduler outputs a second trigger signal to the first memory reader according to the first completion signal, so that the first memory reader performs the first transmission subtask. In response to the second trigger signal, the first memory reader starts to execute the first transmission subtask and transmits the first data to the second chip. By setting the first scheduler, the AI ​​computing within the chip and the data transmission between chips are scheduled in a hardware manner, so that the communication between chips no longer depends on the processor software scheduling. In this implementation, the switching overhead of switching from user state to kernel state required by S101, the switching overhead of interrupt scheduling, interrupt processing and kernel state to user state required by S102, and the switching overhead of switching from user state to kernel state required by S104 can all be eliminated. Except for the AI ​​computing overhead of the first AI accelerator and the data transmission overhead of the first memory reader, the scheduling overhead and communication overhead of the first scheduler are small and can be ignored compared to the delay of software scheduling. Therefore, the delay and jitter caused by the scheduling and operation of the first processor can be eliminated, and the problem of large time overhead can be improved.

[0087] S260: The second processor outputs, to the second scheduler, an execution order of the plurality of tasks executed by the second chip based on a request of the second application run by the second processor.

[0088] S270: After the second chip receives the first data from the first chip, the second scheduler outputs a fifth trigger signal to the second AI accelerator based on the second scheduling subtask.

[0089] S280: The second AI accelerator performs AI calculation based on the first data based on the third computing subtask and in response to the fifth trigger signal.

[0090] In some embodiments, the execution order of each of the multiple tasks executed by the second chip is fixed to complete fixed AI computing and inter-chip communication functions. The request of the second application can be used to instruct the second processor to control each hardware unit to perform fixed AI computing and inter-chip communication functions.

[0091] In other embodiments, the execution order of each of the multiple tasks performed by the second chip is customized by the user / second application to perform corresponding AI calculations and inter-chip communication functions according to the needs of the user / second application. The request of the second application can be used to generate the execution order of each task and instruct the hardware units of the second processor to execute each task according to the execution order of each task. Furthermore, the execution order of each of the multiple tasks performed by the second chip can be changed, for example, based on the update instruction sent by the second application.

[0092] Exemplarily, the structure between each of the multiple tasks executed by the second chip can be at least one of a sequential structure, a branch structure, or a loop structure. Optionally, the structure between each of the multiple tasks executed by the second chip can also be other structures, which is not limited in the embodiments of the present application.

[0093] In the communication method provided in the embodiment of the present application, the second processor only needs to send the execution order of multiple tasks executed by the second chip to the second scheduler. Since the execution order of sending multiple tasks is not included in the AI ​​computing time and communication time, the time when the second processor sends the execution order of multiple tasks does not affect the AI ​​computing time and communication time, and the second processor is less occupied.

[0094] Moreover, compared with the software-scheduled AI computing and data transmission process run by the second processor, the AI ​​computing and data transmission process of the embodiment of the present application is scheduled by the second scheduler of the hardware unit. The second scheduler can actively or passively know whether the second chip receives the first data from the first chip, and then the second scheduler outputs a fifth trigger signal to the second AI accelerator based on the second scheduling subtask, so that the second AI accelerator performs the third computing subtask based on the first data. In response to the fifth trigger signal, the second AI accelerator starts to execute the third computing subtask and performs AI computing based on the first data. The second AI accelerator can only execute the third computing subtask when the second scheduler confirms that the first data has arrived. By setting the second scheduler, the inter-chip data transmission and the intra-chip AI computing are scheduled in a hardware manner, so that the inter-chip communication no longer depends on the processor software scheduling. In this embodiment, the switching overhead of the user state switching to the kernel state required by S108 can be eliminated. In addition to the AI ​​computing overhead of the second AI accelerator, the scheduling overhead and communication overhead of the second scheduler are small, which can be ignored compared to the delay of software scheduling. In this way, the delay and jitter caused by the scheduling and operation of the second processor can be removed, and the problem of large time overhead can be improved.

[0095] During the data transmission process between multiple chips, the processor offloads the scheduling task to the hardware scheduler for execution. The above introduces the process of the hardware scheduler scheduling data transmission between chips. Next, an example is given to illustrate how the hardware scheduler determines the data transmission time.

[0096] In one possible implementation, S240 (the first scheduler outputs a second trigger signal to the first memory reader based on the first scheduling subtask according to the first completion signal) may include: the first scheduler outputs a second trigger signal to the first memory reader at a first time interval based on the first scheduling subtask. The first time period is greater than the time for the second chip to perform AI calculations each time. In this way, by transmitting data to the second chip at a regular interval, it can be ensured that the first chip and the second chip are processed serially, avoiding the first chip sending the first data to be processed this time to the second chip before the second chip has processed the data to be processed last time, causing data trampling.

[0097] In another possible implementation, S240 (the first scheduler outputs a second trigger signal to the first memory reader based on the first scheduling subtask and according to the first completion signal) may include: the first scheduler outputs a second trigger signal to the first memory reader based on the first scheduling subtask and in response to the first indication signal and according to the first completion signal, the first indication signal being used to indicate that the second chip has processed the second data, and the second data is the data obtained by the previous AI calculation of the first AI accelerator.

[0098] Among them, the first scheduler can actively check whether the first indication signal is received. Exemplarily, the second chip can store the information (such as 0) carried by the first indication signal in the first register of the first chip. For example, the first register can be a PCIE base address register (BAR) address mapping space. The first scheduler can periodically search for event data at the corresponding position of the first register. If the event data is 1, it means that the first scheduler has not received the first indication signal. If the event data is 0, it means that the first scheduler has received the first indication signal.

[0099] In the communication method provided in the embodiment of the present application, the first scheduler can learn from the first indication signal that the second chip has processed the second data sent last time, and the accelerator of the second chip is in an idle state. At this time, the first scheduler can output a second trigger signal to the first memory reader to schedule the first memory reader to transmit the first data to the second chip. In this way, the first chip and the second chip can be processed serially to avoid the first chip sending the first data to be processed this time to the second chip before the second chip has processed the second data sent last time, causing data trampling. In addition, compared with the method of transmitting data to the second chip at a fixed time, the time for transmitting the first data to the second chip can be flexibly set according to the first indication signal, which can further reduce the time overhead.

[0100] In this embodiment, S280 (the second AI accelerator performs AI calculations based on the first data based on the third computing subtask and in response to the fifth trigger signal) may specifically include: the second AI accelerator performs AI calculations based on the first data based on the third computing subtask and in response to the fifth trigger signal, and outputs a second completion signal to the second scheduler, where the second completion signal is used to indicate that the execution of the AI ​​calculations based on the first data is completed.

[0101] The method further includes S290: the second scheduler sends a third notification signal to the first chip based on the second scheduling subtask and the second completion signal, where the third notification signal is used to indicate that the second chip has processed the first data.

[0102] In the communication method provided in the embodiment of the present application, the second scheduler learns from the second completion signal from the second AI accelerator that the second AI accelerator has completed the AI ​​calculation based on the first data, and the second scheduler can send a third notification signal to the first chip to indicate that the second chip has processed the first data, and the first chip can send the data required for the next AI calculation. In this way, the first chip and the second chip can execute data interaction and AI calculation in multiple cycles, and the first chip and the second chip can be guaranteed to be processed serially to avoid the first chip sending the next data to be processed to the second chip before the second chip has processed the first data sent last time, causing data trampling. In addition, compared to the method of transmitting data to the second chip at a fixed time, the time required for transmitting the next AI calculation to the second chip can be flexibly set according to the third notification signal, which can further reduce time overhead.

[0103] In some embodiments, please refer to Figure 4 The first chip further includes a first notification circuit, and the plurality of tasks further include a first notification subtask. The method further includes S231: the first notification circuit receives a first notification signal from the second chip based on the first notification subtask, and outputs a first indication signal obtained according to the first notification signal to the first scheduler, wherein the first notification signal is used to indicate that the second chip has processed the second data.

[0104] Among them, the first scheduler can passively receive the first indication signal. Exemplarily, the second chip can store the information (such as 0) carried by the first notification signal in the first register of the first chip. The first notification circuit can periodically search for event data at the corresponding position of the first register. If the event data is 1, it means that the first notification circuit has not received the first notification signal. If the event data is 0, it means that the first notification circuit has received the first notification signal. After the first notification circuit receives the first notification signal, the event data in the first register is reset to 1 again. Exemplarily, the first notification circuit parses the first notification signal to obtain the first indication signal, and outputs the first indication signal to the first scheduler.

[0105] In the communication method provided in the embodiment of the present application, the first chip also includes a first notification circuit, which receives a first notification signal from the second chip based on the first notification subtask, obtains a first indication signal according to the first notification signal, and outputs the first indication signal to the first scheduler. In this way, the first scheduler does not need to actively check whether the first indication signal is received at regular intervals, but passively receives the first indication signal from the first notification circuit, which can reduce the occupancy of the first scheduler, speed up the scheduling speed, and further reduce the time overhead.

[0106] In this embodiment, please refer to Figure 4The second chip further includes a second notification circuit, and the plurality of tasks further include a second notification subtask. S290: (the second scheduler sends a third notification signal to the first chip based on the second scheduling subtask and the second completion signal) may specifically include:

[0107] S291: The second scheduler outputs a sixth trigger signal to the second notification circuit based on the second scheduling subtask and the second completion signal.

[0108] S292: The second notification circuit sends a third notification signal to the first chip based on the second notification subtask and in response to the sixth trigger signal.

[0109] S293: The second notification circuit outputs a third completion signal to the second scheduler based on the second notification subtask, where the third completion signal is used to indicate that the third notification signal has been sent to the first chip.

[0110] In the communication method provided in the embodiment of the present application, the second chip also includes a second notification circuit, and the second scheduler dispatches the second notification circuit to send a third notification signal to the first chip by outputting a sixth trigger signal to the second notification circuit. In this way, the second scheduler does not need to write the information carried by the third notification signal into the first chip, but only needs to output the sixth trigger signal to the second notification circuit inside the second chip. Since the operation of outputting the sixth trigger signal is relatively simple, the occupancy of the second scheduler can be reduced, the scheduling speed can be accelerated, and the time overhead can be further reduced.

[0111] In one possible implementation, please refer to Figure 4 , after S250 (the first memory reader transmits the first data to the second chip in response to the second trigger signal based on the first transmission subtask), the method may further include:

[0112] S251: The first memory reader sends a fourth completion signal to the first scheduler based on the first transmission subtask, where the fourth completion signal is used to indicate that the first data has been transmitted to the second chip.

[0113] S252: After the first memory reader transmits the first data to the second chip, the first scheduler outputs a third trigger signal to the first notification circuit based on the first scheduling subtask.

[0114] S253: The first notification circuit sends a second notification signal to the second chip based on the first notification subtask and in response to the third trigger signal, where the second notification signal is used to instruct the second chip to perform AI calculation based on the first data.

[0115] S254: The first notification circuit sends a fifth completion signal to the first scheduler based on the first notification subtask, where the fifth completion signal is used to indicate that the second notification signal has been sent to the second chip.

[0116] In the communication method provided in the embodiment of the present application, after the first memory reader transmits the first data to the second chip, the first scheduler outputs a third trigger signal to the first notification circuit, scheduling the first notification circuit to send a second notification signal to the second chip, so that the second chip knows that the first data has been transmitted to the second chip, so that the second chip can perform AI calculation based on the first data. In this way, the first chip and the second chip can be processed serially, avoiding the second chip being unable to determine the time to execute the third calculation subtask (AI calculation based on the first data).

[0117] In this embodiment, please refer to Figure 4 The method may also include S255: the second notification circuit receives a second notification signal from the first chip based on the second notification subtask, and outputs a second indication signal obtained according to the second notification signal to the second scheduler, wherein the second notification signal is used to instruct the second chip to perform AI calculation based on the first data, and the second indication signal is used to instruct the second scheduler to output a fifth trigger signal to the second AI accelerator.

[0118] Among them, the second scheduler can passively receive the second indication signal. Exemplarily, the first chip can store the information (such as 0) carried by the second notification signal in the second register of the second chip. For example, the second register can be a PCIE base address register (BAR) address mapping space. The second notification circuit can periodically search for event data at the corresponding position of the second register. If the event data is 1, it means that the second notification circuit has not received the second notification signal. If the event data is 0, it means that the second notification circuit has received the second notification signal. After the second notification circuit receives the second notification signal, the event data in the second register is reset to 1 again. Exemplarily, the second notification circuit parses the second notification signal to obtain the second indication signal, and outputs the second indication signal to the second scheduler.

[0119] In the communication method provided in the embodiment of the present application, the second notification circuit receives the second notification signal from the first chip based on the second notification subtask, and then obtains the second indication signal according to the second notification signal, and outputs the second indication signal to the second scheduler. In this way, the second chip can be informed that the first data has been transmitted to the second chip, ensuring that the first chip and the second chip are processed in series, and avoiding the second chip from being unable to determine the time to execute the third calculation subtask (AI calculation based on the first data). In addition, the second scheduler does not have to actively check whether the second indication signal is received at regular intervals, but passively receives the second indication signal from the second notification circuit, which can reduce the occupancy of the second scheduler, speed up the scheduling speed, and further reduce the time overhead. In addition, the one interrupt scheduling overhead, one interrupt processing overhead, and one kernel state to user state switching overhead required by S106 can be eliminated, thereby removing the delay and jitter caused by the scheduling and operation of the second processor.

[0120] In another possible implementation, please refer to Figure 5 , after S250 (the first memory reader transmits the first data to the second chip in response to the second trigger signal based on the first transmission subtask), the method may further include:

[0121] S256: After transmitting the first data to the second chip, the first memory reader sends a second notification signal to the second chip based on the first transmission subtask, where the second notification signal is used to instruct the second chip to perform AI calculation based on the first data.

[0122] S257: The first memory reader sends a fifth completion signal to the first scheduler based on the first transmission subtask, where the fifth completion signal is used to indicate that the second notification signal has been sent to the second chip.

[0123] In the communication method provided in the embodiment of the present application, the first transmission subtask may include sending a second notification signal to the second chip, and the second notification signal is sent by the first memory reader to the second chip. Compared with the method in which the second notification signal is sent by the first notification circuit to the second chip (such as steps S251 to S254), this implementation can save the step of the first scheduler knowing that the first memory reader transmits the first data to the second chip, and can save the step of the first scheduler sending the third trigger signal to the first notification circuit.

[0124] In this embodiment, please refer to Figure 5The second chip may further include a second memory reader. The method may further include S258: the second memory reader receives a second notification signal from the first chip based on the second transmission subtask, and outputs a second indication signal obtained according to the second notification signal to the second scheduler, wherein the second notification signal is used to instruct the second chip to perform AI calculation based on the first data, and the second indication signal is used to instruct the second scheduler to output a fifth trigger signal to the second AI accelerator.

[0125] Exemplarily, the second memory reader may be a communication module with a built-in DMA controller. The communication module may be a hardware unit such as a PCIE device or a network port. The communication module may implement DMA technology, and data transmission does not require processor involvement.

[0126] In the communication method provided in an embodiment of the present application, the second transmission subtask may include receiving a second notification signal from the first chip, the second notification signal is received by the second memory reader, and the second indication signal is sent by the second memory reader to the second scheduler.

[0127] The above describes possible implementation methods of data transmission and notification signal transmission between the first chip and the second chip. Next, examples are given to illustrate the data cache methods inside the first chip and the second chip.

[0128] In one possible implementation, please refer to Figure 4 and Figure 5 , the first chip also includes a first memory. S230 (the first AI accelerator performs AI calculation based on the first computing subtask and responds to the first trigger signal to obtain the first data, and specifically includes: the first AI accelerator performs AI calculation based on the first computing subtask and responds to the first trigger signal to obtain the first data, and writes the first data into the first storage space of the first memory. S250 (the first memory reader transmits the first data to the second chip based on the first transmission subtask and responds to the second trigger signal) specifically includes: the first memory reader reads the first data from the first storage space based on the first transmission subtask and responds to the second trigger signal, and transmits the first data to the second chip.

[0129] Exemplarily, the first memory may be a memory of the first chip, for example, a double data rate synchronous dynamic random access memory (DDR). The first storage space is a memory space accessible to both the first AI accelerator and the first memory reader, and access includes reading and / or writing. Before the first processor issues multiple tasks to be executed by the first chip, it is necessary to apply for the first storage space in the memory in advance for access by the first AI accelerator and the first memory reader.

[0130] In the communication method provided in the embodiment of the present application, the storage space where the first AI accelerator outputs the first data and the storage space accessed by the first memory reader when acquiring the first data are both the first storage space in the first memory, and no data copying is required. In this way, the one-time memory copy overhead required in S103 can be eliminated, further reducing the time overhead and reducing the storage space bandwidth requirement.

[0131] In this embodiment, please refer to Figure 4 and Figure 5 The second chip also includes a second memory, and the second storage space of the second memory is used to store the first data. The second storage space is a storage space for the second chip to perform memory registration (memory registration, MR) for the first chip.

[0132] S250 (the first memory reader transmits the first data to the second chip based on the first transmission subtask and in response to the second trigger signal) may specifically include: the first memory reader writes the first data in the second storage space of the second chip based on the first transmission subtask and in response to the second trigger signal.

[0133] S280 (the second AI accelerator performs AI calculation based on the first data based on the third computing subtask and in response to the fifth trigger signal) may specifically include: the second AI accelerator reads the first data from the second storage space based on the third computing subtask and in response to the fifth trigger signal, and performs AI calculation based on the first data.

[0134] Exemplarily, the second memory may be a memory of the second chip such as (DDR). The second storage space is a memory space accessible to both the second AI accelerator and the first memory reader, and access includes reading and / or writing. Before the second processor issues multiple tasks to be executed by the second chip, it is necessary to apply for the second storage space in the memory in advance for access by the first AI accelerator and the first memory reader.

[0135] In the communication method provided in the embodiment of the present application, the second storage space in the second memory is the storage space in which the second chip is registered (MR) for the first chip. The storage space in which the first memory reader writes the first data in the second chip and the storage space accessed by the second AI accelerator when acquiring the first data are both the second storage space in the second memory, and no data copying is required. In this way, the one-time memory copy overhead required by S107 can be eliminated, further reducing the time overhead, and reducing the storage space bandwidth requirements.

[0136] Next, combine Figure 6The first scheduling subtask and the second scheduling subtask are introduced from the perspective of transmitting data from the first chip 310 to the second chip 320. Exemplarily, the first chip 310 includes a first scheduler 311, a first AI accelerator 312, a first memory reader 313, and a first notification circuit 314, and the second chip 320 includes a second scheduler 321, a second AI accelerator 322, and a second notification circuit 323.

[0137] The first scheduling subtask includes information required to trigger each hardware unit to perform the corresponding task, such as the input and output addresses of the first AI accelerator, the input and output information of the first memory reader, the event data and address information required by the first notification circuit, and the execution order of each subtask.

[0138] The first scheduling subtask may specifically include: the first scheduler 311 schedules the first AI accelerator 312 to perform AI calculation to obtain the first data, and writes the first data into the first storage space. When the first indication signal obtained according to the first notification signal is not received, the first scheduler 311 waits. When the first indication signal is received, the first scheduler 311 schedules the first memory reader 313 to read the first data from the first storage space, and writes the first data into the second storage space of the second chip 320. Then, the first scheduler 311 schedules the first notification circuit 314 to send a second notification signal to the second chip 320.

[0139] The second scheduling subtask includes the information required to trigger each hardware unit to perform the corresponding task, such as the input and output addresses of the second AI accelerator and the event data and address information required by the second notification circuit, as well as the execution order of each subtask.

[0140] The second scheduling subtask may specifically include: after the second scheduler 321 performs the AI ​​calculation last time, the second notification circuit 323 is scheduled to send a first notification signal to the first chip 310, so that the first scheduler 311 receives the first indication signal obtained according to the first notification signal. When the second indication signal obtained according to the second notification signal is not received, the second scheduler 321 waits. When the second indication signal is received, the second scheduler 321 schedules the second AI accelerator 322 to read the first data from the second storage space and perform AI calculation based on the first data. After the AI ​​calculation based on the first data is completed, the second scheduler 321 schedules the second notification circuit 323 to send a third notification signal to the first chip 310.

[0141] For example, when the first chip performs AI calculations for the first time, the first scheduler can directly schedule the first memory reader to perform data transmission without waiting for an indication signal. When the second chip performs AI calculations for the first time, the second scheduler needs to wait for an indication signal before scheduling the second AI accelerator to perform AI calculations on the second data.

[0142] In one possible implementation, please refer to Figure 7 , the operating system of the first chip includes a user state and a kernel state. The operating system of the first chip can control the hardware to perform multiple tasks. The user state of the first chip includes a first process and a first interface, the kernel state of the first chip includes a driver of a first scheduler, a driver of a first AI accelerator, and a driver of a first memory reader, and the hardware of the first chip includes a first scheduler, a first AI accelerator, a first notification circuit, and a first memory reader. The multiple tasks performed by the first chip may include a first scheduling task, a first computing task, a first transmission task, and a first notification task.

[0143] The control flow of the first chip may include: the first process run by the first processor may call the driver of the first scheduler through the first interface to send the first scheduling task to the first scheduler, send the first notification task to the first notification circuit, call the driver of the first AI accelerator to send the first computing task to the first AI accelerator, and call the driver of the first memory reader to send the first transmission task to the first memory reader. The first scheduler schedules the first AI accelerator to perform the first computing task, schedules the first notification circuit to perform the first notification task, and schedules the first memory reader to perform the first transmission task based on the first scheduling task. Each of the above tasks may include multiple subtasks. For example, the first computing task includes multiple computing subtasks, and each execution of an AI calculation is regarded as executing a computing subtask.

[0144] Taking the transmission of the first data as an example, the data flow of the first chip may include: the first process obtains the initial data, sends the initial data to the driver of the first scheduler through the first interface, and then sends it to the first scheduler. The first scheduler sends the initial data to the first AI accelerator to perform the first computing subtask (perform AI computing based on the initial data) to obtain the first data, the first memory reader obtains the first data, and transmits the first data to the second chip through inter-chip communication.

[0145] In another possible implementation, please refer to Figure 8 , the operating system of the second chip includes a user state and a kernel state. The operating system of the second chip can control the hardware to perform multiple tasks. The user state of the second chip includes a second process and a second interface, the kernel state of the second chip includes a driver for a second scheduler, a driver for a second AI accelerator, and a driver for a second memory reader, and the hardware of the second chip includes a second scheduler, a second AI accelerator, a second notification circuit, and a second memory reader. The multiple tasks performed by the second chip may include a second scheduling task, a second computing task, a second transmission task, and a second notification task.

[0146] The control flow of the second chip may include: the second process run by the second processor may call the driver of the second scheduler through the second interface to send the second scheduling task to the second scheduler, send the second notification task to the second notification circuit, call the driver of the second AI accelerator to send the second computing task to the second AI accelerator, and call the driver of the second memory reader to send the second transmission task to the second memory reader. The second scheduler schedules the second AI accelerator to perform the second computing task, schedules the second notification circuit to perform the second notification task, and schedules the second memory reader to perform the second transmission task based on the second scheduling task. Each of the above tasks may include multiple subtasks. For example, the second computing task includes multiple computing subtasks, and each execution of an AI calculation is regarded as executing a computing subtask.

[0147] Taking the transmission of the first data as an example, the data flow of the second chip may include: the second AI accelerator obtains the first data through inter-chip communication, the second AI accelerator performs the third computing subtask (performs AI computing based on the first data) to obtain the third data. The second AI accelerator sends the third data to the driver of the second AI accelerator, and then sends it to the second process through the second interface.

[0148] The above is an introduction from the perspective of data transmission from the first chip to the second chip. Next, an introduction is made from the perspective of data transmission from the second chip to the first chip.

[0149] In a possible implementation, the multiple tasks executed by the first chip also include a second computing subtask, and the method further includes: after the first chip receives the third data from the second chip, the first scheduler outputs a fourth trigger signal to the first AI accelerator based on the first scheduling subtask, and the third data is data obtained by the second chip performing AI computing based on the first data. Based on the second computing subtask, the first AI accelerator performs AI computing based on the third data in response to the fourth trigger signal.

[0150] In the communication method provided in the embodiment of the present application, the first chip can also receive the third data from the second chip, and the first scheduler outputs the fourth trigger signal to the first AI accelerator based on the first scheduling subtask to schedule the first AI accelerator to perform AI calculation based on the third calculation subtask and the third data. In this way, the communication method provided in the embodiment of the present application can be applied to a variety of data interaction scenarios.

[0151] In this embodiment, the second chip further includes a second memory reader, and the plurality of tasks further include a second transmission subtask. The method further includes: after the second AI accelerator completes the AI ​​calculation based on the first data, the second scheduler outputs a seventh trigger signal to the second memory reader based on the second scheduling subtask. The second memory reader transmits third data to the first chip in response to the seventh trigger signal based on the second transmission subtask, and the third data is data obtained by the second AI accelerator performing AI calculation based on the first data.

[0152] In the communication method provided in the embodiment of the present application, the second scheduler can also output a seventh trigger signal to the second memory reader based on the second scheduling subtask to schedule the second memory reader to transmit the third data to the first chip based on the second transmission subtask. In this way, the communication method provided in the embodiment of the present application can be applied to a variety of data interaction scenarios.

[0153] In a possible implementation, the communication method provided in the embodiment of the present application can be applied to collaboratively completing subtasks between multiple chips, and is not limited to collaboratively completing subtasks between two chips.

[0154] In low-cost intelligent driving system solutions, the hardware capabilities of a single chip, such as processors and AI accelerators, are often insufficient, and two or even more chips are needed to form different solutions of low cost, medium cost, and high cost, so as to support different intelligent driving experiences, and the communication efficiency between chips is very important. At present, the communication between chips is generally connected by PCIE devices. PCIE devices have the characteristics of large bandwidth and low latency, and can provide high-performance communication means. However, in the end-to-end communication link from the sender to the receiver, data copying and communication scheduling often become communication bottlenecks, resulting in a sharp decline in end-to-end communication performance. The present invention realizes end-to-end high-performance communication by adopting means such as hardware scheduler and data copy-free chip, and the communication scheduling delay can be reduced to less than 1us.

[0155] The above mainly introduces the first chip and the second chip of the communication method and the application of the communication method. It can be understood that in order to realize the above functions, the first chip and the second chip include hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the structures and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0156] The embodiment of the present application can divide the functional modules according to the communication device corresponding to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0157] When each module is divided from the hardware perspective, Fig. 9 A possible structural schematic diagram of the communication device 400 involved in the above embodiment is shown. The communication device 400 is applied to the first chip, and the communication device 400 is configured to perform multiple tasks, including a first scheduling subtask, a first computing subtask and a first transmission subtask. The communication device 400 includes a first scheduler 410, a first AI accelerator 420 and a first memory reader 430. The first scheduler 410 is used to output a first trigger signal to the first AI accelerator 420 based on the first scheduling subtask. The first AI accelerator 420 is used to perform AI calculation based on the first computing subtask in response to the first trigger signal to obtain the first data, and output a first completion signal to the first scheduler 410, wherein the first data is the required data for the second chip to perform AI calculation; the first completion signal is used to indicate that the first computing subtask has been completed. The first scheduler 410 is used to output a second trigger signal to the first memory reader 430 based on the first scheduling subtask according to the first completion signal. The first memory reader 430 is used to transmit the first data to the second chip in response to the second trigger signal based on the first transmission subtask.

[0158] In one possible implementation, the first scheduler 410 is specifically used to, based on the first scheduling subtask, respond to the first indication signal, and output a second trigger signal to the first memory reader 430 according to the first completion signal, wherein the first indication signal is used to indicate that the second chip has processed the second data, and the second data is the data obtained by the previous AI calculation of the first AI accelerator 420.

[0159] In a possible implementation, the communication device 400 further includes a first notification circuit, and the plurality of tasks further include a first notification subtask. The first notification circuit is configured to receive a first notification signal from the second chip based on the first notification subtask, and output a first indication signal obtained according to the first notification signal to the first scheduler 410, wherein the first notification signal is configured to indicate that the second chip has processed the second data.

[0160] In a possible implementation, after the first memory reader 430 transmits the first data to the second chip, the first scheduler 410 is further configured to output a third trigger signal to the first notification circuit based on the first scheduling subtask. The first notification circuit is further configured to send a second notification signal to the second chip in response to the third trigger signal based on the first notification subtask, wherein the second notification signal is used to instruct the second chip to perform AI calculation based on the first data.

[0161] In a possible implementation, the communication device 400 further includes a first memory. The first AI accelerator 420 is specifically configured to perform AI calculation based on the first computing subtask and in response to the first trigger signal to obtain the first data, and write the first data into the first storage space of the first memory. The first memory reader 430 is specifically configured to read the first data from the first storage space and transmit the first data to the second chip in response to the second trigger signal based on the first transmission subtask.

[0162] In a possible implementation, the multiple tasks further include a second computing subtask. After the first chip receives the third data from the second chip, the first scheduler 410 is further configured to output a fourth trigger signal to the first AI accelerator 420 based on the first scheduling subtask, where the third data is data obtained by the second chip performing AI computing based on the first data. The first AI accelerator 420 is further configured to perform AI computing based on the third data in response to the fourth trigger signal based on the second computing subtask.

[0163] In a possible implementation, the first chip further includes a first processor. The first processor is configured to output the execution order of the multiple tasks to the first scheduler 410 based on a request of a first application executed by the first processor.

[0164] The various components of the above-mentioned communication device 400 provided in the embodiment of the present application are respectively used to implement the functions of the corresponding steps of the above-mentioned communication method. Since each step has been described in detail in the above-mentioned communication method embodiment, it will not be repeated here.

[0165] Fig.10 Another possible structural diagram of the communication device 500 involved in the above embodiment is shown. The communication device 500 is applied to the second chip, and the communication device 500 is configured to perform multiple tasks, including a second scheduling subtask and a third computing subtask. The communication device 500 includes a second scheduler 510 and a second AI accelerator 520. After the second chip receives the first data from the first chip, the second scheduler 510 is used to output a fifth trigger signal to the second AI accelerator 520 based on the second scheduling subtask. The second AI accelerator 520 is used to perform AI calculation based on the first data in response to the fifth trigger signal based on the third computing subtask.

[0166] In a possible implementation, the second AI accelerator 520 is specifically configured to perform AI calculation based on the first data in response to the fifth trigger signal based on the third calculation subtask, and output a second completion signal to the second scheduler 510, where the second completion signal is used to indicate that the AI ​​calculation based on the first data is completed. The second scheduler 510 is further configured to send a third notification signal to the first chip based on the second scheduling subtask according to the second completion signal, where the third notification signal is used to indicate that the second chip has processed the first data.

[0167] In a possible implementation, the second chip further includes a second notification circuit, and the plurality of tasks further include a second notification subtask;

[0168] The second scheduler 510 is specifically configured to output a sixth trigger signal to the second notification circuit based on the second scheduling subtask and according to the second completion signal. The second notification circuit is specifically configured to send a third notification signal to the first chip in response to the sixth trigger signal based on the second notification subtask.

[0169] In one possible implementation, the second notification circuit is further used to receive a second notification signal from the first chip based on the second notification subtask, and output a second indication signal obtained according to the second notification signal to the second scheduler 510, wherein the second notification signal is used to instruct the second chip to perform AI calculations based on the first data, and the second indication signal is used to instruct the second scheduler 510 to output a fifth trigger signal to the second AI accelerator 520.

[0170] In a possible implementation, the second chip further includes a second memory, and the second storage space of the second memory is used to store the first data, and the second storage space is a storage space in which the second chip is registered (MR) for the first chip. The second AI accelerator 520 is specifically configured to read the first data from the second storage space based on the third computing subtask and respond to the fifth trigger signal, and perform AI computing based on the first data.

[0171] In a possible implementation, the second chip further includes a second memory reader, and the plurality of tasks further include a second transmission subtask. After the second AI accelerator 520 completes the AI ​​calculation based on the first data, the second scheduler 510 is further configured to output a seventh trigger signal to the second memory reader based on the second scheduling subtask. The second memory reader is further configured to transmit third data to the first chip in response to the seventh trigger signal based on the second transmission subtask, the third data being data obtained by the second AI accelerator 520 performing AI calculation based on the first data.

[0172] In a possible implementation, the second chip further includes a second processor. The second processor is further configured to output the execution order of the multiple tasks to the second scheduler 510 based on a request of a second application executed by the second processor.

[0173] The various components of the above-mentioned communication device 500 provided in the embodiment of the present application are respectively used to implement the functions of the corresponding steps of the above-mentioned communication method. Since each step has been described in detail in the above-mentioned communication method embodiment, it will not be repeated here.

[0174] The present application also provides a chip system, please refer to Fig.11 The chip system 600 includes a first chip 610 and a second chip 620. The first chip 610 may include Fig. 9 In the communication device 400 shown, the second chip 620 may include Fig.10 The components of the chip system 600 provided in the embodiment of the present application are respectively used to implement the functions of the corresponding steps of the aforementioned communication method. Since the various steps have been described in detail in the aforementioned communication method embodiment, they will not be repeated here.

[0175] The present application also provides an electronic device. Fig.12 The electronic device 700 includes an interface circuit 710 and Fig.11 The chip system 600 is shown. The interface circuit 710 is coupled to the chip system 600. The electronic device 700 supports the execution of at least one step in the above method embodiment. The above electronic device 700 provided in the embodiment of the present application is used to implement the functions of the corresponding steps of the above communication method. Since each step has been described in detail in the above communication method embodiment, it will not be repeated here.

[0176] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A communication method, characterized in that: The method executes a plurality of tasks based on a first chip, the plurality of tasks including a first scheduling subtask, a first computing subtask, and a first transmission subtask, the first chip including a first scheduler, a first AI accelerator, and a first memory reader, and the method includes: The first scheduler outputs a first trigger signal to the first AI accelerator based on the first scheduling subtask; The first AI accelerator performs AI calculation based on the first computing subtask and in response to the first trigger signal to obtain first data, and outputs a first completion signal to the first scheduler, where the first data is data required for the second chip to perform AI calculation; the first completion signal is used to indicate that the first computing subtask has been completed; The first scheduler outputs a second trigger signal to the first memory reader based on the first scheduling subtask and according to the first completion signal; The first memory reader transmits the first data to the second chip based on the first transmission subtask and in response to the second trigger signal.

2. The method according to claim 1, characterized in that The first scheduler outputs a second trigger signal to the first memory reader based on the first scheduling subtask and according to the first completion signal, including: Based on the first scheduling subtask, the first scheduler responds to the first indication signal and outputs the second trigger signal to the first memory reader according to the first completion signal, wherein the first indication signal is used to indicate that the second chip has processed the second data, and the second data is the data obtained by the previous AI calculation of the first AI accelerator.

3. The method according to claim 2, characterized in that The first chip further includes a first notification circuit, the plurality of tasks further include a first notification subtask; and the method further includes: The first notification circuit receives a first notification signal from the second chip based on the first notification subtask, and outputs the first indication signal obtained according to the first notification signal to the first scheduler, wherein the first notification signal is used to indicate that the second chip has processed the second data.

4. The method according to claim 3, characterized in that The method further comprises: After the first memory reader transmits the first data to the second chip, the first scheduler outputs a third trigger signal to the first notification circuit based on the first scheduling subtask; Based on the first notification subtask, the first notification circuit sends a second notification signal to the second chip in response to the third trigger signal, where the second notification signal is used to instruct the second chip to perform AI calculation based on the first data.

5. The method according to any one of claims 1 to 4, characterized in that: The first chip also includes a first memory, The first AI accelerator performs AI calculation based on the first computing subtask and in response to the first trigger signal to obtain first data, including: The first AI accelerator performs AI calculation based on the first computing subtask and in response to the first trigger signal to obtain the first data, and writes the first data into a first storage space of the first memory; The first memory reader transmits the first data to the second chip based on the first transmission subtask and in response to the second trigger signal, including: Based on the first transmission subtask and in response to the second trigger signal, the first memory reader reads the first data from the first storage space and transmits the first data to the second chip.

6. The method according to any one of claims 1 to 5, characterized in that: The plurality of tasks further include a second computing subtask, and the method further includes: After the first chip receives the third data from the second chip, the first scheduler outputs a fourth trigger signal to the first AI accelerator based on the first scheduling subtask, where the third data is data obtained by the second chip performing AI calculation based on the first data; The first AI accelerator performs AI computing based on the third data in response to the fourth trigger signal based on the second computing subtask.

7. The method according to any one of claims 1 to 6, characterized in that: The first chip further includes a first processor, and the method further includes: The first processor outputs the execution order of the plurality of tasks to the first scheduler based on a request of a first application executed by the first processor.

8. A communication method, characterized in that: The method executes a plurality of tasks based on a second chip, the plurality of tasks including a second scheduling subtask and a third computing subtask, the second chip including a second scheduler and a second AI accelerator, and the method including: After the second chip receives the first data from the first chip, the second scheduler outputs a fifth trigger signal to the second AI accelerator based on the second scheduling subtask; The second AI accelerator performs AI calculation based on the first data in response to the fifth trigger signal based on the third computing subtask.

9. The method according to claim 8, characterized in that The second AI accelerator performs AI calculation based on the first data in response to the fifth trigger signal based on the third computing subtask, including: The second AI accelerator performs AI calculation based on the first data in response to the fifth trigger signal based on the third computing subtask, and outputs a second completion signal to the second scheduler, where the second completion signal is used to indicate that the execution of the AI ​​calculation based on the first data is completed; The method further comprises: The second scheduler sends a third notification signal to the first chip based on the second scheduling subtask and according to the second completion signal, where the third notification signal is used to indicate that the second chip has processed the first data.

10. The method according to claim 9, characterized in that The second chip further includes a second notification circuit, and the plurality of tasks further include a second notification subtask; The second scheduler sends a third notification signal to the first chip based on the second scheduling subtask and according to the second completion signal, including: The second scheduler outputs a sixth trigger signal to the second notification circuit based on the second scheduling subtask and according to the second completion signal; The second notification circuit sends the third notification signal to the first chip based on the second notification subtask and in response to the sixth trigger signal.

11. The method according to claim 10, characterized in that The method further comprises: The second notification circuit receives a second notification signal from the first chip based on the second notification subtask, and outputs a second indication signal obtained according to the second notification signal to the second scheduler, wherein the second notification signal is used to instruct the second chip to perform AI calculation based on the first data, and the second indication signal is used to instruct the second scheduler to output the fifth trigger signal to the second AI accelerator.

12. The method according to any one of claims 8 to 11, characterized in that The second chip further includes a second memory, a second storage space of the second memory is used to store the first data, and the second storage space is a storage space where the second chip is registered (MR) for the first chip; The second AI accelerator performs AI calculation based on the first data in response to the fifth trigger signal based on the third computing subtask, including: Based on the third computing subtask, the second AI accelerator responds to the fifth trigger signal, reads the first data from the second storage space, and performs AI computing based on the first data.

13. The method according to any one of claims 8 to 12, characterized in that: The second chip further includes a second memory reader, the plurality of tasks further include a second transmission subtask; and the method further includes: After the second AI accelerator completes AI calculation based on the first data, the second scheduler outputs a seventh trigger signal to the second memory reader based on the second scheduling subtask; Based on the second transmission subtask, the second memory reader transmits third data to the first chip in response to the seventh trigger signal, where the third data is data obtained by the second AI accelerator performing AI calculation based on the first data.

14. The method according to any one of claims 8 to 13, characterized in that The second chip further includes a second processor, and the method further includes: The second processor outputs the execution order of the plurality of tasks to the second scheduler based on a request of a second application executed by the second processor.

15. A communication device, characterized in that: The device is applied to a first chip, the device is configured to perform multiple tasks, the multiple tasks include a first scheduling subtask, a first computing subtask and a first transmission subtask, and the device includes a first scheduler, a first AI accelerator and a first memory reader; The first scheduler is configured to output a first trigger signal to the first AI accelerator based on the first scheduling subtask; The first AI accelerator is used to perform AI calculation based on the first computing subtask and in response to the first trigger signal to obtain first data, and output a first completion signal to the first scheduler, wherein the first data is data required for the second chip to perform AI calculation; the first completion signal is used to indicate that the first computing subtask has been completed; The first scheduler is configured to output a second trigger signal to the first memory reader according to the first completion signal based on the first scheduling subtask; The first memory reader is used to transmit the first data to the second chip in response to the second trigger signal based on the first transmission subtask.

16. The device according to claim 15, characterized in that The first scheduler is specifically used to, based on the first scheduling subtask, respond to a first indication signal, and output the second trigger signal to the first memory reader according to the first completion signal, wherein the first indication signal is used to indicate that the second chip has processed the second data, and the second data is the data obtained by the previous AI calculation of the first AI accelerator.

17. The device according to claim 16, characterized in that The apparatus further includes a first notification circuit, and the plurality of tasks further includes a first notification subtask; The first notification circuit is used to receive a first notification signal from the second chip based on the first notification subtask, and output the first indication signal obtained according to the first notification signal to the first scheduler, wherein the first notification signal is used to indicate that the second chip has processed the second data.

18. The device according to claim 17, characterized in that After the first memory reader transmits the first data to the second chip, the first scheduler is further configured to output a third trigger signal to the first notification circuit based on the first scheduling subtask; The first notification circuit is further used to send a second notification signal to the second chip based on the first notification subtask and in response to the third trigger signal, wherein the second notification signal is used to instruct the second chip to perform AI calculation based on the first data.

19. The device according to any one of claims 15 to 18, characterized in that The device also includes a first memory; The first AI accelerator is specifically configured to perform AI calculation based on the first computing subtask and in response to the first trigger signal to obtain the first data, and write the first data into a first storage space of the first memory; The first memory reader is specifically configured to read the first data from the first storage space and transmit the first data to the second chip in response to the second trigger signal based on the first transmission subtask.

20. The device according to any one of claims 15 to 19, characterized in that The plurality of tasks also includes a second computing subtask; After the first chip receives third data from the second chip, the first scheduler is further configured to output a fourth trigger signal to the first AI accelerator based on the first scheduling subtask, where the third data is data obtained by the second chip performing AI calculation based on the first data; The first AI accelerator is further configured to perform AI calculation based on the third data in response to the fourth trigger signal based on the second computing subtask.

21. The device according to any one of claims 15 to 20, characterized in that The first chip also includes a first processor; The first processor is configured to output the execution order of the plurality of tasks to the first scheduler based on a request of a first application executed by the first processor.

22. A communication device, characterized in that: The device is applied to a second chip, the device is configured to execute multiple tasks, the multiple tasks include a second scheduling subtask and a third computing subtask, and the device includes a second scheduler and a second AI accelerator; After the second chip receives the first data from the first chip, the second scheduler is used to output a fifth trigger signal to the second AI accelerator based on the second scheduling subtask; The second AI accelerator is used to perform AI calculation based on the first data in response to the fifth trigger signal based on the third computing subtask.

23. The device according to claim 22, characterized in that The second AI accelerator is specifically configured to perform AI calculation based on the first data in response to the fifth trigger signal based on the third computing subtask, and output a second completion signal to the second scheduler, wherein the second completion signal is used to indicate that the execution of the AI ​​calculation based on the first data is completed; The second scheduler is further configured to send a third notification signal to the first chip based on the second scheduling subtask and according to the second completion signal, wherein the third notification signal is configured to indicate that the second chip has processed the first data.

24. The device according to claim 23, characterized in that The second chip further includes a second notification circuit, and the plurality of tasks further include a second notification subtask; The second scheduler is specifically configured to output a sixth trigger signal to the second notification circuit based on the second scheduling subtask and according to the second completion signal; The second notification circuit is specifically configured to send the third notification signal to the first chip in response to the sixth trigger signal based on the second notification subtask.

25. The device according to claim 24, characterized in that The second notification circuit is further used to receive a second notification signal from the first chip based on the second notification subtask, and output a second indication signal obtained according to the second notification signal to the second scheduler, wherein the second notification signal is used to instruct the second chip to perform AI calculation based on the first data, and the second indication signal is used to instruct the second scheduler to output the fifth trigger signal to the second AI accelerator.

26. The device according to any one of claims 22 to 25, characterized in that The second chip further includes a second memory, a second storage space of the second memory is used to store the first data, and the second storage space is a storage space where the second chip is registered (MR) for the first chip; The second AI accelerator is specifically configured to read the first data from the second storage space based on the third computing subtask and in response to the fifth trigger signal, and perform AI computing based on the first data.

27. The device according to any one of claims 22 to 26, characterized in that The second chip further includes a second memory reader, and the plurality of tasks further includes a second transmission subtask; After the second AI accelerator completes AI calculation based on the first data, the second scheduler is further configured to output a seventh trigger signal to the second memory reader based on the second scheduling subtask; The second memory reader is further used to transmit third data to the first chip in response to the seventh trigger signal based on the second transmission subtask, where the third data is data obtained by the second AI accelerator performing AI calculation based on the first data.

28. The device according to any one of claims 22 to 27, characterized in that The second chip also includes a second processor; The second processor is further configured to output the execution order of the plurality of tasks to the second scheduler based on a request of a second application executed by the second processor.

29. A chip system, characterized in that: The system comprises a first chip and a second chip, the first chip comprising the communication device according to any one of claims 15 to 21, and the second chip comprising the communication device according to any one of claims 22 to 28.

30. An electronic device, characterized in that: The electronic device comprises an interface circuit and a chip system as claimed in claim 29, wherein the interface circuit is coupled to the chip system.

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