Flexible Memory System

Abstract

Techniques are disclosed for operating a memory system that include a first memory client executing a first request to access data at a first memory address, where the first memory address points to data in a first memory portion coupled to the first memory client via a direct memory connection, processing the first request via the direct memory connection, the first client executing a second request to access data at a second memory address, where the second memory address points to data in a second memory portion coupled to the first client via a cross-connect, and processing the second request via the cross-connect.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 17 / 565,315, filed December 29, 2021, and is incorporated by reference as if fully set forth herein. [Background technology]

[0002] Memory performance is a critical aspect of computing, and therefore computer memories are constantly being improved.

[0003] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of an example device capable of implementing one or more aspects of the present disclosure. [Diagram 2] FIG. 1 illustrates a memory system, according to an example. [Diagram 3] FIG. 1 illustrates an exemplary configuration in which each memory client is on a different client chip, but a single memory chip contains all memory portions. [Figure 4] FIG. 1 illustrates an exemplary configuration in which memory clients are co-located within a single chip. [Diagram 5] FIG. 1 illustrates a configuration in which each memory client is on its own client chip and each memory portion is on its own memory chip. [Figure 6] FIG. 1 shows a configuration in which all memory clients are on a single memory client chip, with each memory portion on a separate memory chip. [Figure 7] FIG. 1 illustrates a configuration in which all memory clients and all memory units and interconnects are contained within a single system-on-chip. [Figure 8]1 is a flow diagram of a method for operating a memory system, according to an example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] Techniques are disclosed for operating a memory system that include executing a first request by a first memory client to access data at a first memory address, the first memory address pointing to data in a first memory portion coupled to the first memory client via a direct memory connection, processing the first request via the direct memory connection, executing a second request by the first client to access data at a second memory address, the second memory address pointing to data in a second memory portion coupled to the first client via a cross connection, and processing the second request via the cross connection.

[0006] 1 is a block diagram of an example device 100 in which aspects of the disclosure may be implemented. Device 100 may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 may also include optional input drivers 112 and output drivers 114. It should be understood that device 100 may include additional components not shown in FIG. 1.

[0007] Processor 102 may include a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. Memory 104 may be located on the same die as processor 102, or may be located separately from processor 102. Memory 104 may include volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0008] Storage devices 106 include fixed or removable storage devices (e.g., hard disk drives, solid state drives, optical disks, flash drives). Input devices 108 include keyboards, keypads, touch screens, touch pads, detectors, microphones, accelerometers, gyroscopes, biometric scanners, or network connections (e.g., wireless local area network cards for transmitting and / or receiving wireless IEEE 802 signals). Output devices 110 include displays, speakers, printers, haptic feedback devices, one or more optics, antennas, or network connections (e.g., wireless local area network cards for transmitting and / or receiving wireless IEEE 802 signals).

[0009] Input driver 112 communicates with processor 102 and input device 108, allowing processor 102 to receive input from input device 108. Output driver 114 communicates with processor 102 and output device 110, allowing processor 102 to send output to output device 110. It should be noted that input driver 112 and output driver 114 are optional components and that device 100 operates in the same manner when input driver 112 and output driver 114 are not present.

[0010] In some embodiments, the processor 102 executes an operating system 103 that provides various functions such as loading and executing software, interfacing with hardware, memory management, and many other functions. In some examples, memory management includes memory allocation, which includes reserving portions of memory 104 (or other memory) for entities such as software or hardware that require memory.

[0011] 2 illustrates a memory system 200, according to an example. The memory system includes memory clients 202 and a unified memory 204. Each memory client 202 is coupled to a corresponding memory portion 206 via a corresponding direct memory connection 208. Each direct memory connection 208 is coupled to each other direct memory connection 208 via a cross-connect 210.

[0012] Each memory client 202 is a processing unit that performs a particular type of task. Some exemplary memory clients 202 include a central processing unit, a graphics processing unit, an input and / or output processor, a multimedia processor, or any other type of processing component that utilizes access to memory. In some examples, the unified memory 204 is or is part of a system memory (e.g., memory 104). In some examples, any or all of the memory clients 202 are part of the processor 102. In some examples, the two different memory units 206 have different performance characteristics. Some exemplary performance characteristics include capacity, latency, bandwidth, power, and cost. In terms of capacity, it is possible for the two or more memory units 206 to have different capacities, i.e., to store different numbers of bytes. In terms of latency, it is possible for the two or more memory units 206 to have different latencies, meaning that such different memory units 206 respond to an access request (e.g., read or write) in different amounts of time. In terms of bandwidth, two or more memory units 206 may have different bandwidths, where bandwidth refers to the amount of data the memory units 206 can store or read per unit time. In terms of cost, two or more different memory units 206 may be manufactured using memory technologies that have different costs, where cost refers to the amount of money needed to manufacture each unit of storage (e.g., each gigabyte or megabyte), as the case may be.

[0013] The performance characteristics of each memory portion 206 are tailored to operate with an associated memory client 202. In one example, one memory client 202 (such as a video processor) performs better with higher bandwidth, while another memory client 202 (such as a central processing unit) performs better with lower latency.

[0014] Each of the memory clients 202 has a direct memory connection 208 to an associated memory unit 206. The direct memory connection 208 provides a high bandwidth and / or low latency connection between the associated memory client 202 and the associated memory unit 206. The low latency and / or high bandwidth of the direct memory connection 208 is compared to that provided by the cross-connect 210. In other words, the memory client 202 can access any memory unit 206 only through the direct memory connection 208 or only through the cross-connect 210, or in combination with at least a portion of the direct memory connection 208. Thus, a memory client 202 can access the associated memory unit 206 with high performance, and all memory clients 202 can access all memory units 206 with somewhat lower high performance. The direct connection 208 and the cross-connect 210 together form the interconnect 201.

[0015] It should be understood that memory portions 206 are part of unified memory 204. Unified memory 204 has a single, contiguous physical address space. More specifically, each memory portion 206 has data elements corresponding to a set of addresses. The full set of addresses for all of memory portions 206 form a contiguous physical memory address space. In one example, each memory portion 206 is associated with a particular range of physical memory addresses, with the first physical address (except the first) of any particular memory portion 206 immediately following the last physical address of the previous memory portion 206. Thus, unified memory 204 forms a single physical memory address space with different portions having different performance characteristics, each portion being considered to be "dedicated" or "associated" with a particular memory client 202.

[0016] Any memory portion 206 may be on the same physical chip as any other memory portion 206. At least one memory portion 206 may be on a different physical chip than any other memory portion 206. In some examples, all of the memory portions 206 are in a single chip. In other examples, some (one or more) memory portions 206 are on one physical chip and another (one or more) memory portions 206 are on another physical chip. In yet other examples, all of the memory portions 206 are on their own physical chip.

[0017] Additionally, unified memory 204 may be included on the same physical chip as one or more of memory clients 202 and some or all of interconnect 201. In one example, memory clients 202, interconnect 201, and unified memory 204 are all on the same physical chip. In another example, memory client 202 shares a chip with direct connection 208 coupled to memory client 202 and memory portion 206 coupled to the direct connection. In such an example, each combination of memory client 202 and memory portion 206 is on a chip, and the chips are coupled to each other by cross-connect 210.

[0018] As described above, a memory client 202 can access an associated memory portion 206 via a direct connection 208 and can access other memory portions 206 via a cross connection 210. Thus, if a memory client 202 performs a read access to read requested data from an address within a memory portion 206 associated with that memory client 202, that memory portion 206 provides the requested data to the memory client 202 via the direct connection 208. If a memory client 202 performs a write access to write data to an address within a memory portion 206 associated with that memory client 202, the memory client 202 transmits the data to the associated memory portion 206 via the direct connection 208. If a memory client 202 performs a read access to read requested data from an address within a memory portion 206 not associated with that memory client 202, the memory portion 206 provides the requested data via the cross connection 210 that couples the memory portion 206 to the memory client 202. When a memory client 202 performs a write access to write data to an address in a memory section 206 that is not associated with the memory client 202, the memory client 202 sends the data to the memory section 206 via a cross-connect 210, which couples the memory client 202 to the memory section 206.

[0019] The statement that the memory unit 206 is associated with (or corresponds to) the memory client 202, or that the memory client 202 is associated with (or corresponds to) the memory unit 206, means that the memory unit 206 is coupled to the memory client 202 via a direct connection 208.

[0020] 3 to 7 show exemplary configurations of the memory system.

[0021] 3 illustrates an exemplary configuration in which a single memory chip 304 contains all of the memory portions 206, although each memory client 202 is on a different client chip 302. In this example, the memory portions 206 share a single physical memory chip. However, each memory client 202 is on its own separate physical chip (client chip 302).

[0022] 4 illustrates an exemplary configuration in which each memory client 202 is co-located within a single chip 402. Additionally, in this configuration, memory portion 206 is also found within a single memory chip 304. The chip 402 on which memory clients 202 reside is different from the chip 304 on which memory portion 206 resides.

[0023] 5 shows a configuration in which each memory client 202 is on its own client chip 302 and each memory portion 206 is on its own memory chip 502. In this configuration, each of the illustrated elements is on its own physical chip. Communication is via connections between the chips. The interconnect 201 may be on its own chip or may consist of a combination of interconnects between various chips.

[0024] 6 illustrates a configuration in which all memory clients 202 are on a single memory client chip 602, with each memory portion 206 on a separate memory chip 502. In this configuration, all of the illustrated memory clients 202 share a single physical chip, and every memory portion 206 has its own memory chip 502. The interconnect 201 may be on a separate chip, may be fully or partially integrated with the memory client chip 602, and / or may be fully or partially integrated with one or more of the memory chips 502.

[0025] 7 illustrates a configuration in which all memory clients 202 and all memory units 206, as well as interconnect 201, are contained within a single system-on-chip 702. In this configuration, each of the illustrated elements are on the same physical chip.

[0026] As discussed above, memory portions 206 form a contiguous physical address space. It should be understood that this physical address space is different from a virtual address space. A virtual address space is an address space in which an address translation system (which may include, for example, one or more page tables, one or more translation lookaside buffers, and / or other elements) translates virtual addresses to physical addresses. A physical address is an address used to access the memory itself. A physical address does not require an address translation system to access the underlying memory. It should further be understood that memory portions 206 are separate portions of the physical address space. Data does not need to be copied from one memory portion 206 to another memory portion 206 in order to be accessed. Data can be accessed directly by memory clients 202 via interconnect 201.

[0027] It is described elsewhere herein that each memory client 202 has a direct connection 210 to the memory portion 206. Thus, the memory client 202 has what is considered to be the "best performance" for the memory portion 206 associated with that memory client 202. Thus, in response to software executing on a particular memory client 202 requesting a memory allocation from the operating system 103, the operating system 103 allocates that memory in the memory portion 206 associated with that memory client 202. In one example, a software application, such as a video game that uses a graphics processing unit (any of the memory clients 202), requests a memory allocation from the operating system 103 for data to be processed by the graphics processing unit. In response, the operating system 103 allocates the requested memory on the memory portion 206 associated with the graphics processing unit. Thus, the operating system 103 allocates memory for the memory client 202 in the memory portion 206 corresponding to the memory client 202. In another example, a software application, such as a productivity application, requests a memory allocation from the operating system 103. In response, the operating system 103 allocates the requested memory on the memory portion 206 associated with the central processing unit. In short, in many circumstances, the operating system 103 allocates memory within the memory portion 206 associated with the primary memory client 202 and uses data in that memory allocation.

[0028] It should be noted that while each memory client 202 is shown having one associated memory portion 206, embodiments of the memory system need not be so limited. In particular, it is possible for multiple memory clients 202 to have direct connections 208 to the same memory portion 206 and / or multiple memory portions 206 to have direct connections 208 to the same memory client 202.

[0029] 8 is a flow diagram of a method of operating a memory system, according to an example. Although described with respect to the systems of FIGS. 1-7, one skilled in the art will understand that any system configured to perform the steps of method 800 in any technically feasible order is within the scope of the present disclosure.

[0030] In step 802, the first memory client 202 executes a first request to access data at a first memory address. The first memory address points to data in the first memory portion 206. The first memory portion 206 is coupled to the first memory client 202 via a direct memory connection 208. In step 804, the first memory client 202 services the first request via the direct memory connection 208.

[0031] In step 806, the first client 202 executes a second request to access data at a second memory address, the second memory address pointing to data in a second memory portion 206 coupled to the first client via the cross-connect 210. In step 808, the first memory client 202 services the second request via the cross-connect 210.

[0032] In some examples, the direct memory connection 208 has a lower latency than the cross connection 210. In some examples, the direct memory connection 208 has a higher bandwidth than the cross connection 210. In some examples, the operating system 103 allocates memory for data at a first address in a first memory portion because the first memory portion is coupled to a first memory client via the direct memory connection 208. In some examples, the operating system 103 allocates memory for data at a first address in a first memory portion because the data is used for software executing on the first client 202. In some examples, the operating system 103 allocates memory for data at a second memory address in a second memory portion because the second memory portion is coupled to a second memory client via the direct memory connection 208. In some examples, the operating system allocates memory for data at a second address in a second memory portion because the data is used for software executing on the second client 202.

[0033] Although the term "chip" is sometimes used herein, it should be understood that this term can be interchanged with "package." In some cases, a package is a single physical entity but has multiple physical chips.

[0034] It should be understood that many variations are possible based on the disclosure herein, and although features and elements have been described above in particular combinations, each feature or element may be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0035] Various elements described herein may be implemented as circuitry, as software running on a processor, or as a combination thereof, performing the functions described herein. In FIG. 1, processor 102 is a computer processor that performs the operations described herein. Input driver 112, output driver 114, input device 108, and output device 110 are software running on one or more processors, hardware, or a combination thereof. Memory client 202, interconnect 201, and memory unit 206 may be implemented as hardwired circuitry, as a processor, as software running on one or more processors, or a combination thereof, performing the operations described herein.

[0036] The provided methods may be implemented in a general purpose computer, processor, or processor core. Suitable processors include, by way of example, general purpose processors, special purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application specific integrated circuits (ASICs), field programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data such as netlists (such instructions may be stored in a computer readable medium). The result of such processing may be a mask work that is used in a subsequent semiconductor manufacturing process to manufacture a processor implementing aspects of the embodiments.

[0037] The methods or flow diagrams provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A method of operating a memory system, comprising: executing, by a first memory client, a first request to access data at a first memory address, the first memory address pointing to data in a first memory portion coupled to the first memory client via a direct memory connection; Processing the first request via the direct memory connection; executing a second request by the first memory client to access data at a second memory address, the second memory address pointing to data in a second memory portion coupled to the first client via a cross-connect; and processing the second request via the cross-connect. method.

2. the direct memory connection has a higher bandwidth than the cross connection; 2. The method of claim 1.

3. the direct memory connection has a lower latency than the cross connection; 2. The method of claim 1.

4. the first memory portion and the second memory portion form a portion of a physical address space; 2. The method of claim 1.

5. allocating data of the first memory portion in response to a request by the first memory client.

2. The method of claim 1.

6. allocating data of the second memory portion in response to a request by a second memory client different from the first memory client.

2. The method of claim 1.

7. the first memory portion having different bandwidth characteristics than the second memory portion; 2. The method of claim 1.

8. the first memory unit has different latency characteristics than the second memory unit; 2. The method of claim 1.

9. the first memory portion has a different capacity than the second memory portion; 2. The method of claim 1.

10. the first memory portion has a different cost than the second memory portion; 2. The method of claim 1.

11. 1. A system comprising: A first memory unit; A second memory unit; a first memory client coupled to the first memory portion via a direct memory connection and coupled to the second memory portion via a cross connection; The first memory client includes: Fulfilling a first request to access data at a first memory address, the first memory address pointing to data in the first memory portion; Processing the first request via the direct memory connection; Fulfilling a second request to access data at a second memory address, the second memory address pointing to data in the second memory portion; and processing the second request via the cross-connect; and 4. The method of claim 3, system.

12. the direct memory connection has a higher bandwidth than the cross connection; The system of claim 11.

13. the direct memory connection has a lower latency than the cross connection; The system of claim 11.

14. the first memory portion and the second memory portion form a portion of a physical address space; The system of claim 11.

15. the first memory portion is configured to allocate data of the first memory portion in response to requests by the first memory client; The system of claim 11.

16. the second memory portion is configured to allocate data of the second memory portion in response to a request by a second memory client different from the first memory client. The system of claim 11.

17. the first memory portion having different bandwidth characteristics than the second memory portion; The system of claim 11.

18. the first memory unit has different latency characteristics than the second memory unit; The system of claim 11.

19. the first memory portion has a different capacity than the second memory portion; The system of claim 11.

20. the first memory portion has a different cost than the second memory portion; The system of claim 11.

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