Method and apparatus for managing power states - Patents.com

Abstract

A method and apparatus for managing a power state of a computer system includes powering up a first circuit in response to an event received by a processor, and in response to the event not being processable by the first circuit, powering up at least a second circuit of the computer system to process the event.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 17 / 562,854, filed December 27, 2021, the contents of which are incorporated by reference as if fully set forth herein. [Background technology]

[0002] During power save mode in a system on chip (SOC) computer system, different power off modes are entered causing various parts of the chip to be shut down. When a SOC with multiple power states is in a power down mode, a wake up signal is sent to power up the system again. In some systems, the entire system or a large portion of the system will wake up in response to such a signal. However, the rest of the system may decide which subsequent power state to enter. However, this technique consumes power to determine which power state to enter.

[0003] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0004] [Figure 1] 1 is a block diagram of an example device capable of implementing one or more features of the present disclosure. [Figure 2A] FIG. 2 is a block diagram of the example system of FIG. 1 in a partial power-down state. [Figure 2B] 2 is a block diagram of the example system of FIG. 1 in a second partial power-down state. [Figure 2C] 2 is a block diagram of the example system of FIG. 1 in a third partial power-down state. [Figure 3A] FIG. 2 is a block diagram of a memory controller in a first wake state. [Figure 3B] FIG. 13 is a block diagram of a memory controller in a second wake state. [Figure 4] FIG. 4 is a flow diagram of an exemplary method for managing power states, according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] Although the method and apparatus are developed in more detail below, a method for managing power states is briefly described herein. For example, in a system-on-a-chip (SOC) computer system, to achieve power saving, some areas associated with the SOC may be powered down to save power. As will be described in more detail below, a SOC is a device in which many components of the entire system reside on a chip. For example, a SOC may include a processor, memory, storage, input and output drivers, and other components on a single chip.

[0006] When the SOC is powered down to a sufficiently low power state and then processes a command to enter a higher power state, the SOC enters an intermediate power state. In this intermediate power state, the SOC can determine with some accuracy which further power state to enter. The SOC can decide to change to any of a variety of states, including a lower power state, such as a state in which only the display controller is powered up, or a higher power state, such as a state in which additional components of the SOC are powered up.

[0007] A method for managing power states in a computer system includes powering up a first circuit in response to an event received by a processor, and in response to the event not being serviceable by the first circuit, powering up at least a second circuit of the computer system to service the event.

[0008] An apparatus for managing power states in a computer system includes a first circuit, a second circuit, and a processor operatively coupled to and in communication with the first circuit and the second circuit, the processor configured to power up the first circuit in response to a received event, and in response to the event not being processable by the first circuit, the processor powers up a second circuit of the computer system to process the event.

[0009] A processor for managing power states in a computer system includes a processor configured to power up a first circuit of the computer system operatively coupled to and in communication with the processor in response to a received event, and in response to the event not being processable by the first circuit, the processor powers up a second circuit of the computer system operatively coupled to and in communication with the processor to process the event.

[0010] 1 is a block diagram of an example device 100 capable of implementing one or more features of the present disclosure. Device 100 may include, for example, a computer, a server, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, memory 104, storage 106, one or more input devices 108, and one or more output devices 110. For purposes of illustration, output device 110 is shown to be a display 110, but it is understood that other output devices may be included.

[0011] Device 100 may also optionally include input drivers 112 and output drivers 114. Additionally, device 100 includes a memory controller 115 that communicates with processor 102 and memory 104, and may also communicate with external memory 116. In some embodiments, memory controller 115 will be included within processor 102. It should be understood that device 100 may include additional components not shown in FIG.

[0012] As described above, the processor 102 , memory 104 , storage 106 , input drivers 112 , output drivers 114 , and memory controller 115 may be included on the SOC 101 .

[0013] In various alternatives, the processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, the memory 104 is located on the same die as the processor 102 or is located separately from the processor 102. The memory 104 may include volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0014] Storage 106 includes fixed or removable storage (e.g., hard disk drive, solid state drive, optical disk, flash drive). Input devices 108 include, but are not limited to, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). Output devices 110 include, but are not limited to, a display, a speaker, a printer, a haptic feedback device, one or more optical, antennae, or network connections (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0015] The input driver 112 communicates with the processor 102 and the input device 108, allowing the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, allowing the processor 102 to send output to the output device 110. It should be noted that the input driver 112 and the output driver 114 are optional components and that the device 100 operates in the same manner when the input driver 112 and the output driver 114 are not present.

[0016] The external memory 116 may be similar to the memory 104 and may exist in the form of off-chip memory. In addition, the external memory may be memory resident in a server with which the memory controller 115 communicates via a network interface to access the external memory 116.

[0017] There are advantages to powering down different regions in a system. By powering down regions, it is possible to achieve power savings by operating and powering only the circuits that are utilized in a particular powered down state. The areas required to process an event can then be awakened and powered up, thus using only the amount of power required to process the event and not resulting in excessive power usage.

[0018] Figure 2A is a block diagram of the example system of Figure 1 in a partial power-down state. The example system 100 of Figure 2A shows the SOC 101 in a partial power-down state, with some components powered down to conserve power.

[0019] 2A, memory 104, storage 106, input driver 112, output driver 114, and memory controller 115 are powered down. Processor 102 in SOC 101 is shown as powered up. In embodiments in which processor 102 is a GPU, processor 102 may also be powered down.

[0020] In this state, power savings are achieved by powering down circuits associated with components that do not need to operate, thus allowing power to be utilized by active, operating areas. For example, the video controller, display controller, and GPU may be powered down during the system's sleep mode.

[0021] Figure 2B is a block diagram of the example system of Figure 1 in a second partial power-down state. The example system 100 of Figure 2B shows that the storage 106, the input driver 112, and the output driver 114 are powered down. In this state, the processor 102, the memory controller 115, and the memory 104 are awake to process events that are processed.

[0022] 2B, a limited wakeup occurs utilizing the wakeup of memory controller 115, the more detailed wakeup of which is described in more detail below. By waking up memory controller 115, memory operations to memory 104 and external memory 116 can be accomplished. For example, when a wakeup event is received by SOC 101 that requires a read or write to memory, memory controller 115 and memory 104 are awakened.

[0023] FIGURE 2C is a block diagram of the example system of FIGURE 1 in a third partial power-down state. The example system 100 of FIGURE 2C shows that the storage 106, the input driver 112, and the output driver 114 are powered down. In this state, the processor 102, the output driver 114, the memory controller 115, and the memory 104 are awake to process wake-up events.

[0024] In this state, to process an event received by SOC 101, it is determined that the event being processed requires additional components to those of FIGS. 2A and 2B.

[0025] For example, a received event that requires both the memory controller 115 and the display controller may warrant waking up the memory controller 115, the memory 104, and the output drivers 114.

[0026] 2A, 2B, and 2C may be referred to as horizontal wakeups, i.e., the components awake in SOC 101 are horizontally related and are one or more components that should be awakened to process an event without waking additional components.

[0027] For example, memory controller 115 may be awakened to handle memory reads or writes without having to awaken output drivers 114 if rendering to a display is not required.

[0028] In horizontal wakeup, an event received by SOC 101 determines which components of SOC 101 need to be awakened. The determination can be made by processor 102 of SOC 101 or by any other SOC HW or FW components by examining the received event and determining which horizontal components of SOC 101 should be awakened.

[0029] Again, the processor 102 may initially awaken a limited portion of the SOC 101. If the type or duration of the event being processed requires that additional components be awakened, then additional SOC 101 components may be awakened.

[0030] For example, wake-up events may include user-triggered events (e.g., mouse movement, keyboard click) or timer events. In addition, incoming WiFi events, PCIe events, or GPIO (General Purpose IO) associated ACPI events may trigger a wake-up. These events may require the wake-up of additional components from SOC 101.

[0031] For example, a mouse movement or keyboard click may require waking up input drivers and input circuits within SOC 101. An incoming WiFi, PCIe, or GPIO event may require waking up circuits involved in transmitting data along a bus that may be used to transmit the data.

[0032] 3A is a block diagram of memory controller 115 in a first wake state. As described above, memory controller 115 may be woken up to process an event requiring a memory operation.

[0033] 3A, the memory controller includes four memory area circuits, designated, for example, MC0, MC1, MC2, and MC3, which are associated with active areas for different performance states of the memory controller 115.

[0034] For example, MC0 is associated with a first performance state; MC0 and MC1 are associated with a second performance state; MC0, MC1, and MC2 are associated with a third performance state; and MC0, MC1, MC2, and MC3 are associated with a fourth performance state.

[0035] Although four performance states are shown, it should be understood that more or less than four performance states may be associated with a memory controller.

[0036] Each of the performance states is associated with parameters that determine how many states should be awakened. For example, a first set of parameters may be associated with awakening one state, a second set of parameters may be associated with awakening a second state, a third set of parameters may be associated with awakening a third state, and a fourth set of parameters may be associated with awakening a fourth state.

[0037] As discussed above, the first set of parameters may require only waking up a first area of ​​the memory controller. For example, the first set of parameters may require the memory controller to perform only limited functions, such as memory reads.

[0038] 3A, a first set of parameters associated with a wake-up event is received by SOC 101, which determines that only MC0 of the memory controller is to be woken up. Other areas of memory controller 115 remain in a powered down state. That is, MC1, MC2, and MC3 remain powered down, and only MC0 is awake.

[0039] Memory controller 115 may additionally communicate with memory 104 or external memory 116 to perform the necessary memory events. In this manner, memory controller 115 may perform memory writes or memory reads to memory 104, for example. It should also be noted that memory controller 115 may perform operations with an external memory, such as external memory 116, as discussed above.

[0040] 3B is a block diagram of memory controller 115 in a second wake state. As described above, memory controller 115 may be woken up to process an event requiring a memory operation.

[0041] 3B, a second set of parameters associated with a wake-up event is received by SOC 101, which determines to wake up memory controllers MC0, MC1, MC2, and MC3. In this state, the entire memory controller 115 is woken up to process the memory event.

[0042] Again, the memory controller 115 also communicates with the memory 104 and the external memory 116 to perform memory operations.

[0043] 3A and 3B, vertical wakeup is enabled, i.e., elements within the components of SOC 101 are woken up according to a wakeup event.

[0044] During this vertical wakeup, additional areas within the same component that is awake may or may not need to be awakened. For example, referring to the example of Figures 3A and 3B, after waking a first area of ​​memory controller 115 to process an event, if it is determined that the event can be processed by waking only that area, then the additional areas do not need to be awakened.

[0045] However, if additional areas need to be woken up to process the event, the additional areas are also awakened: if a second area needs to be awakened, area M1 is awakened; if a third area is needed to process the event, area M2 is also awakened; if the entire memory controller 115 is needed, MC0, MC1, MC2, and MC3 of the memory controller 115 are awakened, as shown in FIG. 3B.

[0046] That is, if a memory operation is required that MC0 cannot handle alone, MC1-MC3 will wake up to handle the operation. For example, a large amount of data to be read from or written to a memory area may not be processable by limiting it to only one area of ​​the memory controller. In this case, additional areas of the memory controller will wake up to handle the event.

[0047] Although examples of horizontal and vertical wake-up are described above, additionally, methods of managing power states associated with both vertical and horizontal wake-up are utilized, and therefore, in the following, methods of managing power states are described.

[0048] 4 is a flow diagram of an example method 400 for managing power states, according to an embodiment. The example method 400 applies to both vertical and horizontal wake-ups as discussed above.

[0049] In step 410, a wake-up event signal is received by SOC 101. For example, the signal may be received from an input device or from a microcontroller on a device that requires an event to be processed by SOC 101. The signal may be received by any component of SOC 101. For example, processor 102 may receive the signal from an input device, memory controller 115 may receive the signal from an event that requires a memory operation. However, these components are not limited to the components that may receive a signal that triggers a wake-up.

[0050] SOC 101 then powers up (or awakens) the first hardware in response to receiving the wake-up event (step 420). For example, processor 102 may awaken to determine whether the event can be processed without waking up additional areas of SOC 101.

[0051] If the entire system should be awakened to process the event (step 430), the SOC 101 wakes up the entire system (step 440). For example, in some embodiments, additional metrics may track the history of SOC 101 wakeups associated with a particular event. A decision to wake up the entire SOC 101 is then made based on that history.

[0052] Further details regarding the prediction engine for wake-up are provided below, but in brief, if the prediction of the wake-up component based on an event indicates that the entire SOC101 should be woken up to handle that event, then the entire SOC101 is woken up.

[0053] If, in step 430, the entire system does not need to be woken up, SOC 101 determines whether the system can be powered down again (step 450). That is, if the event does not require additional areas to be powered up and can be handled with minimal power-up, SOC 101 powers down the system again (step 460).

[0054] If the system should not be powered down again (step 450), the SOC 101 wakes areas that are powered up and should be awakened to execute the task event based on parameters associated with the event (step 470).

[0055] For example, a graphics processing event may not require the entire GPU to be awakened in response to the event. That is, graphics processing may not require the processing power of all cores of the GPU to process the event for non-graphics intensive processing events. In this case, awakening all cores of the GPU is unnecessary and creates additional power requirements that are not needed. Thus, a single core of the GPU or multiple cores of the GPU may be powered up to process the event. This results in power savings by not waking up all of the cores of the GPU.

[0056] In addition, a timer parameter may be utilized to determine whether additional areas of the SOC 101 need to be awakened to process the event, i.e., a timer may be utilized to track the duration of processing the event, and if the event cannot be processed within a predetermined time, it is deemed that additional areas need to be awakened to process the event.

[0057] So, if an event exceeds a predetermined period of time in which the event can be processed, additional areas are awakened within SOC 101 to process the event. For example, if additional cores, either CPU or GPU, are needed, those cores can be awakened and powered up to process the event.

[0058] Additionally, each component of SOC 101 may include different criteria that determine whether or not to wake the component. Based on knowledge of the event criteria, SOC 101 may determine which areas to wake in step 470.

[0059] For example, the plugging of a new component into a universal serial bus (USB) port may be a criterion indicating that the display controller should be awakened. In this way, potential user action can be requested on the display to determine the next step.

[0060] Additionally, for example, plugging in a USB flash drive may require a decision by the user whether to copy a file from the drive, or any other action the user may deem desirable. As mentioned above, a memory read or write event may be the criterion that determines to wake the memory controller 115 and memory areas (e.g., memory 104).

[0061] Thus, the components necessary to function to allow the user to determine a course of action when a USB flash drive is plugged in are awakened. For example, the display may be awakened to present the user with options from which to choose. Also, as described above, if a copy operation is required, the areas of memory controller 115 required to perform a memory copy are awakened.

[0062] Additionally, the history of events and components that are powered up can be tracked by the SOC 101. That is, certain events that occur can be predicted to require waking up certain components. If these predictions are correct, counters can be incremented and stored to know which components to wake up.

[0063] For example, if an event is predicted to require waking up the display controller and the display controller wakes up to process the event, a counter can be incremented. In this manner, machine learning is used to determine when to wake up the display controller next for that event.

[0064] As mentioned above, a display controller is used to control a display, such as display 110. The display controller may include circuitry that may comprise any or a combination of the following elements: firmware circuitry, software configurable processing circuitry, or the like.

[0065] Thus, in response to an event, all or part of the display controller circuitry may be powered up and awakened, while other portions of the display controller circuitry that are not expected to be needed may remain powered down.

[0066] Using the same example, if waking the display controller does not process the event, the counter is decremented. The SOC101's machine learning in this case learns that the prediction is less accurate based on that event.

[0067] Thus, by incrementing or decrementing the counter, the machine learning that occurs improves the prediction; that is, as the counter continues to be incremented, the prediction becomes more refined and accurate. In this way, a more reliable prediction of whether or not the awakened component will process the event can be achieved. This can be implemented by setting a predefined threshold against which the counter can be compared.

[0068] For example, if the counter remains above a predefined threshold, the component that is awakened based on the prediction will continue to be awakened if an event of that type is passed to SOC 101. If the counter is below the threshold, the component that is awakened may be kept in a powered down state.

[0069] As mentioned above, when different areas enter the power down mode, power saving can be achieved at the same time. In addition, when a wake-up event is received by SOC 101, only the areas that need to be awakened are powered up to use the minimum amount of power.

[0070] Power-up can be a horizontal awakening, i.e., one or more components within SOC 101 can be individually awakened without waking other components.

[0071] Additionally, the power-up can be a vertical wake-up. In this type of wake-up, areas within a single component can be powered up based on the event being processed. For example, as described above, different power states of the memory controller 115 can be utilized to process different events. Some areas of the memory controller may not need to be powered up based on the event and task being processed.

[0072] The provided methods may be implemented in a general purpose computer, processor, or processor core. Suitable processors include, by way of example, a general purpose processor, a purpose processor, a conventional processor, a digital signal processor (DSP), multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine. Such a processor may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data (instructions that may be stored in a computer readable medium) including a netlist. The results of such processing may be a mask work that is used in a subsequent semiconductor manufacturing process to manufacture a processor that implements the features of the present disclosure. Furthermore, although the above-described methods and apparatus are described in the context of controlling and configuring PCIe links and ports, the methods and apparatus may be utilized in any interconnect protocol in which link width is negotiated.

[0073] The methods or flow charts provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs). For example, the methods described above may be implemented in processor 102 or on any other processor in computer system 100. Additionally, the methods described above may be implemented in a controller, processor, or circuitry in any component (e.g., a component of SOC 101).

Claims

1. 1. A method for managing a power state of a computer system, comprising: powering up the first circuit in response to the event received by the processor; in response to the event being not processable by the first circuitry, powering up at least a second circuitry of the computer system to process the event. method.

2. the first circuit and the second circuit reside in the same component of the computer system; 2. The method of claim 1.

3. the first circuit resides in a first component of the computer system and the second circuit resides in a second component of the computer system; 2. The method of claim 1.

4. powering up a third circuit in response to the event not being processable by the first circuit and the second circuit.

2. The method of claim 1.

5. determining that the circuitry has successfully processed the event due to being powered up; 2. The method of claim 1.

6. incrementing a counter based on the circuit being powered up thereby successfully processing the event. The method of claim 5.

7. powering up the same circuitry for the same event determined to be successful based on the value of the counter being equal to or greater than a predetermined threshold. The method of claim 6.

8. decrementing a counter based on the failure of the circuitry to process the event upon being powered up. The method of claim 5.

9. powering up additional circuitry for the same event determined to have failed based on the value of the counter being less than a predetermined threshold.

9. The method of claim 8.

10. 1. An apparatus for managing a power state of a computer system, comprising: A first circuit; A second circuit; and a processor operatively coupled to the first circuit and the second circuit and in communication with the first circuit and the second circuit; The processor, powering up the first circuit in response to the received event; in response to the event not being processable by the first circuitry, powering up the second circuitry of the computer system to process the event; 4. The method of claim 3, Device.

11. the first circuit and the second circuit reside in the same component of the computer system; 11. The apparatus of claim 10.

12. the first circuit resides in a first component of the computer system and the second circuit resides in a second component of the computer system; 11. The apparatus of claim 10.

13. the processor is configured to power up a third circuit in response to the event not being processable by the first circuit and the second circuit.

11. The apparatus of claim 10.

14. the processor is configured to determine that the circuitry has successfully processed the event because the circuitry has been powered up; 11. The apparatus of claim 10.

15. the processor is configured to increment a counter based on the circuit being powered up thereby successfully processing the event.

15. The apparatus of claim 14.

16. the processor is configured to power up the same circuitry for the same event determined to be successful based on the value of the counter being equal to or greater than a predetermined threshold.

16. The apparatus of claim 15.

17. The processor is configured to decrement a counter based on a failure of the circuit to process the event upon powering up.

17. The apparatus of claim 16.

18. the processor is configured to power up additional circuitry for the same event determined to have failed based on the value of the counter being less than a predetermined threshold.

20. The apparatus of claim 17.

19. 1. A processor for managing a power state of a computer system, comprising: The processor, powering up a first circuit of the computer system operatively coupled to and in communication with the processor in response to the received event; in response to the event not being processable by the first circuitry, powering up a second circuitry of the computer system operatively coupled to and in communication with the processor for processing the event; 4. The method of claim 3, Processor.

20. the processor is configured to power up a third circuit in response to the event not being processable by the first circuit and the second circuit.

20. The processor of claim 19.

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