Multiqubit architecture using mode-selective charge coupling between novel fracsonium molecular qubits

Abstract

The qubit structure includes a first flaxonium qubit having a first Josephson junction (JJ) in parallel with a first capacitor and a first superconducting inductor. A second flaxonium qubit includes a second JJ in parallel with a second capacitor and a second superconducting inductor and is coupled in series with the first flaxonium qubit. A third capacitor is coupled in parallel with the first and second flaxonium qubits in series.

Description

[Technical field]

[0001] The present disclosure relates generally to quantum computing, and more particularly to superconducting structures and methods for creating same. [Background technology]

[0002] Superconducting quantum computing is the implementation of quantum computers in superconducting electronic circuits. Quantum computing studies the application of quantum mechanical phenomena for information processing and communication. There are various models of quantum computing, the most common one incorporating the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states, but can be in a quantum superposition of both states. A quantum gate is a generalization of a logic gate, but a quantum gate describes the change that one or more qubits undergo after a gate is applied to them, given an initial state.

[0003] The ability to include more superconducting qubits is important in enabling the potential of quantum computers to be realized. However, as the number of such qubits increases, crosstalk between the qubits can increase error rates. Even if techniques exist to control crosstalk between superconducting qubits, such structures tend to have lower anharmonicity than other superconducting qubits, which can limit the speed and therefore the fidelity of quantum gates. Various quantum mechanical phenomena, such as superposition and entanglement, have no analogues in the classical computing field and therefore may require specialized structures, techniques, and materials. Summary of the Invention

[0004] Exemplary and non-limiting embodiments are summarized below. According to one embodiment, a qubit structure includes a first fluxonium qubit including a first Josephson Junction (JJ) in parallel with a first capacitor and a first superconducting inductor. A second fluxonium qubit includes a second JJ in parallel with a second capacitor and a second superconducting inductor and is coupled in series with the first fluxonium qubit. A third capacitor is coupled in parallel with the first and second fluxonium qubits in series.

[0005] In one embodiment, the first and second capacitors are each a superconductor capacitor pad. A common node at an interface of the series connection between the first flaxonium qubit and the second flaxonium qubit is a middle superconductor capacitor pad. The first capacitor pad and the second capacitor pad are capacitively coupled by a third capacitor.

[0006] In one embodiment, the capacitive coupling of the third capacitor is configured to hybridize plasmon-like excitations associated with the first and second fluxonium qubits into bright and dark modes.

[0007] In one embodiment, the dark mode has a higher frequency than the bright mode.

[0008] In one embodiment, the first difluxonium qubit, the second difluxonium qubit, and the third capacitor create a first difluxonium qubit. The qubit structure further includes a second difluxonium qubit. A bus resonator is coupled between the first difluxonium qubit and the second difluxonium qubit.

[0009] In one embodiment, the bus resonator has a first node capacitively coupled to a middle pad of a first diffluxonium qubit. The bus resonator has a second node capacitively coupled to a middle pad of a second diffluxonium qubit.

[0010] In one embodiment, the bus resonator structure is configured to provide mode-selective charge coupling to suppress crosstalk between uncoupled qubit modes.

[0011] In one embodiment, the first fluxonium qubit and the second fluxonium qubit are implemented by resonator induced phase (RIP) gates.

[0012] In one embodiment, the first fluxonium qubit and the second fluxonium qubit are in separate modes.

[0013] In one embodiment, the first and second fluxonium qubits are configured to operate in a zero magnetic field.

[0014] In one embodiment, there is a magnetic shield configured to prevent dephasing of the first and second fluxonium qubits due to magnetic flux noise.

[0015] According to one embodiment, a method of providing a multi-qubit entanglement gate includes providing a first fluxonium qubit including a first Josephson junction (JJ) in parallel with a first capacitor and a first superconducting inductor. A second fluxonium qubit is provided including a second JJ in parallel with a second capacitor and a second superconducting inductor and coupled in series with the first fluxonium qubit. A third capacitor is coupled in parallel with the first and second fluxonium qubits in series.

[0016] In one embodiment, the first capacitor pad and the second capacitor pad are capacitively coupled by a third capacitor. A common node at an interface of the series connection between the first flaxonium qubit and the second flaxonium qubit is configured as an intermediate superconductor capacitor pad. The first and second capacitors are each configured as a superconductor capacitor pad.

[0017] In one embodiment, plasma-like excitations associated with the first and second fluxonium qubits are hybridized into bright and dark modes by capacitive coupling.

[0018] In one embodiment, the first difluxonium qubit, the second difluxonium qubit, and the third capacitor create a first difluxonium qubit. The method further includes providing a second difluxonium qubit. A bus resonator is coupled between the first difluxonium qubit and the second difluxonium qubit.

[0019] In one embodiment, the method further includes capacitively coupling a first node of the bus resonator to a middle pad of the first diffluxonium qubit. A second node of the bus resonator is coupled to a middle pad of the second diffluxonium qubit.

[0020] In one embodiment, mode-selective charge coupling is performed by a bus resonator to suppress crosstalk between uncoupled qubit modes.

[0021] In one embodiment, the first fluxonium qubit and the second fluxonium qubit are operated in separate modes.

[0022] In one embodiment, the first and second fluxonium qubits are operated in a zero magnetic field.

[0023] In one embodiment, dephasing of the first and second fluxonium qubits due to magnetic flux noise is prevented via a magnetic shield.

[0024] According to one embodiment, a resonator-induced phase (RIP) gate includes a first difluxonium qubit comprising a first Josephson junction (JJ) in parallel with a first capacitor and a first superconducting inductor, a second flaxonium qubit including a second JJ in parallel with a second capacitor and a second superconducting inductor and coupled in series with the first flaxonium qubit, and a third capacitor coupled in parallel with the first and second flaxonium qubits in series. There is a third diflaxonium qubit including a third Josephson junction (JJ) in parallel with a fourth capacitor and a third superconducting inductor, a fourth diflaxonium qubit including a fourth JJ in parallel with a fifth capacitor and a fourth superconducting inductor and coupled in series with the third diflaxonium qubit, and a sixth capacitor coupled in parallel with the third and fourth diflaxonium qubits in series. There is a bus resonator coupled between the first diflaxonium qubit and the second diflaxonium qubit.

[0025] The teachings herein provide a quantum computing architecture that allows for fast and accurate two-qubit entanglement gates with low crosstalk between qubits. The architecture is substantially insensitive to modest variations in qubit frequency due to poorly controlled device parameters (e.g., Josephson junction size). Maximizing qubit anharmonicity allows for the fastest possible single-qubit and two-qubit gates.

[0026] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0027] The drawings are of exemplary embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more efficient illustration. Some embodiments may be practiced with additional components or steps, or without all components or steps illustrated, or both. When the same reference numeral appears in different drawings, it refers to the same or similar components or steps. [Brief description of the drawings]

[0028] [Figure 1A] FIG. 1 is an example circuit diagram of a fluxonium qubit, in accordance with an example embodiment. [Figure 1B] FIG. 2 is an example circuit diagram of a variably coupled qubit. [Figure 1C] FIG. 1C is a diagram of an example capacitor design representing the first and second capacitors of FIG. 1B in accordance with an exemplary embodiment. [Figure 1D] 1 is a diagram of an example mode structure of a variably coupled qubit, according to an example embodiment. [Diagram 2] FIG. 1 is a diagram of an example Diffluxonium circuit in accordance with an example embodiment. [Diagram 3] FIG. 3 provides some example device parameters of the diffluxonium qubit circuit of FIG. 2 in accordance with an example embodiment. [Figure 4] FIG. 1 is a diagram of an example circuit of a bus resonator with mode-selective coupling for two diffluxonium qubits, in accordance with an example embodiment. [Diagram 5] FIG. 1 is an example flow diagram of an example non-limiting process for performing mode-selective charge coupling in a multi-qubit architecture in accordance with one or more embodiments described herein. [Figure 6]FIG. 1 provides an example, non-limiting operating environment in which one or more embodiments described herein may be facilitated. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] overview In the following detailed description, numerous specific details are set forth as examples to provide a thorough understanding of the relevant teachings. However, it will be apparent that the present teachings can be practiced without such details. In other instances, well-known methods, procedures, components, or circuit configurations, or combinations thereof, have been described at a relatively high level, without detail, to avoid unnecessarily obscuring aspects of the present teachings.

[0030] In discussing the present technology, it may be helpful to explain various key terms: As used herein, a qubit refers to a quantum bit, and a quantum gate is an operation performed on a qubit, such as controlling the superposition between two qubits.

[0031] As used herein, an entanglement gate is an operation in which an external field (e.g., a microwave pulse) is applied to a quantum processor to create an entangled state between two or more separate qubits. The term C-phase refers to a controlled phase gate in which the Z rotation of one qubit is dictated by the state of another qubit. A C-phase gate is an entanglement gate in which one qubit acquires a phase shift only if both qubits are in an initial excited state.

[0032] As used herein, a resonator-induced phase (RIP) gate is a multi-qubit entanglement gate. This allows high flexibility in qubit frequencies, making it suitable for quantum computing in large-scale architectures. The advantage of the RIP gate is that it can couple qubits even when they are substantially detuned with respect to each other. Thus, the RIP gate can overcome the difficulties due to constraints on the frequency configuration of qubits that can hinder scalability to larger quantum architectures. The RIP gate is a controlled-Z (CZ) gate that uses strong coupling between qubits and resonators in a quantum system. This can be achieved by applying a detuned pulsed microwave drive to a shared bus cavity, sometimes referred to herein as a bus resonator.

[0033] As used herein, ZZ refers to a state-dependent qubit interaction that can be used to form a C-phase gate. For example, ZZ interaction is a type of interaction between two qubits or modes where the excitation of one qubit or mode causes a shift in the transition frequency of the other qubit or mode. Thus, a state-dependent shift in qubit frequency can be equivalent to a state-dependent phase shift, and this represents a way to entangle two different qubits and create a C-phase gate. Static ZZ interaction refers to the interaction that exists between two qubits or modes in the absence of an external microwave drive. This "always-on" interaction can be detrimental to a system of qubits by inhibiting independent control of each qubit and creating undesired entanglement. Ideally, in the absence of an applied field, the static ZZ interaction should be zero.

[0034] As used herein, the term flux variable refers to a device whose frequency is dependent on the magnetic flux.

[0035] As used herein, a fluxonium qubit is a qubit that includes a Josephson junction (JJ) shunted by both a capacitor and a large inductance (sometimes called a superinductor). In this regard, FIG. 1A illustrates an example circuit diagram of a fluxonium qubit. The fluxonium qubit 100 includes a capacitor 108 and an inductance energy E L A Josephson energy E J This includes JJ106 having the following structure:

[0036] A multi-mode qubit refers to any quantum system that contains strongly interacting anharmonic oscillators. The composite system is characterized by multiple modes of excitation with strong longitudinal coupling between the modes (i.e., excitation of one mode can strongly shift the transition frequency of the other). For example, such a system may be a tunable-coupling qubit (TCQ). In this regard, see FIG. 1B, which shows an example circuit diagram 120 of a TCQ. The TCQ 120 is connected to a second Josephson junction 124 (in FIG. 1B, E J2 1B ) is coupled to a first Josephson junction 122 (denoted as E J1 In this example embodiment, the first Josephson junction 122 and / or the second Josephson junction 124 may include one or more superconducting films (e.g., superconducting metal films) and / or one or more non-superconducting films (e.g., normal metal films) formed on a substrate (e.g., a silicon (Si) substrate, etc.).

[0037] As shown in the example embodiment depicted in FIG. 1B, each Josephson junction has a corresponding capacitor coupled in parallel, shown as a first capacitor C1 (128) and a second capacitor C2 (126), respectively. In the example embodiment shown in FIG. 1B, the first capacitor 128 and the second capacitor 126 represent direct capacitive shunts across the first Josephson junction 122 and the second Josephson junction 124, respectively. In this regard, FIG. 1C illustrates an example capacitor design 140 representing the first capacitor 128 and the second capacitor 126 of FIG. 1B, according to an example embodiment. For example, the capacitor design 140 may be implemented by superconducting pads 130A, 130B, and 130C connected by Josephson junctions 132 and 134.

[0038] The TCQ 120 has two distinct modes corresponding to symmetric and antisymmetric combinations of excitations associated with its two junctions 122 and 124. In this regard, see FIG. 1D, which illustrates an example mode structure of a TCQ, according to an example embodiment. The B-mode, sometimes referred to herein as the dark mode, is higher in frequency than the A-mode. The A-mode has a net dipole moment and is generally lower in frequency than the B-mode, sometimes referred to herein as the bright mode.

[0039] For example, in various cases, a two-junction qubit may support and / or exhibit two distinct excitation modes, a dark mode and a bright mode. These two distinct excitation modes may have two different spatial symmetries or two different transition frequencies (e.g., a dark mode transition frequency and a bright mode transition frequency) or both. More specifically, the dark mode of a two-junction qubit may be a higher frequency excitation mode that has no net dipole moment. In other words, the dark mode may refrain from coupling to a global electric field. In contrast, the bright mode of a two-junction qubit may be a lower frequency excitation mode that has a net dipole moment. That is, the bright mode may couple to a global electric field. In various cases, a two-junction qubit may be encoded in either a dark mode (e.g., and thus may have a dark mode transition frequency) or a bright mode (e.g., and thus may have a bright mode transition frequency).

[0040] In various embodiments, a short microwave pulse may be used to switch a two-junction qubit between encodings (e.g., a suitable microwave pulse may be applied to a two-junction qubit to switch it from a dark mode to a bright mode, or from a bright mode to a dark mode, or both).

[0041] For example, the superconducting qubit 134 and the second superconducting qubit 132 shown in the example embodiment depicted in FIG. 1C may each operate in a first oscillation mode (e.g., A or bright mode) or a second oscillation mode (e.g., B or dark mode). In some embodiments, the first oscillation mode and the second oscillation mode may correspond to different (e.g., distinct) frequencies and / or different (e.g., distinct) spatial symmetries with respect to one another. In these embodiments, the first oscillation mode and the second oscillation mode may exhibit symmetric and antisymmetric combinations of excitations associated with the first Josephson junction 122 and the second Josephson junction 124. In these embodiments, such symmetric and antisymmetric combinations of excitations associated with the first Josephson junction 122 and the second Josephson junction 124 may result from capacitive coupling between the first superconducting pad 130C and the third superconducting pad 130A.

[0042] As used herein, a transmon is a type of superconducting qubit whose charging energy, Ec, is much smaller than the Josephson energy, Ej.

[0043] As used herein, a drive line refers to a qubit control line that carries a signal to a qubit.

[0044] As used herein, the terms "coupled" and / or "electrically coupled" do not mean that elements must be directly coupled to one another; that is, intervening elements may be provided between "coupled" or "electrically coupled" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present. The term "electrically connected" refers to a low ohmic electrical connection between elements that are electrically connected to one another.

[0045] As used herein, certain terms such as "lossless," "superconductor," "superconducting," "absolute zero," etc. are used to indicate what may be considered ideal behavior, and these terms are intended to cover functionality that may not be strictly ideal for a given application, but is within an acceptable margin. For example, certain levels of loss or tolerances may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms.

[0046] In this specification, terms such as first, second, third, etc. may be used to describe various elements, but these elements should not be limited by such terms. Such terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the example embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Example embodiments are described herein with reference to schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations may be expected as a result, for example, of manufacturing techniques and / or tolerances. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not necessarily indicative of the actual shape or extent of a region of a device.

[0048] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the spirit and scope as defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0049] The present disclosure relates generally to superconducting devices, and more particularly to providing a quantum computing architecture that enables fast and accurate two-qubit entanglement gates with low crosstalk between qubits. Electromagnetic energy associated with the qubits can be stored in so-called Josephson junctions, as well as capacitive and inductive elements used to form the qubits. In one example, to read out the qubit state, a microwave signal is applied to a microwave readout cavity that couples to the qubits at the cavity frequency. The transmitted (or reflected) microwave signal passes through multiple thermal isolation stages and low-noise amplifiers that are used to block or reduce noise and improve the signal-to-noise ratio. Alternatively or additionally, a microwave signal (e.g., a pulse) may be used to entangle one or more qubits. The amplitude and / or phase of the returned / output microwave signal carries information about the qubit state, such as whether the qubit has dephasised to a ground or excited state. The microwave signal that carries quantum information about the qubit state is typically weak (e.g., on the order of a few microwave photons) and can be affected by crosstalk.

[0050] The ability to include more qubits is important to be able to realize the potential of scalable quantum computers. Crosstalk between qubits can increase the error rate. In general, there are two main sources of gate errors: decoherence (stochastic) and non-ideal interactions (deterministic). The latter includes parasitic couplings, leakage into non-computational states, and control crosstalk.

[0051] The inventors have realized that increasing the computational complexity and reliability of quantum computers requires improvements along two main dimensions. The first is the number of qubits themselves. The more qubits in a quantum processor, the more states can in principle be manipulated and stored. The second is low error rates, which relate to precisely manipulating the qubit states and performing a sequence of operations that yields a consistent result rather than simply unreliable data. Thus, to improve the fault tolerance of quantum computers, the use of a large number of physical qubits for the storage of logical qubits is required. In this way, local information is delocalized in a way that makes quantum computers less susceptible to local errors and to the performance of measurements in the eigenbasis of the qubits, similar to the parity checks of classical computers, thus evolving towards more fault-tolerant qubits.

[0052] In recent years, there has been active interest in the use of flaxonium qubits due to their high anharmonicity and long coherence times. However, as with other superconducting qubits, realizing high-fidelity two-qubit gates with minimal crosstalk between flaxonium qubits has remained an unsolved challenge. Although crosstalk between superconducting qubits can be controlled through the use of mode-selective coupling between TCQs, such TCQs tend to have lower anharmonicity than other superconducting qubits, which can limit the speed and therefore the fidelity of quantum gates.

[0053] In one aspect, the teachings herein are based on the inventor's insight that direct application of conventional integrated circuit techniques for interacting with computing elements to superconducting quantum circuits may be ineffective due to unique challenges presented by quantum circuits not presented in classical computing architectures. Accordingly, embodiments of the present disclosure are further based on the recognition that the problems unique to quantum circuits are taken into account when evaluating the applicability of conventional integrated circuit techniques to building superconducting quantum circuits, and in particular, in selecting the methods and architectures used to efficiently interact with qubits.

[0054] The teachings herein provide a quantum computing architecture that allows for fast and accurate two-qubit entanglement gates with low crosstalk between qubits. The architecture is substantially insensitive to moderate variations in qubit frequency due to poorly controlled device parameters (e.g., Josephson junction size). Maximizing qubit anharmonicity allows for the fastest possible single-qubit and two-qubit gates. The techniques described herein can be implemented in several ways. Exemplary implementations are provided below with reference to the following figures.

[0055] Example Circuit Diagram 2 illustrates a diffluxonium circuit 200 according to an example embodiment. The circuit includes a first capacitor 228 (C1) and a first superconducting inductor 240 (E L1 ) in parallel with the first Josephson junction 222 (E J1 ) and a second capacitor 226 (C2) and a second superconducting inductor 242 (E L2 ) in parallel with the second Josephson junction 224 (E J2) and a second flaxonium qubit 252 having a second capacitance C. The first and second flaxonium qubits 250, 252 are connected in series and share a common node 230. In one embodiment, the common node 230 is a superconducting capacitor pad, sometimes referred to herein as a middle pad. The first node 251 of the first flaxonium qubit and the first node 253 of the second flaxonium qubit are superconducting capacitor pads, sometimes referred to herein as a bottom pad and a top pad, respectively. The top pad 253 and the bottom pad 251 form a third capacitor C. S The two fluxonium qubits are capacitively coupled by means of a capacitive coupling via 232. Such capacitive coupling (i.e., between lower capacitor pad 252 and upper capacitor pad 250) causes the plasmon-like excitations associated with the two fluxonium qubits to hybridize into a first mode and a second mode (e.g., A and B), similar to having two TCQs.

[0056] For example, the third capacitor 232 represents a capacitive coupling between the first pad 252 and the second pad 250, which may enable the creation of first and second vibrational modes having different frequencies and different spatial symmetries with respect to each other. In this example embodiment, such an interaction between the first and second vibrational modes may enable the creation of extended states (e.g., hybridized quantum states, hybridized vibrational modes, etc.) of the first and second fluxonium qubits.

[0057] Thus, the architecture of circuit 200 provides two fluxonium qubits 250 and 252 connected in series and includes an additional capacitive coupling 232. This diflaxonium architecture produces a novel multi-mode qubit with the high anharmonicity (relative to the anharmonicity of conventional transmon qubits) as well as the high coherence of fluxonium (relative to the coherence time of conventional transmon qubits).

[0058] In one embodiment, selective charge coupling is used for only one mode of the diflaxonium, which allows for suppression of crosstalk between qubit modes (i.e., uncoupled modes) while still allowing for two-qubit gates.

[0059] In one embodiment, the Diffluxonium circuit 200 is operated in a zero magnetic field, as given by the following equation:

[0060] (φ ext,1 =φ ext,2 =0) (Formula 1)

[0061] The device may be magnetically shielded to prevent dephasing due to magnetic flux noise. In this regard, it is noted that operating a superconducting quantum computer without the need for an external magnetic field makes it possible to suppress the effects of magnetic flux noise that can cause dephasing of qubits and degrade gate fidelity. The Hamiltonian of the diffluxonium qubit circuit 200 is given by:

[0062]

number

number

[0063] Different capacitive elements C1, C2, and C S The passive energy of (i.e., 228, 226, and 232) is given by:

[0064]

number

[0065]

number

[0066]

number

[0067] FIG. 3 provides some example device parameters of the diffluxonium qubit circuit 200 of FIG. 2, in accordance with an example embodiment. More specifically, FIG. 3 illustrates the first capacitor C1 (228), the second capacitor C2 (226), the shunt capacitor C S (232), the energy of the first and second Josephson junctions E J1 , E J2 (222, 224), and the energy E of the first and second inductors L1 , E L1 Example values ​​for (240, 242) are provided. In the example of Figure 3, the A-mode frequency is 5.16 GHz with an anharmonicity of -550 MHz. The B-mode frequency is 6.20 GHz.

[0068] Reference is now made to Figure 4, which is a circuit 400 of a bus resonator with mode-selective coupling for two diffluxonium qubits, according to an exemplary embodiment. The circuit 400 illustrates that two diffluxonium circuits 200 of Figure 2 may be connected together by a bus resonator 424. In the exemplary embodiment shown in Figure 4, the middle pad 430A of the first diffluxonium qubit 402A may be capacitively coupled to the superconducting bus resonator 424, which is represented by the coupling capacitor 422A. Similarly, the middle pad 430B of the second diffluxonium qubit 402B may be capacitively coupled to the superconducting bus resonator 424, which is represented by the coupling capacitor 422B.

[0069] In some embodiments, the first and second diffluxonium qubits 402A and 402B may encode qubit information in the same mode (e.g., bright or dark) when the bus resonator is coupled to the opposite mode (e.g., dark or bright). For example, when the second diffluxonium qubit 402B is in a first mode (e.g., mode A or bright) and the bus resonator is coupled to the second mode (e.g., B mode or dark mode) of the two diffluxonium qubits, the first diffluxonium qubit 402A may be in a first mode (e.g., mode A or bright) or vice versa.

[0070] For example, the superconducting bus resonator 424 may be coupled to the first diffluxonium qubit 402A and the second diffluxonium qubit 402B based on (e.g., according to) the first diffluxonium qubit 402A corresponding to mode B of FIG. 1D, which may include a coupling mode. In this embodiment, the second diffluxonium qubit 402B may enable encoding and / or storing quantum information (e.g., qubit information, quantum state information, etc.) in the A mode of the first diffluxonium qubit 402A and the second diffluxonium qubit 402B, which may include a data mode. The mode-selective coupling discussed herein facilitates a two-qubit entanglement gate while suppressing crosstalk between qubit modes. Such mode combination schemes described in the above embodiments may constitute mode-selective combination schemes that may be implemented by an entity (e.g., a human, a computing device, a software application, an agent, a machine learning model, an artificial intelligence model, etc.) implementing one or more of the embodiments of the subject disclosure described herein.

[0071] In the illustrated embodiment of FIG. 4, for the first diffluxonium qubit 402A, the A-mode frequency fA becomes 5.3GHz, and the frequency f B The parameters of the first and second diffraxonium qubits 402A and 402B were chosen such that the A-mode frequency f A = 5.6 GHz, and the frequency of B mode is f B 6.67 GHz. Using the Hamiltonian described herein above, the Z between the diffractive A-modes is a very small 0.07 kHz, which is significantly smaller than known transmon devices, for example. For example, excitation of the second diffractive qubit in the A-mode does not substantially affect the transition frequency of the first diffractive qubit.

[0072] The ZZ coupling between the A mode of the first diffraxonium qubit 402A and the bus resonator 424 is large (eg, 14 MHz), and the ZZ coupling between the A mode of the second diffraxonium qubit 402B and the bus resonator 424 is also large at 4.4 MHz.

[0073] Therefore, for a given fluxonium qubit, E J and E LThere is a 10% asymmetry between the A modes of the diffluxonium qubit 402A and the B modes of the diffluxonium qubit 402B. The bus resonator 424 has an exchange coupling of about 46 MHz to the B mode of the diffluxonium qubit. As shown in FIG. 4, the static ZZ between the A modes of the diffluxonium qubit 402A and the A modes of the diffluxonium qubit 402B is small, demonstrating low crosstalk. In this regard, it is noted that the large static ZZ between each A mode and the bus resonator 424 indicates that there is a large longitudinal coupling between the qubit modes and the bus resonator 424. This coupling allows for the implementation of a two-qubit gate by a RIP gate (e.g., by driving the bus resonator 424 detuned). For example, in this embodiment, based on detuning the driving of the superconducting bus resonator 424, the device 400 and / or the superconducting bus resonator 424 can operate as a RIP gate, which can generate a ZZ interaction between a first diffusonium qubit 402A and a second diffusonium qubit 402B that are present when there is a microwave drive (e.g., a microwave pulse, a microwave signal, a control signal, etc.) in the superconducting bus resonator 424 (e.g., when there is a microwave signal applied to the superconducting bus resonator 424).

[0074] Example Process Given the foregoing overview of the exemplary architectures 200, 300, and 400, it may be helpful to now consider a high-level discussion of the exemplary processes. As such, FIG. 5 illustrates an exemplary flow diagram of an exemplary, non-limiting process 500 for performing mode-selective charge coupling in a multi-qubit architecture, according to one or more embodiments described herein. The process 500 is illustrated as a collection of blocks in a logical flow chart, which represent a sequence of operations that may be performed in hardware, software, or a combination thereof. In the context of software, the blocks represent computer-executable instructions that, when executed by one or more processors, perform the described operations. In general, computer-executable instructions may include routines, programs, objects, components, data structures, etc. that perform a function or implement an abstract data type. In each process, the order in which the operations are described is not intended to be construed as a limitation, and any number of the described blocks may be combined in any order and / or executed in parallel to perform the process. For ease of explanation, the process 500 is described with respect to the architectures of FIGS. 2 and 4.

[0075] In block 502, a first fluxonium qubit 250 is provided that includes a first Josephson junction (JJ) 222 in parallel with a first capacitor 228 and a first superconducting inductor 240.

[0076] In block 504, a second fluxonium qubit 252 is provided that includes a second JJ 224 in parallel with a second capacitor 226 and a second superconducting inductor 242 and is coupled in series with the first fluxonium qubit 250.

[0077] In block 506, a third capacitor 232 is coupled in parallel with the first and second fluxonium qubits 250, 252 in series.

[0078] In one embodiment, the first flaxonium qubit, the second flaxonium qubit, and the third capacitor create a first diflaxonium qubit 402 A. In block 508, a second diflaxonium qubit 402 B is provided.

[0079] In block 510, a bus resonator 424 is coupled between the first diffluxonium qubit and the second diffluxonium qubit.

[0080] Exemplary Computer Platform In one embodiment, functionality relating to performing mode-selective charge coupling in a multi-qubit architecture in accordance with one or more embodiments described herein may be performed, at least in part, through the use of one or more computing devices. Figure 6 provides an example non-limiting operating environment 600 in which one or more embodiments described herein may be facilitated. Although aspects of these embodiments are described above in the general context of computer-executable instructions that may be executed on one or more computers, those skilled in the art will recognize that these embodiments may also be implemented in combination with other program modules, or as a combination of hardware and software, or both.

[0081] The operating environment 600 may include a central processing unit (CPU) 604, a hard disk drive (HDD) 606, random access memory (RAM) and / or read-only memory (ROM) 608, a keyboard 610, a mouse 612, a display 614, and a communication interface 616 connected to a system bus 602.

[0082] In one embodiment, a number of program modules may be stored in memory 606, 608, and / or CPU 604, including an operating system 642, one or more application programs 644, other program modules 646, and program data 648.

[0083] Although the modules 642-648 and various functions described herein are illustrated in FIG. 6 as being part of the CPU 604, the HDD 606, and / or the RAM / ROM 608, in some embodiments, one or more of these modules may be implemented in the hardware of the computing device 600. For example, the modules discussed herein may be implemented partly in hardware and partly in software. That is, one or more of the components of the memory address translation unit 640 illustrated in FIG. 6 may be implemented in the form of an electronic circuit having transistors, diodes, capacitors, resistors, inductors, varactors, or memristors, or a combination thereof. In other words, the module 646 may be implemented using one or more dedicated electronic circuits that perform the specific tasks and functions described herein.

[0084] conclusion The description of various embodiments of the present teachings has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The technical terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology available on the market, or to allow other skilled in the art to understand the embodiments disclosed herein.

[0085] While the above describes what is believed to be the best mode and / or other examples, it should be understood that various modifications may be made, that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied to many applications, only some of which are described herein. It is intended by the following claims to claim all such applications, modifications, and variations that fall within the true scope of the present teachings.

[0086] The components, steps, features, objects, benefits, and advantages discussed herein are merely illustrative. None of them, nor the discussion thereof, are intended to limit the scope of protection. Although various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, estimates, positions, dimensions, sizes, and other specifications described herein, including the following claims, are approximate and not precise. They are intended to have a reasonable range consistent with the functions involved and practices in the relevant technical field.

[0087] Many other embodiments are contemplated. These include embodiments having fewer, additional, or different or combinations of components, steps, features, objects, benefits, and advantages. These also include embodiments in which the components and / or steps are arranged and / or ordered differently. For example, any of the signals discussed herein may be scaled, buffered, scaled and buffered, converted to another state (e.g., voltage, current, charge, time, etc.), or converted to another state (e.g., high to low and low to high) without significantly altering the underlying control methodology.

[0088] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" does not mean best or optimal, but merely an example. Except as immediately stated, nothing described or illustrated is intended to, or should be construed to, provide the public with any component, step, feature, object, benefit, advantage, or equivalent, whether or not claimed.

[0089] It will be understood that the terms and expressions used herein have the ordinary meanings accorded such terms and expressions with respect to their respective corresponding fields of study and research, unless a specific meaning is otherwise set forth herein. Relative terms such as first and second may be used solely to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or sequence between the one entity or operation and another. The terms "comprises", "comprising" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements may include not only those elements, but also other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by "a" or "an" does not, without further constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0090] The Abstract of the Disclosure is provided to enable the reader to quickly comprehend the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. It can also be seen that in the above Detailed Description, various features have been grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description as if each were an independent and separate claimed subject matter.

Claims

1. 1. A qubit structure comprising: a first fluxonium qubit including a first Josephson junction (JJ) in parallel with a first capacitor and a first superconducting inductor; a second fluxonium qubit coupled in series with the first fluxonium qubit, the second fluxonium qubit including a second JJ in parallel with a second capacitor and a second superconducting inductor; a third capacitor coupled in parallel with the first flaxonium qubit and the second flaxonium qubit; The qubit structure comprises:

2. the first capacitor and the second capacitor are each a superconductor capacitor pad; a common node at an interface of a series connection between the first flaxonium qubit and the second flaxonium qubit is a middle superconductor capacitor pad; the first capacitor pad and the second capacitor pad are capacitively coupled by the third capacitor; The qubit structure of claim 1 .

3. 3. The qubit structure of claim 2, wherein capacitive coupling of the third capacitor is configured to hybridize plasmon-like excitations associated with the first fluxonium qubit and the second fluxonium qubit into bright and dark modes.

4. The qubit structure of claim 3 , wherein the dark mode is higher in frequency than the bright mode.

5. the first flaxonium qubit, the second flaxonium qubit, and the third capacitor create a first diflaxonium qubit; the qubit structure comprising: a second diflaxonium qubit; and a bus resonator coupled between the first diffluxonium qubit and the second diffluxonium qubit; Further comprising: The qubit structure of claim 1 .

6. the bus resonator having a first node capacitively coupled to a middle pad of the first diffluxonium qubit; the bus resonator having a second node capacitively coupled to a middle pad of the second diffluxonium qubit; The qubit structure of claim 5 .

7. The qubit structure of claim 5 , wherein the bus resonator is configured to provide mode-selective charge coupling to suppress crosstalk between uncoupled qubit modes.

8. 6. The qubit structure of claim 5, wherein the first and second fluxonium qubits are implemented by resonator-induced phase (RIP) gates.

9. The qubit structure of claim 5 , wherein the first fluxonium qubit and the second fluxonium qubit are in separate modes.

10. 10. The qubit structure of claim 1, wherein the first fluxonium qubit and the second fluxonium qubit are configured to operate in a zero magnetic field.

11. 10. The qubit structure of claim 1, further comprising a magnetic shield configured to prevent dephasing of the first and second flaxonium qubits due to magnetic flux noise.

12. 1. A method for providing a multi-qubit entanglement gate, comprising: providing a first fluxonium qubit including a first Josephson junction (JJ) in parallel with a first capacitor and a first superconducting inductor; providing a second fluxonium qubit coupled in series with the first fluxonium qubit, the second fluxonium qubit including a second JJ in parallel with a second capacitor and a second superconducting inductor; coupling a third capacitor in parallel to the first fluxonium qubit and the second fluxonium qubit; A method comprising:

13. capacitively coupling the first capacitor pad and the second capacitor pad with the third capacitor; configuring a common node at an interface of a series connection between the first flaxonium qubit and the second flaxonium qubit as an intermediate superconductor capacitor pad; configuring the first capacitor and the second capacitor as superconductor capacitor pads, respectively; The method of claim 12 further comprising:

14. 14. The method of claim 13, further comprising hybridizing plasmon-like excitations associated with the first and second fluxonium qubits into bright and dark modes by capacitive coupling of the third capacitor.

15. the first flaxonium qubit, the second flaxonium qubit, and the third capacitor create a first diflaxonium qubit; The method further comprising: providing a second diflaxonium qubit; coupling a bus resonator between the first diffluxonium qubit and the second diffluxonium qubit; Further comprising: The method of claim 12.

16. capacitively coupling a first node of the bus resonator to a middle pad of the first diffluxonium qubit; capacitively coupling a second node of the bus resonator to a middle pad of the second diffluxonium qubit; The method of claim 15 further comprising:

17. 16. The method of claim 15, further comprising providing mode-selective charge coupling by the bus resonator to suppress crosstalk between uncoupled qubit modes.

18. 16. The method of claim 15, further comprising operating the first fluxonium qubit and the second fluxonium qubit in separate modes.

19. 13. The method of claim 12, further comprising preventing dephasing of the first and second flaxonium qubits due to magnetic flux noise via a magnetic shield.

20. A resonator-induced phase (RIP) gate comprising: A first diffluxonium qubit, a first fluxonium qubit including a first Josephson junction (JJ) in parallel with a first capacitor and a first superconducting inductor; a second fluxonium qubit coupled in series with the first fluxonium qubit, the second fluxonium qubit including a second JJ in parallel with a second capacitor and a second superconducting inductor; a third capacitor coupled in parallel to the first and second flaxonium qubits; a second diflaxonium qubit, a third fluxonium qubit including a third Josephson junction (JJ) in parallel with a fourth capacitor and a third superconducting inductor; a fourth fluxonium qubit coupled in series with the third fluxonium qubit, the fourth fluxonium qubit including a fourth JJ in parallel with a fifth capacitor and a fourth superconducting inductor; the second diffractive fluxonium qubit comprising a sixth capacitor coupled in parallel with the third diffractive fluxonium qubit and the fourth diffractive fluxonium qubit; a bus resonator coupled between the first diffluxonium qubit and the second diffluxonium qubit; A resonator-induced phase (RIP) gate comprising:

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