Pixel circuit for liquid crystal-on-silicon phase modulators.

Abstract

Disclosed herein is a frame buffer pixel circuit having a first data pass gate transistor G1, a first storage capacitor C1, a voltage boost line Vb, a source follower transistor F, a pull-down transistor P, and a second data pass gate transistor G2. The pull-down transistor P is connected to the drain of transistor F and the source of transistor G2, and the storage capacitor C1 is connected to the voltage boost line Vb. In operation, when data is being transferred to the C1 capacitor through the G1 gate, Vb is set to zero volts. After frame data is loaded onto the C1 capacitor in all pixels, Vb is set to a designed voltage and the G2 gates in all pixels are opened to charge the Clcd capacitor. Then, Vb is set to zero volts again before starting to load the next frame data onto the pixels. Such a process is repeated within the liquid crystal on silicon (LCOS) operation time.

Description

Detailed Description of the Invention

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 290,150, filed December 16, 2021, entitled "PIXEL CIRCUITS FOR LIQUID CRYSTAL ON SILICON PHASE MODULATOR," the disclosure of which is expressly incorporated by reference in its entirety. [Technical field]

[0002] The present disclosure relates generally to pixel circuits for liquid crystal on silicon (LCOS) phase modulator devices, and more particularly to frame buffer pixel circuits that can improve the performance of phase modulators. Although some embodiments are described herein with particular reference to their applications, it will be understood that the present disclosure is not limited to such fields of use, but may be applicable in broader contexts. [Background technology]

[0003] Liquid crystal on silicon (LCOS) devices are known in the art for use as optical phase modulators, among other applications. LCOS devices can spatially manipulate optical signals by applying a spatially dependent phase profile to the signal. This has many applications, such as beam steering, image display, spectral compensation, and forward wave shaping.

[0004] Referring to FIG. 1, a conventional LCOS device 100 is illustrated diagrammatically. The LCOS device 100 has a liquid crystal (LC) material 102 sandwiched between a transparent glass substrate 104 having a transparent electrode Vcom 106 and a metal mirror 108 mounted on a silicon substrate 110. The mirror 108 is divided into a two-dimensional (2D) array of individually addressable pixels. Each pixel can be individually driven by a voltage signal to provide a local phase change to an optical signal, thereby providing a two-dimensional array of phase manipulation regions. The liquid crystal elements are pre-aligned by two alignment layers 112a, 112b disposed on the surfaces of the glass substrate 104 and the silicon substrate 110, respectively.

[0005] The second electrode on the silicon backplane consists of a 2D array of pixel circuits. As shown in Figure 2, a typical analog pixel circuit 200 consists of a CMOS data transfer gate G and a data storage capacitor C. In operation, when the gate G is open, data is transferred and stored on the capacitor to drive the liquid crystal element. Although such pixel circuits are simple, they have several disadvantages, including a narrow driving voltage range, a low contrast ratio, high image flicker, and low light output efficiency in some applications.

[0006] The LCOS with the pixel circuit above uses a time-sequential pixel addressing approach that is not suitable for some applications such as holographic displays and color sequential displays. In such displays, the light source needs to be blocked when the LCOS panel is capturing frame data, resulting in low light output efficiency and poor image display quality. Another drawback of the LCOS with such circuit is that the alternating current (AC) drive requirement for the liquid crystal modulator requires the common electrode Vcom on the glass substrate to be fixed at the midpoint of the pixel output voltage range. To achieve AC drive for the LC element, one frame voltage profile is designed into two profiles, one with a positive potential voltage and the other with a negative potential voltage compared to Vcom. Thus, the maximum amplitude of the voltage applied to the LC element is half of the voltage provided by the pixel on the silicon backplane. A low LC drive voltage amplitude has a significant impact on the gray scale of the image.

[0007] Frame buffer pixel circuit technology has attracted the attention of researchers and industry engineers. Lee et al. disclosed a frame buffer pixel circuit 300 as shown in FIG. 3 for an LCOS display device. The circuit consists of a first data passing gate made of CMOS transistors M1 and M2, a storage capacitor Cmem, a source follower transistor M3, and a second data passing gate with transistor M4. In operation, when the first gate is opened, data is transferred from the data line to the capacitor Cmem. After the frame data is stored in all the pixel Cmem capacitors, the second data passing gates in all the pixels are opened to transfer the data to the pixel electrodes (PE).

[0008] Compared with a typical LCOS phase modulator, the LCOS phase modulator with this frame buffer pixel circuit 300 can achieve a higher image contrast ratio and a larger gray scale. Also, the LCOS phase modulator with such a frame buffer pixel circuit is likely to be used for holographic displays, color sequential displays, and wavefront correction for astronomical observation to significantly improve light output efficiency and image quality. Another advantage of such a frame buffer pixel is that the voltage applied to the LC element can be easily set by adjusting the potential voltage of the flip-flop Vcom to meet the requirements for various applications. This is very important for LCOS phase modulators that require high voltage to fully drive the LC element, such as polarization-independent LCOS (PI-LCOS) phase modulators.

[0009] However, to maximize the output voltage range, conventional frame buffer pixel circuits use CMOS data transfer gates, which result in the need for more doping wells. This can complicate the silicon backplane manufacturing process, increase pixel size, and reduce yields. Another disadvantage of conventional frame buffer pixel circuits is that the output voltage at the PE in such frame buffer pixel circuits decays quickly due to current leakage and other effects, resulting in relatively large phase flicker for LCOS phase modulators. Summary of the Invention

[0010] In conventional frame buffer pixel circuits, CMOS transistors are used to maximize the output voltage range of the pixel circuit. Such a circuit structure has the disadvantages of larger pixel size, more complex silicon backplane manufacturing process, and lower yield compared to pixel circuits with only NMOS or PMOS transistors.

[0011] Therefore, in some embodiments of the present disclosure, a simple pixel circuit, a small pixel size, a large output voltage range, and a stable voltage can be realized by using a different frame buffer pixel circuit structure and a voltage boosting technique. The LCOS phase modulator with such a pixel circuit has special applications such as high resolution, color sequential, and holographic displays.

[0012] Instability in the potential voltage on each pixel causes phase variations in the LCOS phase modulator. For applications with high sensitivity to signal flicker, conventional techniques cannot be used with LCOS phase modulators (e.g., LCOS phase modulators for wavelength selective switches (WSS) used in communication networks).

[0013] Therefore, we propose some embodiments of the present disclosure that provide a method for generating a stable phase in an LCOS modulator. With the invented circuit, a so-called source follower is added to keep the pixel output PE charged so as to keep driving the liquid crystal element with a stable potential voltage, the LCOS phase modulator can greatly reduce phase flicker.

[0014] Embodiments of the present disclosure will now be described, by way of example only, with reference to the following drawings, in which: [Brief description of the drawings]

[0015] [Figure 1] FIG. 2 is a side view of an LCOS phase modulator. [Diagram 2] FIG. 2 is a schematic diagram of an analog pixel circuit. [Diagram 3] FIG. 1 is a schematic diagram of a prior art frame buffer pixel circuit; [Figure 4] FIG. 2 is a schematic diagram of a first embodiment of a frame buffer pixel circuit; [Diagram 5] FIG. 13 illustrates simulation results for the output voltage range of the first embodiment of the frame buffer pixel circuit. [Figure 6]1A and 1B are schematic diagrams of a second embodiment of a frame buffer pixel circuit; [Figure 7] FIG. 13 is a diagram showing simulation results of the output voltage range and voltage holding ratio of the second embodiment of the frame buffer pixel circuit. [Figure 8] FIG. 4 is a schematic diagram of a third embodiment of a frame buffer pixel circuit. [Figure 9] 13 shows simulation results of the output voltage range and voltage holding ratio of the third embodiment of the frame buffer pixel circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The subject matter of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. With respect to the figures, like numerals refer to like elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0017] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant art and this disclosure, and it will be further understood that they are not to be interpreted in an idealized or overly formal sense unless expressly defined as such in this specification.

[0018] A first embodiment of a frame buffer pixel circuit 400 is shown in Figure 4. The circuit consists of a first data pass gate transistor G1, a first storage capacitor C1, a voltage boost line Vb, a source follower transistor F, a pull-down transistor P, and a second data pass gate transistor G2. Compared to the previous frame buffer pixel circuit 300 shown in Figure 3, differences include, but are not limited to: 1) the pull-down transistor P is now connected to the drain of transistor F and the source of transistor G2; 2) the storage capacitor C1 is connected to the voltage boost line Vb instead of GND; and 3) all transistors are NMOS transistors.

[0019] Placing transistor P in front of G2 reduces current leakage to Clcd and the parasitic gate capacitor, resulting in increased voltage stability. The use of voltage boost Vb allows the pixel output voltage range to be extended much more than without the voltage booster. In operation, when data is being transferred to the C1 capacitor through the G1 gate, Vb is set to zero volts. After the frame data is loaded onto the C1 capacitor in all pixels, Vb is set to a designed voltage and the G2 gates in all pixels are opened to charge the Clcd capacitor. Then, Vb is set to zero volts again before starting to load the next frame data onto the pixel. This process is repeated within the LCOS operation time.

[0020] FIG. 5 shows the simulation results of the output voltage range for the first embodiment of the frame buffer pixel with different boost voltages. The simulation results show that the maximum voltage range can be achieved when Vb is near the transistor threshold voltage (for example, 0.8V here). The maximum output voltage range is greater than 4V, as in the case of the prior art frame buffer pixel circuit. Compared with the prior art frame buffer pixel using CMOS gate transistors, this circuit uses all NMOS transistors, which simplifies the circuit structure and is conducive to the design of small size pixels and high resolution LCOS phase modulators. The LCOS phase modulator with this pixel circuit is advantageous for some special applications, such as holographic displays and color sequential displays, where small pixel size and high resolution are crucial to achieve large viewing angles and high quality displays.

[0021] Holographic displays allow the viewer to look around an object and see it from different perspectives. This results in a more comfortable and natural-like viewing experience without all the complexities associated with stereo 3D displays. In recent years, the development of digital and computer-generated holographic display technologies has been widely carried out in research institutes and industrial enterprises. Holographic communication may be one of the most interesting features of the sixth generation (6G) network. As the 5G / 6G network deployment progresses, holographic displays will become more and more attractive to researchers, engineers, investors, and consumers. The core component in such a holographic display system is the phase modulator. LCOS phase modulators have competitive advantages over others, such as high resolution, small pixel size, and high pixel fill factor. For holographic displays with conventional LCOS phase modulators, the light needs to be blocked during data capture to minimize the flicker of high diffraction orders. LCOS phase modulators with frame buffer pixel circuits can perform data capture and display in parallel, offering several advantages over typical LCOS phase modulators (e.g., higher optical efficiency, higher display quality, and lower flicker of higher-order diffraction lights), and therefore have a high potential for use in computer-generated holographic displays.

[0022] Color sequential display systems are much simpler than common color display systems, with fewer spatial light modulators and a much simpler optical system. Color sequential LCOS displays are widely used in projection displays, wearable displays (including near-eye displays), and smart watches. For color sequential displays, LCOS phase modulators with frame buffer pixel circuits have significant advantages over common LCOS phase modulators (e.g., much higher light output efficiency and much higher display quality). When using traditional LCOS phase modulators, the light is shut off during data capture and only turned on during the display period. When using frame buffer pixel-based LCOS phase modulators, data capture and display can be performed in parallel, which can greatly improve light efficiency and display quality.

[0023] Wavefront correction is mainly used in astronomical observation and also in free-space optical (FSO) communications. In astronomical observation and flying object tracking, atmospheric turbulence causes two effects on telescope images: image resolution loss and intensity loss. By dynamically correcting wavefront distortions, image quality can be significantly improved and light intensity can be increased. Using an LCOS phase modulator with frame buffer pixels allows wavefront correction to be performed on a frame-by-frame basis, which can significantly improve image quality compared to using line-scan LCOS phase modulators.

[0024] FIG. 6A shows a second embodiment of a frame buffer pixel circuit 600. The second embodiment includes a data input line, a first data pass gate transistor G1, a first data storage capacitor C1, a first source follower transistor F1, a pull-up transistor P1, a second pass gate transistor G2, a second data storage capacitor C2, a second source follower transistor F2, and a pull-down transistor P2. In operation, signal data is sent to the source side of G1 through the data line. When the first transistor gate G1 is opened, data is transferred to the drain of the transistor and stored in the first storage capacitor C1. After C1 is fully charged, the G1 gate is closed. When the full frame data is fully captured in the C1 capacitor in all pixels, the second G2 gate in all pixels is opened simultaneously. The full frame data is transferred and stored in the C2 capacitor in all pixels. When the C2 capacitor is fully charged, the G2 gate is closed. The second source follower F2 then charges the Clcd and the parasitic capacitors and provides a voltage PE to drive the LC element. The pull-up transistor P1 opens when the gate transistor G2 opens, then closes after G2 closes to fully charge the capacitor C2. The pull-down transistor P2 is used to clean the capacitance at the PE point before Clcd is charged.

[0025] Since there are two source followers in the pixel circuit, the design needs to be optimized so that the circuit can provide a large enough output voltage range to drive the LC element with a large gray scale. To maximize the output voltage range, the two source followers have one follower (circuit 600) with PMOS transistors and the other (circuit 602) with NMOS transistors, as shown in Figures 6A and 6B, respectively.

[0026] Figure 7 shows the simulation results of pixel output voltage range and voltage holding ratio. The output voltage range is larger than 3.0V, which is generally high enough to fully drive the LC element. In the circuit, the data storage capacitor C2 and the LC drive electrode PE are separated by a second source follower, so C2 is not affected by the LC element, shunt current leakage, and the interference of surrounding pixels. Therefore, the voltage holding ratio is greatly improved compared to the prior art frame buffer pixel circuit. An LCOS phase modulator with such a pixel circuit may have advantages for applications with strict requirements for flicker of phase modulation, such as LCOS phase modulators for wavelength selective switches (WSS) that are widely used in optical communication networks.

[0027] A third embodiment of a frame buffer pixel circuit 800 is shown in FIG. 8. Compared with the second embodiment of the frame buffer pixel circuit 600 / 602, this pixel circuit 800 is modified to use all NMOS transistors, and the data storage capacitors C1 and C2 are connected to voltage boost lines Vb1 and Vb2, respectively. In operation, when data is being transferred to C1 through the G1 gate, Vb1 is set to zero volts. After the frame data is captured onto the C1 capacitor in all pixels, Vb1 is set to a designed voltage, and the G2 gates in all pixels are opened to charge the C2 capacitor to a designed potential voltage. After the G2 gates are closed, Vb2 is set to a designed voltage to expand the voltage at the PE point.

[0028] 9 shows the simulation results of the output voltage range and voltage holding ratio of this third embodiment of the frame buffer pixel 800. From the simulation results, the output voltage range is greater than 3.0V, and the voltage is very stable. Using only NMOS transistors in this circuit may simplify the circuit design and improve performance.

[0029] Reconfigurable add / drop multiplexers (ROADMs) facilitate the addition of new services without requiring costly upgrades or major changes to the communication network. ROADM systems allow remote, accurate and flexible selection of wavelengths, thus significantly increasing network capacity without significant expense. The ROADM market is predicted to have significant growth following the progress of 5G / 6G network deployment. LCOS phase modulators are widely used in WSS systems, which are the core subsystem of ROADM systems. Currently, all LCOS phase modulators used can only perform polarization-dependent phase modulation. Therefore, the light polarization needs to be carefully manipulated, resulting in a complex optical system. The second and third frame buffer pixel circuits can be used in polarization-independent LCOS (PI-LCOS) phase modulators. Using PI-LCOS phase modulators, WSS systems can have a much simpler optical system, higher performance, and lower cost compared to WSS systems using common LCOS phase modulators.

[0030] In the drawings and specification, exemplary embodiments of the present disclosure are disclosed. However, many variations and modifications can be made to these embodiments without substantially departing from the principles of the present disclosure. Thus, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, and the scope of the present disclosure is defined by the following claims.

Claims

1. 1. A circuit for controlling pixel electrodes of a liquid crystal on silicon backplane phase modulator, comprising: a first data transfer controller and a second data transfer controller; a data storage unit; A voltage booster, a signal amplification unit having a pull-down unit; A circuit in which an analog data signal is first transferred through the first data transfer controller and stored in the data storage unit, then the voltage booster is switched from zero volts to a desired voltage, and then the data is transferred to the liquid crystal drive electrode through the second data transfer controller.

2. 2. The circuit of claim 1, wherein the data storage unit is composed of a voltage-independent capacitor and a gate capacitor of the signal amplification unit.

3. 2. The circuit of claim 1, wherein a pull-down transistor is placed before the second data transfer controller.

4. 2. The circuit of claim 1, wherein all transistors in said circuit are NMOS transistors.

5. 2. The circuit of claim 1, wherein the data storage unit is connected to a voltage booster switch that can provide 0V or a desired boost voltage.

6. A circuit for controlling pixel electrodes of a liquid crystal on a silicon phase modulator, comprising: The data line and a first data transfer controller and a second data transfer controller; a first storage unit and a second storage unit; a first amplifier circuit and a second amplifier circuit; the first data transfer controller is enabled by a first control signal to store a first analog data signal containing pixel data in the first storage unit; Then, the pixel data is coupled by the first amplifier circuit to an input of the second data transfer controller enabled by a second control signal, and an output of the first amplifier circuit is coupled to the second storage unit, thereby storing a second analog data signal proportional to the first analog data signal in the second storage unit; the second storage unit is directly coupled to the second amplifier circuit, and an output voltage proportional to the second analog data signal is generated at an output electrode to drive a liquid crystal element and perform optical phase modulation in the liquid crystal on the silicon phase modulator; and the first amplifier circuit and the second data transfer controller provide isolation between the first storage unit and the second storage unit; The second amplifier circuit provides isolation between the second storage unit and the output electrode.

7. 7. The circuit of claim 6, wherein the first storage unit is comprised of a voltage-independent capacitor and a gate capacitor of the first amplifier circuit.

8. 7. The circuit of claim 6, wherein the second storage unit is comprised of a voltage-independent capacitor and a gate capacitor of the second amplifier circuit.

9. 7. The circuit of claim 6, wherein the first storage unit and the second storage unit can be independently optimized to achieve best performance.

10. 7. The circuit of claim 6, wherein the first amplifier circuit and the second amplifier circuit each use different MOS transistors, either PMOS transistors or NMOS transistors.

11. A circuit for controlling pixel electrodes of liquid crystal on a silicon phase modulator, the circuit comprising: a data line, a first data transfer controller, a second data transfer controller, a first storage unit and a second storage unit connected to a first voltage booster and a second voltage booster, and a first amplifier circuit and a second amplifier circuit, wherein when data is being transferred to the first storage unit via the first data transfer controller, the first voltage booster is set to 0V, then when the data is being transferred to the second storage unit via the second data transfer controller, the first voltage booster is set to a desired voltage, the second voltage booster is set to 0V, then the second voltage booster is set to a desired voltage, the second amplifier circuit charges the pixel electrodes to drive the liquid crystal elements, and then the first voltage booster is set to 0V again before starting to load the next frame data into the pixels.

12. The circuit of claim 11, wherein the first memory unit and the second memory unit are connected to the first voltage booster and the second voltage booster, respectively.

13. 12. The circuit of claim 11, wherein the first storage unit and the second storage unit can be independently optimized to achieve best performance.

14. 12. The circuit of claim 11, wherein all transistors are NMOS transistors.

15. 1. A system for controlling pixel electrodes of a liquid crystal on silicon backplane phase modulator, the system comprising: a first data transfer controller and a second data transfer controller; a data storage unit; A voltage booster, a signal amplification unit with a pull-down unit.

16. 16. The system of claim 15, wherein an analog data signal is first transferred through the first data transfer controller and stored in the data storage unit, then the voltage booster is switched from zero volts to a predetermined voltage, and then the data is transferred to the liquid crystal drive electrodes through the second data transfer controller.

17. 16. The system of claim 15, wherein the data storage unit includes a voltage-independent capacitor and a gate capacitor of an amplifier circuit.

18. 16. The system of claim 15, further comprising a pull-down transistor disposed before the second data transfer controller.

19. 16. The system of claim 15, wherein each transistor in the system is an NMOS transistor.

20. 16. The system of claim 15, further comprising a data storage capacitor connected to a voltage booster switch capable of providing 0V or a predetermined boosted voltage.

21. 1. A system for controlling pixel electrodes of a liquid crystal on a silicon phase modulator, the system comprising: The data line and a first data transfer controller and a second data transfer controller; a first storage unit and a second storage unit; a first amplifier circuit and a second amplifier circuit; the first data transfer controller is enabled by a first control signal to store a first analog data signal containing pixel data in the first storage unit; Then, the pixel data is coupled by the first amplifier circuit to an input of the second data transfer controller enabled by a second control signal, and the output of the first amplifier circuit is coupled to the second storage unit, thereby storing a second analog data signal proportional to the first analog data signal in the second storage unit; the second storage unit is directly coupled to the second amplifier circuit; an output voltage proportional to the second analog data signal is generated at an output electrode to drive a liquid crystal element and perform optical phase modulation within the liquid crystal on the silicon phase modulator; The first amplifier circuit and the second data transfer controller provide isolation between the first storage unit and the second storage unit, and the second amplifier circuit provides isolation between the second storage unit and the output electrode.

22. 22. The system of claim 21, wherein the first storage unit includes a voltage-independent capacitor and a gate capacitor of the first amplifier circuit.

23. 22. The system of claim 21, wherein the second storage unit includes a voltage-independent capacitor and a gate capacitor of the second amplifier circuit.

24. 22. The system of claim 21, wherein the first storage unit and the second storage unit are independently optimized to achieve best performance.

25. 22. The system of claim 21, wherein the first amplifier circuit and the second amplifier circuit each use different MOS transistors, either PMOS transistors or NMOS transistors.

26. 1. A system for controlling pixel electrodes of a liquid crystal on a silicon phase modulator, the system comprising: The data line and a first data transfer controller and a second data transfer controller; a first storage unit and a second storage unit connected to the first voltage booster and the second voltage booster; a first amplifier circuit and a second amplifier circuit; When data is being transferred to the first storage unit via the first data transfer controller, the first voltage booster is set to 0V, then when the data is being transferred to the second storage unit via the second data transfer controller, the first voltage booster is set to a predetermined voltage, the second voltage booster is set to 0V, then the second voltage booster is set to a predetermined voltage, the second amplifier circuit charges the pixel electrodes to drive the liquid crystal elements, and then before starting to load the next frame data into the pixels, the first voltage booster is set to 0V again.

27. 27. The system of claim 26, wherein the first storage unit and the second storage unit are connected to the first voltage booster and the second voltage booster, respectively.

28. 27. The system of claim 26, wherein the first storage unit and the second storage unit are independently optimized to achieve best performance.

29. 27. The system of claim 26, wherein all transistors in the system are NMOS transistors.

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