Oscillator Frequency Accuracy and Amplitude Control

Abstract

In some examples, an electronic device (104) includes an oscillator circuit (118) configured to provide an output signal, and a controller (112) coupled to the oscillator circuit, the controller configured to receive a first target rate and a second target rate, dynamically adjust a frequency accuracy of the output signal based on the first target rate, and dynamically adjust an amplitude of the output signal based on the second target rate.

Description

[Background technology]

[0001] Circuits perform various operations. Some circuit operations may benefit from a clock signal. An oscillator may provide such a clock signal to a circuit. Oscillators may provide clock signals having different frequencies, and an oscillator may provide a clock signal of a particular frequency with various levels of accuracy. For example, in an application requiring a high level of clock signal frequency accuracy (such as radio frequency communication), an oscillator may operate in a high power mode and provide a clock signal that varies only slightly from a target frequency. Conversely, in an application requiring a low level of clock signal frequency accuracy (such as idle timekeeping), an oscillator may operate in a low power mode and provide a clock signal that may vary more from a target frequency. Summary of the Invention

[0002] In some examples, an electronic device includes an oscillator circuit configured to provide an output signal, and a controller coupled to the oscillator circuit, the controller configured to receive first and second target rates, dynamically adjust a frequency accuracy of the output signal based on the first target rate, and dynamically adjust an amplitude of the output signal based on the second target rate.

[0003] In some examples, a method includes receiving a first target value and a first threshold rate for a frequency accuracy of an oscillator output signal, receiving a second target value and a second threshold rate for an amplitude of the oscillator output signal, adjusting the first value of the frequency accuracy of the oscillator output signal toward the first target value at a rate equal to or less than the first threshold rate, and adjusting a second value of the amplitude of the oscillator output signal toward a second target value at a rate equal to or less than the second threshold rate. [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of a system configured to control oscillator frequency accuracy and amplitude in accordance with various examples.

[0005] [Diagram 2] 1 is a circuit schematic diagram of an electronic device configured to control oscillator frequency precision and amplitude, according to various examples.

[0006] [Diagram 3] 1 is a timing diagram illustrating the operation of an electronic device configured to control oscillator frequency precision and amplitude in various examples.

[0007] [Figure 4] FIG. 1 is a block diagram of an amplitude controller of an electronic device configured to control oscillator frequency accuracy and amplitude, according to various examples.

[0008] [Diagram 5] 1 illustrates data structures useful in operating an electronic device configured to control oscillator frequency precision and amplitude, according to various examples.

[0009] [Figure 6] FIG. 1 is a block diagram of a mode controller of an electronic device configured to control oscillator frequency precision and amplitude, according to various examples.

[0010] [Figure 7] 1 illustrates data structures useful in operating an electronic device configured to control oscillator frequency precision and amplitude, according to various examples.

[0011] [Figure 8] 1 is a flowchart of a method for operating an electronic device configured to control oscillator frequency precision and amplitude, according to various examples.

[0012] [Figure 9] 1 is a circuit schematic diagram of an electronic device configured to control oscillator frequency precision and amplitude, according to various examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] As discussed above, oscillators have different operating modes that exploit tradeoffs between power consumption and clock signal frequency accuracy. For example, an oscillator may have a first power mode that consumes a large amount of power but provides a highly accurate clock signal frequency, and a second power mode that consumes less power but provides a less accurate clock signal frequency.

[0014] However, for many applications, two oscillator power modes do not provide adequate granularity. Some applications may require additional power modes between the first and second power modes. For example, an application may require medium frequency accuracy and medium power consumption, rather than high frequency accuracy and high power consumption or low frequency accuracy and low power consumption. Other applications may require even finer granularity.

[0015] Also, large gradients between power modes can cause the oscillator circuit to become unstable. For example, switching from a high power, high frequency accuracy mode to a low power, low frequency accuracy mode can cause a large fluctuation in the amount of energy in the oscillator circuit crystal. This energy gradient applied to the oscillator circuit crystal can cause the oscillator circuit to become unstable, which can result in malformed clock pulses, missing clock pulses, or cessation of oscillation.

[0016] This description provides various examples of electronic devices that alleviate the above-mentioned problems. Specifically, the electronic device includes a crystal oscillator circuit and a digital controller coupled to the oscillator circuit. The digital controller receives inputs (e.g., from a processor in the electronic device) that specify target amplitude and frequency precision levels for the oscillator circuit clock signal. These inputs also specify the rate at which the oscillator transitions from the current amplitude and frequency precision levels to the target amplitude and frequency precision levels. The digital controller controls components in the oscillator circuit, such as variable capacitors, variable resistors, current mirrors, etc., to achieve the target amplitude and frequency precision levels specified by the inputs to the digital controller. The digital controller also controls the oscillator circuit to achieve these target amplitude and frequency precision levels at the target rate rates specified by the inputs to the digital controller. In this manner, the oscillator circuit can be controlled to provide a particular clock signal amplitude and frequency precision level with a high level of granularity. The oscillator circuit can also be controlled to transition smoothly and gradually to the target clock signal amplitude and frequency precision levels, thereby avoiding oscillator circuit instability derived from large energy gradients in the oscillator circuit crystal.

[0017] FIG. 1 is a block diagram of a system 100 configured to control oscillator frequency precision and power (e.g., amplitude) in various examples. The example system 100 may be, include, or be part of a personal computer, a server, an appliance, a networking device, an automobile, an aircraft, a spacecraft, or any other suitable technology that may include an oscillator. The system 100 includes a processor 102, an electronic device 104, a circuit 106, and a storage 108. In some examples, the components of the electronic device 104 are included in a single semiconductor package. In some examples, the components of the electronic device 104 are distributed across two or more semiconductor packages. The circuit 106 is any type of circuit that uses a clock signal generated by an oscillator. The circuit 106 may utilize the clock signal to implement, for example, radio frequency, computing, and / or timekeeping applications. The storage 108 is any suitable type of storage, such as, for example, a random access memory (RAM) or a read-only memory (ROM). In some examples, the processor 102, the electronic device 104, the circuitry 106, and / or the storage 108 are implemented together on a common printed circuit board (not explicitly shown). In other examples, the processor 102, the electronic device 104, the circuitry 106, and / or the storage 108 are mounted on two or more printed circuit boards.

[0018] The storage 108 includes executable code 110 which, when executed by the processor 102, causes the processor 102 to perform some or all of the actions attributed to the processor 102 herein. The electronic device 104 includes a digital controller 112 which includes an amplitude controller 114 and a mode controller 116. Example structures and operations of the amplitude controller 114 and the mode controller 116 are described below. The electronic device 104 also includes an oscillator circuit 118, example structures and operations of which are described below. The processor 102 includes one or more registers 120, example operations of which are described below.

[0019] A connection 122 couples the processor 102 to the amplitude controller 114. A connection 124 couples the processor 102 to the mode controller 116. A connection 126 couples the amplitude controller 114 to the oscillator circuit 118. A connection 128 couples the mode controller 116 to the oscillator circuit 118. A connection 130 couples the oscillator circuit 118 to the circuit 106. An amplitude feedback connection 132 couples the oscillator circuit 118 to the amplitude controller 114 and the mode controller 116. The oscillator circuit 118 is coupled to a crystal 134. In some examples, the crystal 134 is part of the electronic device 104, and in other examples, the crystal 134 is external to the electronic device 104. Similarly, various components shown in FIG. 1 as being within the electronic device 104 may be external to the electronic device 104 in some examples. The various connections described herein are examples and do not limit the scope of the description. In the drawings, a diagonal line extending across a connection indicates that the connection may include multiple connections, but is depicted and referenced herein as a single connection for clarity and brevity. It is within the scope of this description if a connection that does not have a diagonal line extending across it includes one or multiple connections. Similarly, the scope of this description is not limited to the precise configuration of components shown in the drawings.

[0020] In operation, the oscillator circuit 118 provides a clock signal CLK to the circuit 106. The circuit 106 uses the CLK in any suitable manner. The digital controller 112 controls the oscillator circuit 118 based on inputs received from the register 120. For example, the digital controller 112 dynamically adjusts components in the oscillator circuit 118 to dynamically control the amplitude and frequency accuracy of the CLK. For example, the digital controller 112 may adjust a variable capacitor in the oscillator circuit 118 to more closely match the frequency of the CLK to a target frequency. Similarly, the digital controller 112 may adjust a variable capacitor in the oscillator circuit 118 to cause the frequency of the CLK to vary to a greater extent relative to the target frequency (e.g., the digital controller 112 may tolerate a decrease in the CLK frequency accuracy). For example, the digital controller 112 may adjust a variable resistor in the oscillator circuit 118, a current mirror in the oscillator circuit 118, or a combination thereof to increase or decrease the amplitude of the CLK. As described below, in some examples, the amplitude controller 114 is configured to control the amplitude of CLK by adjusting a current mirror of the oscillator circuit 118 via connection 126. Similarly, as described below, in some examples, the mode controller 116 is configured to control the amplitude of CLK and the frequency accuracy of CLK by adjusting a variable resistor and a variable capacitor, respectively, of the oscillator circuit 118 via connection 128. An amplitude feedback connection 132 provides amplitude feedback from the oscillator circuit 118 to the amplitude controller 114 and the mode controller 116 to enable the amplitude controller 114 and the mode controller 116 to maintain a target amplitude of CLK.

[0021] The amplitude controller 114 and the mode controller 116 control the CLK by manipulating the oscillator circuit 118 as described above and in more detail below. In some examples, the behavior of the amplitude controller 114 and the mode controller 116 is determined by the contents of the register 120. In other words, a user, such as an engineer, designer, computer scientist, or software developer, may instruct the processor 102 (e.g., using an input device such as a keyboard, mouse, microphone, etc.) as to a target amplitude and a target frequency accuracy of the CLK. The user may also instruct the processor 102 as to a target rate at which the amplitude and frequency accuracy of the CLK should be changed to the target amplitude and frequency accuracy. As described above, rapid changes in amplitude and / or frequency accuracy may destabilize the oscillator circuit 118. Thus, in some examples, the target rate facilitates smooth, gradual changes in the amplitude and frequency accuracy of the CLK. The processor 102 receives such input and stores it in the register 120 in any suitable data format, such as a data format that the amplitude controller 114 and the mode controller 116 can understand. The amplitude controller 114 reads the contents of the register 120 via connection 122, and the mode controller 116 reads the contents of the register 120 via connection 124. The amplitude controller 114 and the mode controller 116 then operate to control the oscillator circuit 118 based on the contents of the fetched register. In the remainder of this description, various components of Figure 1 will be described in further detail with reference to Figures 2-9.

[0022] FIG. 2 is a circuit schematic diagram of the electronic device 104 in various examples. As mentioned above, the electronic device 104 includes a digital controller 112 coupled to an oscillator circuit 118. In some examples, the oscillator circuit 118 is a Pierce oscillator circuit. The scope of this description includes other oscillator circuits, such as a Colpitts oscillator circuit and a Clapp oscillator circuit. Although FIG. 2 illustrates the oscillator circuit 118 as a crystal oscillator circuit, non-crystal oscillator circuits may also be useful. The exemplary oscillator circuit 118 includes a current mirror 204 including a transistor 206 (e.g., a field effect transistor (FET) such as a metal oxide semiconductor FET (MOSFET)) and a transistor 208 (e.g., a FET). In some examples, the transistors 206 and 208 are p-type FETs. The sources of the transistors 206 and 208 are coupled to each other and to a voltage source 209. The gates of the transistors 206 and 208 are coupled to each other at a node 212. The drain of transistor 206 is coupled to node 212. The drain of transistor 208 is coupled to node 213.

[0023] The node 212 is coupled to a first end of a variable resistor 210 (eg, a digital potentiometer). A second end of the variable resistor 210 is coupled to a node 222.

[0024] Node 213 is coupled to a first end of resistor 211. A second end of resistor 211 is coupled to node 214. A crystal 134 (e.g., a piezoelectric crystal) is coupled across nodes 213 and 214. A transistor 216 (e.g., an n-type FET) is coupled between nodes 213 and 222. For example, a drain of transistor 216 is coupled to node 213 and a source of transistor 216 is coupled to node 222. A gate of transistor 216 is coupled to node 214.

[0025] A variable capacitor 218 (e.g., a digitally adjustable capacitor, a digitally programmable variable capacitor) is coupled between nodes 213 and 222. A variable capacitor 220 is coupled between nodes 214 and 222. Variable capacitors 218 and 220 may be referred to as load capacitors. Node 222 is coupled to another voltage source 224. In some examples, voltage source 224 is grounded.

[0026] An amplitude detector 226 has an input coupled to node 214. In some examples, the amplitude detector 226 may be coupled to nodes 213 and 214 in parallel with a crystal 134. The amplitude detector 226 has an output coupled to an input of an analog to digital converter (ADC) 228. The output of the ADC 228 is coupled to the amplitude feedback connection 132. The output of the oscillator circuit 118 is labeled as connection 130 at node 213 and provides the clock signal CLK.

[0027] The digital controller 112 includes an amplitude controller 114 and a mode controller 116. An amplitude feedback connection 132 to the amplitude controller 114 and the mode controller 116 provides amplitude feedback from an oscillator circuit 118. In some examples, the amplitude feedback connection 132 couples directly to the mode controller 116, which couples directly to the amplitude controller 114, as shown in Figure 1. In other examples, the amplitude feedback connection 132 couples directly to the mode controller 116, which provides an amplitude feedback signal to the amplitude controller 114 on the amplitude feedback connection 132 (which shares the number 132 with the connection 132 provided to the mode controller 116 for consistency), as shown in Figure 2. Other configurations are contemplated.

[0028] The amplitude controller 114 receives a target ratio input via connection 122. The target ratio indicates to the amplitude controller 114 how it should control the current mirrors 204 in the oscillator circuit 118 to achieve the target amplitude of CLK. In some examples, the amplitude controller 114 receives the target ratio from a register 120 (FIG. 1).

[0029] The mode controller 116 receives input from the register 120 (FIG. 1) via connection 124. As mentioned above, one or more connections shown in the drawings may include multiple physical connections even when shown as a single connection. For example, the connections 124 may include nine physical connections: three target input connections, three time increment input connections, and three step size input connections. The three target input connections indicate target values ​​for the variable resistor 210, the variable capacitor 218, and the variable capacitor 220. The three time increment input connections indicate the time the mode controller 116 waits between receiving the target values ​​for the variable resistor 210, the variable capacitor 218, and the variable capacitor 220 and enabling those target values ​​in the oscillator circuit 118. The three step size input connections indicate the maximum steps the mode controller 116 may take when adjusting the variable resistor 210, the variable capacitor 218, and the variable capacitor 220. For example, the step size input may indicate that the mode controller 116 should take the smallest possible steps when adjusting the variable resistor 210. So, instead of changing the digital control output to the variable resistor 210 from 0000 to 0100, the mode controller 116 may change the digital control output to the variable resistor 210 from 0000 to 0001, then 0010, then 0011, then 0100. In this manner, the mode controller 116 achieves smooth, gradual changes between resistance and capacitance values ​​in the oscillator circuit 118. Figure 2 also shows connection 128, which may include three separate connections. The first connection is an output connection from the mode controller 116 to a variable resistor 210, which controls the variable resistor 210; the second connection is an output connection from the mode controller 116 to a variable capacitor 218, which controls the variable capacitor 218; and the third connection is an output connection from the mode controller 116 to a variable capacitor 220, which controls the variable capacitor 220.

[0030] The operation of the electronic device 104 will now be described. First, the operation of the oscillator circuit 118 will be described, followed by the operation of the digital controller 112. The crystal 134 is a piezoelectric crystal. Thus, when a voltage is applied across the crystal 134, the crystal 134 undergoes a physical deformation. When no voltage is applied across the crystal 134, the crystal 134 reverses its physical deformation and provides a voltage across its terminals (e.g., nodes 213 and 214). The transistor 216 acts as an amplifier, where a small voltage change at the gate of the transistor 216 produces a large change in the drain current. The crystal 134 and the transistor 216 are coupled together in a loop. The loop includes the transistor 216, the node 213, the crystal 134, and the node 214. The variable capacitors 218, 220 (which may also be referred to as load capacitors) are coupled to the nodes 213 and 214, respectively, such that the variable capacitors 218, 220 are also part of the loop. The voltage through the loop begins to oscillate and continues to oscillate as long as certain oscillation criteria, known as the Barkhausen criteria, are met. The Barkhausen criteria for oscillation include: i) the product of the gain around the loop at the desired oscillation frequency must be at least 1; and ii) the total phase shift around the loop must be 0 or any integer multiple of 2π (360 degrees). When the Barkhausen criteria are met, the loop begins the start-up phase of oscillation. Specifically, transistor 216 amplifies the noise in the loop (which can be any noise from any source in the circuit) and provides the amplified signal to crystal 134. Crystal 134 has a unique resonant frequency and acts as a filter by responding only to signals with this resonant frequency. Crystal 134 does not respond to signals at other frequencies. Crystal 134 returns the signal at the resonant frequency to transistor 216, which amplifies the signal it receives from crystal 134 and provides the amplified signal to crystal 134. This oscillating process of amplification and frequency filtering continues between transistor 216 and crystal 134. This oscillation continues as long as the loop meets the Barkhausen criterion.

[0031] The loop of Figure 2 satisfies the Barkhausen criterion because i) transistor 216 is selected to provide a gain of at least 1, and ii) the total phase shift around the loop including transistor 216, crystal 134, and variable capacitors 218 and 220 is designed to be 0 or an integer multiple of 2π. For example, crystal 134, in combination with variable capacitors 218 and 220, forms a π network bandpass filter providing a 180° phase shift and output-to-input voltage gain near the resonant frequency of crystal 134. At this frequency of oscillation, crystal 134 appears inductive. The combination of the 180° phase shift (e.g., inverting gain) from the π network and the negative gain from transistor 216 results in a positive loop gain that destabilizes the bias point set by resistor 211, resulting in oscillation.

[0032] The variable capacitors 218, 220 provide significant control over the frequency accuracy of the signal oscillating in the loop, and therefore the clock signal CLK. More specifically, the crystal 134 is fabricated so that the resonant frequency is at a target value when the load capacitance provided by the variable capacitors 218, 220 (e.g., load capacitors) is at a certain value. If the load capacitance is smaller, the resonant frequency of the crystal 134 will be higher than the specified value (e.g., the frequency error will be larger), but less power will be required to maintain the oscillation. Because the variable capacitors 218, 220 are tied to ground, they are in series across the crystal 134. So, for example, if the variable capacitors 218, 220 are both set to 16 picofarads, the crystal 134 will have a load capacitance of 8 picofarads (equivalent to two 16 picofarad capacitors in series). If the crystal 134 is specified to have a load capacitance of 8 picofarads, then setting the variable capacitors 218, 220 to 16 picofarads each will result in the target resonant frequency. If instead the variable capacitors 218, 220 are set to 10 picofarads each, then the combined load capacitance will be 5 picofarads and the resonant frequency will be higher than the target. Thus, adjusting the capacitance of the variable capacitors 218, 220 will affect the frequency accuracy of the oscillating signal (and therefore of the CLK).

[0033] The current provided to transistor 216 via node 213 significantly controls the amplitude of the oscillating signal in the loop, and therefore the amplitude of CLK. Current mirror 204 and variable resistor 210 control the amplitude of the current flowing through transistor 216 via node 213. Within current mirror 204, transistor 206 (e.g., a p-type FET) and transistor 208 (e.g., a p-type FET) are coupled to each other and to voltage source 209, so that transistors 206, 208 are on as long as voltage source 209 provides power. For example, the sources of transistors 206 and 208 are coupled to voltage source 209, and the gates of transistors 206 and 208 are not coupled to a voltage source but are instead coupled to node 212, so that the gate-to-source voltages of each of transistors 206 and 208 are low enough that transistors 206 and 208 are on as long as voltage source 209 provides power. Also, because the gates of transistors 206 and 208 are coupled together and the sources of transistors 206 and 208 are coupled together, transistors 206 and 208 behave in substantially identical fashion. Transistor 208 may have a larger size (e.g., a larger dimension facilitating a larger drain-source channel) than transistor 206, such that transistor 208 may provide a larger current than transistor 206 for the same gate-source voltage. The current (or size) ratio of transistor 206 to transistor 208 may be expressed as 1:M, where transistor 208 is M times the size of transistor 206 and transistor 208 provides M times the current of transistor 206. In some examples, transistor 208 represents multiple transistors coupled in parallel with one another, where the total current that the multiple transistors may provide is M times the current that transistor 206 may provide. In such an example, individual bits of a digital code (e.g., a digital control output on connection 126) may be applied to individual gates of multiple transistors represented by transistors 208, thereby individually controlling each of the multiple transistors to be on or off. By tying the drains of multiple transistors together and tying the sources of multiple transistors together, a single current may be provided at node 213.In some such instances, the gates of multiple transistors may not be coupled to the gate of transistor 206 .

[0034] In operation, the value of M in the above-mentioned ratio 1:M can be adjusted, such as by turning on and / or off one or more transistors represented by transistor 208. As the value of M is adjusted, for a given current through transistor 206, the current through transistor 208 (e.g., a set of transistors coupled in parallel) and node 213 varies. Thus, the amplitude of the oscillating signal in the loop and CLK can be increased or decreased. Increasing the current output of transistor 208 (or the set of transistors represented by transistor 208) can increase the amplitude of CLK, and decreasing the current output of transistor 208 (or the set of transistors represented by transistor 208) can decrease the amplitude of CLK. The current through transistor 206 can be varied by adjusting the resistance of variable resistor 210. Increasing the resistance can decrease the current through variable resistor 210 and transistor 206, and decreasing the resistance can increase the current through variable resistor 210 and transistor 206. Modulating the current through transistor 206 by adjusting variable resistor 210 also changes the current through node 213, thus affecting the amplitude of CLK and the amplitude of the signal oscillating in the loop, which can therefore vary depending on how current mirror 204, variable resistor 210, or a combination thereof, are controlled.

[0035] As described above, in the oscillator circuit 118, the capacitance of the variable capacitors 218, 220 may be dynamically adjusted to control the frequency accuracy of CLK. Also, as described above, in the oscillator circuit 118, the resistance of the variable resistor 210 and the ratio 1:M of the current mirror 204 may be dynamically adjusted to control the amplitude of CLK. These four components, namely, the variable capacitor 218, the variable capacitor 220, the variable resistor 210, and the current mirror 204, may be controlled by the digital controller 112. The operation of the digital controller 112 will now be described.

[0036] The amplitude controller 114 is configured to control the current mirror 204. The amplitude controller 114 receives a target ratio as an input. The target ratio specifies a target ratio of 1:M for the current mirror 204. In some examples, the target ratio is represented in a digital format, and the amplitude controller 114 is configured to interpret the digital format. In response to receiving the target ratio, the amplitude controller 114 provides a control signal on connection 126 to the current mirror 204. For example, the amplitude controller 114 provides a digital control signal on connection 126 that turns on and / or off individual transistors represented by transistors 208, as described above. In some examples, the amplitude controller 114 receives amplitude feedback via amplitude feedback connection 132 indicative of the amplitude of CLK. The amplitude controller 114 uses the amplitude feedback to control the amplitude of CLK to approximate a target amplitude (e.g., set by a user, read from a register, etc.), which is the minimum amplitude required to provide reliable oscillation and conserve power. Thus, if the amplitude feedback indicates that the amplitude of CLK is greater than the target amplitude plus a margin for hysteresis (e.g., a margin set by a user, a margin read from a register, etc.), the amplitude controller 114 may decrease the current, and if the amplitude is less than the target amplitude, the amplitude controller 114 may increase the current. In this way, the amplitude of CLK is maintained within a range defined by the target amplitude at the lower boundary and the target amplitude plus a margin for hysteresis at the upper boundary.

[0037] The mode controller 116 is configured to control the variable resistor 210, the variable capacitor 218, and the variable capacitor 220. The mode controller 116 may receive three inputs for each of the variable resistor 210, the variable capacitor 218, and the variable capacitor 220. In some examples, for the variable resistor 210, the mode controller 116 may receive a target value, a time increment value, and a step size value. For the variable capacitor 218, the mode controller 116 may receive a target value, a time increment value, and a step size value. For the variable capacitor 220, the mode controller 116 may receive a target value, a time increment value, and a step size value.

[0038] The target values ​​indicate the desired values ​​for the respective components. For example, the target value for variable resistor 210 indicates the desired resistance setting for variable resistor 210. The target value for variable capacitor 218 indicates the desired capacitance setting for variable capacitor 218. The target value for variable capacitor 220 indicates the desired capacitance setting for variable capacitor 220.

[0039] The time increment indicates the amount of time that elapses between each change in the value of a component. For example, the variable resistor 210 may be adjusted a first time from a current resistance value toward a target resistance value, wait a time increment, and then adjusted a second time toward the target resistance value. For example, the variable capacitor 218 may be adjusted a first time from a current capacitance value toward a target capacitance value, wait a time increment, and then adjusted a second time toward the target capacitance value. For example, the variable capacitor 220 may be adjusted a first time from a current capacitance value toward a target capacitance value, wait a time increment, and then adjusted a second time toward the target capacitance value.

[0040] The step size value indicates the maximum range a component may be adjusted between time increments. For example, the variable resistor 210 may be adjusted in multiple steps from a current resistance value toward a target resistance value, with each successive pair of steps separated by a time increment value, and each step being less than the step size value. The step size value may include separate and independent step size values ​​for each variable circuit element (variable resistor 210, variable capacitor 218, variable capacitor 220, etc.).

[0041] Mode controller 116 receives various input values ​​as described above. Based on these inputs, mode controller 116 controls the resistance setting of variable resistor 210, the capacitance setting of variable capacitor 218, and the capacitance setting of variable capacitor 220. Mode controller 116 may also receive amplitude feedback on amplitude feedback connection 132. Based on this amplitude feedback, mode controller 116 may temporarily halt mode transitions and / or changes to variable components (e.g., in response to the amplitude of CLK being outside of the target ranges described above). Example operations of amplitude controller 114 and mode controller 116 are described in more detail below.

[0042] FIG. 3 is a timing diagram illustrating the operation of the electronic device 104 in various examples. More specifically, the timing diagram illustrates an example operation of the mode controller 116 (FIG. 2). The top row 300 of the timing diagram illustrates an example clock signal used by the mode controller 116. The mode controller 116 can receive the clock signal from another device or the mode controller 116 can generate the clock signal. The clock signal has pulses whose rising edges are numbered 0, 1, 2, 3, etc. for ease of reference. Rows 302, 304, 306, and 308 illustrate the target value, time increment value, step size value, and actual value of the variable capacitor 218, respectively. Rows 310, 312, 314, and 316 illustrate the target value, time increment value, step size value, and actual value of the variable capacitor 220, respectively. Rows 318, 320, 322, and 324 respectively show the target value, the time increment value, the step size value, and the actual value of the variable resistor 210. The various values ​​shown in the timing diagram of Figure 3 are not meant to represent realistic values ​​(e.g., a value of 6 in the timing diagram does not necessarily represent a capacitance value of 6 picofarads). Instead, the example values ​​in the timing diagram are for convenience in explaining the operation of the mode controller 116.

[0043] 3, in an example operation, the mode controller 116 previously received a target value of 10 for the variable capacitor 218, but in clock cycle 2, the mode controller 116 begins to receive a target value of 6. In response to receiving the modified target value of 6, the mode controller 116 begins to adjust the capacitance value of the variable capacitor 218 from a current value of 10 to a target value of 6. Because the step size is 1, the mode controller 116 adjusts the capacitance value of the variable capacitor 218 from 10 to 9, then to 8, then to 7, then to 6. If the step size was 2, the mode controller 116 could have adjusted the capacitance value of the variable capacitor 218 from 10 to 8, then to 6. If the step size was 4, the mode controller 116 could have adjusted the capacitance value of the variable capacitor 218 from 10 to 6. In some examples, the mode controller 116 may use a smaller step size than indicated by the step size value. For example, even if the step size was 4, the mode controller 116 could adjust the capacitance value of the variable capacitor 218 from 10 to 9, then to 8, then to 7, then to 6. Thus, the step size value indicates the maximum allowable step size.

[0044] Also, the time increment value is 2. Thus, the mode controller 116 adjusts the current capacitance value 10 to the target capacitance value 6 in step sizes of 1, with each successive pair of steps separated by a time increment of 2 clock cycles plus an extra clock cycle as a buffer. For example, at the rising edge of clock cycle 2, the target value 6 is received. At the rising edge of clock cycle 5, which is 3 clock cycles difference (the time increment of 2 clock cycles plus the buffer clock cycle), the mode controller 116 adjusts the capacitance value of the variable capacitor 218 by 1, the specified step size. At the rising edge of clock cycle 8, which occurs after a time increment of 2 clock cycles plus the buffer clock cycle, the mode controller 116 again adjusts the capacitance value of the variable capacitor 218 by 1. This process continues until the mode controller 116 achieves the target capacitance value 6 at the rising edge of clock cycle 14.

[0045] For the target value (row 310), time increment value (row 312), step size value (row 314), and actual value (row 316) of the variable capacitor 220, the mode controller 116 performs the same process as described above for the variable capacitor 218.

[0046] For the target value (row 318), time increment value (row 320), step size value (row 322), and actual value (row 324) of the variable resistor 210, the mode controller 116 performs the same process as described above, except that the mode controller 116 modifies the resistance value of the variable resistor 210 from a current value of 8 to a target value of 5 with a time increment of 3 clock cycles and a step size of 1. Thus, the actual resistance value of the variable resistor 210 shown in row 324 changes from a value of 8 to a value of 7 at the rising edge of clock cycle 6, changes to a value of 6 at the rising edge of clock cycle 10, and changes to a value of 5 at the rising edge of clock cycle 14. In the event that the current value provided by the mode controller 116 (e.g., a current capacitance value or a current resistance value) is closer to the target value (e.g., a target capacitance value or a target resistance value) than the step size, the mode controller 116 may adjust the variable capacitor or resistor to the target value.

[0047] In some examples, the mode controller 116 may alternate between making adjustments to the current mirror 204, the variable resistor 210, and the variable capacitors 218, 220 to maintain the energy in the crystal of the oscillator circuit 118 within a target range. For example, the mode controller 116 may adjust the current mirror 204 to control the amplitude of CLK, then adjust the variable capacitor 218 to control the frequency precision of CLK, then adjust the variable resistor 210 to control the amplitude of CLK, then adjust the variable capacitor 220 to control the frequency precision of CLK. The mode controller 116 may adjust the variable components of the oscillator circuit 118 in an appropriate manner so long as the threshold rate specified by the time increment and step size values ​​provided on connection 124 is not exceeded.

[0048] 4 is a block diagram of the amplitude controller 114 in various examples. The amplitude controller 114 includes a processor 400 (e.g., random access memory, read only memory) coupled to a storage 402. In other examples, the amplitude controller 114 may include a purely hardware implementation using sequential and combinational logic. The storage 402 includes a data structure 404 and executable code 406. The storage 402 may include additional data structures 404. The executable code 406, when executed by the processor 400, causes the processor 400 to perform one or more operations attributed to the processor 400 and / or the amplitude controller 114 herein. The processor 400 may store data in or retrieve data from the data structure 404. The processor 400 receives a target ratio input on connection 122 as described above. The processor 400 receives an amplitude feedback on amplitude feedback connection 132 as described above. Processor 400 provides control signals, such as digital control signals, on connection 126 as described above.

[0049] 5 illustrates an example data structure 404. The example data structure 404 includes a first column and a second column. The first column provides an example target ratio that may be received as an input on connection 122 (FIG. 4). This input may be shown, for example, in digital form. The second column provides an example digital control output value that the amplitude controller 114 may provide on connection 126 (FIG. 4). A programmer, engineer, architect, or other user may program the data structure 404 with a variety of digital values, examples of which are shown in FIG. 5.

[0050] In some examples, amplitude controller 114 may receive a target ratio, such as 00001, on connection 122. In response to receiving this target ratio, amplitude controller 114 may use data structure 404 as a look-up table to determine that the digital control output corresponding to a target ratio of 00001 is 11001 (row 500). Thus, amplitude controller 114 may provide bits 11001 to current mirror 204 ( FIG. 2 ) over connection 126. Current mirror 204 may adjust components of current mirror 204, such as a transistor represented by transistor 208, based on the received bits on connection 126, as described above. In this manner, data structure 404 is useful as a “translator” to convert received digital codes into digital codes compatible with the architecture of processor 400 and / or the architecture of current mirror 204.

[0051] 6 is a block diagram of an example mode controller 116 in various examples. The example mode controller 116 includes a processor 600 coupled to a storage 602 (e.g., random access memory, read only memory). In other examples, the mode controller 116 may include a purely hardware implementation using sequential and combinatorial logic. The storage 602 includes a data structure 604, but may also include additional data structures 604. The storage 602 includes executable code 606, which when executed by the processor 600, causes the processor 600 to perform one or more of the operations attributed to the processor 600 and / or the mode controller 116 herein. The processor 600 stores an example register A, an example register B, an example register C, and an example register D. The processor 600 receives target values ​​(e.g., target capacitance values ​​for the variable capacitors 218, 220, target resistance values ​​for the variable resistor 210) on a connection 608 and stores them in register A. The processor 600 receives time increment values ​​on connection 610 for each of the variable capacitors 218, 220 and the variable resistor 210 and stores the time increment values ​​in register B. The processor 600 receives step size values ​​on connection 612 for each of the variable capacitors 218, 220 and the variable resistor 210 and stores these step size values ​​in register C. The processor 600 also receives amplitude feedback on amplitude feedback connection 132, as described above. The processor 600 provides a control signal (e.g., a digital control signal) to the variable resistor 210 on connection 614. The processor 600 provides a control signal (e.g., a digital control signal) to the variable capacitor 218 on connection 616. The processor 600 provides a control signal (e.g., a digital control signal) to the variable capacitor 220 on connection 618. A register D in the processor 600 stores the output signals that the processor 600 provides on connections 614, 616, and 618. Thus, in some examples, each time the processor 600 changes the capacitance value of the variable capacitors 218 or 220, the processor 600 updates the value stored in the corresponding register D.Similarly, each time the processor 600 changes the resistance value of the variable resistor 210, the processor 600 updates the value stored in the corresponding register D.

[0052] When processor 600 adjusts the capacitance of variable capacitor 218 from its current value (register D) to its target value (register A), processor 600 uses the time increment and step size values ​​stored in registers B and C, respectively, as described above. When processor 600 adjusts the capacitance of variable capacitor 220 from its current value (register D) to its target value (register A), processor 600 uses the time increment and step size values ​​stored in registers B and C, respectively, as described above. When processor 600 adjusts the resistance of variable resistor 210 from its current value (register D) to its target value (register A), processor 600 uses the time increment and step size values ​​stored in registers B and C, respectively, as described above.

[0053] FIG. 7 illustrates an example data structure 604. The example data structure 604 includes a first column and a second column. The first column provides example target capacitance values ​​that may be received as inputs on connection 608 (FIG. 6). Such inputs may be shown, for example, in digital form. The second column provides example digital control output values ​​that the mode controller 116 may provide on connections 614, 616, and / or 618 (FIG. 6). A programmer, engineer, architect, or other user may program the data structure 604 with various digital values, examples of which are shown in FIG. 7. In response to receiving the target capacitance value 00010 (row 700), for example, the mode controller 116 may compare the target capacitance value to the data structure 604 as a look-up table and determine that the target capacitance value 00010 corresponds to the digital control output value 01111. Thus, the mode controller 116 may provide the digital control output value 01111 to the variable capacitor 218 via connection 616. In this manner, the data structure 604 is useful as a “translator” to convert received digital codes into digital codes compatible with the architecture of the processor 600 and / or the architecture of the variable resistor 210 and / or the variable capacitors 218, 220.

[0054] In some examples, values ​​stored in registers A, B, C, and D in processor 600 may be values ​​shown in the left column of data structure 604. In some examples, values ​​stored in registers A, B, C, and D in processor 600 may be values ​​shown in the right column of data structure 604. In some examples, some of the values ​​stored in registers A, B, C, and / or D are values ​​shown in the left column of data structure 604 and other values ​​stored in registers A, B, C, and / or D are values ​​shown in the right column of data structure 604.

[0055] 8 is a flowchart of a method 800 for operating the electronic device 104 in various examples. In some examples, the processor 600 performs the method 800. In some examples, the method 800 is encoded in the executable code 606. The method 800 begins with the processor 600 receiving (802) a first target value and a first threshold rate for the frequency accuracy of the oscillator output signal. For example, the processor 600 may receive a target capacitance value for the variable capacitor 218. The processor 600 may also receive a time increment value and a step size value (which together specify a threshold rate that is the maximum rate at which the processor 600 is allowed to adjust the variable capacitor 218). In some examples, the processor 600 may also receive a target value and a threshold rate for the variable capacitor 220.

[0056] The method 800 includes the processor 600 receiving 804 a second target value and a second threshold rate for the amplitude of the oscillator output signal. For example, the processor 600 may receive a target resistance value for the variable resistor 210. The processor 600 may also receive a time increment value and a step size value (which together specify a threshold rate that is the maximum rate at which the processor 600 is allowed to adjust the variable resistor 210).

[0057] The method 800 includes the processor 600 adjusting a first current value of the frequency accuracy of the oscillator output signal toward a first target value at a rate equal to or less than a first threshold rate (806). As described above, the processor 600 does not adjust the current value toward the target value by a step size that exceeds the received step size value. Similarly, the processor 600 does not adjust the current value toward the target value more frequently than permitted by the time increment value.

[0058] The method 800 includes the processor 600 adjusting a second current value of the amplitude of the oscillator output signal toward a second target value at a rate equal to or less than a second threshold rate (808). As described above, the processor 600 does not adjust the current value toward the target value by a step size that exceeds the received step size value. Similarly, the processor 600 does not adjust the current value toward the target value more frequently than is permitted by the time increment value.

[0059] FIG. 9 is a circuit schematic diagram of an example electronic device 104 in accordance with various examples. The example of FIG. 9 is a more general version of the example shown in FIG. 2. The example electronic device 104 includes an oscillator circuit 900 and a digital controller 901 coupled to the oscillator circuit 900. In some examples, the oscillator circuit 900 is a Pierce oscillator circuit. The scope of this description includes other oscillator circuits, such as a Colpitts oscillator circuit and a Clapp oscillator circuit. Although FIG. 9 illustrates the oscillator circuit 900 as a crystal oscillator circuit, non-crystal oscillator circuits may also be useful.

[0060] The exemplary oscillator circuit 900 includes an inverter 902 operating as an amplifier. A resistor 904 is coupled in parallel to the inverter 902 across nodes 924 and 926. A current source 906 is coupled to a voltage source 908 and is useful for providing a current to the inverter 902. In some examples, the current source 906 is a transistor (e.g., a FET) or multiple transistors (e.g., FETs) configured to increase or decrease the amount of current provided to the inverter 902 based on a control signal from the amplitude controller 114, as described below. A variable capacitor 910 is coupled to the input of the inverter 902 at node 924. A variable capacitor 912 is coupled to the output of the inverter 902 at node 926. Both variable capacitors 910, 912 are coupled to ground 922. The variable capacitors 910, 912 are controllable by the mode controller 116, as described below. An amplitude detector 914 is coupled across nodes 924, 926 and is coupled to the ADC 915. The ADC 915 is coupled to the mode controller 116 by an amplitude feedback connection 132. A crystal 917 is coupled in parallel to the resistor 904 across nodes 924 and 926.

[0061] Resistor 904 acts as a feedback resistor and biases inverter 902 in a linear region of operation, causing inverter 902 to operate as a high gain inverting amplifier. The ability of inverter 902 to provide gain depends on receiving an appropriate power supply for the desired gain, and current source 906 provides this power supply. Inverter 902 and crystal 917 form an oscillating loop similar to the loop formed by transistor 216 and crystal 134 of FIG. 2. Therefore, the operation of such a loop will not be repeated here. Variable capacitors 910, 912 operate similarly to variable capacitors 218, 220 (FIG. 2), and therefore their operation will not be repeated here. Amplitude detector 914 detects the amplitude of the signal across nodes 924, 926 and provides an analog representation of this amplitude to ADC 915. ADC 915 provides a digital representation of the amplitude to mode controller 116 via amplitude feedback connection 132. The mode controller 116 may use an analog representation of the amplitude, as described above, and / or may provide a digital representation of the amplitude to the amplitude controller 114 via the amplitude feedback connection 132.

[0062] The amplitude controller 114 operates as described above. In particular, the amplitude controller 114 controls the current source 906 via connection 916, thereby controlling the amplitude of the current provided to power the inverter 902. The mode controller 116 also operates as described above. In particular, the mode controller 116 controls the capacitance of the variable capacitors 910, 912 via connections 918, 920, respectively. The mode controller 116 may provide input to the amplitude controller 114 via connection 928 as to the manner in which the amplitude of the current provided by the current source 906 is controlled (e.g., the target amplitude, the rate at which the current is adjusted, etc.).

[0063] The term "coupled" is used throughout this specification. This term may encompass connection, communication, or signal path that enables a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B when device A generates a signal to control device B to perform a certain operation, or in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A when the intervening component C does not substantially change the functional relationship between device A and device B.

[0064] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) to perform that function by a manufacturer at the time of manufacture and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be accomplished by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or by a combination of these.

[0065] A circuit or device described herein as including certain components may instead be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be coupled to at least some of the passive elements and / or sources, either during or after manufacture, by, for example, an end user and / or a third party, to form the described structure.

[0066] Although certain components may be described herein as being of a particular process technology, these components may be replaced with components of other process technologies. The circuits described herein are reconfigurable to include these replaced components and provide functionality at least partially similar to that available prior to the replacement of the components. Components illustrated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the illustrated resistor, unless otherwise noted. For example, a resistor or capacitor illustrated and described herein as a single component may be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0067] In this description, unless specifically stated otherwise, "about," "near," or "substantially" preceding a parameter means within ±10 percent of that parameter. Variations in the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. 1. An electronic device comprising: an oscillator circuit configured to provide an output signal; a controller coupled to the oscillator circuit; Including, The controller: receiving first and second target rates; dynamically adjusting a frequency accuracy of the output signal based on the first target rate; dynamically adjusting an amplitude of the output signal based on the second target rate; It is configured as follows: Electronic devices.

2. 2. The electronic device of claim 1, wherein the oscillator circuit includes a variable capacitor, and the controller is configured to dynamically adjust the frequency accuracy by adjusting the variable capacitor.

3. 2. The electronic device of claim 1, wherein the oscillator circuit includes a variable resistor, and the controller is configured to dynamically adjust the amplitude by adjusting the variable resistor.

4. 13. The electronic device of claim 1, further comprising a second controller coupled to the oscillator circuit, the second controller configured to adjust a current mirror in the oscillator circuit to control the amplitude of the output signal.

5. 2. The electronic device of claim 1, wherein the controller is configured to alternate between adjusting the frequency accuracy and the amplitude to maintain an energy of a crystal of the oscillator circuit within a target range.

6. 2. The electronic device of claim 1, wherein the oscillator circuit is a Pierce oscillator circuit.

7. 1. An electronic device comprising: an oscillator circuit including a first adjustable component configured to control a frequency accuracy of an output signal of the oscillator circuit and a second adjustable component configured to control an amplitude of the output signal; a controller coupled to the oscillator circuit; Including, The controller: adjusting a first value of the first adjustable component to a first target value at a first rate not exceeding a first threshold rate; adjusting a second value of the second adjustable component to a second target value at a second rate not exceeding a second threshold rate; It is configured as follows: the first target value and the first threshold rate being dynamically adjustable inputs to the controller; the second target value and the second threshold rate are dynamically adjustable inputs to the controller. Electronic devices.

8. 8. The electronic device of claim 7, wherein the oscillator circuit is a crystal oscillator circuit.

9. 8. The electronic device of claim 7, wherein the oscillator circuit is a Pierce oscillator circuit.

10. 8. The electronic device of claim 7, wherein the first adjustable component is a variable capacitor coupled to an amplifier of the oscillator circuit.

11. 8. The electronic device of claim 7, wherein the second adjustable component is a variable resistor configured to provide a variable resistance.

12. 8. The electronic device of claim 7, further comprising a second controller configured to control the amplitude of the output signal by adjusting a current mirror of the oscillator circuit, the current being coupled to an amplifier of the mirror oscillator circuit.

13. 8. The electronic device of claim 7, wherein the first threshold rate comprises a step size and a time increment, the step size indicating a maximum allowable change in the first value toward the first target value for each instance of the time increment.

14. 8. The electronic device of claim 7, wherein the controller is configured to alternate between adjustments to the first adjustable component and adjustments to the second adjustable component to maintain energy in a crystal of the oscillator circuit within a target range.

15. 1. A method comprising: receiving a first target value and a first threshold rate for a frequency accuracy of the oscillator output signal; receiving a second target value and a second threshold rate for the amplitude of the oscillator output signal; adjusting the first value of the frequency accuracy of the oscillator output signal toward the first target value at a rate equal to or less than the first threshold rate; adjusting a second value of the amplitude of the oscillator output signal toward the second target value at a rate equal to or less than the second threshold rate; A method comprising:

16. 16. The method of claim 15, wherein the first threshold rate comprises a step size and a time increment, the step size indicating a maximum allowable change in the first value toward the first target value for each time increment instance.

17. 16. The method of claim 15, further comprising receiving a time increment and delaying the adjustment of the first value by the time increment.

18. 16. The method of claim 15, wherein adjusting the first value comprises adjusting a variable capacitor coupled to an amplifier in an oscillator, the oscillator configured to output the oscillator output signal.

19. 20. The method of claim 18, wherein adjusting the second value comprises adjusting a variable resistor configured to provide a variable resistance within the oscillator.

20. 20. The method of claim 18, further comprising alternating between adjustments to the first value and adjustments to the second value to maintain energy in the oscillator crystal within a target range.

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