Semiconductor device and power conversion device

Abstract

To provide a semiconductor device which controls cracking caused by a stress accompanied by temperature fluctuations during operation of the semiconductor device, and can suppress deterioration of an insulation layer.SOLUTION: A semiconductor device 110 includes a conductor layer 1, an insulation layer 2 laminated on the conductor layer 1, a power lead 3 which is a conductive member arranged on the insulation layer 2, a power semiconductor element 4 arranged on the power lead 3, and a resin sealing body 10 for sealing the power semiconductor element 4, a part of the power lead 3, the insulation layer 2, and a part of the conductor layer 1. The conductor layer 1 is composed of a non-lamination part 11 and a lamination part 12, the non-lamination part 11 is formed so that the upper surface and the side face of the conductor layer 1 are brought into contact with the resin sealing body 10, and the lamination part 12 is formed so that the upper surface of the conductor layer 1 is brought into contact with the insulation layer 2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a power conversion device. [Background technology]

[0002] Conventionally, resin molded semiconductor devices that are inexpensive and have excellent heat dissipation properties have been known. In some resin molded semiconductor devices, the roles of insulation and heat dissipation are performed by a conductor layer such as a metal plate and a resin insulating layer laminated on the conductor layer (see, for example, Patent Document 1). The conductor layer and the insulating layer are formed so that the area of ​​a surface perpendicular to the lamination direction of the conductor layer and the area of ​​a surface perpendicular to the lamination direction of the insulating layer are the same, and the conductor layer is sealed by a resin sealer so that a part of the conductor layer is exposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-196495 A Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional semiconductor devices are multi-layer structures made of a plurality of different materials, and therefore, as the temperature changes during operation of the semiconductor device, stress occurs due to the difference in thermal expansion coefficient between the materials. The stress caused by the temperature changes during operation of the semiconductor device is particularly concentrated at the interface between the resin and metal, which have significantly different thermal expansion coefficients in a high-temperature environment, and at corners, which are shape-changing parts with a high stress concentration factor, and causes cracks. In addition, cracks caused by the stress caused by the temperature changes during operation of the semiconductor device are also likely to occur in the outer periphery of the resin encapsulant exposed to the outside of the semiconductor device, where the residual stress applied during the manufacturing process of the semiconductor device is high. The generated cracks progress at the interface between the resin and metal, or inside the resin, which is softer and more brittle than metal. In the semiconductor device of Patent Document 1, if a crack occurs starting from the edge of the interface between the resin encapsulant and the side surface of the conductor layer, that is, the portion of the interface between the resin encapsulant and the side surface of the conductor layer that is exposed to the outside of the semiconductor device, the crack will progress from the interface between the resin encapsulant and the conductor layer along the interface between the conductor layer and the resin insulating layer, and eventually progress into the resin insulating layer. When the crack progresses into the resin insulating layer, the creepage distance decreases, resulting in poor insulation.

[0005] The present disclosure has been made to solve the problems described above, and aims to provide a semiconductor device and a power conversion device that can control cracks caused by stress accompanying temperature fluctuations during operation of the semiconductor device and suppress the progression of cracks near the insulating layer. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a conductor layer, an insulating layer laminated on the conductor layer, a conductive member disposed on the insulating layer, a semiconductor element disposed on the conductive member, and a resin encapsulant that encapsulates the semiconductor element, a portion of the conductive member, the insulating layer, and a portion of the conductor layer. The conductor layer is composed of a non-laminated portion and a laminated portion, and the non-laminated portion is characterized in that the upper surface and side surfaces of the conductor layer are in contact with the resin encapsulant, and the laminated portion is characterized in that the upper surface of the conductor layer is in contact with the insulating layer.

[0007] The power conversion device according to the present disclosure has a semiconductor device according to the present disclosure and includes a main conversion circuit that converts and outputs input power, and a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit. Effect of the Invention

[0008] According to the semiconductor device and power conversion device of the present disclosure, by providing a conductor layer composed of a non-laminated portion in which the upper and side surfaces of the conductor layer are in contact with the resin sealing body, and a laminated portion in which the upper surface of the conductor layer is in contact with the insulating layer, it is possible to control cracks caused by stress accompanying temperature fluctuations during operation of the semiconductor device and to suppress the progression of cracks near the insulating layer. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] 1 is a schematic diagram showing a relationship between a conductor layer and an insulating layer of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 3] 1 is a schematic plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 4] FIG. 13 is an enlarged view of a main portion showing a crack that occurs during operation of a conventional semiconductor device. [Diagram 5] 4 is an enlarged view of a main part showing a crack that occurs during operation of the semiconductor device according to the first embodiment of the present disclosure. FIG. [Figure 6] 2 is a schematic diagram illustrating an example of an insulating layer of the semiconductor device according to the first embodiment of the present disclosure. [Figure 7] 5 is a schematic diagram showing another example of an insulating layer of the semiconductor device according to the first embodiment of the present disclosure. FIG. [Figure 8] 4 is a schematic diagram showing a relationship between a conductor layer and an insulating layer of a semiconductor device according to a first modification of the first embodiment of the present disclosure. FIG. [Figure 9] 11 is a schematic diagram showing another example of the relationship between the conductor layers and the insulating layers of the semiconductor device according to the first modification of the first embodiment of the present disclosure. FIG. [Figure 10] 11 is an enlarged view of a main portion of a semiconductor device according to a second embodiment of the present disclosure. FIG. [Figure 11] 11 is an enlarged view of a main part showing a propagation path of a crack that occurs during operation of a semiconductor device according to a second embodiment of the present disclosure. FIG. [Figure 12] 11 is an enlarged view of a main portion showing another example of a semiconductor device according to the second embodiment of the present disclosure. FIG. [Figure 13] 13 is an enlarged view of a main part illustrating a propagation path of a crack that occurs during operation of another example of a semiconductor device according to the second embodiment of the present disclosure. FIG. [Figure 14] FIG. 11 is an enlarged view of a main portion of a semiconductor device according to a third embodiment of the present disclosure. [Figure 15] 11 is an enlarged view of a main part showing a propagation path of a crack that occurs during operation of a semiconductor device according to a third embodiment of the present disclosure. FIG. [Figure 16] FIG. 11 is an enlarged view of a main portion of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 17] 13 is an enlarged view of a main part showing a propagation path of a crack that occurs during operation of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. [Figure 18] FIG. 11 is an enlarged view of a main portion of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 19] 13 is an enlarged view of a main part showing a propagation path of a crack that occurs during operation of a semiconductor device according to a fifth embodiment of the present disclosure. FIG. [Figure 20] FIG. 13 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a sixth embodiment of the present disclosure is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following, an example of a semiconductor device according to the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are given the same reference numerals, and the description thereof will not be repeated. In addition, the XYZ orthogonal coordinate system is defined so that the Z direction is the vertical direction and the XY plane is the horizontal plane. When a positive or negative sign is given to a direction, the +X, +Y, and +Z directions refer to the arrow directions of the orthogonal coordinate system shown in each drawing, and the +Z direction will be described below as the upward direction.

[0011] Embodiment 1 <Configuration of Semiconductor Device> The configuration of a semiconductor device 110 according to a first embodiment of the present disclosure will be described with reference to Figs. 1, 2, and 3. Fig. 1 is a schematic cross-sectional view of the semiconductor device 110 according to the first embodiment. Fig. 2 is a schematic diagram showing the relationship between a conductor layer 1 and an insulating layer 2 of the semiconductor device 110, with Fig. 2(a) being a schematic XY plane view seen from the top side and Fig. 2(b) being a schematic XZ side view. Fig. 3 is a schematic XY plane view of the semiconductor device seen from the bottom side. Fig. 1 shows a cross section taken along line II in Fig. 3.

[0012] 1, the semiconductor device 110 includes a flat conductor layer 1 arranged parallel to the XY plane, an insulating layer 2 provided on the conductor layer 1, a power lead 3 which is a conductive member provided on the insulating layer 2, a power semiconductor element 4 which is a semiconductor element connected to the power lead 3 via solder, a control lead 5 which is a conductive member, a control semiconductor element 6 which is a semiconductor element connected to the control lead 5 via solder, a power wire 7 which electrically connects the power semiconductor element 4 and the power lead 3, a signal wire 8 which electrically connects the power semiconductor element 4 and the control semiconductor element 6, a control wire 9 which electrically connects the control semiconductor element 6 and the control lead 5, and a resin sealant 10 which seals a part of the conductor layer 1, the insulating layer 2, a part of the power lead 3, the power semiconductor element 4, a part of the control lead 5, the control semiconductor element 6, the power wire 7, the signal wire 8, and the control wire 9. The semiconductor device 110 has a configuration in which the insulating layer 2, the power lead 3, and the power semiconductor element 4 are stacked in this order in the Z direction on the conductor layer 1. Hereinafter, the Z direction is also referred to as the stacking direction.

[0013] As shown in FIG. 2, the area of ​​the surface perpendicular to the lamination direction of the conductor layer 1 is larger than the area of ​​the surface perpendicular to the lamination direction of the insulating layer 2, and the insulating layer 2 is not laminated on the outer periphery of the upper surface of the conductor layer 1. Therefore, the conductor layer 1 is composed of a non-laminated portion 11 in which the upper surface and side surface of the conductor layer 1 are in contact with the resin encapsulant 10, and a laminated portion 12 in which the upper surface of the conductor layer 1 is in contact with the insulating layer 2. The shape of the surface perpendicular to the lamination direction of the conductor layer 1 and the insulating layer 2 is rectangular. Here, the surface perpendicular to the lamination direction of the conductor layer 1 is the upper surface of the conductor layer 1, and the surface perpendicular to the lamination direction of the insulating layer 2 is the lower surface of the insulating layer 2. Note that the non-laminated portion 11 does not necessarily have to be formed around the entire periphery of the upper surface of the conductor layer 1, and the non-laminated portion 11 may be formed on a part of the outer periphery of the upper surface of the conductor layer 1.

[0014] Further, the conductor layer 1 is configured such that the non-laminated portion 11 of the conductor layer 1 is located outside the end portion 21 of the insulating layer 2. The upper surface and the side surface of the non-laminated portion 11 of the conductor layer 1 are covered by the resin encapsulant 10. Similarly, the upper surface and the side surface of the insulating layer 2 are also covered by the resin encapsulant 10.

[0015] The conductor layer 1 dissipates heat generated inside the semiconductor device 110 to the outside. The lower surface of the conductor layer 1 is exposed from the resin encapsulant 10 as a heat dissipation surface. As the material of the conductor layer 1, a high thermal conductivity member such as copper (Cu) is used. Note that the material of the conductor layer 1 may be other metals or inorganic substances having high thermal conductivity and conductivity. Further, in order to improve the heat dissipation performance of the semiconductor device 110, the conductor layer 1 may have a heat dissipation fin (not shown) or the like attached to the lower surface.

[0016] The insulating layer 2 insulates the conductor layer 1 from the power lead 3 which is a conductive member. The insulating layer 2 insulates not only the power lead 3 but also the conductive member disposed on the insulating layer 2 from the conductor layer 1. Heat generated from the power semiconductor element 4 is dissipated from the conductor layer 1 through the insulating layer 2. The insulating layer 2 is composed of a thermosetting resin such as an epoxy resin and a filler having excellent insulation and thermal conductivity such as silica, alumina, or boron nitride.

[0017] The joined conductor layer 1 and insulating layer 2 are collectively referred to as a heat dissipation layer. It is desirable that the heat dissipation layer be formed such that the distance D from the end portion of the conductor layer 1 to the end portion 21 of the insulating layer 2 at one end of the heat dissipation layer is longer than the thickness E of the conductor layer 1 (E < D).

[0018] The power lead 3 is composed of an internal power lead 31 sealed inside the resin sealing body 10 and an external power lead 32 exposed from the resin sealing body 10. In FIG. 1, the boundary between the internal power lead 31 and the external power lead 32 is indicated by line II-II. The internal power lead 31 includes a die pad portion formed in a planar shape so that the power semiconductor element 4 can be mounted thereon. The power semiconductor element 4 is placed on the die pad portion and joined to the die pad portion by solder. In addition, the electrodes of the power semiconductor element 4 and the internal power lead 31, and the electrodes of the power semiconductor element 4 and the control semiconductor element 6 are connected by wires. Specifically, the emitter electrode of the power semiconductor element 4 is electrically connected to the internal power lead 31 by the power wire 7, and the gate electrode of the power semiconductor element 4 is electrically connected to the control semiconductor element 6 by the signal wire 8. The joining material between the power semiconductor element 4 and the internal power lead 31 is not limited to solder, and silver paste or the like may be used.

[0019] The power lead 3 is made of, for example, copper (Cu). As shown in Fig. 1, the external power lead 32 is bent in the +Z direction outside the resin sealing body 10. The surface of the external power lead 32 is plated with tin (Sn) or the like to improve solder wettability and corrosion resistance.

[0020] The power semiconductor element 4 is, for example, an IGBT (Insulated Gate Bipolar Transistor) using silicon (Si) as a semiconductor material. In this embodiment, a semiconductor device including an IGBT is described as the power semiconductor element 4, but the present invention is not limited thereto, and the power semiconductor element 4 may include a semiconductor element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a diode. In this embodiment, an example is described in which the semiconductor material of the power semiconductor element 4 is silicon (Si), but the present invention is not limited thereto, and the power semiconductor element 4 may be a wide band gap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), or diamond (C).

[0021] The power wire 7 is made of, for example, aluminum (Al), which is a metal with high electrical conductivity. Note that the material constituting the power wire 7 is not limited to aluminum, and may be any metal with high electrical conductivity, such as an aluminum alloy containing a small amount of additive such as iron (Fe) or copper (Cu).

[0022] The control lead 5 is composed of an internal control lead 51 sealed inside the resin sealing body 10 and an external control lead 52 exposed from the resin sealing body 10. In FIG. 1, the boundary between the internal control lead 51 and the external control lead 52 is indicated by line III-III. The internal control lead 51 includes a die pad portion formed in a planar shape on which the control semiconductor element 6 is mounted. The control semiconductor element 6 is disposed on the die pad portion and joined to the die pad portion by solder. In addition, the electrodes of the control semiconductor element 6 and the internal control lead 51, and the electrodes of the control semiconductor element 6 and the power semiconductor element 4 are connected by wires. Specifically, the electrodes of the control semiconductor element 6 are electrically connected to the internal control lead 51 by the control wires 9, and the electrodes of the control semiconductor element 6 are electrically connected to the control semiconductor element 6 by the signal wires 8. The joining material between the control semiconductor element 6 and the internal control lead 51 is not limited to solder, and silver paste or the like may be used.

[0023] The control lead 5 is formed of, for example, copper (Cu). As shown in Fig. 1, the external control lead 52 is bent in the +Z direction outside the resin sealing body 10. The surface of the external control lead 52 may be plated with tin (Sn) or the like to improve solder wettability and corrosion resistance.

[0024] The control semiconductor element 6 is, for example, a high voltage IC (HVIC) and a low voltage IC (LVIC).

[0025] The signal wires 8 and the control wires 9 are made of a metal such as gold (Au), silver (Ag), copper (Cu) or a copper alloy.

[0026] The resin encapsulant 10 is formed by transfer molding so as to encapsulate a part of the conductor layer 1, the insulating layer 2, a part of the power leads 3, the power semiconductor element 4, a part of the control leads 5, the control semiconductor element 6, the power wires 7, the signal wires 8, and the control wires 9. As shown in Fig. 3, the resin encapsulant 10 encapsulates the conductor layer 1 so that the lower surface of the conductor layer 1 is exposed as a heat dissipation surface. The resin encapsulant 10 also encapsulates the multiple power leads 3 and control leads 5 so that one end of the external power lead 32 and the external control lead 52 is exposed.

[0027] The resin encapsulant 10 is made of an insulating resin such as epoxy resin, phenol resin, silicon resin, or polyimide resin, or an insulating composite material in which a filler is dispersed in any of these resins. The glass transition temperature and thermal expansion coefficient vary depending on the type and amount of filler, the composition of the resin, etc.

[0028] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 110 according to the first embodiment of the present disclosure will be described. Note that in this embodiment, only the manufacturing process of the heat dissipation layer in which the conductor layer 1 and the insulating layer 2 are bonded to each other will be described among the manufacturing processes of the semiconductor device 110.

[0029] The heat dissipation layer is produced by bonding a conductor layer 1 and an insulating layer 2. For example, the heat dissipation layer may be produced by bonding a conductor layer 1 and an insulating layer 2 that have been cut into a predetermined shape in advance. Alternatively, the heat dissipation layer may be produced by bonding a conductor layer 1 having a size corresponding to a plurality of semiconductor devices 110 and an insulating layer 2 having the same size as the conductor layer 1 together, cutting the conductor layer 1 into a size corresponding to one semiconductor device 110, and removing the resin at the corners and ends of the insulating layer 2 with a laser or the like.

[0030] <Effects of the semiconductor device> Next, the operation and effects of the semiconductor device 110 according to the first embodiment of the present disclosure will be described by comparing a conventional semiconductor device with the semiconductor device of the present disclosure.

[0031] First, the mechanism of crack occurrence and propagation due to stress accompanying the operation of a conventional semiconductor device will be described with reference to Fig. 4. Fig. 4 is an enlarged view of a main part of a conventional semiconductor device 500. Fig. 4(a) shows the state before the conventional semiconductor device 500 is operated, and Fig. 4(b) shows the state after the conventional semiconductor device 500 has been operated multiple times. In Fig. 4, the creepage distance between the conductor layer 1 and the power lead 3, which is a conductive member, is represented by a thin arrow, and the propagation path of the crack is represented by a thick white arrow. The crack refers to peeling or breaking.

[0032] As shown in Fig. 4(a), in a conventional semiconductor device 500, a conductor layer 1, an insulating layer 2, and a power lead 3, which is a conductive member, are arranged so that the creepage distance satisfies the standard, and are sealed with a resin sealant 10. In the conventional semiconductor device 500, the conductor layer 1 and the insulating layer 2 have the same surface area perpendicular to the stacking direction, and in the heat dissipation layer where they are joined, the end of the conductor layer 1 and the end of the insulating layer 2 are aligned. In other words, the side surface of the conductor layer 1 and the side surface of the insulating layer 2 are arranged on the same plane. The resin sealant 10 contacts the side surface of the conductor layer 1, but does not contact the top surface of the conductor layer 1. As described above, the conventional semiconductor device 500 is made of a plurality of different materials, and each member has its own thermal expansion coefficient. For example, the thermal expansion coefficient of copper (Cu), which is the material of the conductor layer 1 and the power lead 3, is 16×10 -6 / °C. It is known that the thermal expansion coefficient of the resin constituting the resin sealing body 10 changes abruptly at the glass transition temperature, and it is 10×10 -6 / ℃ to 60×10 -6 / ℃. At room temperature, the difference between the thermal expansion coefficient of copper and that of resin is small, so no significant stress is applied to each component. However, at high temperatures above 125℃, the difference between the thermal expansion coefficient of copper and that of resin is significant, so a large stress is applied to each component.

[0033] When the conventional semiconductor device 500 is operated multiple times and temperature changes are repeated, stress occurs due to the difference in thermal expansion coefficient between the materials, and cracks occur inside the semiconductor device 500. Stress caused by temperature fluctuations during operation of a semiconductor device is concentrated particularly at the interface between resin and metal, which have significantly different thermal expansion coefficients in a high-temperature environment, and at corners, which are shape-changing parts with a high stress concentration factor.

[0034] Furthermore, cracks caused by stress accompanying temperature fluctuations during operation of the semiconductor device 500 are also likely to occur in locations where residual stress imparted in the manufacturing process is high. An example of a location where residual stress imparted in the manufacturing process is the outer periphery of the resin encapsulant 10 exposed to the outside of the semiconductor device. In the resin encapsulant 10, the resin is cured by changing the temperature from the resin curing temperature to room temperature in the resin encapsulation process, so residual stress is imparted due to differences in heat distribution caused by heat transfer during resin curing. This residual thermal stress is high in locations where the differences in heat distribution caused by heat transfer are large, so the residual stress in the resin encapsulant 10 is higher in the outer periphery than in the interior.

[0035] For this reason, cracks caused by stress accompanying temperature fluctuations during operation of the semiconductor device 500 tend to occur at the interface between resin and metal, at a shape-changing portion with a high stress concentration factor, and at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1, which is a location with high residual stress. That is, of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1, the portion exposed to the outside of the semiconductor device 500 tends to be the starting point of the cracks.

[0036] As shown in FIG. 4(b), the cracks in the conventional semiconductor device 500 after the temperature change progress along the interface between different materials with significantly different thermal expansion coefficients. The path of the cracks is path F. Specifically, the cracks start from the lower end of the interface between the resin encapsulant 10 and the side of the conductor layer 1, and progress along the interface between the resin encapsulant 10 and the side of the conductor layer 1 in the +Z direction. When the cracks progress along the interface between the conductor layer 1 and the insulating layer 2, the cracks eventually progress into the insulating layer 2, and the creepage distance decreases. When the creepage distance decreases and does not meet the standard, the semiconductor device 500 has poor insulation. That is, when the cracks generated inside the semiconductor device 500 progress along path F and progress to the vicinity of the insulating layer 2, and the cracks progress into the insulating layer 2, the insulating layer 2 cannot fulfill its role of insulating the conductor layer 1 and the power lead 3, which is a conductive member.

[0037] In contrast, the semiconductor device 110 according to the first embodiment of the present disclosure is capable of controlling cracks due to its configuration. The mechanism for controlling cracks in the semiconductor device 110 according to the first embodiment of the present disclosure will be described with reference to FIG. 5. FIG. 5 is an enlarged view of a main part showing cracks that occur during operation of the semiconductor device 110, and shows the part surrounded by a dashed line in the lower left of FIG. 1. FIG. 5(a) shows the state before the semiconductor device 110 is operated, and FIG. 5(b) shows the state after the semiconductor device 110 is operated multiple times. In FIG. 5, the creepage distance between the conductor layer 1 and the power lead 3, which is a conductive member, is shown by a thin arrow, and the propagation path of the crack is shown by a thick white arrow.

[0038] 5(a), in the semiconductor device 110 according to the first embodiment of the present disclosure, the conductor layer 1, the insulating layer 2, and the power lead 3, which is a conductive member, arranged so that the creepage distance satisfies the standard, are sealed with a resin sealant 10. In this manner, the semiconductor device 110 is a multi-layer structure composed of a plurality of different materials, similar to the conventional semiconductor device 500. For this reason, stress is generated inside the semiconductor device 110 due to the difference in thermal expansion coefficient between the materials as the temperature changes during the operation of the semiconductor device 110, and cracks are generated due to the stress.

[0039] As with the conventional semiconductor device 500, cracks caused by stress accompanying the operation of the semiconductor device 110 according to the first embodiment of the present disclosure are likely to occur at the interface between resin and metal, at a shape-changing portion with a high stress concentration factor, and at a location with high residual stress, namely, at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1. That is, of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1, a portion exposed to the outside of the semiconductor device 110 is likely to be the starting point of the crack.

[0040] Here, the conventional semiconductor device 500 and the semiconductor device 110 of the first embodiment of the present disclosure are compared in terms of the locations that are likely to be the starting points of cracks. Both of them have the same feature that the lower end of the interface between the resin encapsulant 10 and the side of the conductor layer 1, which is the interface between resin and metal and a shape-changing part with a high stress concentration factor and a part with high residual stress, is likely to be the starting point of cracks. However, the positional relationship between the locations that are likely to be the starting points of cracks and the insulating layer 2 is different. In the semiconductor device 110 of the first embodiment of the present disclosure, the non-laminated part 11, the upper surface and side surface of which are in contact with the resin encapsulant 10, is provided in the conductor layer 1, so that the locations that are likely to be the starting points of cracks are located farther away from the insulating layer 2 than in the conventional semiconductor device 500.

[0041] As shown in FIG. 5(b), due to a configuration different from that of the conventional semiconductor device 500, a crack in the semiconductor device 110 after a temperature change progresses along two paths: path F, which progresses through the interface between different materials having significantly different thermal expansion coefficients, and path G, which progresses inside the resin sealing body 10, which is softer and more brittle than the conductor layer 1. In the semiconductor device 110 according to the first embodiment of the present disclosure, the conductor layer 1 has a surface area perpendicular to the lamination direction that is larger than the surface area perpendicular to the lamination direction of the insulating layer 2, and is composed of a non-laminated portion 11 where the upper surface and side surface of the conductor layer 1 contact the resin encapsulant 10, and a laminated portion 12 where the upper surface of the conductor layer 1 contacts the insulating layer 2. With this configuration, the heat dissipation layer where the conductor layer 1 and the insulating layer 2 are bonded has a step at the end. Therefore, a crack that occurs at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1 progresses in the +Z direction at the interface between the resin encapsulant 10 and the conductor layer 1, and when it progresses to the corner formed by the upper surface and side surface of the conductor layer 1, it is divided into two paths, path F and path G, at the corner with a high stress concentration coefficient.

[0042] In the semiconductor device 110 of the first embodiment, the path F that progresses at the interface between different materials having significantly different thermal expansion coefficients is extended in distance until the crack progresses to the vicinity of the insulating layer 2, as compared with the conventional semiconductor device 500. This is because the position of the starting point of the crack is farther away from the insulating layer 2 than with the conventional semiconductor device 500. In the semiconductor device 110 of the first embodiment, the non-laminated portion 11 whose upper surface and side surface are in contact with the resin encapsulant 10 is provided in the conductor layer 1, and thus the distance of the interface between the resin encapsulant 10 and the conductor layer 1 in the progress path F is extended by the length of the upper surface of the non-laminated portion 11 of the conductor layer 1, as compared with the conventional semiconductor device 500. That is, the configuration of the conductor layer 1 including the non-laminated portion 11 and the laminated portion 12 can extend the distance until the crack progresses to the vicinity of the insulating layer 2. Therefore, if a crack that occurs at the lower end of the interface between the resin sealing body 10 and the side of the conductor layer 1 propagates along path F, as long as the crack propagates along the interface between the stretched resin sealing body 10 and the conductor layer 1, the crack is unlikely to propagate inside the insulating layer 2, and the creepage distance will not decrease.

[0043] In the semiconductor device 110 of the first embodiment, the path G that progresses inside the resin encapsulant 10 is a path that originates from a corner formed by the upper surface and side surface of the non-laminated portion 11 of the conductor layer 1, which is a shape-changing portion with a high stress concentration factor. In the conventional semiconductor device 500, the upper surface of the conductor layer 1 is not in contact with the resin encapsulant 10, and the interface between the resin encapsulant 10 and the conductor layer 1 does not include the corner formed by the upper surface and side surface of the conductor layer 1. For this reason, as shown in FIG. 4(b), a crack that occurs at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1 hardly progresses toward the inside of the resin encapsulant 10, specifically, in a direction corresponding to the path G in FIG. 5(b). In contrast, in the semiconductor device 110 according to the first embodiment of the present disclosure, the semiconductor device 110 is composed of a non-laminated portion 11 in which the upper surface and side surface of the conductor layer 1 contact the resin encapsulant 10, and a laminated portion 12 in which the upper surface of the conductor layer 1 contacts the insulating layer 2, and therefore the interface between the resin encapsulant 10 and the conductor layer 1 includes a corner formed by the upper surface and side surface of the conductor layer 1. The corner formed by the upper surface and side surface of the non-laminated portion 11 of the conductor layer 1, which is a shape-changing portion with a high stress concentration factor, becomes a singular point of stress, and a path G that progresses inside the resin encapsulant 10 is generated. When a crack that occurs at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1 propagates along path G, the crack is unlikely to propagate into the insulating layer 2 as long as it propagates inside the resin encapsulant 10, so the creepage distance does not decrease. In addition, when a crack that occurs at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1 propagates along path G, stress is released, and therefore the propagation of the crack to path F is suppressed.

[0044] As described above, according to the semiconductor device 110 of the first embodiment of the present disclosure, by providing a conductor layer 1 composed of a non-laminated portion 11 in which the upper and side surfaces of the conductor layer 1 contact the resin sealing body 10 and a laminated portion 12 in which the upper surface of the conductor layer 1 contacts the insulating layer 2, it is possible to control cracks caused by stress accompanying temperature fluctuations during operation of the semiconductor device and to suppress the progression of cracks toward the vicinity of the insulating layer 2.

[0045] Furthermore, according to the semiconductor device according to the first embodiment of the present disclosure, the time until the creepage distance between the conductor layer 1 and the power lead 3 decreases can be extended, thereby extending the temperature cycle life of the semiconductor device.

[0046] Although the insulating layer 2 has been described as an example of a flat plate-like structure arranged parallel to the XY plane, the insulating layer 2 may have a structure in which a chamfered portion is provided at the corner portion. This structure will be described with reference to Figs. 6 and 7. Fig. 6 is a schematic diagram showing a semiconductor device 111 in which a curved surface is provided at the corner portion of the insulating layer 2 of the semiconductor device 110 according to the first embodiment, Fig. 6(a) is a schematic diagram of the XY plane seen from above, and Fig. 6(b) is a schematic cross-sectional view taken along line IV-IV in Fig. 6(a). Fig. 7 is a schematic diagram showing a semiconductor device 112 in which a plane of a predetermined angle is provided at the corner portion of the insulating layer 2 of the semiconductor device 110, and Fig. 7(a) is a schematic diagram of the XY plane seen from above, and Fig. 7(b) is a schematic cross-sectional view taken along line VV in Fig. 7(a).

[0047] As shown in FIGS. 6 and 7, the insulating layer 2 may be provided with chamfered portions 22 at corners formed by the upper surface and the side surface of the insulating layer 2, and at corners formed by the side surfaces of the insulating layer 2. Cracks caused by stress due to temperature fluctuations during the operation of the semiconductor device occur at locations where stress concentrates. At the interface between the insulating layer 2 and the resin encapsulant 10, the corners formed by the upper surface and the side surface of the insulating layer 2, and the corners formed by the side surfaces of the insulating layer 2 are shape change portions with a high stress concentration coefficient. To prevent cracks from occurring at the corners of the interface between the insulating layer 2 and the resin encapsulant 10 and spreading into the interior of the insulating layer 2, it is effective to provide the chamfered portions 22 on the insulating layer 2.

[0048] As shown in FIG. 6, the chamfered portion 22 of the insulating layer 2 may be provided with a curved surface. By making the chamfered portion 22 of the insulating layer 2 a curved surface, it becomes possible to round the corners of the insulating layer 2 and reduce discontinuity, resulting in a lower stress concentration coefficient. The smaller the curvature of the curved surface of the chamfered portion 22 of the insulating layer 2, the lower the stress concentration coefficient and the less likely cracks are to occur.

[0049] As shown in FIG. 7, the chamfered portion 22 of the insulating layer 2 may be provided with a plane at a predetermined angle. By providing a plane at a predetermined angle on the chamfered portion 22 of the insulating layer 2, it becomes possible to reduce the discontinuity at the corners of the insulating layer 2, resulting in a lower stress concentration coefficient.

[0050] Also in the heat dissipation layer shown in FIGS. 6 and 7, it is desirable that the conductor layer 1 be formed such that the distance D from the end of the conductor layer 1 at one end of the heat dissipation layer to the end 21 of the insulating layer 2 is longer than the thickness E of the conductor layer 1 (E < D).

[0051] Furthermore, when the chamfered portion 22 is provided at the corner formed by the side surfaces of the insulating layer 2, the surface perpendicular to the lamination direction of the insulating layer 2 has a smaller area than before the chamfered portion 22 is provided. That is, by providing the chamfered portion 22, the area of ​​the non-laminated portion 11 of the conductor layer 1 increases, and the distance of the interface between the non-laminated portion 11 of the conductor layer 1 and the resin encapsulant 10, which is the crack propagation path F, is further extended. Therefore, by providing the chamfered portion 22 at the corner formed by the side surfaces of the insulating layer 2, the distance until the crack propagates to the vicinity of the insulating layer 2 can be further extended, and the propagation of the crack to the vicinity of the insulating layer 2 can be suppressed. Furthermore, by extending the time until the creepage distance between the conductor layer 1 and the power lead 3 decreases, the temperature cycle life of the semiconductor device can be extended.

[0052] Variation 1. Next, a first modified example of the first embodiment will be described. In the first embodiment, a configuration in which the entire periphery of the outer periphery on the upper surface of the conductor layer 1 is the non-laminated portion 11 has been described. In the first modified example, a configuration in which a part of the outer periphery on the upper surface of the conductor layer 1 is the non-laminated portion 11 will be described with reference to Figs. 8 and 9. Note that a description of the same configuration as in the first embodiment will be omitted. Fig. 8 is a schematic diagram showing the relationship between the conductor layer and the insulating layer of a semiconductor device 113 according to a first modified example of the first embodiment, Fig. 8(a) is a schematic XY plane view seen from the top side, Fig. 8(b) is a schematic cross-sectional view taken along line VI-VI in Fig. 8(a), and Fig. 8(c) is a schematic cross-sectional view taken along line VII-VII in Fig. 8(a). 9A and 9B are schematic diagrams showing another example of the relationship between the conductor layers and the insulating layers of a semiconductor device 114 relating to variant example 1 of embodiment 1, where FIG. 9A is a schematic XY plane diagram seen from the top side, FIG. 9B is a schematic cross-sectional diagram along line VIII-VIII in FIG. 9A, and FIG. 9C is a schematic cross-sectional diagram along line IX-IX in FIG. 9A.

[0053] As shown in FIGS. 8 and 9, the area of the plane perpendicular to the stacking direction of the conductor layer 1 is larger than the area of the plane perpendicular to the stacking direction of the insulating layer 2, and the insulating layer 2 is not stacked in the vicinity of the corners of the outer peripheral portion on the upper surface of the conductor layer 1. For this reason, the conductor layer 1 is composed of a non-stacked portion 11 where the upper surface and the side surface of the conductor layer 1 are in contact with the resin sealing body 10, and a stacked portion 12 where the upper surface of the conductor layer 1 is in contact with the insulating layer 2 and the side surface of the conductor layer 1 is in contact with the resin sealing body 10. The non-stacked portion 11, which is a structure for controlling the progress of cracks, is formed only in the vicinity of the corners of the outer peripheral portion on the upper surface of the conductor layer 1. Note that the non-stacked portion 11 does not necessarily have to be formed in the vicinity of all the corners of the outer peripheral portion on the upper surface of the conductor layer 1, and the non-stacked portion 11 may be formed at some of the corners. The vicinity of the corner refers to a region that includes one corner and does not overlap with the vicinity of other corners.

[0054] Also, in the heat dissipation layer shown in FIGS. 8 and 9, it is desirable that the conductor layer 1 be formed such that the distance F from the corner of the conductor layer 1 at one end of the heat dissipation layer to the corner of the lower surface of the insulating layer 2 is longer than the thickness E of the conductor layer 1 (E < F).

[0055] As shown in FIGS. 8 and 9, chamfered portions 22 are provided at the corners formed by the upper surface and the side surface of the insulating layer 2 and at the corners formed by the side surfaces of the insulating layer 2. As shown in FIG. 8, a curved surface may be provided on the chamfered portion 22 of the insulating layer 2. Also, as shown in FIG. 9, a plane at a predetermined angle may be provided on the chamfered portion 22 of the insulating layer 2. By providing the chamfered portion 22 of the insulating layer 2, it is possible to reduce the discontinuity of the corners of the insulating layer 2 and lower the stress concentration coefficient. As a result, the stress concentration points at the interface between the insulating layer 2 and the resin sealing body 10 can be removed, and the generation of cracks in the vicinity of the insulating layer 2 can be prevented.

[0056] Next, the effects of the semiconductor devices 113 and 114 according to Modification 1 will be described. Stress-induced cracks occurring inside the semiconductor device 110 tend to occur at the interface between resin and metal, which have significantly different thermal expansion coefficients in a high-temperature environment, and at corners with a high stress concentration factor. The corners of the surface perpendicular to the lamination direction of the conductor layer 1 have a particularly high stress concentration factor. Therefore, cracks are particularly likely to occur at the interface between the resin encapsulant 10 and the corners included in the non-laminated portion 11 of the conductor layer 1. Therefore, according to variant example 1, even if the non-laminated portion 11 of the conductor layer 1 is only in the area near the corner of the outer periphery on the upper surface of the conductor layer 1, it is possible to control cracks caused by stress accompanying temperature fluctuations during operation of the semiconductor device and to obtain the effect of suppressing the progression of cracks toward the vicinity of the insulating layer 2.

[0057] Furthermore, in the case where the entire periphery of the outer periphery on the upper surface of the conductor layer 1 is made into the non-laminated portion 11 as in the first embodiment, it is necessary to make the area of ​​the surface perpendicular to the lamination direction of the conductor layer 1 larger than that of the conventional case in order to maintain the creepage distance by the insulating layer 2. However, according to the first modification, in the case where only the area near the corner of the outer periphery on the upper surface of the conductor layer 1 is made into the non-laminated portion 11 as in Figs. 8 and 9, it is not necessary to make the area of ​​the surface perpendicular to the lamination direction of the conductor layer 1 larger than that of the conventional case as long as the creepage distance in the non-laminated portion 11 is maintained. Therefore, it is possible to form the non-laminated portion 11 of the conductor layer 1 without increasing the size of the semiconductor device, and it is possible to obtain the effect of controlling cracks caused by stress accompanying temperature fluctuations during the operation of the semiconductor device and suppressing the progression of cracks to the vicinity of the insulating layer.

[0058] Embodiment 2 In the first embodiment, a structure in which the conductor layer 1 is composed of a non-laminated portion 11 and a laminated portion 12 has been described. In the second embodiment, a structure in which a protrusion portion 13 is provided on the non-laminated portion 11 of the conductor layer 1 will be described. In the second embodiment, the same components as those in the first embodiment of the present disclosure are designated by the same reference numerals, and descriptions of the same or corresponding portions will be omitted. Hereinafter, a semiconductor device 120 according to the second embodiment will be described with reference to the drawings.

[0059] <Configuration of Semiconductor Device> 10 is an enlarged view of a main part of a semiconductor device 120 according to a second embodiment of the present disclosure. The protrusion 13 is formed at least in one of the upper surface of the non-laminated portion 11 of the conductor layer 1 and the side surface of the non-laminated portion 11 of the conductor layer 1, and is covered by a resin encapsulant 10. Although an example in which one protrusion 13 is provided is shown in FIG. 10, a plurality of protrusions 13 may be provided. From the viewpoint of manufacturing, it is preferable to provide the protrusion 13 at a corner formed by the upper surface and the side surface of the non-laminated portion 11 of the conductor layer 1, as shown in FIG. 10. It is preferable that the protrusion 13 of the non-laminated portion 11 of the conductor layer 1 has a shape in which the width becomes narrower from the base of the protrusion 13 toward the tip.

[0060] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 120 according to the second embodiment of the present disclosure will be described. In the present embodiment, only a manufacturing process for a heat dissipation layer in which the protrusion 13 is formed on the non-laminated portion 11 of the conductor layer 1 will be described among the manufacturing processes for the semiconductor device 120.

[0061] The heat dissipation layer of the semiconductor device 120 is fabricated by bonding together the conductor layer 1 and the insulating layer 2, which have been cut into a predetermined shape in advance. When providing a protrusion 13 at a corner formed by the upper surface and side surface of the non-laminated portion 11 of the conductor layer 1, the protrusion 13 is formed by intentionally processing the conductor layer 1 so as to generate burrs when the conductor layer 1 is cut or punched. When a plurality of protrusions 13 are provided on the non-laminated portion 11 of the conductor layer 1, or when the protrusions 13 are provided on the flat portion of the non-laminated portion 11, a die for forming the protrusions 13 is used to simultaneously perform a press process on the non-laminated portion 11 when the conductor layer 1 is cut or punched. Alternatively, the non-laminated portion 11 may be press-processed to form the protrusions 13 after the conductor layer 1 is cut or punched. Alternatively, the non-laminated portion 11 of the conductor layer 1 may be press-processed in the process of attaching the conductor layer 1 and the insulating layer 2 to each other.

[0062] <Effects of the semiconductor device> Next, the mechanism for controlling cracks in the semiconductor device 120 configured as above will be described with reference to Fig. 11. Fig. 11 is an enlarged view of a main part showing the propagation path of a crack that occurs during operation of the semiconductor device 120 according to the second embodiment of the present disclosure. In Fig. 11, the creepage distance between the conductor layer 1 and the power lead 3, which is a conductive member, is represented by a thin arrow, and the propagation path of the crack is represented by a thick white arrow.

[0063] As shown in FIG. 10, the semiconductor device 120 has a protrusion 13 in the non-laminated portion 11 of the conductor layer 1, and the protrusion 13 is sealed by the resin sealing body 10. The resin sealing body 10 covering the protrusion 13 is a shape-changing portion with a high stress concentration factor. For this reason, as shown in FIG. 11, a crack caused by stress occurring inside the semiconductor device 120 is likely to progress inside the resin sealing body 10 starting from the protrusion 13. That is, the protrusion 13 can guide a crack occurring at the lower end of the interface between the resin sealing body 10 and the side surface of the conductor layer 1 to a path G that progresses inside the resin sealing body 10, rather than a path F that progresses toward the insulating layer. By guiding the crack and allowing it to progress along the path G, the stress is released, and therefore the progress of the crack to the path F that progresses toward the insulating layer 2 can be suppressed.

[0064] According to the semiconductor device 120 of the second embodiment described above, by providing the protrusions 13 on the non-laminated portion 11 of the conductor layer 1, it is possible to control cracks caused by stress accompanying temperature fluctuations during operation of the semiconductor device and suppress the progression of cracks to the vicinity of the insulating layer. Also, according to the semiconductor device 120, it is possible to extend the time until the creepage distance between the conductor layer 1 and the power lead 3 decreases, thereby extending the temperature cycle life of the semiconductor device.

[0065] Although the protrusion 13 of the non-laminated portion 11 of the conductor layer 1 has been described as having a shape in which the width of the protrusion 13 narrows from the base to the tip, the protrusion 13 may have the same width at the base and at the top, and the surface perpendicular to the lamination direction of the protrusion 13, i.e., the top surface of the protrusion 13, may have a rectangular shape. This structure will be described with reference to FIG. 12. FIG. 12 is a schematic diagram showing an example in which the protrusion 13 has a rectangular shape in a semiconductor device 121 according to the second embodiment. In FIG. 12, the creepage distance between the conductor layer 1 and the power lead 3, which is a conductive member, is indicated by an arrow.

[0066] 12, protrusion 13 of non-laminated portion 11 of conductor layer 1 may have a structure in which the width of the base and the top surface of protrusion 13 are the same, and the shape of a surface perpendicular to the lamination direction of protrusion 13 is rectangular. If a part of non-laminated portion 11 of conductor layer 1 is structured to be thicker than laminated portion 12 of conductor layer 1, protrusion 13 shown in FIG. 12 is formed in non-laminated portion 11 due to the difference in thickness.

[0067] Next, the mechanism for controlling cracks in the semiconductor device 121 thus configured will be described with reference to Fig. 13. Fig. 13 is an enlarged view of a main part showing the propagation path of a crack that occurs during operation of the semiconductor device 121 having the protrusion 13 in a rectangular shape. In Fig. 13, the creepage distance between the conductor layer 1 and the power lead 3, which is a conductive member, is represented by a thin arrow, and the propagation path of the crack is represented by a thick white arrow.

[0068] As shown in FIG. 13, the protrusion 13 of the non-laminated portion 11 of the conductor layer 1 is shaped so that the width of the base and the top surface of the protrusion 13 are the same, that is, a part of the non-laminated portion 11 of the conductor layer 1 is made thicker than the laminated portion 12 of the conductor layer 1, and the distance of the interface between the resin encapsulant 10 and the conductor layer 1 in the propagation path F is extended by the amount of the thickness of the non-laminated portion 11 of the conductor layer 1 being made thicker than the thickness of the laminated portion 12 of the conductor layer 1. In other words, by making the non-laminated portion 11 of the conductor layer 1 thicker than the laminated portion 12 of the conductor layer 1, the distance until the crack propagates to the vicinity of the insulating layer 2 can be extended. Therefore, when a crack that occurs at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1 propagates along the path F, the insulating layer 2 does not deteriorate and the creepage distance does not decrease as long as the crack propagates along the interface between the extended resin encapsulant 10 and the conductor layer 1.

[0069] As shown in FIG. 12, the interface between the non-laminated portion 11 of the conductor layer 1 and the resin encapsulant 10 includes a plurality of corners formed by providing the protruding portion 13, whose surface perpendicular to the lamination direction is rectangular. The plurality of corners formed by providing the protruding portion 13 are shape-changing portions with a high stress concentration factor. For this reason, as shown in FIG. 13, cracks caused by stress accompanying the operation of the semiconductor device 121 tend to progress inside the resin encapsulant 10, starting from the plurality of corners formed by providing the protruding portion 13. That is, the protruding portion 13 can guide a crack generated at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1 to a path G that progresses inside the resin encapsulant 10, rather than a path F that progresses toward the insulating layer. By guiding the crack and allowing it to progress along path G, stress is released, and therefore the progress of the crack to path F that progresses toward the insulating layer 2 can be suppressed.

[0070] That is, according to the semiconductor device 121 of the second embodiment, by providing the protrusion 13 whose base and top face have the same width and whose face perpendicular to the stacking direction is rectangular, it is possible to control the cracks caused by the stress generated by the difference in the thermal expansion coefficient between the materials accompanying the temperature change during the operation of the semiconductor device, and to suppress the progress of the cracks to the vicinity of the insulating layer. Also, by extending the time until the creepage distance between the conductor layer 1 and the power lead 3 decreases, the temperature cycle life of the semiconductor device can be extended.

[0071] Embodiment 3 In the second embodiment, a configuration in which a protrusion portion 13 is provided on the non-laminated portion 11 of the conductor layer 1 is described. In the third embodiment, a configuration in which a bent portion 14 is provided on the non-laminated portion 11 of the conductor layer 1 is described. In the third embodiment, the same components as those in the second embodiment of the present disclosure are designated by the same reference numerals, and descriptions of the same or corresponding portions are omitted. Hereinafter, a semiconductor device 130 according to the third embodiment will be described with reference to the drawings.

[0072] <Configuration of Semiconductor Device> 14 is an enlarged view of a main part of a semiconductor device 130 according to a third embodiment of the present disclosure. The bent portion 14 is formed by bending a part of the non-laminated portion 11 of the conductor layer 1 toward the upper surface side. Of the lower surface of the conductor layer 1, the region that becomes the lower surface of the bent portion 14 is sealed with a resin sealing body 10. Note that the bent portion 14 may be provided around the entire outer periphery of the upper surface of the conductor layer 1, or may be provided on both opposing ends.

[0073] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 130 according to the third embodiment of the present disclosure will be described. In this embodiment, only a manufacturing process of a heat dissipation layer in which the bent portion 14 is formed in the non-laminated portion 11 of the conductor layer 1 will be described among the manufacturing processes of the semiconductor device 130.

[0074] The heat dissipation layer of the semiconductor device 130 is fabricated by bonding together the conductor layer 1 and the insulating layer 2, which have been cut into a predetermined shape in advance. The bent portion 14 of the non-laminated portion 11 of the conductor layer 1 is formed by bending the non-laminated portion 11 at the same time as cutting or punching the conductor layer 1. The bent portion 14 may also be formed by bending the non-laminated portion 11 after cutting the conductor layer 1. Alternatively, the bent portion 14 may also be formed by bending the non-laminated portion 11 of the conductor layer 1 in the process of bonding the conductor layer 1 and the insulating layer 2.

[0075] <Effects of the semiconductor device> Next, the mechanism for controlling cracks in the semiconductor device 130 configured as above will be described with reference to Fig. 15. Fig. 15 is an enlarged view of a main part showing the propagation path of a crack that occurs during operation of the semiconductor device 130 according to the third embodiment of the present disclosure. In Fig. 15, the creepage distance between the conductor layer 1 and the power lead 3, which is a conductive member, is represented by a thin arrow, and the propagation path of the crack is represented by a thick white arrow.

[0076] As shown in FIG. 14, in the semiconductor device 130, a bent portion 14 is provided in the non-laminated portion 11 of the conductor layer 1, and the bent portion 14 is sealed by the resin sealing body 10. The interface between the bent portion 14 of the conductor layer 1 and the resin sealing body 10 includes a corner formed by the upper surface and side surface of the conductor layer 1 and a corner formed by the lower surface and side surface of the conductor layer 1. The corner formed by the upper surface and side surface of the conductor layer 1 and the corner formed by the lower surface and side surface of the conductor layer 1 are shape-changing portions with a high stress concentration factor. For this reason, as shown in FIG. 15, cracks caused by stress accompanying the operation of the semiconductor device 130 tend to progress inside the resin sealing body 10, starting from the corner formed by the upper surface and side surface of the conductor layer 1 and the corner formed by the lower surface and side surface of the conductor layer 1. That is, the bent portion 14 can guide a crack that occurs at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1 to path G that progresses inside the resin encapsulant 10, instead of path F that progresses toward the insulating layer. By guiding the crack to progress to path G, stress is released, and therefore it is possible to suppress the progress of the crack to path F that progresses toward the insulating layer.

[0077] In addition, the bent portion 14 of the non-laminated portion 11 of the conductor layer 1 is formed such that at least a portion of the lower surface of the non-laminated portion 11 of the conductor layer 1 is embedded inside the resin sealing body 10, thereby improving the bending rigidity of the conductor layer 1. Therefore, the bent portion 14 can suppress warping deformation of the conductor layer 1 due to temperature changes in the semiconductor, and can suppress the progression of cracks at the interface between the conductor layer 1 and the insulating layer 2.

[0078] According to the semiconductor device 130 of the third embodiment as described above, by providing the bent portion 14 in the non-laminated portion 11 of the conductor layer 1, it is possible to control cracks caused by stress accompanying temperature fluctuations during operation of the semiconductor device, and to enhance the effect of suppressing the progression of cracks toward the vicinity of the insulating layer 2. Furthermore, according to the semiconductor device 130, it is possible to extend the time until the creepage distance between the conductor layer 1 and the power lead 3 decreases, thereby extending the temperature cycle life of the semiconductor device.

[0079] Embodiment 4 In the third embodiment, a configuration in which a bent portion 14 is provided in the non-laminated portion 11 of the conductor layer 1 is described. In the fourth embodiment, a configuration in which a recessed portion 15 is provided in the non-laminated portion 11 of the conductor layer 1 is described. In the fourth embodiment, the same components as those in the third embodiment of the present disclosure are denoted by the same reference numerals, and descriptions of the same or corresponding portions are omitted. Hereinafter, a semiconductor device 140 according to the fourth embodiment will be described with reference to the drawings.

[0080] <Configuration of Semiconductor Device> 16 is an enlarged view of a main part of a semiconductor device 140 according to a fourth embodiment of the present disclosure. The recessed portion 15 is formed in at least one of the upper surface of the non-laminated portion 11 of the conductor layer 1 and the side surface of the non-laminated portion 11 of the conductor layer 1, and is covered by the resin encapsulant 10. Although an example in which one recessed portion 15 is provided is shown in FIG. 16, a plurality of recessed portions 15 may be provided. In addition, the recessed portion 15 may be provided around the entire outer periphery of the upper surface of the conductor layer 1 at a corner formed by the upper surface and the side surface of the non-laminated portion 11 of the conductor layer 1.

[0081] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 140 according to the fourth embodiment of the present disclosure will be described. In this embodiment, only a manufacturing process of the heat dissipation layer in which the recessed portion 15 is formed in the non-laminated portion 11 of the conductor layer 1 will be described among the manufacturing processes of the semiconductor device 140.

[0082] The heat dissipation layer of the semiconductor device 140 is fabricated by bonding together the conductor layer 1 and the insulating layer 2, which have been cut into a predetermined shape in advance. The recessed portion 15 of the non-laminated portion 11 of the conductor layer 1 is formed by pressing the non-laminated portion 11 at the same time as punching the conductor layer 1 using a die for forming the recessed portion 15. Alternatively, the recessed portion 15 may be formed by pressing the non-laminated portion 11 after cutting the conductor layer 1. Alternatively, the non-laminated portion 11 of the conductor layer 1 may be pressed together in the process of bonding the conductor layer 1 and the insulating layer 2.

[0083] <Effects of the semiconductor device> Next, the mechanism for controlling cracks in the semiconductor device 140 configured as above will be described with reference to Fig. 17. Fig. 17 is an enlarged view of a main part showing the propagation path of a crack that occurs during operation of the semiconductor device 140 according to the fourth embodiment of the present disclosure. In Fig. 17, the creepage distance between the conductor layer 1 and the power lead 3, which is a conductive member, is represented by a thin arrow, and the propagation path of the crack is represented by a thick white arrow.

[0084] 17, in the semiconductor device 140, the recess 15 is provided in the non-laminated portion 11 of the conductor layer 1, and thus the distance of the interface between the resin encapsulant 10 and the conductor layer 1 in the propagation path F is extended by the depth of the recess 15 in the non-laminated portion 11 of the conductor layer 1. That is, the recess 15 can extend the distance until the crack propagates to the vicinity of the insulating layer 2. Therefore, when a crack generated at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1 propagates along the path F, the insulating layer 2 is not deteriorated and the creepage distance is not reduced as long as the crack propagates along the extended interface between the resin encapsulant 10 and the conductor layer 1.

[0085] As shown in FIG. 16, the semiconductor device 140 has a recess 15 in the non-laminated portion 11 of the conductor layer 1, and the recess 15 is sealed by the resin sealing body 10. The interface between the non-laminated portion 11 of the conductor layer 1 and the resin sealing body 10 includes a plurality of corners formed by providing the recess 15. The plurality of corners formed by providing the recess 15 are shape-changing portions with a high stress concentration factor. For this reason, as shown in FIG. 17, a crack caused by stress accompanying the operation of the semiconductor device 140 is likely to progress inside the resin sealing body 10, starting from the plurality of corners formed by providing the recess 15. That is, the recess 15 can guide a crack generated at the lower end of the interface between the resin sealing body 10 and the side surface of the conductor layer 1 to a path G that progresses inside the resin sealing body 10, rather than a path F that progresses toward the insulating layer. By guiding the crack and allowing it to progress to the path G, the stress is released, and therefore the progress of the crack to the path F that progresses toward the insulating layer can be suppressed.

[0086] According to the semiconductor device 140 of the fourth embodiment, by providing the recessed portion 15 in the non-laminated portion 11 of the conductor layer 1, it is possible to control cracks caused by stress due to differences in the thermal expansion coefficient between materials accompanying temperature fluctuations during operation of the semiconductor device, and to enhance the effect of suppressing the progression of cracks to the vicinity of the insulating layer. Also, according to the semiconductor device 140, it is possible to extend the time until the creepage distance between the conductor layer 1 and the power lead 3 decreases, thereby extending the temperature cycle life of the semiconductor device.

[0087] Embodiment 5. In the first to fourth embodiments, a configuration has been described in which the thickness of at least a portion of the non-laminated portion 11 of the conductor layer 1 is thicker than the thickness of the laminated portion 12 of the conductor layer 1. In the fifth embodiment, a configuration will be described in which the thickness of the entire non-laminated portion 11 of the conductor layer 1 is thicker than the thickness of the laminated portion 12 of the conductor layer 1. In the fifth embodiment, the same components as those in the fourth embodiment of the present disclosure are designated by the same reference numerals, and descriptions of the same or corresponding parts will be omitted. Hereinafter, a semiconductor device 150 according to the fifth embodiment will be described with reference to the drawings.

[0088] <Configuration of Semiconductor Device> Fig. 18 is an enlarged view of a main part of a semiconductor device 150 according to a fifth embodiment of the present disclosure. Fig. 18 shows a configuration in which the thickness of the entire non-laminated portion 11 of the conductor layer 1 is greater than the thickness of the laminated portion 12 of the conductor layer 1. The thickness of the conductor layer 1 is not particularly limited as long as the creepage distance falls within a range that satisfies the standard.

[0089] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 150 according to the fifth embodiment of the present disclosure will be described. In this embodiment, only the manufacturing process of the heat dissipation layer constituted by the conductor layer 1 having the non-laminated portion 11 and the laminated portion 12 having different thicknesses will be described among the manufacturing processes of the semiconductor device 150.

[0090] The heat dissipation layer of the semiconductor device 150 is produced by bonding together the conductor layer 1 and the insulating layer 2, which have been cut into a predetermined shape in advance. The conductor layer 1, which includes the non-laminated portion 11 and the laminated portion 12, which have different thicknesses, is formed by pressing the non-laminated portion 11 while punching the conductor layer 1 using a die for forming the non-laminated portion 11 and the laminated portion 12 to have different thicknesses. Alternatively, the non-laminated portion 11 may be pressed after the conductor layer 1 is cut.

[0091] <Effects of the semiconductor device> Next, the mechanism for controlling cracks in the semiconductor device 150 thus configured will be described with reference to Fig. 19. Fig. 19 is an enlarged view of a main part showing the propagation path of a crack that occurs during operation of the semiconductor device 150 according to the fifth embodiment of the present disclosure. In Fig. 19, the creepage distance between the conductor layer 1 and the power lead 3, which is a conductive member, is represented by a thin arrow, and the propagation path of the crack is represented by a thick white arrow.

[0092] 19, in the semiconductor device 150, the thickness of the entire non-laminated portion 11 of the conductor layer 1 is made thicker than the thickness of the laminated portion 12 of the conductor layer 1, and the distance of the interface between the resin encapsulant 10 and the conductor layer 1 in the propagation path F is extended by the thickness of the non-laminated portion 11 of the conductor layer 1 being made thicker than the thickness of the laminated portion 12 of the conductor layer 1. That is, by making the non-laminated portion 11 of the conductor layer 1 thicker than the laminated portion 12 of the conductor layer 1, the distance until the crack propagates to the vicinity of the insulating layer 2 can be extended. Therefore, when a crack generated at the lower end of the interface between the resin encapsulant 10 and the side surface of the conductor layer 1 propagates along the path F, the insulating layer 2 does not deteriorate and the creepage distance does not decrease as long as the crack propagates along the extended interface between the resin encapsulant 10 and the conductor layer 1.

[0093] 19, the semiconductor device 150 has a structure in which the thickness of the entire non-laminated portion 11 of the conductor layer 1 is greater than the thickness of the laminated portion 12 of the conductor layer 1, so that the insulating layer 2 is fitted into a recess formed by the structure of the conductor layer 1 having a different thickness, as shown in Fig. 19. When temperature changes are repeated in this structure, the expansion of the insulating layer 2 is suppressed by the conductor layer 1, so that the progression of cracks at the interface between the conductor layer 1 and the insulating layer 2 can be suppressed.

[0094] According to the semiconductor device 150 of the fifth embodiment as described above, the thickness of the entire area of ​​the non-laminated portion 11 of the conductor layer 1 is thicker than the thickness of the laminated portion 12 of the conductor layer 1, so that it is possible to control cracks caused by stresses due to differences in the thermal expansion coefficients between materials accompanying temperature fluctuations during operation of the semiconductor device, and to enhance the effect of suppressing the progression of cracks to the vicinity of the insulating layer. Also, according to the semiconductor device 150, it is possible to extend the time until the creepage distance between the conductor layer 1 and the power lead 3 decreases, thereby extending the temperature cycle life of the semiconductor device.

[0095] Embodiment 6 In this embodiment, the semiconductor device according to the above-mentioned first to fifth embodiments is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, a case in which the present disclosure is applied to a three-phase inverter will be described below as a sixth embodiment.

[0096] FIG. 20 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0097] The power conversion system shown in Fig. 20 is composed of a power source 200, a power conversion device 300, and a load 400. The power source 200 is a DC power source and supplies DC power to the power conversion device 300. The power source 200 can be composed of various things, for example, a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power source 200 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0098] The power conversion device 300 is a three-phase inverter connected between the power source 200 and the load 400, converts DC power supplied from the power source 200 into AC power, and supplies the AC power to the load 400. As shown in Fig. 20, the power conversion device 300 includes a main conversion circuit 301 that converts DC power into AC power and outputs it, and a control circuit 303 that outputs a control signal for controlling the main conversion circuit 301 to the main conversion circuit 301.

[0099] The load 400 is a three-phase motor driven by AC power supplied from the power conversion device 300. The load 400 is not limited to a specific use, but is a motor mounted on various electric devices, and is used as, for example, a motor for a hybrid car, an electric car, a railroad car, an elevator, or an air conditioner.

[0100] The power conversion device 300 will be described in detail below. The main conversion circuit 301 includes switching elements and free wheel diodes (not shown), and converts DC power supplied from the power source 200 into AC power by switching the switching elements, and supplies the AC power to the load 400. There are various specific circuit configurations of the main conversion circuit 301, but the main conversion circuit 301 according to this embodiment is a two-level three-phase full bridge circuit, and can be configured with six switching elements and six free wheel diodes connected in reverse parallel to each switching element. At least one of the switching elements and free wheel diodes of the main conversion circuit 301 is a switching element or free wheel diode of the semiconductor device 302 corresponding to any of the semiconductor devices of the above-mentioned first to fifth embodiments. The six switching elements are connected in series with two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 301, are connected to the load 400.

[0101] The main conversion circuit 301 also includes a drive circuit (not shown) for driving each switching element, but the drive circuit may be built in the semiconductor device 302, or the semiconductor device 302 may include a drive circuit separate from the semiconductor device 302. The drive circuit generates drive signals for driving the switching elements of the main conversion circuit 301 and supplies them to the control electrodes of the switching elements of the main conversion circuit 301. Specifically, in accordance with a control signal from a control circuit 303 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal for turning the switching element on and a drive signal for turning the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0102] The control circuit 303 controls the switching elements of the main conversion circuit 301 so that a desired power is supplied to the load 400. Specifically, the control circuit 303 calculates the time (on time) for each switching element of the main conversion circuit 301 to be in the on state based on the power to be supplied to the load 400. For example, the main conversion circuit 301 can be controlled by PWM control that modulates the on time of the switching elements according to the voltage to be output. Then, a control command (control signal) is output to a drive circuit provided in the main conversion circuit 301 so that an on signal is output to a switching element that should be in the on state at each point in time, and an off signal is output to a switching element that should be in the off state. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

[0103] In the power conversion device according to the present embodiment, the semiconductor device according to the first to fifth embodiments is applied as the semiconductor device 302 constituting the main conversion circuit 301, so that the progression of cracks near the insulating layer can be controlled and deterioration of the insulating layer can be suppressed.

[0104] In the present embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may be used. In addition, when power is supplied to a single-phase load, the present disclosure may be applied to a single-phase inverter. In addition, when power is supplied to a DC load or the like, the present disclosure may be applied to a DC / DC converter or an AC / DC converter.

[0105] Furthermore, the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0106] Although the present disclosure has been described based on each embodiment, the present disclosure is not limited to each embodiment. Furthermore, appropriate combinations, modifications, and omissions of each embodiment are also included within the scope of the technical ideas shown in the embodiments. [Explanation of symbols]

[0107] 1 Conductor layer 2. Insulation layer 3 Power Lead 4 Power semiconductor elements 5 Control Leads 6. Control Semiconductor Devices 7 Power Wire 8 Signal Wires 9 Control Wires 10 Resin sealing body 11 Non-laminated portion of conductor layer 12 Conductor layer stack 13 Protrusion 14 Bending section 15 Recess 21 End of insulating layer 22 Chamfered portion of insulating layer 31 Internal power lead 32 External Power Lead 51 Internal Control Lead 52 External Control Lead 110, 120, 130, 140, 150 Semiconductor device 200 power supply 300 Power Converter 301 Main conversion circuit 302 Semiconductor Devices 303 Control Circuit 400 Load 500 Conventional semiconductor device

Claims

1. A conductor layer; an insulating layer laminated on the conductor layer; a conductive member disposed on the insulating layer; a semiconductor element disposed on the conductive member; a resin encapsulant that encapsulates the semiconductor element, a portion of the conductive member, the insulating layer, and a portion of the conductor layer; the conductor layer is composed of a non-laminated portion in which an upper surface and a side surface of the conductor layer are in contact with the resin encapsulant, and a laminated portion in which the upper surface of the conductor layer is in contact with the insulating layer; Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein said insulating layer is provided with a chamfered portion at a corner formed between a top surface and a side surface of said insulating layer or at a corner formed between side surfaces of said insulating layer.

3. The semiconductor device according to claim 2 , wherein the chamfered portion has a curved surface.

4. The semiconductor device according to claim 2 , wherein the chamfered portion has a flat surface at a predetermined angle.

5. The semiconductor device according to claim 1 , wherein a protrusion is provided on the non-laminated portion of the conductor layer.

6. The semiconductor device according to claim 1 , wherein the non-laminated portion of the conductor layer is provided with a bent portion.

7. The semiconductor device according to claim 1 , wherein the non-laminated portion of the conductor layer is provided with a recess.

8. The semiconductor device according to claim 1 , wherein the thickness of the non-laminated portion of the conductor layer is greater than the thickness of the laminated portion.

9. a main conversion circuit having the semiconductor device according to claim 1, which converts input power and outputs the converted power; a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit; A power conversion device comprising:

Images