Semiconductor device

Abstract

To reduce the number of parts used in a semiconductor device.SOLUTION: A semiconductor substrate 20 includes first to sixth semiconductor element groups G1 to G6, an input terminal 25, output terminals 35, a first internal terminal 40a, a second internal terminal 40b, multiple conductor patterns 23, and a temperature sensor 74. Each of the first to sixth semiconductor element groups G1 to G6 includes multiple semiconductor elements 24. The multiple semiconductor elements 24 each include heat spreaders 24a. The multiple conductor patterns 23 consist of a first conductor pattern 21 and a second conductor pattern 22. The first conductor pattern 21 overlaps with the first internal terminal 40a, the fourth semiconductor element group G4, and the fifth semiconductor element group G5 in a plan view of the semiconductor substrate 20. The second conductor pattern 22 overlaps the input terminal 25, the output terminals 35, and the second internal terminal 40b in a plan view of the semiconductor substrate 20. The second conductor pattern 22 overlaps the first to sixth semiconductor element groups G1 to G6 in a plan view of the semiconductor substrate 20. The number of these groups is less than that of the first conductor pattern 21. A temperature sensor 74 detects the temperature of the first conductor pattern 21.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A known semiconductor device includes a semiconductor substrate having a plurality of semiconductor element groups and a plurality of terminals, and a capacitor substrate having a capacitor. Each of the plurality of semiconductor element groups includes a plurality of semiconductor elements. The plurality of terminals contact the capacitor substrate to electrically connect the capacitor substrate and the semiconductor substrate.

[0003] The semiconductor device described in Patent Document 1 includes multiple temperature sensors for detecting the temperatures of semiconductor elements, one of which detects the temperature of the U-phase semiconductor element, one of which detects the temperature of the V-phase semiconductor element, and the remaining one of which detects the temperature of the W-phase semiconductor element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-228775 A Summary of the Invention [Problem to be solved by the invention]

[0005] It has been desired to reduce the number of temperature sensors provided on a semiconductor substrate, thereby reducing the number of components in a semiconductor device. [Means for solving the problem]

[0006] A semiconductor device that solves the above problem includes a semiconductor substrate provided with a plurality of semiconductor element groups, each of which has a plurality of semiconductor elements, a plurality of terminals, a plurality of conductor patterns, and a temperature sensor, and a capacitor substrate provided with a capacitor, wherein the plurality of semiconductor elements include a heat spreader, and the plurality of terminals contact the capacitor substrate to electrically connect the capacitor substrate and the semiconductor substrate, and the plurality of conductor patterns include a first conductor pattern which is one of the conductor patterns overlapping one of the terminals and the plurality of semiconductor element groups in a planar view of the semiconductor substrate, and a second conductor pattern which is at least one of the conductor patterns other than the first conductor pattern, overlapping one of the terminals in a planar view of the semiconductor substrate and overlapping with fewer semiconductor element groups in a planar view of the semiconductor substrate than the first conductor pattern, and the temperature sensor detects the temperature of the first conductor pattern.

[0007] According to the above configuration, the number of semiconductor element groups overlapping the first conductor pattern in a plan view of the semiconductor substrate is greater than the number of semiconductor element groups overlapping the second conductor pattern in a plan view of the semiconductor substrate. The greater the number of semiconductor element groups overlapping the conductor pattern in a plan view of the semiconductor substrate, the greater the amount of heat transferred from the semiconductor element to the conductor pattern through the heat spreader included in the semiconductor element. Therefore, the first conductor pattern is more likely to have a higher temperature than the second conductor pattern. In this way, the temperature of the first conductor pattern, which is more likely to have a higher temperature than the second conductor pattern, can be detected by the temperature sensor. The temperature sensor can detect the temperature rise of the first conductor pattern caused by the temperature rise of the semiconductor element at an early stage. Since the temperature rise of the semiconductor element provided on the semiconductor substrate can be detected without detecting the temperature of the second conductor pattern, there is no need to provide a temperature sensor on the semiconductor substrate other than the temperature sensor that detects the temperature of the first conductor pattern. Therefore, the number of components in the semiconductor device can be reduced compared to the case where a plurality of temperature sensors are provided on the semiconductor substrate.

[0008] In the semiconductor device, the semiconductor device may be mounted on an industrial vehicle and may further include a control unit that controls an output of a motor that drives the industrial vehicle based on a detection value from the temperature sensor.

[0009] According to the above configuration, industrial vehicles are often operated at low or high temperatures compared to automobiles. Therefore, the temperature of the semiconductor element in the semiconductor device is easily changed depending on the environmental temperature. According to the above configuration, in the semiconductor device mounted on such an industrial vehicle, the temperature of the first conductor pattern, which changes due to the temperature change of the semiconductor element, is detected by the temperature sensor. The control unit controls the output of the motor that drives the industrial vehicle based on the detection value from the temperature sensor. Therefore, even in the semiconductor device of the industrial vehicle in which the temperature of the semiconductor element is easily changed due to the influence of the environmental temperature, the output of the motor can be controlled to a value corresponding to the temperature of the semiconductor element.

[0010] The semiconductor device may further include a cooling section that cools the first conductor pattern, one of the terminals that overlaps with the first conductor pattern in a planar view of the semiconductor substrate, and a group of multiple semiconductor elements that overlap with the first conductor pattern in a planar view of the semiconductor substrate.

[0011] According to the above configuration, the temperature of the first conductor pattern rises due to heat transfer from the terminals and the semiconductor element groups that overlap the first conductor pattern in a plan view of the semiconductor substrate. At this time, cooling by the cooling unit can prevent the terminals and the semiconductor element groups that overlap the first conductor pattern in a plan view of the semiconductor substrate from becoming excessively hot.

[0012] The semiconductor device may further include a cooling section that cools the second conductor pattern, one of the terminals that overlaps with the second conductor pattern in a planar view of the semiconductor substrate, and the group of semiconductor elements that overlaps with the second conductor pattern in a planar view of the semiconductor substrate.

[0013] According to the above configuration, the temperature sensor detects the temperature of the first conductor pattern, but the second conductor pattern, which is not the target of temperature detection by the temperature sensor, and the terminals and semiconductor element group that overlap the second conductor pattern in a planar view of the semiconductor substrate can be cooled by the cooling section. Effect of the Invention

[0014] According to the present invention, the number of parts in a semiconductor device can be reduced. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is an exploded perspective view showing a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a top view showing a semiconductor substrate in the embodiment. [Diagram 3] FIG. 3 is an enlarged top view of a portion of the semiconductor substrate according to the embodiment. [Figure 4] FIG. 4 is a perspective view showing an internal terminal. [Diagram 5] FIG. 5 is a cross-sectional view taken along line 5-5 in FIG. [Figure 6] FIG. 6 is a circuit diagram of the semiconductor device. [Figure 7] FIG. 7 is an enlarged top view showing a part of a semiconductor device in a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment in which the semiconductor device is embodied in an inverter will be described. The inverter of this embodiment is mounted on a forklift as a battery-powered industrial vehicle. <Basic inverter configuration> 1, an inverter 10 serving as a semiconductor device includes a heat sink 11. The heat sink 11 is made of a metal such as an aluminum-based metal or copper. The heat sink 11 includes a plate-shaped fixing portion 12 and fins 13. The fins 13 protrude from one surface of the fixing portion 12 in the plate thickness direction.

[0017] The inverter 10 includes a semiconductor substrate 20 and a capacitor substrate 50. The inverter 10 further includes a control substrate 60. In this embodiment, the semiconductor substrate 20, the capacitor substrate 50, and the control substrate 60 are glass epoxy substrates. The thickness direction of the semiconductor substrate 20, the thickness direction of the control substrate 60, and the thickness direction of the capacitor substrate 50 are aligned with each other. The control substrate 60 is disposed at a distance from the semiconductor substrate 20 in the thickness direction of the semiconductor substrate 20. The capacitor substrate 50 is disposed between the semiconductor substrate 20 and the control substrate 60. The capacitor substrate 50 is disposed at a distance from the semiconductor substrate 20 in the thickness direction of the semiconductor substrate 20. The heat sink 11, the semiconductor substrate 20, the capacitor substrate 50, and the control substrate 60 are disposed in layers.

[0018] A plurality of capacitors 54 are provided on the capacitor substrate 50. The capacitors 54 are, for example, cylindrical. The capacitors 54 are arranged on the capacitor substrate 50 such that the axial direction of the capacitors 54 and the plate thickness direction of the capacitor substrate 50 coincide with each other.

[0019] The capacitor substrate 50 is formed with a recess 52, an output hole 53, and a first insertion hole H1. The recess 52 penetrates the capacitor substrate 50 in the plate thickness direction of the capacitor substrate 50. The recess 52 is formed in the capacitor substrate 50 so as to open to both ends in the longitudinal direction of the capacitor substrate 50. The output hole 53 is provided between the recess 52 at one end and the recess 52 at the other end in the longitudinal direction of the capacitor substrate 50. The capacitor substrate 50 is formed with three output holes 53. Each of the output holes 53 and the first insertion hole H1 is a hole that penetrates the capacitor substrate 50 in the plate thickness direction of the capacitor substrate 50.

[0020] Three output holes 61 are formed in the control board 60. The output holes 61 penetrate the control board 60 in the plate thickness direction. A through hole 62 is formed in the control board 60. Electronic components (not shown) are mounted on the control board 60. These electronic components constitute, for example, a control circuit that controls first to sixth semiconductor element groups G1 to G6, which will be described later.

[0021] <Semiconductor substrate> The semiconductor substrate 20 is fixed to one of the two surfaces of the fixing portion 12 in the plate thickness direction, opposite to the surface on which the fins 13 are provided. The semiconductor substrate 20 is provided with first to sixth semiconductor element groups G1 to G6 as a plurality of semiconductor element groups, two input terminals 25, three output terminals 35, and two internal terminals 40. The semiconductor element 24 in this embodiment is a MOSFET. The semiconductor element 24 may be a semiconductor element other than a MOSFET. For example, an insulated gate bipolar transistor may be adopted as the semiconductor element 24. In this embodiment, the two input terminals 25, the three output terminals 35, and the two internal terminals 40 correspond to a plurality of terminals.

[0022] A pin header 46 is provided on the semiconductor substrate 20. The pin header 46 is inserted into a through hole 62 of the control substrate 60. By inserting the pin header 46 into the through hole 62, the control substrate 60 and the semiconductor substrate 20 are connected to each other.

[0023] As shown in FIGS. 2 and 3, the first to sixth semiconductor element groups G1 to G6 each have a plurality of semiconductor elements 24. In this embodiment, each of the first to sixth semiconductor element groups G1 to G6 has six semiconductor elements 24. In each of the first to sixth semiconductor element groups G1 to G6, the six semiconductor elements 24 are arranged in a straight line at equal intervals from one another. Hereinafter, the direction in which the semiconductor elements 24 constituting the first to sixth semiconductor element groups G1 to G6 are arranged is referred to as a first direction. Of the directions along both sides of the semiconductor substrate 20, a direction perpendicular to the first direction is referred to as a second direction. Of both ends of the semiconductor substrate 20 in the first direction, one is referred to as a first end 20a, and the other end is referred to as a second end 20b.

[0024] The pin header 46 is mounted on a portion of the semiconductor substrate 20 where the first to sixth semiconductor element groups G1 to G6 are not mounted. The pin header 46 in the present embodiment is located closer to the second end 20b than the first to sixth semiconductor element groups G1 to G6 in the first direction.

[0025] In the first to sixth semiconductor element groups G1 to G6, the semiconductor elements 24 each include a heat spreader 24a. The heat spreader 24a is for dissipating heat from the semiconductor element 24 to the outside of the semiconductor element 24. For example, the semiconductor elements 24 each include the heat spreader 24a and a main body portion 24b. The main body portion 24b is, for example, a metal layer containing silicon molded with resin.

[0026] The first to sixth semiconductor element groups G1 to G6 are spaced apart from each other in the second direction. The first semiconductor element group G1 constitutes an upper arm of the U phase of the inverter 10. The second semiconductor element group G2 constitutes a lower arm of the U phase of the inverter 10. The third semiconductor element group G3 constitutes a lower arm of the V phase of the inverter 10. The fourth semiconductor element group G4 constitutes an upper arm of the V phase of the inverter 10. The fifth semiconductor element group G5 constitutes an upper arm of the W phase of the inverter 10. The sixth semiconductor element group G6 constitutes a lower arm of the W phase of the inverter 10.

[0027] A plurality of second through holes H2 are formed in the semiconductor substrate 20. The plurality of second through holes H2 are holes penetrating the semiconductor substrate 20 in the thickness direction of the semiconductor substrate 20. The number of the second through holes H2 formed in the semiconductor substrate 20 is the same as the number of the first through holes H1 formed in the capacitor substrate 50. The second through holes H2 are aligned with the first through holes H1 in the thickness direction of the semiconductor substrate 20.

[0028] 2, the two input terminals 25 and the three output terminals 35 are arranged at intervals in the second direction. The first to sixth semiconductor element groups G1 to G6 are located between the two input terminals 25 in the second direction. The three output terminals 35 are disposed between the two input terminals 25 in the second direction. The output terminals 35 are disposed between the first semiconductor element group G1 and the second semiconductor element group G2, between the third semiconductor element group G3 and the fourth semiconductor element group G4, and between the fifth semiconductor element group G5 and the sixth semiconductor element group G6.

[0029] 1, the input terminal 25 includes a base 26, a columnar portion 27 protruding from the base 26, and a seat portion 28 protruding from the peripheral surface of the columnar portion 27. Two terminal holes 26h are formed in the base 26 of the input terminal 25. The terminal holes 26h communicate with the second insertion hole H2 of the semiconductor substrate 20.

[0030] The output terminal 35 includes a base 36 and a columnar portion 37 protruding from the base 36. A terminal hole 36h is formed in the base 36 of the output terminal 35. The terminal hole 36h communicates with a second insertion hole H2 of the semiconductor substrate 20. The input terminal 25 and the output terminal 35 are made of a metal such as an aluminum-based metal or copper. The columnar portion 27 of the input terminal 25 and the columnar portion 37 of the output terminal 35 are arranged and spaced apart from each other in the second direction.

[0031] The two internal terminals 40 are arranged side by side at a distance from each other in the second direction. Each internal terminal 40 is disposed between two output terminals 35 in the second direction. The internal terminals 40 are made of a metal such as an aluminum-based metal or copper.

[0032] The columnar portion 27 of the input terminal 25 is inserted into the recess 52 of the capacitor board 50. A battery 71, which will be described later, is connected to the columnar portion 27 of the input terminal 25. The columnar portion 37 of the output terminal 35 is inserted into the output hole 53 of the capacitor board 50 and the output hole 61 of the control board 60. The columnar portion 37 of the output terminal 35 is connected to a motor 72, which serves as a three-phase motor, which will be described later.

[0033] The columnar portion 27 of the input terminal 25 contacts an end surface of the capacitor substrate 50 that defines the recess 52. In this manner, two of the multiple terminals, the input terminals 25, contact the capacitor substrate 50, thereby electrically connecting the capacitor substrate 50 and the semiconductor substrate 20.

[0034] The columnar portion 37 of the output terminal 35 contacts an end surface of the capacitor substrate 50 that defines the output hole 53. In this manner, three of the multiple output terminals 35 contact the capacitor substrate 50, thereby electrically connecting the capacitor substrate 50 and the semiconductor substrate 20.

[0035] As shown in FIG. 4, the internal terminal 40 includes a rectangular plate-shaped main body 41. The main body 41 includes a base 45 and two contact portions 43 protruding from the base 45. The two contact portions 43 protrude from the base 45 in the plate thickness direction of the main body 41. The two contact portions 43 are arranged side by side in the longitudinal direction of the main body 41. The internal terminal 40 includes a terminal hole 44. The terminal hole 44 penetrates the main body 41 in the plate thickness direction of the main body 41. The terminal hole 44 is provided in a portion of the main body 41 that includes the contact portions 43. The terminal hole 44 communicates with the second insertion hole H2 of the semiconductor substrate 20.

[0036] The internal terminal 40 has a first contact surface 47 and a second contact surface 48. The first contact surface 47 is one of the two surfaces in the plate thickness direction of the main body 41 opposite to the surface on which the contact portions 43 are provided. The second contact surface 48 is a tip surface of each of the contact portions 43. Each of the first contact surface 47 and the second contact surface 48 is smoothed by cutting, for example, when the internal terminal 40 is formed.

[0037] 2, of the two internal terminals 40, one internal terminal 40 is also referred to as a first internal terminal 40a, and the other internal terminal 40 is also referred to as a second internal terminal 40b. The second internal terminal 40b is disposed between the second semiconductor element group G2 and the third semiconductor element group G3. The first internal terminal 40a is disposed between the fourth semiconductor element group G4 and the fifth semiconductor element group G5.

[0038] 2 and 4, a first contact surface 47 of the second internal terminal 40b contacts a second conductor pattern 22 described below. A second contact surface 48 of the second internal terminal 40b contacts the capacitor substrate 50. In this way, the second internal terminal 40b contacts the capacitor substrate 50, thereby electrically connecting the capacitor substrate 50 and the semiconductor substrate 20.

[0039] 1, the inverter 10 includes a plurality of screws S1 and an insulating collar C. The plurality of screws S1 are inserted into the first insertion hole H1 of the capacitor board 50 and the second insertion hole H2 of the semiconductor board 20 together with the collar C via the terminal hole 26h of the input terminal 25, the terminal hole 36h of the output terminal 35, and the terminal hole 44 of the internal terminal 40. In this way, the plurality of screws S1 fasten the capacitor board 50 and the semiconductor board 20 to the fixing portion 12 of the heat sink 11. Note that the control board 60 may be fastened to the fixing portion 12 by inserting a screw member (not shown) inserted into a screw hole (not shown) of the control board 60 into a screw hole (not shown) of the fixing portion 12 of the heat sink 11.

[0040] A body 41 of the first internal terminal 40a overlaps a first conductor pattern 21, which will be described later, in a plan view of the semiconductor substrate 20. A first contact surface 47 contacts the first conductor pattern 21 of the semiconductor substrate 20. As a result, the first contact surface 47 is electrically connected to the first conductor pattern 21 of the semiconductor substrate 20. The capacitor substrate 50 and the semiconductor substrate 20 are electrically connected via the base 26 of the input terminal 25 and the internal terminal 40.

[0041] <Conductor pattern> As shown in FIG. 3, a plurality of conductor patterns 23 are provided on the semiconductor substrate 20. The plurality of conductor patterns 23 are composed of a first conductor pattern 21, which is one conductor pattern 23, and a second conductor pattern 22. The second conductor pattern 22 is at least one conductor pattern 23 other than the first conductor pattern 21 among the plurality of conductor patterns 23. In this embodiment, the plurality of conductor patterns 23 are composed of one first conductor pattern 21 and five second conductor patterns 22. The plurality of conductor patterns 23 are arranged in the second direction at intervals. A semiconductor element 24 is connected to each of the plurality of conductor patterns 23. Note that, in FIG. 3, one first conductor pattern 21 and three second conductor patterns 22 are illustrated among the plurality of conductor patterns 23. In FIG. 3, the two second conductor patterns 22, which are the other conductor patterns 23, are omitted from the illustration. Two second insertion holes H2 are provided in each of the portions of the semiconductor substrate 20 where the plurality of conductor patterns 23 are arranged.

[0042] 2 and 3, one of the two second conductor patterns 22 is connected to an input terminal 25 located at one end of the semiconductor substrate 20 in the second direction, and the other is connected to an input terminal 25 located at the other end of the semiconductor substrate 20 in the second direction. That is, one terminal is connected to each of the two second conductor patterns 22. The second conductor patterns 22 are located on one side and the other side of the first to sixth semiconductor element groups G1 to G6 in the second direction. As a result, the first to sixth semiconductor element groups G1 to G6 are located between the two second conductor patterns 22 in the second direction.

[0043] An output terminal 35 is connected to each of the three second conductor patterns 22. That is, one terminal is connected to each of the three second conductor patterns 22. Each of the three second conductor patterns 22 is disposed between the first semiconductor element group G1 and the second semiconductor element group G2, between the third semiconductor element group G3 and the fourth semiconductor element group G4, and between the fifth semiconductor element group G5 and the sixth semiconductor element group G6.

[0044] A second internal terminal 40b serving as one terminal is connected to one second conductor pattern 22. This second conductor pattern 22 is disposed between the second semiconductor element group G2 and the third semiconductor element group G3.

[0045] The base 26 of the input terminal 25, the base 36 of the output terminal 35, and the body 41 of the second internal terminal 40b overlap different second conductor patterns 22 in a plan view of the semiconductor substrate 20. As a result, the input terminal 25 overlaps the second conductor pattern 22 as one terminal in a plan view of the semiconductor substrate 20. The output terminal 35 overlaps the second conductor pattern 22 as one terminal in a plan view of the semiconductor substrate 20.

[0046] The first semiconductor element group G1, the second semiconductor element group G2, the third semiconductor element group G3, and the sixth semiconductor element group G6 overlap different second conductor patterns 22 in a plan view of the semiconductor substrate 20. In detail, the first semiconductor element group G1 overlaps one of the second conductor patterns 22 that overlaps with the two input terminals 25 in a plan view of the semiconductor substrate 20, in the plan view of the semiconductor substrate 20. The first to sixth semiconductor element groups G1 to G6 do not overlap the other second conductor pattern 22 in a plan view of the semiconductor substrate 20. The second semiconductor element group G2, the third semiconductor element group G3, and the sixth semiconductor element group G6 overlap different second conductor patterns 22 in a plan view of the semiconductor substrate 20. The first to sixth semiconductor element groups G1 to G6 do not overlap the second conductor pattern 22 that overlaps with the second internal terminal 40b in a plan view of the semiconductor substrate 20, in a plan view of the semiconductor substrate 20. Thus, in this embodiment, the number of the first to sixth semiconductor element groups G1 to G6 overlapping the second conductor pattern 22 in a plan view of the semiconductor substrate 20 is 0 (zero) or 1.

[0047] <Details of Semiconductor Elements and Terminals Connected to First Conductive Pattern> 5, a first internal terminal 40a serving as one terminal is connected to the first conductor pattern 21. The first contact surface 47 is in contact with the first conductor pattern 21 of the semiconductor substrate 20. As a result, the first contact surface 47 is electrically connected to the first conductor pattern 21 of the semiconductor substrate 20. The second contact surface 48 is in contact with the capacitor substrate 50. In this way, the first internal terminal 40a is in contact with the capacitor substrate 50, thereby electrically connecting the capacitor substrate 50 and the semiconductor substrate 20.

[0048] The first internal terminal 40a is provided on the first conductor pattern 21. As a result, the first conductor pattern 21 overlaps with the first internal terminal 40a in a planar view of the semiconductor substrate 20. The fourth semiconductor element group G4 and the fifth semiconductor element group G5 are provided on the first conductor pattern 21. As a result, the first conductor pattern 21 overlaps with the fourth semiconductor element group G4 and the fifth semiconductor element group G5, which are multiple semiconductor element groups, in a planar view of the semiconductor substrate 20. Therefore, the number of the first to sixth semiconductor element groups G1 to G6 that overlap with the second conductor pattern 22 in a planar view of the semiconductor substrate 20 is smaller than that of the first conductor pattern 21.

[0049] <Inverter control> 1 and 6, the inverter 10 converts DC power input from a battery 71 into AC power and then outputs the AC power to a motor 72. This drives the motor 72. The motor 72 in this embodiment is a three-phase motor. The capacitor 54 is connected to the battery 71.

[0050] The inverter 10 includes a control unit 73. The control unit 73 includes a processor and a storage unit. The processor may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), or a digital signal processor (DSP). The storage unit includes a random access memory (RAM) and a read only memory (ROM). The storage unit stores program codes or instructions configured to cause the processor to execute processes. The storage unit, i.e., the computer readable medium, includes any available medium accessible by a general-purpose or special-purpose computer. The control unit 73 may be configured by a hardware circuit such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The control unit 73, which is a processing circuit, may include one or more processors operating according to a computer program, one or more hardware circuits such as an ASIC or an FPGA, or a combination thereof.

[0051] A temperature sensor 74 is provided on the semiconductor substrate 20. The control unit 73 performs a switching operation of the first to sixth semiconductor element groups G1 to G6 based on, for example, a detection value from the temperature sensor 74. As a result, the control unit 73 controls the output of the motor 72 that drives a forklift as an industrial vehicle based on the detection value from the temperature sensor 74. In detail, the control unit 73 reduces the output of the motor 72 when the temperature detected by the temperature sensor 74 is equal to or higher than a predetermined temperature. As a result, it is possible to prevent the first to sixth semiconductor element groups G1 to G6 from overheating.

[0052] <Temperature sensor> 3, the temperature sensor 74 detects the temperature of the first conductor pattern 21. In detail, the temperature sensor 74 is disposed on the semiconductor substrate 20 between the first conductor pattern 21 and the first end 20a of the semiconductor substrate 20 in the first direction. The temperature sensor 74 is provided at a position equidistant from both the end on the first end 20a side of the fourth semiconductor element group G4 and the end on the first end 20a side of the fifth semiconductor element group G5 in the first direction. By disposing the temperature sensor 74 in the vicinity of the first conductor pattern 21 in this way, the temperature sensor 74 can detect the temperature of the first conductor pattern 21.

[0053] [Operation of the embodiment] In each of the plurality of conductor patterns 23, heat is transferred from the capacitor substrate 50 via the input terminals 25, the output terminals 35, and the internal terminals 40 which are in contact with the conductor pattern 23. Furthermore, in each of the plurality of conductor patterns 23, heat is transferred from the plurality of semiconductor elements 24 via the heat spreaders 24a included in the semiconductor elements 24 of the first to sixth semiconductor element groups G1 to G6 which are in contact with the conductor pattern 23.

[0054] Any one of the input terminal 25, the output terminal 35, the first internal terminal 40a, and the second internal terminal 40b overlaps the plurality of conductor patterns 23 in a plan view of the semiconductor substrate 20. On the other hand, the number of the first to sixth semiconductor element groups G1 to G6 overlapping the second conductor pattern 22 in a plan view of the semiconductor substrate 20 is smaller than that of the first conductor pattern 21. That is, the number of the first to sixth semiconductor element groups G1 to G6 overlapping the first conductor pattern 21 in a plan view of the semiconductor substrate 20 is greater than the number of the first to sixth semiconductor element groups G1 to G6 overlapping the second conductor pattern 22 in a plan view of the semiconductor substrate 20. Thus, the greater the number of the first to sixth semiconductor element groups G1 to G6 overlapping the conductor pattern 23 in a plan view of the semiconductor substrate 20, the greater the amount of heat transferred from the semiconductor element 24 to the conductor pattern 23 via the heat spreader 24a included in the semiconductor element 24. Therefore, the temperature of the first conductor pattern 21 is more likely to become higher than that of the second conductor pattern 22.

[0055] Heat is transferred from the first conductor pattern 21 through the semiconductor substrate 20 to the temperature sensor 74. This enables the temperature sensor 74 to detect the temperature of the first conductor pattern 21. [Effects of the embodiment] The effects of this embodiment will be described.

[0056] (1-1) The plurality of conductor patterns 23 are composed of a first conductor pattern 21 and a second conductor pattern 22. The first conductor pattern 21 overlaps the first internal terminal 40a in a plan view of the semiconductor substrate 20. The second conductor pattern 22 overlaps one of the input terminal 25, the output terminal 35, and the second internal terminal 40b in a plan view of the semiconductor substrate 20. The first conductor pattern 21 overlaps the fourth semiconductor element group G4 and the fifth semiconductor element group G5 in a plan view of the semiconductor substrate 20. The second conductor pattern 22 overlaps with fewer first to sixth semiconductor element groups G1 to G6 in a plan view of the semiconductor substrate 20 than the first conductor pattern 21. The temperature sensor 74 detects the temperature of the first conductor pattern 21. Therefore, the temperature of the first conductor pattern 21, which is likely to be higher in temperature than the second conductor pattern 22, can be detected by the temperature sensor 74. The temperature rise of the first conductor pattern 21 caused by the temperature rise of the semiconductor element 24 can be detected early by the temperature sensor 74. Since a temperature rise of the semiconductor element 24 provided on the semiconductor substrate 20 can be detected without detecting the temperature of the second conductor pattern 22, there is no need to provide a temperature sensor 74 on the semiconductor substrate 20 other than the temperature sensor 74 that detects the temperature of the first conductor pattern 21. Therefore, compared to the case where a plurality of temperature sensors 74 are provided on the semiconductor substrate 20, the number of components in the inverter 10 can be reduced.

[0057] (1-2) Forklifts as industrial vehicles are often operated under low or high temperatures compared to automobiles. Therefore, the temperature of the semiconductor element 24 in the inverter 10 is likely to change according to the environmental temperature. According to the above embodiment, in the inverter 10 mounted on such a forklift, the temperature of the first conductor pattern 21, which changes due to the temperature change of the semiconductor element 24, is detected by the temperature sensor 74. The control unit 73 controls the output of the motor 72 that drives the forklift based on the detection value from the temperature sensor 74. Therefore, even in the inverter 10 of the forklift in which the temperature of the semiconductor element 24 is likely to change due to the influence of the environmental temperature, the output of the motor 72 can be controlled to a value according to the temperature of the semiconductor element 24.

[0058] [Example of change] The above embodiment can be modified as follows: The above embodiment and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0059] As shown in FIG. 7, the inverter 10 may include a cooling unit 81. The cooling unit 81 in this modified example is shown by a solid line in FIG. 7. In the semiconductor substrate 20 illustrated in FIG. 7, the first conductor pattern 21, the first internal terminal 40a, the fourth semiconductor element group G4, and the fifth semiconductor element group G5 on the semiconductor substrate 20 are arranged at different positions from those in the above embodiment. In detail, the first conductor pattern 21, the first internal terminal 40a, the fourth semiconductor element group G4, and the fifth semiconductor element group G5 are located at the end of the semiconductor substrate 20 in the second direction. The cooling unit 81 is, for example, a blower. The cooling unit 81 may be configured to switch the blowing of air on and off by a control device (not shown). The cooling unit 81 may face the first conductor pattern 21 on the semiconductor substrate 20, the first internal terminal 40a overlapping the first conductor pattern 21 in a plan view of the semiconductor substrate 20, and the fourth semiconductor element group G4 and the fifth semiconductor element group G5 in the first direction. Air is blown from the cooling unit 81 toward the first conductor pattern 21 on the semiconductor substrate 20, the first internal terminal 40a overlapping the first conductor pattern 21 in a plan view of the semiconductor substrate 20, and the fourth semiconductor element group G4 and the fifth semiconductor element group G5. In this way, the cooling unit 81 cools the first conductor pattern 21 and the first internal terminal 40a as one terminal overlapping the first conductor pattern 21 in a plan view of the semiconductor substrate 20. The cooling unit 81 cools the fourth semiconductor element group G4 and the fifth semiconductor element group G5 as a plurality of semiconductor element groups overlapping the first conductor pattern 21 in a plan view of the semiconductor substrate 20. According to this modification, the following effects can be obtained.

[0060] (2-1) The cooling section 81 cools the first conductor pattern 21, the first internal terminals 40a overlapping the first conductor pattern 21 in a planar view of the semiconductor substrate 20, and the fourth semiconductor element group G4 and the fifth semiconductor element group G5 overlapping the first conductor pattern 21 in a planar view of the semiconductor substrate 20. The temperature of the first conductor pattern 21 rises due to heat transfer from the first internal terminals 40a, the fourth semiconductor element group G4, and the fifth semiconductor element group G5 overlapping the first conductor pattern 21 in a planar view of the semiconductor substrate 20. At this time, cooling by the cooling section 81 can prevent the first internal terminals 40a, the fourth semiconductor element group G4, and the fifth semiconductor element group G5 overlapping the first conductor pattern 21 in a planar view of the semiconductor substrate 20, and the first conductor pattern 21 from becoming excessively hot.

[0061] The cooling target of the cooling unit 81 may be changed from that of the above modification. The cooling unit 81 in this modification is shown by a two-dot chain line in FIG. 7. The cooling unit 81 in this modification may face all the second conductor patterns 22 on the semiconductor substrate 20, the second internal terminals 40b, the input terminals 25, and the output terminals 35, the first to third semiconductor element groups G1 to G3, and the sixth semiconductor element group G6 in the first direction. Air is blown from the cooling unit 81 toward all the second conductor patterns 22 on the semiconductor substrate 20, the second internal terminals 40b, the input terminals 25, and the output terminals 35, the first to third semiconductor element groups G1 to G3, and the sixth semiconductor element group G6. As a result, the cooling unit 81 cools the second conductor patterns 22, the second internal terminals 40b, the input terminals 25, and the output terminals 35, the first to third semiconductor element groups G1 to G3, and the sixth semiconductor element group G6. Each of the second internal terminal 40b, the input terminal 25, and the output terminal 35 corresponds to one terminal overlapping with the second conductor pattern 22 in a planar view of the semiconductor substrate 20. Each of the first to third semiconductor element groups G1 to G3 and the sixth semiconductor element group G6 corresponds to a semiconductor element group overlapping with the second conductor pattern 22 in a planar view of the semiconductor substrate 20. According to this modification, the following effects can be obtained.

[0062] (3-1) The cooling section 81 cools the multiple second conductor patterns 22, the second internal terminals 40b, the input terminal 25, the output terminal 35, the first to third semiconductor element groups G1 to G3, and the sixth semiconductor element group G6. The temperature sensor 74 detects the temperature of the first conductor pattern 21, but the second conductor pattern 22 is not the target of temperature detection by the temperature sensor 74. The cooling section 81 can cool the second conductor pattern 22, the second internal terminals 40b, the input terminal 25, the output terminal 35, the first to third semiconductor element groups G1 to G3, and the sixth semiconductor element group G6 that overlap the second conductor pattern 22 in a planar view of the semiconductor substrate 20.

[0063] In the above-described modified examples, the cooling unit 81 is not limited to a blower. For example, the cooling unit 81 may be a unit that performs cooling by water cooling. In the above embodiment and each of the modified examples, the arrangement order in the second direction of the first to sixth semiconductor element groups G1 to G6 provided on the semiconductor substrate 20 can be changed.

[0064] The number of semiconductor elements 24 constituting the first to sixth semiconductor element groups G1 to G6 may be changed as appropriate as long as it is, for example, two or more. The number of semiconductor element groups provided on the semiconductor substrate 20 is not limited to six and can be changed according to the number of phases of the motor 72.

[0065] The internal terminals 40 may be fixed to the semiconductor substrate 20 by means of a means other than the screws S1. For example, the internal terminals 40 may be fixed to the semiconductor substrate 20 by a bonding agent such as solder.

[0066] The position of the temperature sensor 74 on the semiconductor substrate 20 may be different from that in the above embodiment. For example, the temperature sensor 74 may be provided in a position close to either one of the ends of the fourth semiconductor element group G4 on the first end 20a side in the first direction and the ends of the fifth semiconductor element group G5 on the first end 20a side in the first direction. The temperature sensor 74 may be provided on the first conductor pattern 21. The temperature sensor 74 may be provided either between two semiconductor elements 24 in the fourth semiconductor element group G4 or between two semiconductor elements 24 in the fifth semiconductor element group G5.

[0067] The first conductor pattern 21 may overlap with semiconductor element groups other than the fourth semiconductor element group G4 and the fifth semiconductor element group G5 among the first to sixth semiconductor element groups G1 to G6 in a planar view of the semiconductor substrate 20. The first conductor pattern 21 may overlap with three or more semiconductor element groups among the first to sixth semiconductor element groups G1 to G6 in a planar view of the semiconductor substrate 20. In short, it is only necessary that the number of semiconductor element groups overlapping the first conductor pattern 21 in a planar view of the semiconductor substrate 20 is greater than the number of semiconductor element groups overlapping the second conductor pattern 22 in a planar view of the semiconductor substrate 20.

[0068] At least one of the semiconductor substrate 20, the capacitor substrate 50, and the control substrate 60 does not have to be a glass epoxy substrate. For example, the semiconductor substrate 20, the capacitor substrate 50, and the control substrate 60 may be an insulating metal substrate or a printed circuit board.

[0069] The inverter 10 may not be installed in an industrial vehicle. For example, the inverter 10 may be installed in an automobile. The semiconductor device is not limited to the inverter 10. For example, the semiconductor device may be a converter. [Explanation of symbols]

[0070] G1...first semiconductor element group as semiconductor element group, G2...second semiconductor element group as semiconductor element group, G3...third semiconductor element group as semiconductor element group, G4...fourth semiconductor element group as semiconductor element group, G5...fifth semiconductor element group as semiconductor element group, G6...sixth semiconductor element group as semiconductor element group, 10...inverter as semiconductor device, 20...semiconductor substrate, 21...first conductor pattern, 22...second conductor pattern, 23...conductor pattern, 24...semiconductor element, 24a...heat spreader, 25...input terminal as terminal, 35...output terminal as terminal, 40...internal terminal as terminal, 50...capacitor substrate, 54...capacitor, 72...motor, 73...control unit, 74...temperature sensor, 81...cooling unit.

Claims

1. a semiconductor substrate provided with a plurality of semiconductor element groups, each of which has a plurality of semiconductor elements, a plurality of terminals, a plurality of conductor patterns, and a temperature sensor; A semiconductor device comprising: the plurality of semiconductor elements include a heat spreader; the plurality of terminals contact the capacitor substrate to electrically connect the capacitor substrate and the semiconductor substrate; the plurality of conductor patterns are comprised of a first conductor pattern which is one of the conductor patterns overlapping one of the terminals and the plurality of the semiconductor element groups in a planar view of the semiconductor substrate, and a second conductor pattern which is at least one of the conductor patterns other than the first conductor pattern, overlapping one of the terminals in a planar view of the semiconductor substrate and overlapping a smaller number of the semiconductor element groups in a planar view of the semiconductor substrate than the first conductor pattern; The semiconductor device is characterized in that the temperature sensor detects a temperature of the first conductor pattern.

2. The semiconductor device is mounted on an industrial vehicle, 2. The semiconductor device according to claim 1, further comprising a control unit that controls an output of a motor that drives the industrial vehicle based on a detection value from the temperature sensor.

3. 3. The semiconductor device according to claim 1, further comprising a cooling section that cools the first conductor pattern, one of the terminals that overlaps with the first conductor pattern in a planar view of the semiconductor substrate, and a group of a plurality of the semiconductor elements that overlap with the first conductor pattern in a planar view of the semiconductor substrate.

4. 3. The semiconductor device according to claim 1, further comprising a cooling section that cools the second conductor pattern, one of the terminals that overlaps with the second conductor pattern in a planar view of the semiconductor substrate, and the semiconductor element group that overlaps with the second conductor pattern in a planar view of the semiconductor substrate.

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