Semiconductor integrated circuit and receiving device

Abstract

To provide a semiconductor integrated circuit capable of suitably generating a digital signal on the basis of an analog signal, and a receiving device.SOLUTION: A semiconductor integrated circuit of an embodiment comprises: a first buffer including an input port supplied with a first signal; a first switching element including a first port connected to the output port of the first buffer and a second port connected to a first node and switching the status on the basis of a first clock signal; a first capacitor including a first port connected to the first node and a second port to be grounded; a second switching element including a first port connected to the first node and a second port connected to a second node and switching the status on the basis of the first clock signal; a second buffer including an input port connected to the second node; and a first converter configured to determine a first bit string from a first output from the second buffer.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The embodiments relate to a semiconductor integrated circuit and a receiving device. [Background technology]

[0002] The transmitting device and the receiving device are connected via a transmission path. The transmitting device superimposes data on an analog signal and outputs the analog signal. The receiving device receives the analog signal that has passed through the transmission path. The receiving device includes a semiconductor integrated circuit that processes the analog signal. The receiving device generates a digital signal based on the analog signal. The receiving device reproduces data based on the generated digital signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-72406 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor integrated circuit and a receiving device are provided that suitably generate a digital signal based on an analog signal. [Means for solving the problem]

[0005] A semiconductor integrated circuit according to an embodiment includes a first buffer, a second buffer, a first switching element, a second switching element, a first capacitor, and a first converter. The first buffer has an input terminal to which a first signal is supplied. The first switching element has a first terminal connected to an output terminal of the first buffer and a second terminal connected to a first node, and switches a state based on a first clock signal. The first capacitor has a first terminal connected to the first node and a second terminal grounded. The second switching element has a first terminal connected to the first node and a second terminal connected to a second node, and switches a state based on the first clock signal. The second buffer has an input terminal connected to the second node. The first converter is configured to determine a first bit string from a first output from the second buffer. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a communication system including a receiving device according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of a receiving circuit included in the receiving device according to the embodiment. [Diagram 3] FIG. 2 is a block diagram showing an example of the configuration of an AD converter included in the receiving circuit according to the embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of a configuration of a portion of a sampling front end included in an AD converter according to the embodiment. [Diagram 5] 4 is a diagram showing an example of a signal tracking process in a sampling front end included in the AD converter according to the embodiment. FIG. [Figure 6] 4 is a diagram showing an example of a signal holding process in a sampling front end included in the AD converter according to the embodiment. FIG. [Figure 7] FIG. 11 is a block diagram showing an example of the configuration of a portion of a sampling front end included in an AD converter according to a first modified example. [Figure 8]FIG. 11 is a block diagram showing an example of the configuration of a portion of a sampling front end included in an AD converter according to a second modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from each other, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. Embodiment An embodiment will be described.

[0010] 1.1 Configuration 1.1.1 Communication Systems First, a configuration of a communication system including a receiving device according to an embodiment will be described. Fig. 1 is a block diagram showing an example of the configuration of a communication system including a receiving device according to an embodiment.

[0011] The communication system 1 is configured to transmit data from one device or circuit to another device or circuit by high-speed serial communication. Specifically, for example, the communication system 1 realizes a communication speed of 128 Gbps. The communication system 1 includes a transmitting device 2, a transmission path 3, and a receiving device 4. The communication system 1 may be configured by a plurality of devices or circuits provided on the same printed circuit board, or may be configured by a plurality of devices or circuits provided on different printed circuit boards.

[0012] The transmitting device 2 is configured to transmit signals TR and / TR to the receiving device 4 via the transmission path 3. The signals TR and / TR are differential signals. The signals TR and / TR are, for example, signals including a plurality of pulse signals. Data is superimposed on each pulse signal of the signals TR and / TR. The voltage level of each pulse signal of the signals TR and / TR corresponds to one or more bits of data. The data superimposed on the pulse signals is transmitted from the transmitting device 2 to the receiving device 4 via the transmission path 3.

[0013] The transmission path 3 is a physical or spatial transmission medium for transmitting the signals TR and / TR to the receiving device 4. The transmission path 3 is, for example, a wiring that connects between the transmitting device 2 and the receiving device 4. The transmission path 3 can have various transmission characteristics depending on the structure and material of the transmission medium. The transmission characteristics of the transmission path 3 include, for example, frequency characteristics accompanied by a loss of gain in a specific frequency band.

[0014] The signals TR and / TR transmitted by the transmitting device 2 pass through the transmission path 3 and are subjected to loss according to the transmission characteristics of the transmission path 3. As a result, inter-symbol interference (ISI) occurs in the signals TR and / TR that have passed through the transmission path 3. For this reason, the signals TR and / TR that have passed through the transmission path 3 are processed as analog signals in the first-stage circuit of the receiving device 4. Hereinafter, the signals TR and / TR that have passed through the transmission path 3 and suffered loss will be referred to as signals RV and / RV.

[0015] The receiving device 4 is configured to receive the signals RV and / RV from the transmitting device 2 via the transmission path 3. The receiving device 4 decodes the data superimposed on the signals TR and / TR by the transmitting device 2 based on the signals RV and / RV. The receiving device 4 has a receiving circuit for correctly decoding the data superimposed on the signals TR and / TR. The receiving circuit is also called a semiconductor integrated circuit.

[0016] 1.1.2 Receiver circuit FIG. 2 is a block diagram showing an example of a configuration of a receiving circuit of the receiving device according to the embodiment.

[0017] The receiving device 4 includes, as a receiving circuit, for example, pads P1 and P2, an AFE 10, a TI-ADC 20, a VREFGEN 30, a DSP 40, and a CDR 50.

[0018] Each of the pads P1 and P2 is a terminal connected to the transmission line 3. In the example of Fig. 2, the pads P1 and P2 receive signals RV and / RV, respectively, from the transmitting device 2 via the transmission line 3.

[0019] The AFE10 is an analog front end. The AFE10 includes, for example, a continuous time linear equalizer (CTLE) and a variable gain amplifier (VGA). The CTLE is an amplifier circuit having a frequency characteristic that compensates for the frequency characteristic of the transmission line 3. The VGA is an amplifier circuit capable of changing the gain. The signals RV and / RV are input to the AFE10 from pads P1 and P2, respectively. The AFE10 performs analog processing on the signals RV and / RV using the CTLE and VGA. The AFE10 generates signals Sin and / Sin based on the signals RV and / RV. That is, the signals Sin and / Sin are analog signals, similar to the signals RV and / RV. The AFE10 outputs the signals Sin and / Sin to the TI-ADC20.

[0020] The TI-ADC20 is a time-interleaved AD converter. In the communication system 1 that realizes 128 Gbps, when the bit depth is 2 bits, the TI-ADC20 realizes, for example, a sampling rate of 64 GS / s. In this case, the Nyquist frequency of the TI-ADC20 is 32 GHz. The TI-ADC20 executes a process of converting an analog signal into a digital signal. The signals Sin and / Sin are input to the TI-ADC20 from the AFE10. The reference voltages VRp and VRn (VRp / n) are input to the TI-ADC20 from the VREFGEN30. The signals CK1 and CK2 are input to the TI-ADC20 from the CDR50. The TI-ADC20 converts the signals Sin and / Sin into a signal X0 based on the reference voltages VRp and VRn and the signals CK1 and CK2. The TI-ADC20 outputs the signal X0 to the DSP40. The configuration of the TI-ADC20 will be described later.

[0021] The reference voltages VRp and VRn are voltages used in the process of converting an analog signal into a digital signal in the TI-ADC 20. The TI-ADC 20 generates a signal X0 based on the magnitude relationship between the potential difference between the signals Sin and / Sin and the potential difference (VRp-VRn) between the reference voltages VRp and VRn.

[0022] The signal CK1 is r1 Contains n clock signals. r1 is an integer equal to or greater than 1 (for example, 8). r1 The clock signals are, for example, at least 360° / n r1 In the following, the phase of n in the signal CK1 is different. r1 The clock signals are represented by signals CK1_0, ..., and CK1_(n r1 The frequency of the signal CK1 is lower than the frequency of the clock signal embedded in the signals TR and / TR by the transmitter 2.

[0023] Signal CK2 is n r2 Contains n clock signals. r2 is n r1The n of signal CK2 is a larger integer (for example, 32). r2 The clock signals are, for example, at least 360° / n r2 In the following, the phase of n in the signal CK2 is different. r2 The clock signals are signals CK2_0, ..., and CK2_(n r2 The frequency of the signal CK2 may be equal to or different from the frequency of the clock signal embedded in the signals TR and / TR by the transmitter 2.

[0024] The signal X0 output by the TI-ADC20 is a digital signal. The signal X0 includes a series of digital values. One digital value included in the signal X0 is sampled from one symbol of the signals Sin and / Sin based on one clock signal (specifically, an edge of the clock signal) of the signal CK2. One digital value is, for example, 8-bit data. The consecutive n digital values ​​included in the signal X0 are r2 The value of each bit of the digital value is n r2 n consecutive occurrences of the signals Sin and / Sin based on the clock signals r2 In the following, the signal X0 is sampled from consecutive n symbols. r2 The period during which the TI-ADC 20 generates n digital values ​​is also referred to simply as a “period.” r2 This digital value is also called "one period of the signal X0."

[0025] In addition, the consecutive n r2 The digital values ​​are digital values ​​X0_0, ..., and X0_(n r2 The string of 8-bit data contained in the digital value X0_j may be represented as a bit string X0_j<0:7> (where 0≦j≦n r2 -1). Note that the bit string X0_j<0:7> is the most significant bit (MSB) X0_j <0> to least significant bit (LSB) X0_j <7> It means a data string consisting of eight bits in order.

[0026] VREFGEN30 is a voltage generation circuit configured to generate reference voltages VRp and VRn.

[0027] The DSP 40 is a digital processing circuit (Digital Signal Processor). The DSP 40 includes, for example, a feed forward equalizer (FFE), a decision feedback equalizer (DFE), and a data decision circuit. A signal X0 is input to the DSP 40. The DSP 40 executes digital processing on the signal X0 using, for example, the FFE, the DFE, and the data decision circuit. Specifically, the DSP 40 generates a signal X and data A based on the signal X0. The DSP 40 outputs the signal X and data A to the CDR 50. The DSP 40 outputs the signal X and data A to a subsequent processing circuit (not shown). The subsequent processing circuit processes the signal X and data A. The signal X and data A output to the CDR 50 and the signal X and data A output to the subsequent processing circuit (not shown) may be the same signal or different signals.

[0028] The signal X is a digital signal, just like the signal X0. The signal X for one period is n r2 A is a set of digital values. Data A is the decoded data based on signal X.

[0029] The CDR50 is a clock data recovery circuit. The signal X and data A are input to the CDR50 every period. For example, the reference clock signal CKREF is input to the CDR50 from the transmitting device 2. The reference clock signal CKREF may be generated in the CDR50 or in the receiving device 4, independent of the transmitting device 2. The CDR50 calculates the phase correction amount of the signals CK1 and CK2 based on the reference clock signal CKREF, the signal X, and the data A. The CDR50 regenerates the signals CK1 and CK2 based on the calculated phase correction amount. The CDR50 outputs the regenerated signals CK1 and CK2 to the TI-ADC20 every period. In this way, the CDR50 regenerates the signals CK1 and CK2 that are the reference for the sampling timing of the signal X0 for one period based on the signal X and data A generated from the signal X0 for one period. Such a cyclic process for each period by the TI-ADC20, the DSP40, and the CDR50 is also called a "CDR loop."

[0030] In the following, (n r1 ,n r2 As a specific example of the combination of (8,32), the case where (8,32) is applied will be described.

[0031] 1.1.3 A / D converter Next, an internal configuration of an AD converter (TI-ADC) included in the receiver circuit according to the embodiment will be described. Fig. 3 is a block diagram showing an example of the configuration of an AD converter included in the receiver circuit according to the embodiment.

[0032] The TI-ADC 20 includes an SFE 21 and a plurality of SAR-ADCs 22. The SFE 21 includes an SFEP 21p and an SFEN 21n. The plurality of SAR-ADCs 22 include 32 SAR-ADCs 22_0, ..., and 22_31. In the example of FIG. 3, four SAR-ADCs 22_0, 22_8, 22_16, and 22_24 are indicated as "SAR-ADC22_0+8k" (0≦k≦3). Similarly, four SAR-ADCs 22_1, 22_9, 22_17, and 22_25 are indicated as "SAR-ADC22_1+8k". Four SAR-ADCs 22_2, 22_10, 22_18, and 22_26 are indicated as "SAR-ADC22_2+8k". Four SAR-ADCs 22_3, 22_11, 22_19, and 22_27 are designated as "SAR-ADC22_3+8k". Four SAR-ADCs 22_4, 22_12, 22_20, and 22_28 are designated as "SAR-ADC22_4+8k". Four SAR-ADCs 22_5, 22_13, 22_21, and 22_29 are designated as "SAR-ADC22_5+8k". Four SAR-ADCs 22_6, 22_14, 22_22, and 22_30 are designated as "SAR-ADC22_6+8k". Four SAR-ADCs 22_7, 22_15, 22_23, and 22_31 are designated as "SAR-ADC22_7+8k".

[0033] First, the configuration of the SFEP 21p will be described.

[0034] The SFEP 21p is a sampling front end corresponding to the signal Sin. The SFEP 21p outputs eight types of voltages VOP_0, VOP_1, VOP_2, VOP_3, VOP_4, VOP_5, VOP_6, and VOP_7 based on the signal Sin.

[0035] The SFEP 21p includes a plurality of buffers BFP and a plurality of sampling circuits THP. The plurality of sampling circuits THP include eight sampling circuits THP_0, THP_1, THP_2, THP_3, THP_4, THP_5, THP_6, and THP_7. Each of the plurality of buffers BFP is, for example, a buffer having a source follower. The plurality of buffers BFP include four first-stage buffers BFP_a, BFP_b, BFP_c, and BFP_d, and eight second-stage buffers BFP_0, BFP_1, BFP_2, BFP_3, BFP_4, BFP_5, BFP_6, and BFP_7. The four first-stage buffers BFP_a to BFP_d and the eight second-stage buffers BFP_0 to BFP_7 may each have the same configuration.

[0036] A signal Sin is input to an input terminal of the first-stage buffer BFP_a. The first-stage buffer BFP_a outputs a voltage VOP_a based on the signal Sin. A first terminal of a sampling circuit THP_0 and a first terminal of a sampling circuit THP_4 are connected to an output terminal of the first-stage buffer BFP_a.

[0037] A signal Sin is input to an input terminal of the first-stage buffer BFP_b. The first-stage buffer BFP_b outputs a voltage VOP_b based on the signal Sin. A first terminal of a sampling circuit THP_2 and a first terminal of a sampling circuit THP_6 are connected to an output terminal of the first-stage buffer BFP_b.

[0038] A signal Sin is input to an input terminal of the first-stage buffer BFP_c. The first-stage buffer BFP_c outputs a voltage VOP_c based on the signal Sin. A first terminal of a sampling circuit THP_1 and a first terminal of a sampling circuit THP_5 are connected to an output terminal of the first-stage buffer BFP_c.

[0039] A signal Sin is input to an input terminal of the first-stage buffer BFP_d. The first-stage buffer BFP_d outputs a voltage VOP_d based on the signal Sin. A first terminal of a sampling circuit THP_3 and a first terminal of a sampling circuit THP_7 are connected to an output terminal of the first-stage buffer BFP_d.

[0040] The sampling circuit THP_0 is configured to perform track processing and hold processing on the voltage VOP_a based on the signal CK1_0. The track processing is a process of making the voltage of a node in the sampling circuit follow the input voltage. The hold processing is a process of making the node in the sampling circuit store the input voltage. Specifically, the sampling circuit THP_0 follows the voltage VOP_a during the period when the signal CK1_0 is at the "H" level. The sampling circuit THP_0 maintains the voltage VOP_a during the period when the signal CK1_0 is at the "H" level during the period when the signal CK1_0 is at the "L" level. The input terminal of the second stage buffer BFP_0 is connected to the output terminal of the sampling circuit THP_0.

[0041] The sampling circuit THP_1 is configured to perform track and hold processing on the voltage VOP_c based on the signal CK1_1. Specifically, the sampling circuit THP_1 tracks the voltage VOP_c during the period when the signal CK1_1 is at the "H" level. The sampling circuit THP_1 maintains the voltage VOP_c during the period when the signal CK1_1 is at the "H" level during the period when the signal CK1_1 is at the "L" level. The input terminal of the second stage buffer BFP_1 is connected to the output terminal of the sampling circuit THP_1.

[0042] The sampling circuit THP_2 is configured to perform track and hold processing on the voltage VOP_b based on the signal CK1_2. Specifically, the sampling circuit THP_2 tracks the voltage VOP_b during the period when the signal CK1_2 is at the "H" level. The sampling circuit THP_2 maintains the voltage VOP_b during the period when the signal CK1_2 is at the "H" level during the period when the signal CK1_2 is at the "L" level. The input terminal of the second stage buffer BFP_2 is connected to the output terminal of the sampling circuit THP_2.

[0043] The sampling circuit THP_3 is configured to perform track and hold processing on the voltage VOP_d based on the signal CK1_3. Specifically, the sampling circuit THP_3 tracks the voltage VOP_d during the period when the signal CK1_3 is at the "H" level. The sampling circuit THP_3 maintains the voltage VOP_d during the period when the signal CK1_3 is at the "H" level during the period when the signal CK1_3 is at the "L" level. The input terminal of the second stage buffer BFP_3 is connected to the output terminal of the sampling circuit THP_3.

[0044] The sampling circuit THP_4 is configured to perform track and hold processing on the voltage VOP_a based on the signal CK1_4. Specifically, the sampling circuit THP_4 tracks the voltage VOP_a during the period when the signal CK1_4 is at the "H" level. The sampling circuit THP_4 maintains the voltage VOP_a during the period when the signal CK1_4 is at the "H" level during the period when the signal CK1_4 is at the "L" level. The input terminal of the second stage buffer BFP_4 is connected to the output terminal of the sampling circuit THP_4.

[0045] The sampling circuit THP_5 is configured to perform track and hold processing on the voltage VOP_c based on the signal CK1_5. Specifically, the sampling circuit THP_5 tracks the voltage VOP_c during the period when the signal CK1_5 is at the "H" level. The sampling circuit THP_5 maintains the voltage VOP_c during the period when the signal CK1_5 is at the "H" level during the period when the signal CK1_5 is at the "L" level. The input terminal of the second stage buffer BFP_5 is connected to the output terminal of the sampling circuit THP_5.

[0046] The sampling circuit THP_6 is configured to perform track and hold processing on the voltage VOP_b based on the signal CK1_6. Specifically, the sampling circuit THP_6 tracks the voltage VOP_b during the period when the signal CK1_6 is at the "H" level. The sampling circuit THP_6 maintains the voltage VOP_b during the period when the signal CK1_6 is at the "H" level during the period when the signal CK1_6 is at the "L" level. The input terminal of the second stage buffer BFP_6 is connected to the output terminal of the sampling circuit THP_6.

[0047] The sampling circuit THP_7 is configured to perform track and hold processing on the voltage VOP_d based on the signal CK1_7. Specifically, the sampling circuit THP_7 tracks the voltage VOP_d during the period when the signal CK1_7 is at the "H" level. The sampling circuit THP_7 maintains the voltage VOP_d during the period when the signal CK1_7 is at the "H" level during the period when the signal CK1_7 is at the "L" level. The input terminal of the second stage buffer BFP_7 is connected to the output terminal of the sampling circuit THP_7.

[0048] The second-stage buffer BFP_0 outputs a voltage VOP_0 based on a voltage VOP_a output from the sampling circuit THP_0. The SAR-ADCs 22_0, 22_8, 22_16, and 22_24 are connected to the output terminal of the second-stage buffer BFP_0.

[0049] The second-stage buffer BFP_1 outputs a voltage VOP_1 based on a voltage VOP_c output from the sampling circuit THP_1. The output terminal of the second-stage buffer BFP_1 is connected to the SAR-ADCs 22_1, 22_9, 22_17, and 22_25.

[0050] The second-stage buffer BFP_2 outputs a voltage VOP_2 based on the voltage VOP_b output from the sampling circuit THP_2. The output terminal of the second-stage buffer BFP_2 is connected to the SAR-ADCs 22_2, 22_10, 22_18, and 22_26.

[0051] The second-stage buffer BFP_3 outputs a voltage VOP_3 based on the voltage VOP_d output from the sampling circuit THP_3. The SAR-ADCs 22_3, 22_11, 22_19, and 22_27 are connected to the output terminal of the second-stage buffer BFP_3.

[0052] The second-stage buffer BFP_4 outputs a voltage VOP_4 based on the voltage VOP_a output from the sampling circuit THP_4. The SAR-ADCs 22_4, 22_12, 22_20, and 22_28 are connected to the output terminal of the second-stage buffer BFP_4.

[0053] The second-stage buffer BFP_5 outputs a voltage VOP_5 based on the voltage VOP_c output from the sampling circuit THP_5. The output terminal of the second-stage buffer BFP_5 is connected to the SAR-ADCs 22_5, 22_13, 22_21, and 22_29.

[0054] The second-stage buffer BFP_6 outputs a voltage VOP_6 based on the voltage VOP_b output from the sampling circuit THP_6. The output terminal of the second-stage buffer BFP_6 is connected to the SAR-ADCs 22_6, 22_14, 22_22, and 22_30.

[0055] The second-stage buffer BFP_7 outputs a voltage VOP_7 based on a voltage VOP_d output from the sampling circuit THP_7. The SAR-ADCs 22_7, 22_15, 22_23, and 22_31 are connected to the output terminal of the second-stage buffer BFP_7.

[0056] Next, the configuration of the SFEN 21n will be described.

[0057] SFEN21n is a sampling front end corresponding to the signal / Sin. SFEN21n outputs eight types of voltages VON_0, VON_1, VON_2, VON_3, VON_4, VON_5, VON_6, VON_7, and VON_8 based on the signal / Sin. SFEP21p and SFEN21n have the same configuration except for different inputs and outputs. That is, although not shown in FIG. 3, SFEN21n includes four first-stage buffers BFN_a to BFN_d, eight sampling circuits THN0 to THN_7, and eight second-stage buffers BFN_0 to BFN_7.

[0058] A signal / Sin is input to an input terminal of the first-stage buffer BFN_a. The first-stage buffer BFN_a outputs a voltage VON_a based on the signal / Sin. A first terminal of a sampling circuit THN_0 and a first terminal of a sampling circuit THN_4 are connected to an output terminal of the first-stage buffer BFN_a.

[0059] A signal / Sin is input to an input terminal of the first-stage buffer BFN_b. The first-stage buffer BFN_b outputs a voltage VON_b based on the signal / Sin. A first terminal of a sampling circuit THN_2 and a first terminal of a sampling circuit THN_6 are connected to an output terminal of the first-stage buffer BFN_b.

[0060] A signal / Sin is input to an input terminal of the first-stage buffer BFN_c. The first-stage buffer BFN_c outputs a voltage VON_c based on the signal / Sin. A first terminal of a sampling circuit THN_1 and a first terminal of a sampling circuit THN_5 are connected to an output terminal of the first-stage buffer BFN_c.

[0061] A signal / Sin is input to an input terminal of the first-stage buffer BFN_d. The first-stage buffer BFN_d outputs a voltage VON_d based on the signal / Sin. A first terminal of a sampling circuit THN_3 and a first terminal of a sampling circuit THN_7 are connected to an output terminal of the first-stage buffer BFN_d.

[0062] The sampling circuit THN_0 is configured to perform track and hold processing on the voltage VON_a based on the signal CK1_0. Specifically, the sampling circuit THN_0 tracks the voltage VON_a during the period when the signal CK1_0 is at the "H" level. The sampling circuit THN_0 maintains the voltage VON_a during the period when the signal CK1_0 is at the "H" level during the period when the signal CK1_0 is at the "L" level. The input terminal of the second stage buffer BFN_0 is connected to the output terminal of the sampling circuit THN_0.

[0063] The sampling circuit THN_1 is configured to perform track and hold processing on the voltage VON_c based on the signal CK1_1. Specifically, the sampling circuit THN_1 tracks the voltage VON_c during the period when the signal CK1_1 is at the "H" level. The sampling circuit THN_1 maintains the voltage VON_c during the period when the signal CK1_1 is at the "H" level during the period when the signal CK1_1 is at the "L" level. The input terminal of the second stage buffer BFN_1 is connected to the output terminal of the sampling circuit THN_1.

[0064] The sampling circuit THN_2 is configured to perform track and hold processing on the voltage VON_b based on the signal CK1_2. Specifically, the sampling circuit THN_2 tracks the voltage VON_b during the period when the signal CK1_2 is at the "H" level. The sampling circuit THN_2 maintains the voltage VON_b during the period when the signal CK1_2 is at the "H" level during the period when the signal CK1_2 is at the "L" level. The input terminal of the second stage buffer BFN_2 is connected to the output terminal of the sampling circuit THN_2.

[0065] The sampling circuit THN_3 is configured to perform track and hold processing on the voltage VON_d based on the signal CK1_3. Specifically, the sampling circuit THN_3 tracks the voltage VON_d during the period when the signal CK1_3 is at the "H" level. The sampling circuit THN_3 maintains the voltage VON_d during the period when the signal CK1_3 is at the "H" level during the period when the signal CK1_3 is at the "L" level. The input terminal of the second stage buffer BFN_3 is connected to the output terminal of the sampling circuit THN_3.

[0066] The sampling circuit THN_4 is configured to perform track and hold processing on the voltage VON_a based on the signal CK1_4. Specifically, the sampling circuit THN_4 tracks the voltage VON_a during the period when the signal CK1_4 is at the "H" level. The sampling circuit THN_4 maintains the voltage VON_a during the period when the signal CK1_4 is at the "H" level during the period when the signal CK1_4 is at the "L" level. The input terminal of the second stage buffer BFN_4 is connected to the output terminal of the sampling circuit THN_4.

[0067] The sampling circuit THN_5 is configured to perform track and hold processing on the voltage VON_c based on the signal CK1_5. Specifically, the sampling circuit THN_5 tracks the voltage VON_c during the period when the signal CK1_5 is at the "H" level. The sampling circuit THN_5 maintains the voltage VON_c during the period when the signal CK1_5 is at the "H" level during the period when the signal CK1_5 is at the "L" level. The input terminal of the second stage buffer BFN_5 is connected to the output terminal of the sampling circuit THN_5.

[0068] The sampling circuit THN_6 is configured to perform track and hold processing on the voltage VON_b based on the signal CK1_6. Specifically, the sampling circuit THN_6 tracks the voltage VON_b during the period when the signal CK1_6 is at the "H" level. The sampling circuit THN_6 maintains the voltage VON_b during the period when the signal CK1_6 is at the "H" level during the period when the signal CK1_6 is at the "L" level. The input terminal of the second stage buffer BFN_6 is connected to the output terminal of the sampling circuit THN_6.

[0069] The sampling circuit THN_7 is configured to perform track and hold processing on the voltage VON_d based on the signal CK1_7. Specifically, the sampling circuit THN_7 tracks the voltage VON_d during the period when the signal CK1_7 is at the "H" level. The sampling circuit THN_7 maintains the voltage VON_d during the period when the signal CK1_7 is at the "H" level during the period when the signal CK1_7 is at the "L" level. The input terminal of the second stage buffer BFN_7 is connected to the output terminal of the sampling circuit THN_7.

[0070] The second-stage buffer BFN_0 outputs a voltage VON_0 based on the voltage VON_a output from the sampling circuit THN_0. The SAR-ADCs 22_0, 22_8, 22_16, and 22_24 are connected to the output terminal of the second-stage buffer BFN_0.

[0071] The second-stage buffer BFN_1 outputs a voltage VON_1 based on the voltage VON_c output from the sampling circuit THN_1. The output terminal of the second-stage buffer BFN_1 is connected to the SAR-ADCs 22_1, 22_9, 22_17, and 22_25.

[0072] The second-stage buffer BFN_2 outputs a voltage VON_2 based on the voltage VON_b output from the sampling circuit THN_2. The output terminal of the second-stage buffer BFN_2 is connected to the SAR-ADCs 22_2, 22_10, 22_18, and 22_26.

[0073] The second-stage buffer BFN_3 outputs a voltage VON_3 based on the voltage VON_d output from the sampling circuit THN_3. The output terminal of the second-stage buffer BFN_3 is connected to the SAR-ADCs 22_3, 22_11, 22_19, and 22_27.

[0074] The second-stage buffer BFN_4 outputs a voltage VON_4 based on the voltage VON_a output from the sampling circuit THN_4. The SAR-ADCs 22_4, 22_12, 22_20, and 22_28 are connected to the output terminal of the second-stage buffer BFN_4.

[0075] The second-stage buffer BFN_5 outputs a voltage VON_5 based on the voltage VON_c output from the sampling circuit THN_5. The output terminal of the second-stage buffer BFN_5 is connected to the SAR-ADCs 22_5, 22_13, 22_21, and 22_29.

[0076] The second-stage buffer BFN_6 outputs a voltage VON_6 based on the voltage VON_b output from the sampling circuit THN_6. The SAR-ADCs 22_6, 22_14, 22_22, and 22_30 are connected to the output terminal of the second-stage buffer BFN_6.

[0077] The second-stage buffer BFN_7 outputs a voltage VON_7 based on the voltage VON_d output from the sampling circuit THN_7. The output terminal of the second-stage buffer BFN_7 is connected to the SAR-ADCs 22_7, 22_15, 22_23, and 22_31.

[0078] Each of the SAR-ADC22_0 to SAR-ADC22_31 is a successive approximation register AD converter. Each of the SAR-ADC22_0 to SAR-ADC22_31 has the same configuration. Signals CK2_0 to CK2_31 are input to the SAR-ADC22_0 to SAR-ADC22_31 as control signals, respectively. Reference voltages VRp and VRn are supplied to the SAR-ADC22_0 to SAR-ADC22_31 via different wirings, respectively. The SAR-ADC22_0 to SAR-ADC22_31 output signals X0_0 to X0_31, respectively, based on the signals CK2_0 to CK2_31 and the reference voltages VRp and VRn input correspondingly thereto.

[0079] The period when each of the signals CK2_0, CK2_8, CK2_16, and CK2_24 is at the “H” level is included in the period when the signal CK1_0 is at the “L” level. The period when each of the signals CK2_1, CK2_9, CK2_17, and CK2_25 is at the “H” level is included in the period when the signal CK1_1 is at the “L” level. The period when each of the signals CK2_2, CK2_10, CK2_18, and CK2_26 is at the “H” level is included in the period when the signal CK1_2 is at the “L” level. The period when each of the signals CK2_3, CK2_11, CK2_19, and CK2_27 is at the “H” level is included in the period when the signal CK1_3 is at the “L” level.

[0080] The period when each of the signals CK2_4, CK2_12, CK2_20, and CK2_28 is at the “H” level is included in the period when the signal CK1_4 is at the “L” level. The period when each of the signals CK2_5, CK2_13, CK2_21, and CK2_29 is at the “H” level is included in the period when the signal CK1_5 is at the “L” level. The period when each of the signals CK2_6, CK2_14, CK2_22, and CK2_30 is at the “H” level is included in the period when the signal CK1_6 is at the “L” level. The period when each of the signals CK2_7, CK2_15, CK2_23, and CK2_31 is at the “H” level is included in the period when the signal CK1_7 is at the “L” level.

[0081] 1.1.4 Sampling Front End Fig. 4 is a block diagram showing an example of a configuration of a part of a sampling front end included in an AD converter according to an embodiment. In Fig. 4, a part of SFE21 that operates in association with signal CK1_0 is shown as an example. Note that the configuration of the part that operates in association with each of signals CK1_1 to CK1_7 is equivalent to the configuration of the part that operates in association with signal CK1_0.

[0082] 4, the SFE21 includes first stage buffers BFP_a and BFN_a, sampling circuits THP_0 and THN_0, and second stage buffers BFP_0 and BFN_0 as a part related to the signal CK1_0. The sampling circuit THP_0 includes switching elements SW1p_0 and SW2p_0, and a capacitor C1p_0. The sampling circuit THN_0 includes switching elements SW1n_0 and SW2n_0, and a capacitor C1n_0. The SFE21 further includes switching elements SW3_0 and SW4_0, and an inverter INV_0 as a part related to the signal CK1_0.

[0083] The switching element SW1p_0 has a first terminal connected to the output terminal of the first-stage buffer BFP_a and a second terminal connected to a node N1p_0. The switching element SW2p_0 has a first terminal connected to the node N1p_0 and a second terminal connected to the node N2p_0. The capacitor C1p_0 has a first terminal connected to the node N1p_0 and a second terminal grounded. Being grounded means being connected to a wiring to which a reference potential (for example, a voltage VSS=0V) is applied when the SFE21 operates. The switching elements SW1p_0 and SW2p_0 may each be composed of a transistor.

[0084] The switching element SW1n_0 has a first terminal connected to the output terminal of the first stage buffer BFN_a and a second terminal connected to a node N1n_0. The switching element SW2n_0 has a first terminal connected to the node N1n_0 and a second terminal connected to a node N2n_0. The capacitor C1n_0 has a first terminal connected to the node N1n_0 and a second terminal grounded. The switching elements SW1n_0 and SW2n_0 may each be composed of a transistor.

[0085] The switching element SW3_0 has a first terminal connected to the node N2p_0 and a second terminal connected to the node N2n_0. The switching element SW4_0 has a first terminal connected to the node N3p_0 and a second terminal connected to the node N3n_0. Each of the switching elements SW3_0 and SW4_0 may be formed of a transistor.

[0086] The second stage buffer BFP_0 has an input terminal connected to the node N2p_0 and an output terminal connected to the node N3p_0. The second stage buffer BFN_0 has an input terminal connected to the node N2n_0 and an output terminal connected to the node N3n_0.

[0087] The inverter INV_0 is configured to output a signal / CK1_0 that is an inverted signal of the signal CK1_0 based on the signal CK1_0.

[0088] Each of the switching elements SW1p_0, SW1n_0, SW3_0, and SW4_0 is switched between an on state and an off state based on a signal CK1_0. Each of the switching elements SW2p_0 and SW2n_0 is switched between an on state and an off state based on a signal / CK1_0.

[0089] 1.2 Operation Next, the operation of the sampling front end according to the embodiment will be described.

[0090] 1.2.1 Track Processing Fig. 5 is a diagram showing an example of a signal tracking process in a sampling front end included in an AD converter according to an embodiment. Fig. 5 shows a schematic diagram of a state during tracking process of the various configurations shown in Fig. 4.

[0091] As shown in FIG. 5, the track process corresponds to the operation when the signal CK1_0 is at the “H” level. When the signal CK1_0 is at the “H” level, the switching elements SW1p_0 and SW1n_0 are turned on. This causes the first stage buffers BFP_a and BFN_a to be electrically connected to the nodes N1p_0 and N1n_0, respectively. Therefore, the capacitors C1p_0 and C1n_0 are charged to follow the voltages VOP_a and VON_a, respectively.

[0092] When the signal CK1_0 is at the “H” level, the switching elements SW2p_0 and SW2n_0 are turned off, so that the nodes N2p_0 and N2n_ are electrically isolated from the nodes N1p_0 and N1n_0, respectively.

[0093] When the signal CK1_0 is at the “H” level, the switching elements SW3_0 and SW4_0 are turned on. As a result, the nodes N2p_0 and N2n_0 are electrically connected to each other. Similarly, the nodes N3p_0 and N3n_0 are electrically connected to each other.

[0094] 1.2.2 Hold processing Fig. 6 is a diagram showing an example of a signal hold process in a sampling front end included in an AD converter according to an embodiment. Fig. 6 shows a schematic diagram of a state during a hold process in each of the configurations shown in Fig. 4.

[0095] As shown in FIG. 6, the hold process corresponds to the operation when the signal CK1_0 is at the "L" level. When the signal CK1_0 is at the "L" level, the switching elements SW1p_0 and SW1n_0 are turned off. As a result, the nodes N1p_0 and N1n_0 are electrically isolated from the first stage buffers BFP_a and BFN_a, respectively. Therefore, the voltages charged in the capacitors C1p_0 and C1n_0 during the track process are maintained throughout the hold process.

[0096] When the signal CK1_0 is at the "L" level, the switching elements SW2p_0 and SW2n_0 are turned on. As a result, the nodes N2p_0 and N2n_0 are electrically connected to the nodes N1p_0 and N1n_0, respectively. Therefore, the voltages charged in the capacitors C1p_0 and C1n_0 during the track process are supplied to the second-stage buffers BFP_0 and BFN_0, respectively.

[0097] When the signal CK1_0 is at the "L" level, the switching elements SW3_0 and SW4_0 are turned off. As a result, the nodes N2p_0 and N2n_0 are electrically isolated from each other. Similarly, the nodes N3p_0 and N3n_0 are electrically isolated from each other.

[0098] 1.3 Effects of the embodiment According to the embodiment, when the signal CK1_0 is at the "H" level, the switching elements SW1p_0 and SW1n_0 are in the ON state, and the switching elements SW2p_0 and SW2n_0 are in the OFF state. As a result, the capacitor C1p_0 is electrically connected to the first-stage buffer BFP_a while being electrically insulated from the second-stage buffer BFP_0. Therefore, during the track process, the capacitance of the second-stage buffer BFP_0 as seen from the capacitor C1p_0 and the first-stage buffer BFP_a can be reduced to a negligible level. Therefore, during the track process, the degradation of the bandwidth of each of the capacitor C1p_0 and the first-stage buffer BFP_a, especially in the high frequency band, due to the capacitance of the second-stage buffer BFP_0 can be suppressed.

[0099] Moreover, the switching elements SW3_0 and SW4_0 are turned on when the signal CK1_0 is at the "H" level. As a result, the input terminals of the second-stage buffers BFP_0 and BFN_0 are shorted, and the voltages of the input terminals of the second-stage buffers BFP_0 and BFN_0 are equalized to the intermediate value of the two voltages. Similarly, the output terminals of the second-stage buffers BFP_0 and BFN_0 are shorted, and the voltages of the output terminals of the second-stage buffers BFP_0 and BFN_0 are equalized to the intermediate value of the two voltages. As described above, the second-stage buffers BFP_0 and BFN_0 are differential circuits. Therefore, the voltages of the input terminals of the second-stage buffers BFP_0 and BFN_0 and the voltages of the output terminals of the second-stage buffers BFP_0 and BFN_0 can be equalized to the intermediate value of the amplitude of the differential signal. Therefore, during the track process, the potential difference between the input terminal and the output terminal of each of the second stage buffers BFP_0 and BFN_0 (that is, the gate-source voltage of the source follower) can be made close to zero.

[0100] The switching elements SW3_0 and SW4_0 are turned off when the signal CK1_0 is at the "L" level. As a result, the second-stage buffers BFP_0 and BFN_0 are electrically insulated from each other when the signal CK1_0 is at the "L" level. Therefore, the second-stage buffer BFP_0 can operate based on the voltage charged to the capacitor C1p_0. Similarly, the second-stage buffer BFN_0 can operate based on the voltage charged to the capacitor C1n_0. Also, as described above, during the track process, the potential difference between the input terminal and the output terminal of each of the second-stage buffers BFP_0 and BFN_0 approaches 0. Therefore, the voltages charged to the capacitors C1p_0 and C1n_0 during the track process can be suppressed from fluctuating due to the influence of the gate-source voltage of the source follower during the hold process. Therefore, the distortion occurring in the voltages VOP_0 and VON_0 output from the second-stage buffers BFP_0 and BFN_0, respectively, can be reduced.

[0101] 2. Modifications, etc. The embodiment is not limited to the above-described example, and various modifications may be applied.

[0102] For example, in the above-described embodiment, the input ends of the second stage buffers BFP_0 and BFN_0 are shorted together and the output ends are shorted together during track processing, but the present invention is not limited to this.

[0103] 2.1 First modified example Fig. 7 is a block diagram showing an example of a configuration of a part of a sampling front end included in an AD converter according to Modification 1. Fig. 7 corresponds to Fig. 4 in the embodiment.

[0104] 7, the SFE21A includes first stage buffers BFP_a and BFN_a, sampling circuits THP_0 and THN_0, and second stage buffers BFP_0 and BFN_0 as parts related to the signal CK1_0. The SFE21A further includes switching elements SW5_0 and SW6_0, and an inverter INV_0 as parts related to the signal CK1_0.

[0105] In the first modified example, the configurations of the first stage buffers BFP_a and BFN_a, sampling circuits THP_0 and THN_0, second stage buffers BFP_0 and BFN_0, and inverter INV_0 are equivalent to the configurations of the first stage buffers BFP_a and BFN_a, sampling circuits THP_0 and THN_0, second stage buffers BFP_0 and BFN_0, and inverter INV_0 included in SFE21 in the embodiment.

[0106] The switching element SW5_0 has a first terminal connected to the node N2p_0 and a second terminal connected to the node N3p_0. The switching element SW6_0 has a first terminal connected to the node N2n_0 and a second terminal connected to the node N3n_0. Each of the switching elements SW5_0 and SW6_0 is switched between an on state and an off state based on a signal CK1_0. In a track process, when the signal CK1_0 is at an “H” level, the switching elements SW5_0 and SW6_0 are in an on state. In a hold process, when the signal CK1_0 is at an “L” level, the switching elements SW5_0 and SW6_0 are in an off state. The switching elements SW5_0 and SW6_0 may each be composed of a transistor.

[0107] According to the first modification, the input end and the output end of the second-stage buffer BFP_0 are shorted during the track process, so that the voltages at the input end and the output end of the second-stage buffer BFP_0 are equalized to the intermediate value between the two voltages. Similarly, the input end and the output end of the second-stage buffer BFN_0 are shorted during the track process, so that the voltages at the input end and the output end of the second-stage buffer BFN_0 are equalized to the intermediate value between the two voltages. This allows the voltages at the input end and the output end of the second-stage buffer BFP_0 to be aligned to the intermediate value of the signal amplitude. Similarly, the voltages at the input end and the output end of the second-stage buffer BFN_0 can be aligned to the intermediate value of the signal amplitude. Therefore, the potential difference between the input end and the output end of each of the second-stage buffers BFP_0 and BFN_0 can be brought close to 0 during the track process. Therefore, similarly to the embodiment, it is possible to reduce distortion occurring in the voltages VOP_0 and VON_0 output from the second-stage buffers BFP_0 and BFN_0, respectively.

[0108] 2.2 Second variant Fig. 8 is a block diagram showing an example of a configuration of a part of a sampling front end included in an AD converter according to Modification 2. Fig. 8 corresponds to Fig. 4 in the embodiment.

[0109] 8, the SFE21B includes first stage buffers BFP_a and BFN_a, sampling circuits THP_0 and THN_0, and second stage buffers BFP_0 and BFN_0 as parts related to the signal CK1_0. The SFE21B further includes switching elements SW7_0, SW8_0, SW9_0, and SW10_0, and an inverter INV_0 as parts related to the signal CK1_0.

[0110] In the second modified example, the configurations of the first stage buffers BFP_a and BFN_a, sampling circuits THP_0 and THN_0, second stage buffers BFP_0 and BFN_0, and inverter INV_0 are equivalent to the configurations of the first stage buffers BFP_a and BFN_a, sampling circuits THP_0 and THN_0, second stage buffers BFP_0 and BFN_0, and inverter INV_0 included in SFE21 in the embodiment.

[0111] The switching element SW7_0 has a first terminal connected to the node N2p_0 and a second terminal grounded. The switching element SW8_0 has a first terminal connected to the node N3p_0 and a second terminal grounded. The switching element SW9_0 has a first terminal connected to the node N2n_0 and a second terminal grounded. The switching element SW10_0 has a first terminal connected to the node N3n_0 and a second terminal grounded. Each of the switching elements SW7_0, SW8_0, SW9_0, and SW10_0 is switched between an on state and an off state based on a signal CK1_0. In the track process, when the signal CK1_0 is at the “H” level, each of the switching elements SW7_0, SW8_0, SW9_0, and SW10_0 is in an on state. In the hold process, when the signal CK1_0 is at the “L” level, each of the switching elements SW7_0, SW8_0, SW9_0, and SW10_0 is in the off state. Each of the switching elements SW7_0, SW8_0, SW9_0, and SW10_0 may be formed of a transistor.

[0112] According to the second modification, the input terminal and output terminal of the second stage buffer BFP_0 and the input terminal and output terminal of the second stage buffer BFN_0 are grounded during the track process. As a result, the voltages at the input terminal and output terminal of the second stage buffer BFP_0 and the voltages at the input terminal and output terminal of the second stage buffer BFN_0 are all equalized to 0V. As a result, the potential difference between the input terminal and output terminal of the second stage buffer BFP_0 can be made close to 0 during the track process. Similarly, the potential difference between the input terminal and output terminal of the second stage buffer BFN_0 can be made close to 0 during the track process. Therefore, as in the embodiment, the distortion occurring in the voltages VOP_0 and VON_0 output from the second stage buffers BFP_0 and BFN_0, respectively, can be reduced.

[0113] In addition, some or all of the above-described embodiments can be described as follows, but are not limited to the following.

[0114] <Appendix 1> a first buffer having an input end to which a first signal is provided; a first switching element having a first terminal connected to an output terminal of the first buffer and a second terminal connected to a first node, the first switching element switching a state based on a first clock signal; a first capacitor having a first end connected to the first node and a second end connected to ground; a second switching element having a first end connected to the first node and a second end connected to a second node, the second switching element switching a state based on the first clock signal; a second buffer having an input connected to the second node; a first converter configured to determine a first sequence of bits from a first output from the second buffer; Equipped with Semiconductor integrated circuit.

[0115] <Appendix 2> the first switching element is configured to be in an on state when the first clock signal is at a first logic level, and to be in an off state when the first clock signal is at a second logic level different from the first logic level; the second switching element is configured to be in an off state when the first clock signal is at the first logic level, and to be in an on state when the first clock signal is at the second logic level; 2. The semiconductor integrated circuit of claim 1.

[0116] <Appendix 3> the first converter is configured to determine the first sequence of bits from the first output based on a second clock signal; a period during which the second clock signal is at the first logic level is included in a period during which the first clock signal is at the second logic level; 3. The semiconductor integrated circuit according to claim 2.

[0117] <Appendix 4> a second converter configured to determine a second sequence of bits from the first output based on a third clock signal that is shifted from the second clock signal by a first phase; a period during which the third clock signal is at the first logic level is included in a period during which the first clock signal is at the second logic level; 4. The semiconductor integrated circuit according to claim 3.

[0118] <Appendix 5> a thirteenth switching element having a first terminal connected to the output terminal of the first buffer and a second terminal connected to a fifth node, the thirteenth switching element switching a state based on a fourth clock signal that is shifted from the first clock signal by a second phase; a third capacitor having a first end connected to the fifth node and a second end grounded; a fourteenth switching element having a first terminal connected to the fifth node and a second terminal connected to a sixth node, the fourteenth switching element switching a state based on the fourth clock signal; a fifth buffer having an input connected to the sixth node; a third converter configured to determine a third sequence of bits from a third output from the fifth buffer; Further equipped with 2. The semiconductor integrated circuit of claim 1.

[0119] <Appendix 6> the first switching element is configured to be in an on state when the first clock signal is at a first logic level, and to be in an off state when the first clock signal is at a second logic level different from the first logic level; the second switching element is configured to be in an off state when the first clock signal is at the first logic level and to be in an on state when the first clock signal is at the second logic level; the thirteenth switching element is configured to be in an on state when the fourth clock signal is at the first logic level, and to be in an off state when the fourth clock signal is at the second logic level; the fourteenth switching element is configured to be in an off state when the fourth clock signal is at the first logic level, and to be in an on state when the fourth clock signal is at the second logic level; 6. The semiconductor integrated circuit according to claim 5.

[0120] <Appendix 7> a sixth buffer having an input end to which the first signal is supplied; a fifteenth switching element having a first terminal connected to the output terminal of the sixth buffer and a second terminal connected to a seventh node, the fifteenth switching element switching a state based on a fifth clock signal that is shifted by a third phase from the first clock signal; a fourth capacitor having a first end connected to the seventh node and a second end grounded; a sixteenth switching element having a first terminal connected to the seventh node and a second terminal connected to the eighth node, the sixteenth switching element switching a state based on the fifth clock signal; a seventh buffer having an input connected to the eighth node; a fourth converter configured to determine a fourth sequence of bits from a fourth output from the seventh buffer; Further equipped with 2. The semiconductor integrated circuit of claim 1.

[0121] <Appendix 8> the first switching element is configured to be in an on state when the first clock signal is at a first logic level, and to be in an off state when the first clock signal is at a second logic level different from the first logic level; the second switching element is configured to be in an off state when the first clock signal is at the first logic level and to be in an on state when the first clock signal is at the second logic level; the fifteenth switching element is configured to be in an on state when the fifth clock signal is at the first logic level, and to be in an off state when the fifth clock signal is at the second logic level; the sixteenth switching element is configured to be in an off state when the fifth clock signal is at the first logic level, and to be in an on state when the fifth clock signal is at the second logic level; 8. The semiconductor integrated circuit of claim 7.

[0122] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents as described in the claims, as well as the scope and spirit of the invention. [Explanation of symbols]

[0123] 1. Communication systems 2...Transmitting device 3...Transmission path 4. Receiving device 10…AFE 20…TI-ADC 21, 21A, 21B…SFE 21p…SFEP 21n…SFEN 22…SAR-ADC 30...VREFGEN 40…DSP 50…CDR BFP, BFN...Buffer THP, THN...Sampling circuit SW1p, SW1n, SW2p, SW2n, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10...switching elements C1p, C1n...capacitor INV…Inverter

Claims

1. a first buffer having an input to which a first signal is provided; a first switching element having a first terminal connected to an output terminal of the first buffer and a second terminal connected to a first node, the first switching element switching a state based on a first clock signal; a first capacitor having a first end connected to the first node and a second end connected to ground; a second switching element having a first end connected to the first node and a second end connected to a second node, the second switching element switching a state based on the first clock signal; a second buffer having an input connected to the second node; a first converter configured to determine a first sequence of bits from a first output from the second buffer; Equipped with Semiconductor integrated circuit.

2. the first switching element is configured to be in an on state when the first clock signal is at a first logic level, and to be in an off state when the first clock signal is at a second logic level different from the first logic level; the second switching element is configured to be in an off state when the first clock signal is at the first logic level, and to be in an on state when the first clock signal is at the second logic level.

2. The semiconductor integrated circuit according to claim 1.

3. a third buffer having an input end to which a second signal, which constitutes a differential signal with the first signal, is supplied; a third switching element having a first terminal connected to an output terminal of the third buffer and a second terminal connected to a third node, the third switching element switching a state based on the first clock signal; a second capacitor having a first end connected to the third node and a second end connected to ground; a fourth switching element having a first end connected to the third node and a second end connected to a fourth node, the fourth switching element switching a state based on the first clock signal; a fourth buffer having an input connected to the fourth node; Equipped with the first converter configured to determine the first sequence of bits from the first output and a second output from the fourth buffer; 2. The semiconductor integrated circuit according to claim 1.

4. the first switching element and the third switching element are configured to be in an on state when the first clock signal is at a first logic level, and to be in an off state when the first clock signal is at a second logic level different from the first logic level; the second switching element and the fourth switching element are configured to be in an off state when the first clock signal is at the first logic level, and to be in an on state when the first clock signal is at the second logic level.

4. The semiconductor integrated circuit according to claim 3.

5. a fifth switching element having a first end connected to the second node and a second end connected to the fourth node, the fifth switching element switching a state based on the first clock signal; a sixth switching element having a first terminal connected to the output terminal of the second buffer and a second terminal connected to the output terminal of the fourth buffer, the sixth switching element switching a state based on the first clock signal; Further equipped with 4. The semiconductor integrated circuit according to claim 3.

6. the first switching element, the third switching element, the fifth switching element, and the sixth switching element are configured to be in an on state when the first clock signal is at a first logic level, and to be in an off state when the first clock signal is at a second logic level different from the first logic level; the second switching element and the fourth switching element are configured to be in an off state when the first clock signal is at the first logic level, and to be in an on state when the first clock signal is at the second logic level.

6. The semiconductor integrated circuit according to claim 5.

7. a seventh switching element having a first end connected to the second node and a second end connected to an output end of the second buffer, the seventh switching element switching a state based on the first clock signal; an eighth switching element having a first end connected to the fourth node and a second end connected to an output end of the fourth buffer, the eighth switching element switching a state based on the first clock signal; Further equipped with 4. The semiconductor integrated circuit according to claim 3.

8. the first switching element, the third switching element, the seventh switching element, and the eighth switching element are configured to be in an on state when the first clock signal is at a first logic level, and to be in an off state when the first clock signal is at a second logic level different from the first logic level; the second switching element and the fourth switching element are configured to be in an off state when the first clock signal is at the first logic level, and to be in an on state when the first clock signal is at the second logic level.

8. The semiconductor integrated circuit according to claim 7.

9. a ninth switching element having a first end connected to the second node and a second end grounded, the ninth switching element switching a state based on the first clock signal; a tenth switching element having a first terminal connected to the output terminal of the second buffer and a second terminal grounded, the tenth switching element switching a state based on the first clock signal; an eleventh switching element having a first end connected to the fourth node and a second end grounded, the eleventh switching element switching a state based on the first clock signal; a twelfth switching element having a first terminal connected to the output terminal of the fourth buffer and a second terminal grounded, the twelfth switching element switching a state based on the first clock signal; Further equipped with 4. The semiconductor integrated circuit according to claim 3.

10. the first switching element, the third switching element, the ninth switching element, the tenth switching element, the eleventh switching element, and the twelfth switching element are configured to be in an on state when the first clock signal is at a first logic level, and to be in an off state when the first clock signal is at a second logic level different from the first logic level; the second switching element and the fourth switching element are configured to be in an off state when the first clock signal is at the first logic level, and to be in an on state when the first clock signal is at the second logic level.

10. The semiconductor integrated circuit according to claim 9.

11. A semiconductor integrated circuit according to any one of claims 1 to 10, a processing circuit for processing a signal output from the semiconductor integrated circuit; A receiving device comprising:

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