Configurable pin driver circuit output impedance

Abstract

To provide an automatized test system for transmitting a test signal to a device under test (DUT) and measuring a response signal from the DUT.SOLUTION: The test system can provide a test signal to, or receive a test signal from, a device under test (DUT) via a first signal path. The test system can be configured to present a stable (e.g., 50 ohm) impedance at a DUT interface. In an example, the stable impedance comprises a physical polysilicon resistor in series with an output stage of a driver circuit of the test system. The impedance of the output stage can be a function of an incremental impedance of transistors in a push-pull output circuit. In an example, a control loop is provided to change a bias condition for the transistors to adjust the impedance of the output stage.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] A test system for testing electronic devices may include a pin driver circuit that provides a voltage test pulse to a device under test (DUT). In response, the test system may be configured to measure a response from the DUT, such as to determine whether the DUT meets one or more specified operating parameters. The test system may optionally include multiple driver circuits, such as a Class AB driver circuit and a Class A driver circuit, to provide circuit test signals having different amplitude or timing characteristics. In one example, the test system is configured to measure the response from the DUT using an active load and a comparator circuit to sense transitions at the DUT pins.

[0002] A system for testing digital integrated circuits (ICs) may include a driver circuit configured to provide multiple voltage levels (e.g., Vhigh, Vlow, and Vterm) to a DUT. The DUT may exhibit bidirectional (I / O) capabilities in that it can both source and receive stimuli. The Vhigh and Vlow levels of the driver circuit serve to stimulate the DUT while it is in its "input" state, and Vterm acts as a termination for the DUT in its "output" state. The process of switching between Vhigh, Vlow, and Vterm may be conceptualized as a collection of three switches, each with one terminal connected to either Vhigh, Vlow, or Vterm, and the other terminal connected to a 50 ohm resistor, which is then connected to a DUT node. Transitions between the three levels may be accomplished by opening and closing the appropriate switches, such as closing only one switch at any given time. Summary of the Invention

[0003] The inventors have recognized that, among other things, a problem to be solved includes providing an automated test system for delivering test signals to a device under test (DUT) and measuring response signals therefrom. This problem may include providing a system that is relatively small, inexpensive to manufacture, consumes little power, or provides higher fidelity performance as compared to conventional systems.

[0004] In one example, the problem may include maintaining a stable and known impedance characteristic at the DUT interface of a test system. By convention, the ideal impedance characteristic at the DUT interface may be 50 ohms, although other conventions or impedance values ​​may be used for a particular test or device. If a stable or known impedance characteristic is not maintained, the DUT signal may be degraded or corrupted. For example, sources of corruption may include skin effect losses, dielectric loading, conductor resistance, and waveform reflections. Such signal corruption sources may contribute to undesired changes in the DUT signal as it travels between the DUT and, for example, a comparator configured to measure changes in the DUT signal. Undesired changes in the DUT signal may contribute to signal timing errors due to propagation delays or transmission line effects, which may contribute to erroneous or incorrect test results.

[0005] The inventors have recognized that providing a physical 50 ohm output resistor at the DUT interface is insufficient in some scenarios and impractical in others. The inventors have further recognized that the impedance at the DUT interface is a function of several factors of the test system's output stage, including the "incremental impedance" of the transistors that comprise the test system's output stage.

[0006] In one example, a solution to these and other problems may include or use a test system comprising a comparator circuit coupled to a DUT node, an active load coupled to the DUT node, and an output stage circuit coupled to the DUT node. The output stage circuit may be configured to provide a specified impedance characteristic at the DUT node that is substantially invariant over a specified range of DUT currents. In one example, the output stage circuit includes a class AB driver circuit including output transistors provided in a push-pull configuration. The output stage circuit may further include a bias current controller configured to provide a bias current for the output transistors of the driver circuit based on a first control input. In one example, the output stage circuit may further include a feedback controller configured to provide a feedback current at each base terminal of the output transistors of the driver circuit based on a second control input. The magnitude of the feedback current may be based on the DUT current. A user or other control system may provide control signals to the first and second control inputs to adjust the impedance of the output stage, thereby achieving a more accurate or optimal impedance characteristic at the DUT interface.

[0007] In one example, a solution to the above-mentioned problem may include a method for adjusting a characteristic output impedance of an output stage of a pin driver circuit. The method may include receiving a first control input at a bias current controller and, in response, providing a bias current to a transistor of the output stage of the pin driver circuit. A magnitude of the bias current may correspond to a value of the first control input. The method may further include receiving a second control input at a feedback controller and, in response, providing a feedback current at a base terminal of each of the transistors of the output stage of the pin driver circuit. A magnitude of the feedback current may correspond to a value of the second control input. In this example, the characteristic output impedance of the output stage corresponds to an impedance at an output node coupled to an emitter terminal of the transistor of the output stage.

[0008] This summary is not intended to provide an exclusive or exhaustive description of the invention. The detailed description is included to provide further information regarding the present patent application.

[0009] To easily identify the discussion of any particular element or function, the most significant digit or digits of a reference number refer to the number of the figure in which that element is first introduced. [Brief description of the drawings]

[0010] [Figure 1] 1 generally illustrates an example of a first test system that includes a pin driver. [Diagram 2] 1 generally illustrates an example of an output stage of a pin driver. [Diagram 3] 1 generally illustrates an example of a pin driver output stage having a bias current controller. [Figure 4] 1 illustrates a first diagram showing the relationship between DUT current and output stage impedance; [Diagram 5] 1 generally illustrates an example of a portion of a pin driver output stage having a degeneration resistor. [Figure 6] 1 illustrates a second diagram showing the relationship between DUT current and output stage impedance. [Figure 7] Generally, a first embodiment of a pin driver output stage having a bias current controller and a feedback controller is illustrated. [Figure 8] 1 generally illustrates a second embodiment of a pin driver output stage having a bias current controller and a feedback controller. [Figure 9] Generally speaking, an example of a method for adjusting the characteristic output impedance of an output stage of a pin driver circuit is illustrated. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The pin driver circuitry of the test system can provide voltage pulse stimuli to a device under test (DUT) at specified times and, optionally, measure response signals from the DUT. The test system can be configured to provide high fidelity output signal pulses over a relatively large range of output signal magnitudes to accommodate different tests and different types of devices under test.

[0012] In one example, the test system can include a pin driver architecture that can provide high fidelity stimulus signals with minimal high frequency signal overshoot or spikes and can enhance pulse edge placement accuracy and signal bandwidth at high or low power operating levels. In one example, the test system can include one or more driver stages, which can include a Class A driver stage or a Class AB driver stage, which can be configured to provide a variety of pulsed signals. The system can include control circuitry for precisely adjusting the switching voltage and current signals, as well as for controlling the operating modes and monitoring or measurement activities of the comparators.

[0013] In one example, multiple drivers or driver stages can be used to provide a test system that can be configured to test a variety of semiconductor devices with different voltage and speed requirements. Additionally, multiple drivers can be used to enhance or enable multiple signal level testing or "multiplexing" for physical layer testing. During physical layer testing, multiple drivers can be switched simultaneously to provide different stimuli or drive signals to the DUT.

[0014] In one example, a pin driver stage of a test system comprises a portion of the interface between a tester and a DUT. The pin driver stage can be responsible for establishing the timing accuracy of the test system. That is, the pin driver stage can be configured to accurately deliver DUT stimulus signal edges substantially independent of environmental or other factors. In some examples, the pin driver stage is configured to support higher frequency lower voltage current stimulus signals and lower frequency higher voltage stimulus signals. In one example, the pin driver stage maintains a particular characteristic impedance (e.g., 50 ohms) optimized for bandwidth and timing accuracy. The characteristic impedance can be matched, for example, to the impedance of a transmission line coupling the test system to the DUT.

[0015] The test system may include a comparator circuit or stage configured to receive a high speed voltage or current response signal from the DUT. A comparator is generally a decision element that provides information regarding the relationship of at least two input signals. For example, a comparator may provide a digital output (e.g., a logic high or logic low signal) indicative of the relationship of the signal from the DUT to a reference signal, such as a reference voltage signal. The comparator may include one or more gain stages, which may be coupled in series to obtain a high gain response.

[0016] In some instances, high speed automatic test equipment (ATE) systems have a sufficiently high bandwidth that non-ideal characteristics of the transmission medium between the device under test (DUT) and the ATE pin electronics may limit the overall system performance. This transmission medium or path generally comprises several cables, connectors, printed circuit board traces, and "pogo pins" that electrically couple to the DUT. Losses associated with such components are primarily manifested as "skin effect", where the resistance seen by a propagating signal is a function of the signal frequency. Since any signal can be represented by a superposition of many frequency components, certain components of the signal will experience greater loss than others, thus creating dispersive effects that degrade the signal communicating with the DUT. If the original signal is to be presented to the pin electronics with minimal distortion, great care must be taken in the design of the transmission path. In some cases, the frequency components present in high speed signals are so high that even the highest quality transmission paths can cause significant degradation in signal integrity. In such cases, the pin electronics receiver, typically a comparator, may include or use compensation circuitry to compensate for expected transmission losses.

[0017] FIG. 1 illustrates a first exemplary test system 100 generally showing a test system topology including multiple driver stages, loads, and comparator stages. The first exemplary test system 100 includes a driver system including a first driver AB 102, which may include a class AB driver circuit, and a first driver A 104, which may include a class A driver circuit. The first exemplary test system 100 may further include an output element, such as a first resistor 106, which may be configured to provide a specified output or load impedance. In one example, the first exemplary test system 100 includes a comparator circuit 122 or a first load circuit 108, which may include an active load or other load device. In one example, the test system is configured to provide a first output current 120 (i_OUT) at a DUT interface or DUT node 130. The DUT node 130 may be coupled to a DUT 124 using a load signal path 132. In some examples, the first resistor 106 and the load signal path 132 have matched impedance characteristics.

[0018] In one example, the first driver AB102 can be configured to generate a voltage stimulus signal by selecting between parallel-connected diode bridges, each bridge driven by a unique dedicated DC voltage level. In the first exemplary test system 100 of FIG. 1, DC voltages Vih110 and Vil112 drive the diode bridges in the first driver AB102. The switching stage can be followed by a voltage buffering stage that can provide power gain such that it can be used to generate large currents to serve as a 50 ohm DUT environment.

[0019] In contrast to the first driver AB 102, the first driver A 104 may be configured to generate transitions at the DUT node 130 using a relatively large current switching stage that may be directly coupled to the DUT node 130. The current switching stage of the first driver A 104 may alternately switch current into and out of the DUT node 130 in response to a control signal Swing 118, which may be a voltage control signal. The first driver A 104 may provide high speed operation, for example, because it may offload the Class AB voltage buffering stage with its attendant bandwidth and other performance limitations.

[0020] In one example, the first driver A104 can be configured to provide a relatively low amplitude signal at the DUT node 130. For example, the first driver A104 can generate a signal having a swing of about 2 volts. The first driver AB102 can be configured to provide a relatively high amplitude signal at the DUT node 130, for example, -1.5 to +7 volts. The first driver A104 generally operates at a higher switching speed or bandwidth than the first driver AB102. In one example, the first driver AB102 can be configured to absorb switching current from the first driver A104. That is, the first driver AB102 can act as a buffer through which the first driver A104 can source current, such as through the first resistor 106.

[0021] One or both of the first driver AB102 and the first driver A104 can be selected to meet different DUT test requirements that could not otherwise be met by a single driver. For example, while either driver circuit can provide a DUT waveform, the first driver AB102 can be configured to provide a higher amplitude, lower bandwidth stimulus signal, and the first driver A104 can be configured to provide a lower amplitude, higher bandwidth stimulus signal. In other examples, a single driver (e.g., the first driver AB102) can be used.

[0022] In one example, the first driver AB102 and the first driver A104 do not share an enable pin. Instead, each driver circuit includes independent enable control through pins EnAB114 and EnA116. The independent enable control facilitates the first driver AB102 acting as a slow high voltage stimulus source and as a static non-transition buffer to absorb switching current from the first driver A104.

[0023] 1 includes a comparator circuit 122. The comparator circuit 122 may include a single or multi-stage comparator configured to receive a signal from a DUT 124, such as via a DUT node 130 and a load signal path 132. The comparator circuit 122 may compare the received signal with a comparator reference signal 126 (e.g., Vth) and provide a differential comparator output signal 128 (e.g., OP) accordingly. For example, the comparator circuit 122 may receive a voltage response signal from the DUT 124 and compare the amplitude of the voltage response signal with the amplitude of the comparator reference signal 126. The comparator circuit 122 may provide information regarding the amplitude relationship using the differential comparator output signal 128, which may include a digital signal or a logic output signal.

[0024] 2 illustrates an example of a simplified output stage 200 of a pin driver, such as may generally include the output stage of the first driver AB 102. The simplified output stage 200 comprises a buffer that receives a switching voltage signal at a voltage input node 206 and provides a buffered representation of the switching voltage signal at the DUT node 130. The resistance, inductance, and capacitance characteristics of the buffer create an output stage characteristic impedance, or driver output impedance 204, presented at the DUT node 130. In one example, the total driver output impedance 204 is a function of the driver's output resistor 210 and the characteristic incremental impedance, or AB stage output impedance 202. For example, the driver output impedance 204 can be represented by a series combination of the resistance of the output resistor 210 and an impedance that depends on the bias current of a transistor device coupled to the output of the driver.

[0025] The simplified output stage 200 includes a network of devices including push-pull output transistors qnA and qpA and reference pass transistors qp and qn. In the example of Fig. 2, a first current source ibiasp provides a current signal at the emitter of the reference pass transistor qp, and a second current source ibiasn provides a current signal at the emitter of the reference pass transistor qn. The reference pass transistors are coupled to a voltage input node 206 to receive a switching voltage signal to thereby control the current of the reference pass transistors.

[0026] The output transistors qnA and qpA comprise NPN and PNP devices (or arrays of such devices) respectively coupled in series between a voltage source VCC and a voltage reference VEE. The emitters of the output transistors qnA and qpA are coupled to an intermediate output node 208. In one example, the intermediate output node 208 is coupled to the DUT node 130 via an output resistor 210, Rpoly, which may comprise a fixed value polysilicon (or other) resistor. In this example, the driver output impedance 204 may be represented by a series combination of the AB stage output impedance 202, such as the intermediate output node 208, and the output resistor 210.

[0027] In one example, the impedance or resistance characteristics of the output resistor 210 can be controlled in various ways. For example, the output resistor 210 can be a laser trimmed thin film resistor device whose value is permanently set at the time of manufacture. However, the laser trimming process can be expensive or impractical in some manufacturing processes, and large resistors can add undesirable capacitance effects. In another example, the output resistor 210 can comprise an array of devices (e.g., MOSFET switches or other devices) with impedance characteristics that depend on the number of parallel devices that are enabled or disabled. This solution can have poor bandwidth or voltage characteristics, and relatively large temperature dependence. In yet another example, the output resistor 210 can comprise multiple parallel resistors, and the characteristic impedance of the parallel combination can be adjusted by switching various legs of the resistor network in and out of the DUT current signal path. This solution can be problematic at high switching frequencies due to parasitic capacitance effects associated with the switches in each resistor leg. In one example involving MOS-based switches, the DUT voltage range can be throttled to avoid damaging the MOS devices with voltages outside a predetermined safe operating area envelope. To ensure a stable output impedance characteristic (eg, 50 ohms) of the pin driver output stage, a different solution is required.

[0028] In one example, the voltage difference between the bases of the push-pull output transistors qnA and qpA establishes a bias current through the transistors. To accommodate a higher bandwidth or faster output signal at the DUT node 130, the first current source ibiasp and the second current source ibiasn can provide a larger current signal, resulting in the output transistors qnA and qpA being physically larger (or comprising a respective combination of smaller devices or arrays coupled in parallel). However, using a large bias current signal affects the AB stage output impedance 202 of the driver. In some examples, the effect of the bias current on the AB stage output impedance 202 can be large, causing a mismatch between the impedance of the DUT node 130 and the DUT and the transmission line coupled to the DUT node 130, resulting in poor performance and timing errors. In other words, if the impedance characteristics at the DUT node 130 and the DUT are not matched, signal deviations due to reflections can be introduced into the signal path, reducing timing accuracy and therefore reducing the performance of the test system.

[0029] In one example, the bias current can be controlled to correspondingly adjust or control the AB stage output impedance 202 of the class AB output stage, and therefore the driver output impedance 204. For example, during operation in the non-saturation region, the bipolar transistor incremental emitter impedance (herein, re) can be current and temperature dependent, e.g.,

number

[0030] 3 generally illustrates an example of a simplified output stage 200 having a bias current controller 302 and base resistors associated with the output transistors. The bias current controller 302 can be configured to vary the voltage difference between the bases of the push-pull output transistors qnA and qpA, thereby varying the magnitude of the bias current of the transistors. As explained above, the magnitude of the bias current affects the AB stage output impedance 202 or ABoutZ. In one example, the bias current controller 302 establishes the voltage difference in part by sourcing or sinking current through base resistors Rbasep and Rbasen, which are coupled to the output transistors qnA and qpA, respectively.

[0031] 3, the bias current controller 302 establishes a bias current Ie of 1 mA in the output transistors qnA and qpA. When the bias current is 1 mA, the emitter impedance in each of the output transistors is

number

[0032] 4 illustrates a first chart 400 generally showing the relationship between DUT current at DUT node 130 and AB stage output impedance 202 for a simplified output stage such as 200. The first chart 400 generally shows that as the absolute magnitude of the DUT current increases, the AB stage output impedance 202 decreases. When the current is high (sinking or sourcing) at DUT node 130, the AB stage output impedance 202 approaches zero. At intermediate DUT currents, the AB stage output impedance 202 is approximately 0 to 12.5 ohms.

[0033] In one example, when the bias current is increased to 2 mA, the emitter impedance of each of the output transistors

number

[0034] Thus, based on the relationship between the bias current of the output transistor and the AB stage output impedance 202, a feedback or control loop can be provided to establish the bias current to achieve the adjustable impedance characteristic of the pin driver. In one example, the bias current can be used to help mitigate the effect of or accommodate variations in the resistance value of the output resistor 210. For example, the output resistor 210 can comprise a thin film resistor with some resistance variation (e.g., ±1%, or ±5%, or ±10%, or other variation) due to manufacturing variations. The variation in the output resistor 210 can be accounted for by adjusting the bias current of the output transistor, thereby changing the AB stage output impedance 202 coupled to the output resistor 210.

[0035] For example, to ensure a 50 ohm load from the perspective of the DUT at DUT node 130, the pin driver may present a 50 ohm load that is the series combination of output resistor 210 and AB stage output impedance 202. If the resistance of output resistor 210 was, for example, about 44 ohms, the bias current provided to output transistors qnA and qpA could be set by bias current controller 302 to be about 2 mA, so that when the DUT current is zero, driver output impedance 204 is the series combination of the 6.25 ohm incremental impedance of the transistors and the resistance of the physical resistor of 44 ohms, i.e., about 50 ohms.

[0036] The inventors have recognized that the AB stage output impedance 202 of the push-pull output stage can be made substantially insensitive to the DUT current by providing emitter resistors in series with the output transistors qnA and qpA. Figure 5 generally illustrates an example of a portion of a simplified output stage 200 having emitter or degeneration resistors coupled to the emitter terminals of the output transistors qnA and qpA. In the example of Figure 5, the emitter resistors have the same resistive characteristic R 最適The term "optimum" may refer to the value of each of the emitter resistors, which is selected to be approximately the same as or equal to the output transistor incremental impedance when the magnitude of the current at the DUT node 130 is zero (i.e., when the DUT node 130 is not sourcing or sinking current to the DUT).

[0037] 6 generally illustrates an example of a second chart 600 showing the relationship between DUT current and AB stage output impedance 202 for a simplified output stage 200 such as that having the emitter resistor from the example of FIG. 5. In one example including a degeneration resistor having the "optimum" value described above, the second chart 600 generally illustrates that the AB stage output impedance 202 nominally increases as the DUT current increases from zero, but not as the R 最適 That is, when the current at the DUT node 130 is high (sinking or sourcing), the AB stage output impedance 202 stabilizes at or near R 最適 For example, in a fully rectified DUT current source 602 condition where all of the DUT current is sourced by NPN transistor qnA, the AB stage output impedance 202 approaches R 最適 Similarly, in a fully rectified DUT current sink 604 condition where all of the DUT current is sunk by the PNP transistor qpA, the AB stage output impedance 202 is R 最適 Thus, including a degeneration resistor in the emitter of the output transistor helps to stabilize the AB stage output impedance 202 over most of the DUT current operating range, and allows the AB stage output impedance 202 to be substantially independent of the DUT current.

[0038] In a specific example, assume that the incremental impedance of each of the output stage transistors is 25 ohms, resulting in an R 最適is 25 ohms. In this example, the series combination of the incremental impedance of the NPN transistor qnA and its degeneration resistor is 50 ohms, and the series combination of the incremental impedance of the PNP transistor qpA and its degeneration resistor is 50 ohms. The parallel combination of such impedances is therefore 25 ohms at the AB stage output impedance 202. When the driver sources a large DUT current, the PNP transistor qpA is effectively turned off and all of the DUT current flows through the NPN transistor qnA. In this case, the effective or incremental impedance of the transistor qnA is small. Similarly, when the driver receives or sinks a large DUT current, the NPN transistor qnA is effectively turned off and all of the DUT current flows through the PNP transistor qpA.

[0039] In one example, a high-speed feedback circuit can be provided to function with the feedback loop of the bias current controller. The high-speed feedback circuit can be configured to apply a user-configurable amount of output current to the base resistors Rbasep and Rbasen, thus effectively converting the base resistors into emitter degeneration resistors. The base resistors can remain physically coupled to the bases of the output transistors, and the high-speed feedback action makes them appear as if they are in series with the output stage resistors.

[0040] In one example, the bias current controller 302 is a low bandwidth control circuit loop that provides a user-specified amount of bias current to the output transistor to compensate for uncertainties or variations in the resistance of the output resistor 210. The high bandwidth control loop provides a feedback signal that applies a user-specified amount of feedback current to the base resistor of the output transistor, such as to "transform" the base resistor into an emitter degeneration resistor having an optimal resistance value, as described above, thereby effectively changing the emitter degeneration behavior of the output transistor to change the AB stage output impedance 202. In other words, changing the emitter degeneration behavior of the output stage establishes an optimal condition that makes the driver output impedance substantially independent of the DUT current.

[0041] FIG. 7 generally illustrates a first example of a pin driver output stage having a bias current controller and a feedback controller. The example of FIG. 7 includes a first compensation output stage 700 that can include a bias current controller 302 and a feedback controller 706. The bias current controller 302 can be configured to control a differential voltage across the bases of the output transistors qnA and qpA to establish a controlled bias current through the output transistors. The feedback controller 706 can be configured to control the feedback current signals applied to the base resistors Rbasep and Rbasen, respectively. The bias current controller 302 and the feedback controller 706 help establish the AB stage output impedance 202 of the first compensation output stage 700 to ensure that the driver output impedance 204 is optimally scaled to maximize signal fidelity.

[0042] In one example, the bias current controller 302 is configured to receive a tuning parameter, such as a first control signal at a first control input 702. The first control signal may include, for example, an analog or digital control signal that defines a magnitude of a differential voltage to apply at the base of the output transistor, and thus a magnitude of the bias current of the transistor. In one example, the first control signal is set or provided by a user, or is automatically updated by other aspects of the test system, including the first compensated output stage 700. In one example, the bias current controller 302 comprises a scaled-down replica circuit that represents or corresponds to the output stage circuit.

[0043] In one example, the feedback controller 706 is configured to receive another tuning parameter, such as a second control signal at the second control input 704. The second control signal can include, for example, an analog or digital control signal that defines the magnitude of the current signal to apply at the base of the output transistor, and thus the magnitude of the voltage established at the base resistors Rbasep and Rbasen. In one example, the second control signal is set or provided by a user, or is automatically updated by other aspects of the test system including the first compensation output stage 700. In one example, using the feedback controller 706 to apply a current signal at the base resistor is electrically similar to providing a degeneration or emitter resistor at the emitter of the output transistors qnA and qpA. In some examples, the feedback controller 706 can be used to apply a current signal at the base resistor, and can also provide a degeneration or emitter resistor.

[0044] In one example, the optimum state of the output stage occurs when the current signals applied to the first and second base resistors are provided by the feedback controller 706 to create a voltage at the DUT node 130 that is substantially equal to the voltage created by the DUT current, thereby producing a driver output impedance 204 that is substantially independent of the DUT current. In this example, the DUT current may be a bidirectional current signal applied to the AB stage output impedance 202 or the effective impedance of the push-pull output transistors of the output stage.

[0045] In one example, when the first control signal on the first control input 702 indicates a minimum bias current for the output transistors qnA and qpA of the first compensation output stage 700, the second control signal on the second control input 704 may indicate a minimum feedback current, thereby maintaining or optimizing the AB stage output impedance 202 for a particular DUT current. In some examples, the first control signal may be a function of the second control signal, or the second control signal may be a function of the first control signal.

[0046] 8 illustrates a second example of a pin driver output stage 800 that may generally comprise a portion of the first driver AB 102 or the first exemplary test system 100. The output stage 800 may generally correspond to the simplified output stage 200 or the first compensation output stage 700 from the examples of FIG. 2 and FIG. 7, respectively. For example, the output stage 800 may include an intermediate output node 802 that is coupled to the DUT node 130 using the output resistor 210. The output stage 800 presents an adjustable output impedance at the intermediate output node 802. For example, the output impedance of the output stage 800 may vary based on the magnitude of the DUT current at the DUT node 130.

[0047] 8 includes an input node 804 configured to receive a switching voltage signal. The switching voltage signal is buffered or amplified by the output stage 800 and provided to the DUT node 130 using a push-pull output stage circuit 806 that includes an intermediate output node 802.

[0048] The push-pull output stage circuit 806 comprises a first output transistor 808 (e.g., an NPN transistor) and a second output transistor 810 (e.g., a PNP transistor). The first output transistor 808 and the second output transistor 810 may optionally comprise respective arrays of similarly configured transistors. In one example, a first degeneration resistor 812 is coupled to the emitter of the first output transistor 808, and a second degeneration resistor 814 is coupled to the emitter of the second output transistor 810. The first degeneration resistor 812 and the second degeneration resistor 814 may be coupled at an intermediate output node 802. The intermediate output node 802 may be coupled to the DUT at a DUT node 130 via an output resistor 210. In one example, the first output transistor 808 corresponds to an output transistor array qnA and the second output transistor 810 corresponds to an output transistor array qpA from the various output stage examples of the pin driver described above.

[0049] The output stage 800 further includes an example of a bias current controller 302 coupled, such as between the bases of the first output transistor 808 and the second output transistor 810. The bias current controller 302 establishes a differential voltage between the bases of the output transistors, thereby controlling the magnitude of a bias current that flows through the push-pull output stage circuit 806 and correspondingly changes the impedance characteristics of the push-pull output stage circuit 806. That is, the bias current affects the incremental impedance of the first output transistor 808 and the second output transistor 810, which in turn affects the output impedance of the output stage 800, such as at the intermediate output node 208 or the DUT node 130.

[0050] In one example, the bias current controller 302 comprises a scaled copy of all or a portion of the circuitry comprising the output stage 800. For example, the bias current controller 302 may comprise a ⅛ scaled copy of the output stage 800 circuitry. The bias current controller 302 comprises a first control input 702 configured to receive a control signal for a current generator 816. The current generator 816 may comprise a current source (e.g., comprising a PTAT current generator) that provides a current signal within a specified range of current signal magnitude, such as, for example, ⅛ to ¼ mA (e.g., corresponding to ⅛ of an expected 1 to 2 mA swing of the bias current of the push-pull output stage circuitry 806, such as when the bias current controller 302 comprises a ⅛ copy of the output stage circuitry). Thus, a higher current main stage bias current can be applied in the push-pull output stage circuitry 806 using the controlled current provided by the smaller low power bias current controller 302.

[0051] The output stage 800 further includes an example of a feedback controller 706 that can be configured to deliver a feedback current signal to the base resistors of the first output transistor 808 and the second output transistor 810. In one example, the feedback controller 706 includes a current-selectable DAC to monitor and respond to the current of the push-pull output stage circuit 806 by controlling a folded cascode amplifier to provide a feedback current signal to the base resistors. Using a folded cascode configuration helps ensure a high output impedance, high gain, and high bandwidth of the feedback controller 706, thereby allowing the base resistors Rbasep and Rbasen to be small or low resistance (e.g., 100 ohms). Thus, the feedback loop implemented by the feedback controller 706 can be fast and responsive to changes in the DUT current at the DUT node 130. The transistor network, represented by the multiple "y" devices, includes respective buffers configured to accommodate the fast feedback loop current and maintain one side of each of the base resistors Rbasep and Rbasen at a constant voltage.

[0052] 8 shows one instance of the feedback controller 706 comprising an arrangement of NPN devices coupled to a current source side of a push-pull output stage circuit 806. A similar instance of the feedback controller 706 comprising an arrangement of PNP devices can be coupled to a current sink side of the push-pull output stage circuit 806.

[0053] During operation, an optimal state of the output stage 800 can be achieved whereby the output impedance (e.g., at the DUT node 130) is substantially independent of the DUT current at the DUT node 130, including for sinking or sourcing various amounts of DUT current. Each first voltage can be generated by a feedback current signal from the feedback controller 706 applied to each base resistor. A second voltage can be generated by the DUT current applied to an incremental impedance of a transistor of the push-pull output stage circuit 806, where the incremental impedance can be a function of the bias current applied by the bias current controller 302. The optimal state can occur when the first and second voltages are substantially equal.

[0054] Various modifications can be made to the output stage 800 to adjust the amount of trim range of the output impedance of the push-pull output stage circuit 806 or to adjust the bandwidth of the output stage 800. For example, a wider trim range can be achieved by increasing the resistance values ​​of the base resistors Rbasep and Rbasen. However, such an increase in resistance can reduce the overall bandwidth of the output stage 800 and can reduce the bandwidth or speed of the feedback controller 706, which can result in sluggishness or errors in some operating conditions.

[0055] In one example, a wider trim range can be achieved by increasing the gain of the feedback controller 706 or the magnitude of the feedback control signal. However, increasing the gain may disturb the upstream driver circuit (i.e., preceding the base resistor Rbase in the signal chain), may require a physically larger device in the feedback controller 706, and may consume more power. In one example, a wider trim range can be achieved by reducing the minimum value of the bias current of the output transistor, but this leads to bandwidth limitations at low bias currents.

[0056] In one example, the overall bandwidth of output stage 800 can be increased by reducing the resistive characteristics of base resistors Rbasep and Rbasen and reducing the gain of feedback controller 706. However, such changes may affect the stability of the output impedance characteristics of push-pull output stage circuit 806. As can be seen, optimizing output stage 800 depends on balancing these and other competing considerations.

[0057] 9 illustrates an example of a method 900 that generally includes using a bias current controller and a feedback controller in an output stage of a pin driver circuit. In one example, the method 900 includes or uses the bias current controller 302 and the feedback controller 706 to change the output impedance characteristics of the output stage of the pin driver circuit to ensure that the pin driver circuit presents an impedance stable load (e.g., 50 ohms) at the DUT interface.

[0058] At operation 902, the method 900 can include receiving a first control signal input at a bias current controller, such as bias current controller 302. The first control signal input can include an analog or digital control signal provided by a user or other control system and configured to update or adjust a magnitude of an output impedance characteristic of an output stage of the pin driver circuit. The magnitude of the output impedance corresponds to an impedance of or coupled to an output node of the pin driver, e.g., an emitter terminal of a transistor of the output stage.

[0059] In operation 904, in response to receiving a first control signal input, the bias current controller 302 can be configured to provide a bias current to a transistor of an output stage of the pin driver circuit, the magnitude of the bias current corresponding to a value of the first control signal input. For example, in operation 904, the bias current controller 302 can control a differential voltage applied across the transistors of the class AB push-pull output stage to thereby vary the magnitude of the bias current of the transistors. In one example, operation 904 includes using a scaled replica of the output stage to generate a voltage signal that causes a bias current to flow through the output transistors of the output stage.

[0060] At operation 906, the method 900 may include receiving a second control signal input at a feedback controller, such as feedback controller 706. The second control signal input may include an analog or digital control signal provided by a user or other control system and configured to update or adjust a magnitude of an impedance characteristic of an output stage of the pin driver circuit. At operation 908, in response to receiving the second control signal input, the feedback controller 706 may be configured to provide a feedback current signal at a base terminal of each of the transistors of the output stage of the pin driver circuit. In one example, the feedback current signal is applied to a respective base resistor coupled to the base terminal of the transistor in the push-pull output stage. In one example, the magnitude of the feedback current signal corresponds to a value of the second control signal input.

[0061] In one example, the method 900 can include sensing the DUT current signal at operation 910. Operation 910 can include sensing a direction or magnitude of the DUT current signal. If the direction or magnitude of the DUT current signal changes, at operation 912, the output stage 800 can include updating or changing at least one of the first control signal input or the second control signal input to maintain a specified output impedance characteristic of the pin driver (e.g., 50 ohms).

[0062] Various aspects of the present disclosure can help provide solutions to problems associated with test systems identified herein, as described in the following examples. Example 1 can include a pin driver circuit comprising a push-pull output stage circuit including an output transistor configured to accommodate a bidirectional current signal at an output node, a bias current controller configured to adjust a bias current provided to the output transistor of the output stage circuit and accordingly adjust an impedance characteristic of the output stage circuit at the output node, first and second resistors coupled to respective base terminals of the output transistors, and a feedback circuit configured to selectively provide a feedback current signal to the first and second resistors to adjust an impedance characteristic of the output stage circuit at the output node.

[0063] In Example 2, the subject matter of Example 1 includes the impedance characteristic of the output stage circuit at the output node being substantially independent of the magnitude of the bidirectional current signal at the output node.

[0064] In Example 3, the subject matter of Example 2 includes the feedback current signal being applied to first and second resistors to provide a first voltage; the bidirectional current signal applying a second voltage across an incremental impedance of the output transistor; and when the first and second voltages have the same magnitude, an impedance characteristic of the output stage circuit at the output node is substantially independent of the magnitude of the bidirectional current signal at the output node.

[0065] In example 4, the subject matter of examples 1-3 includes where the magnitude of the feedback current signal is less than the magnitude of the current signal at the output node.

[0066] In example 5, the subject matter of examples 1-4 includes where the magnitude of the feedback current signal is a function of the magnitude of the current signal at the output node and an output impedance tuning parameter.

[0067] In example 6, the subject matter of examples 1-5 includes a data input configured to receive an output impedance tuning parameter indicative of a magnitude of the bias current and a magnitude of the feedback current signal.

[0068] In example seven, the subject matter of examples one through six includes where the bias current controller is configured to vary the magnitude of the bias current in coordination with a change in the magnitude of the feedback current signal.

[0069] In Example 8, the subject matter of Examples 1-7 includes where the bias current controller comprises a scaled-down replica circuit of the push-pull output stage circuit.

[0070] In Example 9, the subject matter of Examples 1-8 includes the feedback circuit comprising a first folded cascode amplifier circuit providing a first feedback current signal to the first resistor, and a second folded cascode amplifier circuit providing a second feedback current signal to the second resistor.

[0071] In example 10, the subject matter of examples 1-9 includes a fixed value polysilicon resistor coupled between an output node of the output stage circuit and a device under test (DUT) node.

[0072] In example 11, the subject matter of example 10 includes a degeneration resistor coupled between the emitter terminal of the output transistor and the output node.

[0073] Example 12 is a system comprising: a comparator circuit coupled to a device under test (DUT) node; an active load coupled to the DUT node; and an output stage circuit coupled to the DUT node, the output stage circuit configured to provide a specified impedance characteristic at the DUT node that is substantially invariant over a specified range of DUT currents, the output stage circuit comprising a class AB driver circuit; a bias current controller configured to provide a bias current for an output transistor of the driver circuit based on a first control input; and a feedback controller configured to provide a feedback current at each base terminal of the output transistor of the driver circuit based on a second control input.

[0074] In Example 13, the subject matter of Example 12 includes when the first control input indicates a minimum bias current for an output transistor of the driver circuit, the second control input indicates a maximum feedback current, thereby maintaining a specified impedance characteristic of the output stage.

[0075] In Example 14, the subject matter of Examples 12-13 includes when the first control input indicates a maximum bias current for an output transistor of the driver circuit, the second control input indicates a minimum feedback current or zero feedback current, thereby maintaining a specified impedance characteristic of the output stage.

[0076] In Example 15, the subject matter of Examples 12-14 includes the first control input being a function of the second control input, or the second control input being a function of the first control input.

[0077] In Example 16, the subject matter of Examples 12-15 includes the output stage circuit comprising an output resistor coupled between the DUT node and an output node of the output transistor.

[0078] In Example 17, the subject matter of Example 16 includes the class AB driver circuit comprising a push-pull output stage comprising output transistors, the output transistors comprising a first array of NPN transistors coupled to a second array of PNP transistors at an output node.

[0079] In Example 18, the subject matter of Examples 16-17 includes the class AB driver circuit comprising a push-pull output stage comprising output transistors, the output transistors comprising a first transistor coupled to the output node via a first degeneration resistor and a second transistor coupled to the output node via a second degeneration resistor.

[0080] In example 19, the subject matter of examples 16-18 includes base resistors respectively coupled to base terminals of the output transistors, the base resistors configured to receive a feedback current from the feedback controller.

[0081] In Example 20, the subject matter of Examples 12-19 includes where the bias current controller comprises a scaled down replica of the Class AB driver circuit.

[0082] In Example 21, the subject matter of Examples 12-20 includes a user interface configured to receive a first control input and a second control input from a user.

[0083] In Example 22, the subject matter of Examples 12-21 includes an output stage configured to provide a characteristic impedance of 50 ohms at the DUT node.

[0084] Example 23 is a method for adjusting a characteristic output impedance of an output stage of a pin driver circuit, the method including: receiving a first control signal input at a bias current controller and, in response, providing bias currents to transistors of the output stage of the pin driver circuit, where a magnitude of the bias current corresponds to a value of the first control signal input; and receiving a second control signal input at a feedback controller and, in response, providing feedback currents at respective base terminals of the transistors of the output stage of the pin driver circuit, where a magnitude of the feedback current corresponds to a value of the second control signal input, wherein the characteristic output impedance corresponds to an impedance at an output node coupled to an emitter terminal of the transistor of the output stage.

[0085] In Example 24, the subject matter of Example 23 includes where providing bias current to transistors in an output stage of the pin driver circuit includes providing bias current to transistors in a class AB push-pull output stage.

[0086] In Example 25, the subject matter of Examples 23-24 includes where providing a feedback current at a base terminal of each of the transistors includes providing the feedback current to a resistor coupled to the base terminal of each of the transistors.

[0087] In Example 26, the subject matter of Examples 23-25 ​​includes providing the bias current using a current source that comprises a scaled replica of the output stage.

[0088] In example 27, the subject matter of examples 23-26 includes receiving information regarding a magnitude of an output current signal at an output node and responsively varying at least one of a value of the first control signal input or a value of the second control signal input so as to maintain a characteristic output impedance.

[0089] Example 28 is at least one machine-readable medium comprising instructions that, when executed by a processing circuit, cause the processing circuit to perform operations implementing any of Examples 1 to 27.

[0090] Example 29 is an apparatus including means for implementing any one of Examples 1 to 27.

[0091] The 30th embodiment is a system for implementing any one of the 1st to 27th embodiments.

[0092] Each of these non-limiting examples may stand on its own or may be combined in various permutations or combinations with one or more of the other examples or features discussed elsewhere herein.

[0093] This detailed description includes references to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only the elements shown or described are provided. The inventors contemplate examples using any combination or permutation of the elements shown or described (or one or more aspects of the elements) with respect to a particular example (or one or more aspects of that example), or with respect to other examples (or one or more aspects of that example) shown or described herein.

[0094] In this document, the terms "a" or "an" are used to include one or more, as is common in patent documents, used independently of any other instance or usage, such as "at least one" or "one or more." In this document, the term "or" is used to refer to non-exclusive, i.e., "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In this document, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein."

[0095] In the claims that follow, the terms "comprise" and "comprising" are open-ended, i.e., systems, devices, articles, compositions, formulations, or processes that include elements in addition to the elements listed after such terms in a claim are still considered to be within the scope of that claim. Moreover, in the claims that follow, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to constrain numerical requirements to their objects.

[0096] The method examples described herein may be at least partially implemented in a machine or computer. Some embodiments may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform the method or circuit operation or circuit configuration instructions as described in the above embodiments. Such method implementations may include code such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Further, in one example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0097] The above description is intended to be illustrative and not limiting. For example, the above-described examples (or one or more aspects of the examples) may be used in combination with each other. Other embodiments may be used by one of ordinary skill in the art, such as by studying the above description. The Abstract is provided to enable the reader to quickly grasp the nature of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be construed as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may reside in all features of a particular disclosed embodiment. Accordingly, it is contemplated that the following claims are incorporated into the Detailed Description of the invention as an example or embodiment, with each claim standing on its own as a separate embodiment, and that such embodiments can be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims, along with the full scope to which such claims are entitled.

Claims

1. 1. A pin driver circuit comprising: a push-pull output stage circuit including an output transistor configured to accommodate a bidirectional current signal at an output node; a bias current controller configured to adjust a bias current provided to the output transistor of the output stage circuit to accordingly adjust an impedance characteristic of the output stage circuit at the output node; first and second resistors coupled to respective base terminals of the output transistors; a feedback circuit configured to selectively provide a feedback current signal to the first and second resistors to adjust the impedance characteristic of the output stage circuit at the output node.

2. 2. The pin driver circuit of claim 1, wherein the impedance characteristic of the output stage circuit at the output node is substantially independent of the magnitude of the bidirectional current signal at the output node.

3. the feedback current signal is applied to the first and second resistors to provide a first voltage; the bidirectional current signal impresses a second voltage across an incremental impedance of the output transistor; 3. The pin driver circuit of claim 2, wherein the impedance characteristic of the output stage circuit at the output node is substantially independent of the magnitude of the bidirectional current signal at the output node when the first and second voltages have the same magnitude.

4. 2. The pin driver circuit of claim 1, wherein the magnitude of the feedback current signal is a function of the magnitude of the current signal at the output node and an output impedance tuning parameter.

5. 2. The pin driver circuit of claim 1, comprising a data input configured to receive an output impedance tuning parameter indicative of a magnitude of the bias current and the magnitude of the feedback current signal.

6. 2. The pin driver circuit of claim 1, wherein the bias current controller is configured to vary the magnitude of the bias current in coordination with changes in the magnitude of the feedback current signal.

7. 2. The pin driver circuit of claim 1, wherein the bias current controller comprises a scaled-down replica of the push-pull output stage circuit.

8. 2. The pin driver circuit of claim 1, wherein the feedback circuit comprises: a first folded cascode amplifier circuit providing a first feedback current signal to the first resistor; and a second folded cascode amplifier circuit providing a second feedback current signal to the second resistor.

9. a fixed value polysilicon resistor coupled between the output node of the output stage circuit and a device under test (DUT) node; 2. The pin driver circuit of claim 1, further comprising: a degeneration resistor coupled between the emitter terminal of the output transistor and the output node.

10. 1. A system comprising: a comparator circuit coupled to a device under test (DUT) node; an active load coupled to the DUT node; an output stage circuit coupled to the DUT node, the output stage circuit configured to provide a specified impedance characteristic at the DUT node that is substantially invariant over a specified range of DUT currents, the output stage circuit comprising: A class AB driver circuit; a bias current controller configured to provide a bias current for an output transistor of the driver circuit based on a first control input; a feedback controller configured to provide a feedback current at a base terminal of each of the output transistors of the driver circuit based on a second control input.

11. 11. The system of claim 10, wherein when the first control input indicates a minimum bias current for the output transistor of the driver circuit, the second control input indicates a maximum feedback current, thereby maintaining the specified impedance characteristic of the output stage.

12. 11. The system of claim 10, wherein when the first control input indicates a maximum bias current for the output transistor of the driver circuit, the second control input indicates a minimum or zero feedback current, thereby maintaining the specified impedance characteristic of the output stage.

13. 11. The system of claim 10, wherein the output stage circuit comprises an output resistor coupled between the DUT node and an output node of the output transistor, and the Class AB driver circuit comprises a push-pull output stage comprising the output transistor, the output transistor comprising a first array of NPN transistors coupled to a second array of PNP transistors at the output node.

14. 11. The system of claim 10, wherein the output stage circuit comprises an output resistor coupled between the DUT node and an output node of the output transistor, and the Class AB driver circuit comprises a push-pull output stage comprising the output transistor, the output transistor comprising a first transistor coupled to the output node through a first degeneration resistor and a second transistor coupled to the output node through a second degeneration resistor.

15. 11. The system of claim 10, further comprising: base resistors respectively coupled to base terminals of the output transistors, the base resistors configured to receive the feedback current from the feedback controller, and the output stage circuitry comprising an output resistor coupled between the DUT node and an output node of the output transistor.

16. 1. A method for adjusting a characteristic output impedance of an output stage of a pin driver circuit, the method comprising: receiving a first control signal input at a bias current controller and, in response, providing a bias current to a transistor of the output stage of the pin driver circuit, the magnitude of the bias current corresponding to a value of the first control signal input; receiving a second control signal input at a feedback controller and, in response, providing a feedback current at a base terminal of each of the transistors in the output stage of the pin driver circuit, the magnitude of the feedback current corresponding to a value of the second control signal input; The method, wherein the characteristic output impedance corresponds to an impedance at an output node coupled to an emitter terminal of the transistor of the output stage.

17. 17. The method of claim 16, wherein providing the bias current to transistors of the output stage of the pin driver circuit comprises providing bias current to transistors of a class AB push-pull output stage.

18. 17. The method of claim 16, wherein providing the feedback current at the respective base terminals of the transistors comprises providing the feedback current to a resistor coupled to the respective base terminals of the transistors.

19. 17. The method of claim 16, wherein providing the bias current comprises using a current source that comprises a scaled replica of the output stage.

20. 17. The method of claim 16, comprising receiving information regarding a magnitude of an output current signal at the output node and responsively varying at least one of the value of the first control signal input or the value of the second control signal input so as to maintain the characteristic output impedance.

Images