Display device

Abstract

To enable more easily designing a circuit for controlling a pixel circuit.SOLUTION: A display region includes: a plurality of pixel circuits; a plurality of first control lines, a plurality of second control lines, a plurality of signal lines, and a plurality of power lines connected with the plurality of pixel circuits. Each pixel circuit of the plurality of pixel circuits includes: a light-emitting element; a plurality of switch transistors having a first conductive type; a light emission control transistor having a second conductive type; a driving transistor having the second conductive type; and a storage capacitor connected with the driving transistor. The plurality of first control lines transmits a first control signal from a driving circuit to the switch transistors having the first conductive type. The plurality of second control lines transmits a second control signal from the driving circuit to the light emission control transistors having the second conductive type. The driving circuit includes a plurality of transistors, a plurality of capacitors, and a plurality of connection wirings. All transistors included in the driving circuit are transistors of the first conductive type.SELECTED DRAWING: Figure 19

Description

[Technical field]

[0001] The present disclosure relates to a display device. [Background technology]

[0002] OLED (Organic Light-Emitting Diode) elements are current-driven self-luminous elements that do not require a backlight, and have the advantages of low power consumption, a wide viewing angle, and a high contrast ratio, making them promising for the development of flat panel displays.

[0003] An active matrix (AM) type OLED display device includes transistors for selecting pixels and driving transistors for supplying current to the pixels. The transistors in an OLED display device are TFTs (Thin Film Transistors), and generally, LTPS (Low Temperature Poly-silicon) TFTs are used.

[0004] TFTs have variations in threshold voltage and charge mobility. Since the drive transistor determines the light emission intensity of an OLED display, variations in these electrical characteristics are problematic. Therefore, the pixel circuit of a typical OLED display is equipped with a compensation circuit to compensate for the variations and fluctuations in the threshold voltage of the drive transistor.

[0005] For example, in OLED displays, afterimages can occur, a phenomenon called image retention. For example, if you try to display a grayscale across the entire screen after displaying a black and white checkerboard pattern for a certain period of time, an afterimage that mimics a checkerboard pattern with a different grayscale will be displayed for a while.

[0006] This is due to the history effect of the drive transistor, which is a phenomenon in which the drain current differs when the gate-source voltage in a field-effect transistor changes from a high voltage to a low voltage and when the voltage changes from a low voltage to a high voltage.

[0007] In other words, the drain current when switching from black to a middle gray level is different from the drain current when switching from white to a middle gray level, which causes a difference in the light emission intensity of the OLED display device. Furthermore, this difference in drain current continues for several frames or more, which is perceived as an afterimage. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] US Patent Application Publication No. 2005 / 0264493 [Patent Document 2] US Patent Application Publication No. 2007 / 0040786 [Patent Document 3] US Patent Application Publication No. 2016 / 0372046 Summary of the Invention [Problem to be solved by the invention]

[0009] A technique is desired that makes it easier to design a circuit that outputs a control signal for controlling a pixel circuit. [Means for solving the problem]

[0010] A display device according to an embodiment of the present disclosure includes a display area and a drive circuit for the display area disposed outside the display area. The display area includes a plurality of pixel circuits, and a plurality of first control lines, a plurality of second control lines, a plurality of signal lines, and a plurality of power supply lines connected to the plurality of pixel circuits. Each pixel circuit of the plurality of pixel circuits includes a light-emitting element, a plurality of switch transistors having a first conductivity type, a light-emitting control transistor having a second conductivity type and controlling ON / OFF of light emission of the light-emitting element, a drive transistor having the second conductivity type and controlling the amount of current to the light-emitting element, and a storage capacitor connected to the drive transistor. The plurality of first control lines each transmit a first control signal from the drive circuit to the switch transistor having the first conductivity type. The plurality of second control lines each transmit a second control signal from the drive circuit to the light-emitting control transistor having the second conductivity type. The drive circuit includes a plurality of transistors, a plurality of capacitors, and a connection wiring. All the transistors included in the drive circuit are transistors of the first conductivity type. Effect of the Invention

[0011] According to one aspect of the present disclosure, a circuit that outputs a control signal for a pixel circuit can be designed more easily. [Brief description of the drawings]

[0012] [Figure 1] 1A and 1B are schematic diagrams illustrating an example of the configuration of a TFT (Thin Film Transistor) substrate of an OLED display device and a control circuit mounted on the TFT substrate. [Diagram 2] 1 illustrates an example of the configuration of a pixel circuit according to an embodiment of the present specification. [Diagram 3] 3 shows an example of a timing chart of signals that control the pixel circuit shown in FIG. [Figure 4] 13A and 13B are schematic diagrams illustrating the relationship between threshold compensation periods and data writing periods in four consecutive pixel circuit rows. [Diagram 5] 2 shows an example of the configuration of a latch circuit included in a latch circuit group. [Figure 6]2 shows a truth table of the latch circuit. [Figure 7] 2 shows an example of a circuit configuration of a latch circuit. [Figure 8] 1A and 1B are schematic diagrams illustrating an example of the configuration of a shift register circuit and a latch circuit group and an example of a wiring layout. [Figure 9] 4 shows input and output signals to and from the Nth stage latch circuit included in the latch circuit group. [Figure 10A] 2A and 2B are schematic diagrams showing an example of the configuration of a shift register circuit and a latch circuit group and an example of the layout of wiring for generating a light emission control signal Em. [Figure 10B] 10B is a timing chart of an output signal Em of the latch circuit group of FIG. 10A. [Figure 11] 1 shows a configuration example in which a signal line for transmitting a selection signal S1 from the latch circuit is connected to a power supply potential VOFF. [Figure 12] 12 shows a timing chart of control signals in the circuit shown in FIG. [Figure 13] Another configuration example in which the power supply potential VOFF is applied to the potential of the S1 signal line is shown. [Figure 14] 14 shows a timing chart of control signals in the configuration example shown in FIG. 13. [Figure 15] 4 shows another example of the configuration of the pixel circuit. [Figure 16] 16 shows a timing chart of signals that control the pixel circuit shown in FIG. 15 during one frame period. [Figure 17] 2 shows an example of the configuration of a latch circuit used in the latch circuit group. [Figure 18] 4 shows a timing chart of input and output signals of a latch circuit. [Figure 19] 13 shows a schematic diagram of an example of a circuit configuration in which control signals S1, S2, and Em are generated and output by a combination of a shift register circuit and a latch circuit group. [Figure 20] FIG. 2 is a plan view illustrating a schematic layout example of a latch circuit. [Figure 21] 21 is a schematic diagram showing a cross-sectional structure taken along line XXI-XXI in FIG. 20. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment will be described with reference to the drawings. The same reference symbols are used for common configurations in each drawing. In order to make the description easier to understand, the dimensions and shapes of the objects shown in the drawings may be exaggerated.

[0014] Hereinafter, a configuration of a circuit that generates and outputs a control signal for a pixel circuit in an emissive display device that uses a light-emitting element that emits light by a driving current, such as an OLED (Organic Light-Emitting Diode) display device, is disclosed. A display device according to an embodiment of this specification generates and outputs a control signal for controlling a pixel circuit by a combination of a shift register circuit and multiple latch circuits. By combining the shift register circuit and multiple latch circuits, a circuit that outputs a signal pulse having a desired pulse width can be easily designed.

[0015] For example, image retention can be reduced by lengthening the time for threshold voltage compensation of the driving TFT. A longer threshold voltage compensation period is possible by performing data writing and threshold voltage compensation in different periods. A combination of a shift register circuit and multiple latch circuits makes it easy to generate control signals for the data writing period and the threshold voltage compensation period.

[0016] The shift register circuit includes a plurality of linked shift register units. For example, each shift register unit outputs a control signal for a data writing period to a corresponding pixel circuit row. Each latch circuit receives control signals from two different shift register units and outputs a control signal for a threshold voltage compensation period to a corresponding pixel circuit row. In this configuration, a shift register circuit for the control signal for the threshold voltage compensation period is not required, and the circuit area can be reduced.

[0017] In another example, a combination of a shift register circuit and multiple latch circuits can generate and output a light emission control signal that controls ON / OFF of light emission of a light emitting element. Each latch circuit receives signals from two different shift register units and outputs a light emission control signal to a corresponding pixel circuit row. This configuration makes it easy to design a driver circuit that generates the light emission control signal.

[0018] The combination of the shift register circuit and the multiple latch circuits may generate and output a data write signal in addition to the light emission control signal. Each shift register unit outputs a control signal for a data write period to a corresponding row of pixel circuits. Each latch circuit receives the data write control signals from two different shift register units and outputs a light emission control signal to a corresponding row of pixel circuits.

[0019] [Display device configuration] The embodiments of the present specification will be described in more detail below. Fig. 1 shows a schematic diagram of a configuration example of a TFT (Thin Film Transistor) substrate of an OLED display device and a control circuit mounted on the TFT substrate. In Fig. 1, only one of a plurality of similar elements is indicated by a reference symbol. The OLED display device 1 includes a TFT substrate 10 on which OLED elements and pixel circuits are formed, and a thin film encapsulation structure (TFE: Thin Film Encapsulation) that encapsulates an organic light-emitting element (not shown).

[0020] The thin film sealing structure is one of the sealing structures, and as another example, the sealing structure may include a sealing substrate that seals the organic light-emitting element and a joint (glass frit seal portion) that joins the TFT substrate and the sealing substrate. Dry nitrogen, for example, is filled between the TFT substrate and the sealing substrate.

[0021] The TFT substrate 10 includes an insulating substrate, on which a display area 101 for displaying an image is formed. A first shift register (SR) circuit 111, a latch circuit group 113, a second shift register circuit 115, and a driver IC 117 are arranged outside the display area 101. In Fig. 1, the shift register circuit 111 is arranged on the left side of the display area 101, and the shift register circuit 115 is arranged on the right side of the display area 101, and they face each other. In the area between the shift register circuit 111 and the latch circuit group 113, wiring 112 is formed to connect them.

[0022] The driver IC 117 is connected to an external device via a flexible printed circuit (FPC) (not shown). A connection terminal of the FPC is interconnected with a connection terminal 139 on the TFT substrate 10.

[0023] The first shift register circuit 111 drives an S2 signal line 132 on the TFT substrate 10. The S2 signal line 132 extends from the shift register circuit 111 along the X-axis and is arranged along the Y-axis. In FIG. 1, the S2 signal line 132 is represented by a dotted line. The shift register circuit 111 sequentially outputs pulses of a control signal S2, which will be described later, to the S2 signal line 132. The latch circuit group 113 drives an S1 signal line 131 on the TFT substrate 10. The S1 signal line 131 extends from the latch circuit group 113 along the X-axis and is arranged along the Y-axis. The latch circuit group 113 sequentially outputs pulses of a control signal S1, which will be described later, to the S1 signal line 131.

[0024] The second shift register circuit 115 drives the emission signal lines (Em signal lines) 133 to control the light emission period of each pixel. The Em signal lines 133 extend from the shift register circuit 115 along the X-axis and are arranged along the Y-axis. The shift register circuit 115 sequentially outputs pulses of an Em signal (light emission control signal) to be described later to the Em signal lines 133.

[0025] The driver IC 117 is implemented using, for example, an anisotropic conductive film (ACF). The driver IC 117 provides power and timing signals (control signals) to the shift register circuits 111 and 115. The driver IC 117 outputs data signals that define the luminance of pixels to the data lines 137. In the configuration example of FIG. 1, the data lines 137 extend along the Y axis and are arranged along the X axis. The driver IC 117 provides each data line 137 with a data signal that defines the luminance of a selected OLED element.

[0026] The display area 101 includes a plurality of pixel circuits 107 that control the emission of the OLED elements of the respective pixels. In the configuration example of FIG. 1, the pixel circuits are arranged in a matrix. The layout of the pixel circuits is not particularly limited. In a color OLED display device, each OLED element emits light of any one of the colors, for example, red, blue, or green. The plurality of pixel circuits constitute a pixel circuit array.

[0027] A pixel circuit row consisting of a plurality of pixel circuits is connected to an S1 signal line 131, an S2 signal line 132, and an Em signal line 133. The S1 signal line 131, the S2 signal line 132, and the Em signal line 133 transmit a control signal S1, a control signal S2, and a control signal Em to the corresponding pixel circuit row, respectively. Each data line 137 is connected to one pixel circuit column, and each pixel circuit column is connected to one pixel circuit in each pixel circuit row. The data line 137 transmits a data signal specifying the emission brightness to the pixel circuits of the selected pixel circuit row.

[0028] An anode power line 141 and a reset power line 142 are disposed on the TFT substrate 10. The anode power line 141 transmits a power supply potential to be applied to the anode of the OLED element. In Fig. 1, the anode power line 141 is indicated by a dashed line, and its pattern includes lines extending along the X-axis and a plurality of lines connected to the lines, extending along the Y-axis, and arranged along the X-axis.

[0029] The reset power line 142 transmits a power supply potential for resetting the potential of a predetermined node of the pixel circuit. In Fig. 1, the reset power line 142 is shown by a dashed line, and its pattern includes a line extending along the X-axis and a plurality of lines connected thereto, extending along the Y-axis, and arranged along the X-axis. These power supply potentials can be provided, for example, from an external power supply circuit or a power supply circuit within the driver IC 117. Note that in Fig. 1, some of the power supply lines, which will be described later with reference to Fig. 2, are omitted.

[0030] As described below, each pixel circuit includes a drive TFT (drive transistor) and a storage capacitor that holds a signal voltage that determines the drive current of the drive TFT. The data signal transmitted by the data line 137 is corrected and stored (written) in the storage capacitor. The voltage of the storage capacitor determines the gate voltage (Vgs) of the drive TFT. The corrected data signal changes the conductance of the drive TFT in an analog manner, and a forward bias current corresponding to the light emission gradation is supplied to the OLED element.

[0031] [Pixel circuit configuration] 2 shows an example of the configuration of a pixel circuit 107 according to an embodiment of the present specification. The pixel circuit 107 is included in an Nth stage (N is an integer) of a pixel circuit row. The pixel circuit 107 includes six transistors (TFTs) M11 to M16 each having a gate, a source, and a drain. In this example, all of the transistors M11 to M16 are P-type TFTs.

[0032] The transistor M11 is a drive transistor that controls the amount of current to the OLED element E1. The drive transistor M11 controls the amount of current provided to the OLED element E1 from the anode power supply that provides the power supply potential PVDD according to the voltage held by the holding capacitor C10. The holding capacitor C10 holds the written voltage throughout one frame period. The cathode of the OLED element E1 is connected to a power supply line 204 that transmits the power supply potential PVEE from the cathode power supply.

[0033] In the configuration example of FIG. 2, the storage capacitor C10 is composed of capacitors C11 and C12 connected in series. One end of the storage capacitor C10 is provided with an anode power supply potential PVDD, and the other end is connected to the source / drain of the switch transistors M13 and M14. The other end of the storage capacitor C10 is connected to the gate of the drive transistor M11. More specifically, one end of the capacitor C12 is connected to the power supply line 141. One end of the capacitor C11 is connected to the source / drain of the switch transistors M13 and M14. An intermediate node between the capacitors C11 and C12 is connected to the gate of the drive transistor M11.

[0034] The voltage of the storage capacitor C10 is the voltage between the gate of the driving transistor M11 and the anode power line 141. The source of the driving transistor M11 is connected to the anode power line 141, and the source potential is the anode power potential PVDD. Therefore, the storage capacitor C10 holds the gate-source voltage of the driving transistor M11. In the configuration example of FIG. 2, the capacitor C12 holds the gate-source voltage of the driving transistor M11.

[0035] The transistor M15 is a switch transistor that controls ON / OFF of the light emission of the OLED element E1. The source of the transistor M15 is connected to the drain of the drive transistor M11. The transistor M15 turns ON / OFF the current supply to the OLED element E1 connected to its drain. The gate of the transistor M15 is connected to an Em signal line (light emission control line) 133, and the transistor M15 is controlled by a light emission control signal Em input to the gate from the shift register circuit 115.

[0036] The transistor M16 operates to supply a reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of the transistor M16 is connected to a power supply line 142 that transmits the reset potential Vrst, and the other end is connected to the anode of the OLED element E1.

[0037] The gate of the transistor M16 is connected to the S1 signal line 131, and the transistor M16 is controlled by a control signal S1. When the transistor M16 is turned ON by the control signal S1 input to its gate from the latch circuit group 113, it supplies the reset potential Vrst transmitted by the power supply line 142 to the anode of the OLED element E1. The transistor M16 also has the function of supplying the reset potential Vrst to the anode of the OLED element E1, and at the same time, bypassing the current flowing from the power supply PVDD via M11 and M15 during the reset period, thereby preventing light leakage.

[0038] The transistor M12 is a switch transistor for writing a voltage for performing threshold correction (threshold compensation) of the driving transistor M11 to the holding capacitor C10, and is a transistor for resetting the gate potential of the driving transistor M11. The source and drain of the transistor M12 connect the gate and drain of the driving transistor M11. Therefore, when the transistor M12 is ON, the driving transistor M11 is in a diode-connected state.

[0039] The transistor M14 is a switch transistor for writing a voltage for performing threshold compensation for the drive transistor M11 to the holding capacitance C10. The transistor M14 controls whether or not a reference potential Vref is supplied to the holding capacitance C10. One end of the source / drain of the transistor M14 is connected to a power supply line 202 that transmits the reference potential Vref, and the other end is connected to one end of the capacitance C11. The gate of the transistor M14 is connected to the S1 signal line 131, and the transistor M14 is controlled by a control signal S1 input to the gate from the latch circuit group 113.

[0040] The transistors M12, M16, and M14 are controlled by a control signal S1. Therefore, these transistors M12, M16, and M14 are simultaneously turned ON / OFF. During the period in which these are in the ON state, the light emission control transistor M15 is turned ON and the gate potential of the drive transistor M11 is reset, and then the light emission control transistor M15 is turned OFF. When the transistors M12 and M14 are ON, the transistor M11 forms a diode-connected transistor. A threshold compensation voltage is written to the storage capacitor C10 between the power supply potential PVDD and the reference potential Vref.

[0041] The transistor M13 is a switch transistor for selecting a pixel circuit to which a data signal is supplied and writing the data signal (data signal voltage) to the storage capacitor C10. One end of the source / drain of the transistor M13 is connected to a data line 137 that transmits a data signal Vdata, and the other end is connected to the storage capacitor C10. More specifically, one end of the source / drain of the transistor M13 is connected to one end of the capacitor C11.

[0042] The gate of the transistor M13 is connected to an S2 signal line 132 that transmits a control signal S2 for selecting a pixel circuit row to which a data signal is to be written. The transistor M13 is controlled by a control signal S2 supplied from the shift register circuit 111. When the transistor M13 is ON, the transistor M13 provides a data signal Vdata, supplied from the driver IC 117 via a data line 137, to the storage capacitor C10.

[0043] Fig. 3 shows an example of a timing chart of signals that control the pixel circuit 107 shown in Fig. 2. Fig. 3 shows a timing chart for writing a threshold compensation voltage of the drive transistor M11 and a data signal Vdata to a pixel circuit in an Nth pixel circuit row. Specifically, Fig. 3 shows the time changes in one frame of the selection signals S1_N, S2_N of the Nth pixel circuit row into which the data signal Vdata is written, the light emission control signal Em_N of the Nth pixel circuit row, and the selection signal S2_N-6 of the (N-6)th pixel circuit row. Fig. 3 shows the changes in signal potential levels. The selection signal is one type of control signal, and is also called a scanning signal.

[0044] 3, the 1H period is a period during which the data signal Vdata is written to the pixel circuit, and is a period during which the selection signal S2 is low. The threshold compensation period is 1H or longer, and is 5H in the example of FIG.

[0045] At time T1, the selection signal S2_N-6 changes from High to Low. As described below, in response to the change in the selection signal S2_N-6, the selection signal S1_N changes from High to Low. In response to the change in the selection signal S1_N, the transistors M12, M14, and M16 are turned ON. At time T1, the light emission control signal Em_N is Low, so the transistor M15 is ON.

[0046] Since the transistors M12, M14 to M16 are ON, the reset potential Vrst is applied to the anode of the OLED element E1, and further to the gate of the driving transistor M11. At time T2, the light emission control signal Em_N changes from Low to High. The period from time T1 to T2 is a reset period of the gate voltage of the driving transistor M11. At time T2, the selection signal S2_N-6 also changes from Low to High. The period from time T1 to T2 is a write period of a data signal to the (N-6)th pixel circuit row. The period from time T1 to T2 is 1H.

[0047] From time T2 to time T3, the potential levels of the signals S1_N, S2_N, Em_N, and S2_N-6 are maintained. The transistors M12, M14, and M16 are ON, and the other transistors including the transistor M15 are OFF. In the period from time T2 to time T3, a threshold compensation voltage is written to the storage capacitor C10. The period from time T2 to time T3 is a threshold compensation period, and its length is 5H.

[0048] At time T3, the selection signal S2_N changes from High to Low. As described below, in response to the change in the selection signal S2_N, the selection signal S1_N changes from Low to High. In response to the change in the selection signal S1_N, the transistors M12, M14, and M16 are turned OFF. After time T3, the selection signal S1_N is maintained at High.

[0049] Furthermore, in response to the change in the selection signal S2_N, the transistor M13 changes from OFF to ON. This starts the writing of the data signal Vdata to the storage capacitor C10. At time T4, the selection signal S2_N changes from High to Low. This causes the transistor M13 to change from ON to OFF, and the writing of data to the Nth stage pixel circuit row ends. The period from time T3 to T4 is a data writing period to the Nth stage pixel circuit row, and its length is 1H. After time T4, the selection signal S2_N is maintained at High.

[0050] At time T4, the light emission control signal Em_N changes from High to Low, causing the transistor M15 to change from OFF to ON, causing a drive current to be applied to the OLED element E1, and the OLED element starts emitting light.

[0051] FIG. 4 shows a schematic diagram of the relationship between the threshold compensation period and the data writing period in four consecutive pixel circuit rows. In each pixel circuit row, the threshold compensation period is followed by a data writing period. The lengths of the data writing period and the threshold compensation period are common to the pixel circuit rows. The length of the data writing period is 1H, and the length of the threshold compensation period is (q-1)*H, where q is an integer equal to or greater than 2. For more appropriate threshold compensation, q is set to an integer equal to or greater than 3. In the example described with reference to FIG. 3, q ​​is 6.

[0052] As described below, the length of the threshold compensation period varies depending on the selection signal S2_N-q of the stage before the selection signal S1_N is changed. As described above, the period during which the selection signal S1_N is low is qH, and the threshold compensation period is (q-1)*H. q is selected so that an appropriate threshold compensation period is obtained in the design of the display device.

[0053] As shown in Fig. 4, data signals are written sequentially into pixel circuit rows. The data write period of each pixel circuit row starts immediately after the data write period of the previous row ends, and the data write periods of different pixel circuit rows do not overlap. The threshold compensation period overlaps with a part of the immediately preceding threshold compensation period and the data write period. The threshold compensation period may overlap with the data write periods of several rows of pixel circuit rows from the immediately preceding row.

[0054] [Combination of shift register circuits and latch circuits] Fig. 5 shows an example of the configuration of a latch circuit 300 included in the latch circuit group 113. The latch circuit 300 shown in Fig. 5 outputs a selection signal S1_N to an Nth stage pixel circuit row. The latch circuit 300 includes a SET terminal 301 and a RST terminal 302 to which signals are input, and a Q terminal 303 that outputs a signal.

[0055] A selection signal S2_N-6 of the (N-6)th stage pixel circuit row from the shift register circuit 111 is input to the SET terminal 301. A selection signal S2_N of the Nth stage pixel circuit row is input to the RST terminal 302. The latch circuit 300 outputs the S1_N signal from the Q terminal 303 to the S1 signal line 131 of the Nth stage pixel circuit row.

[0056] Fig. 6 shows a truth table of the latch circuit 300. In the truth table of Fig. 6, L indicates a logical low level, and H indicates a logical high level. In the configuration described with reference to Figs. 3 to 5, the high potential levels of the signals S1 and S2 correspond to a logical low level, and the low potential levels correspond to a logical high level.

[0057] When the SET input is L and the RST input is L, the Q output is L. When the SET input is H and the RST input is L, the Q output is H, and even if the SET input changes thereafter, the Q output is maintained at H. When the SET input is L and the RST input is H, the Q output is L. The state in which the SET input and RST input are H is prohibited.

[0058] 3 and 5, the shift register circuit 111 sequentially outputs a pulse of the selection signal S2 to the corresponding pixel circuit row. The pulse width is 1H. Each latch circuit 300 outputs the S1 signal to the corresponding pixel circuit row.

[0059] As described above, the Nth stage latch circuit 300 receives a pulse of the low potential level (H logic level) of the selection signal S2_N-q of a predetermined previous stage at the SET terminal 301, and changes the selection signal S1_N from the Q terminal 303 to the low potential level. Thereafter, the selection signal S2_N-q changes to the high potential level (L logic level), but the input S2_N to the RST terminal 302 is at the high potential level, and the selection signal S1_N from the Q terminal 303 is maintained at the low potential level.

[0060] Thereafter, the latch circuit 300 receives a pulse of a low potential level (H logic level) of the selection signal S2_N of the Nth stage pixel circuit row at the RST terminal 302, and changes the selection signal S1_N from the Q terminal 303 to a high potential level (L logic level). The pulse width of the S1_N signal output from the latch circuit 300 is qH.

[0061] 7 shows a circuit configuration example of the latch circuit 300. In the configuration example of FIG. 7, the latch circuit 300 is composed of four transistors and one capacitive element. The four transistors M21 to M24 are P-type transistors. The transistor M21 is in a diode-connected state, and its drain receives an input from a SET terminal 301. The transistor M22 is connected between the transistor M21 and a power supply that provides a power supply potential PVEE, and its gate receives an input from a RST terminal 302.

[0062] The transistor M23 is connected between a power supply providing a power supply potential PVDD and the Q terminal 303, and its gate is connected to the intermediate node between the transistors M21 and M22. The transistor M24 is connected between the transistor M23 and a power supply providing a power supply potential PVEE, and its gate receives the RST input. The capacitance element Cb is connected between the gate of the transistor M23 and the Q terminal 303. The intermediate node between the transistors M23 and M24 is connected to the Q terminal 303.

[0063] 8 is a schematic diagram showing an example of the configuration of the shift register circuit 111 and the latch circuit group 113, and an example of the layout of the wiring 112. The shift register circuit 111 includes a plurality of shift register units connected in series. In FIG. 8, only one shift register unit is indicated by the reference numeral 400.

[0064] 8 shows the (N-6)th stage shift register unit 400 to the (N+3)th stage shift register unit 400. These shift register units 400 correspond to the pixel circuit row of the same stage. Data bits are transferred from the previous stage shift register unit 400 to the next stage shift register unit 400 in accordance with two clock signals CK and CKB. The shift register unit 400 that holds the data bits outputs a signal pulse.

[0065] The latch circuit group 113 includes a plurality of latch circuits 300. In Fig. 8, only one shift latch circuit is indicated by the reference symbol 300. Fig. 8 shows the (N-6)th stage latch circuit 300 to the (N+3)th stage latch circuit 300. These latch circuits 300 correspond to the pixel circuit row in the same stage.

[0066] The shift register circuit 111 includes shift register units 400 corresponding to each pixel circuit row. The shift register unit 400 corresponding to a pixel circuit row outputs a signal pulse to the pixel circuit row and two latch circuits 300. The number of shift register units 400 is greater than the number of pixel circuit rows. Some shift register units 400 (not shown) are not connected to a pixel circuit row and output a signal only to the latch circuits 300.

[0067] The two inputs of each latch circuit 300 are connected to the outputs of the shift register unit 400 of a different stage. Specifically, the output from the earlier stage shift register unit 400 is input to the SET terminal, and the output from the later stage shift register unit 400 is input to the RST terminal. In the configuration example shown in Fig. 8, the output of the (N-6)th stage shift register unit 400 is input to the SET terminal of the Nth stage latch circuit 300, and the output of the Nth stage shift register unit 400 is input to the RST terminal of the Nth stage latch circuit 300.

[0068] The Nth stage shift register unit 400 outputs an Nth stage selection signal S2 to the Nth stage pixel column / row, the RST terminal of the Nth stage latch circuit 300, and the SET terminal of the (N+6)th stage latch circuit 300. The Nth stage shift register unit 400 outputs signal pulses to these simultaneously.

[0069] The Nth stage latch circuit 300 outputs a selection signal S1 from a Q terminal to the Nth stage pixel circuit row. As described above, the Nth stage latch circuit 300 starts a pulse of the selection signal S1 in response to a signal pulse from the (N-6)th stage shift register unit 400, and ends the pulse in response to a signal pulse from the Nth stage shift register unit 400. The pulse from the latch circuit 300 is a first signal pulse, and the pulse from the shift register unit 400 is a second signal pulse. The selection signal S1_N shown in FIG. 3 is generated as described above from two shift register units and one latch circuit.

[0070] The above description of the Nth stage shift register unit 400 and the Nth stage latch circuit 300 can be applied to other stages of shift register units 400 and latch circuits 300 corresponding to the pixel circuit rows. In the above example, the latch circuit 300 is controlled by the output from two shift register units 400 that are six stages apart, but the positional relationship of the shift register units 400 that control the latch circuit 300 is determined according to the pulse width of the selection signal S1.

[0071] More generally, the output of the Nth stage latch circuit 300 is set by a pulse from the Kth stage shift register unit and reset by a signal pulse from the (K+p)th stage shift register unit, where K is an integer and p is an integer equal to or greater than 2. In the above example, K is (N-6) and p is 6.

[0072] The output of the (N+q)th stage latch circuit is set by a signal pulse from the (K+q)th stage shift register unit, and is reset by a signal pulse from the (K+q+p)th stage shift register unit, where q is an integer equal to or greater than 1. The pulse from the latch circuit 300 has a pulse width of p*H. In addition, the pulse from the (N+q)th stage latch circuit 300 has a time delay of q*H with respect to the pulse from the Nth stage latch circuit 300. As described above, the threshold compensation period is (p-1)*H.

[0073] Next, a configuration for generating the light emission control signal Em by combining a shift register circuit and a latch circuit group will be described. Fig. 9 shows input / output signals to / from the Nth stage latch circuit 350 included in the latch circuit group. The truth table of the latch circuit 350 is as described with reference to Fig. 6.

[0074] A selection signal S2_N-5 from the (N-5)th stage shift register is input to the RST terminal 352 of the latch circuit 350. A selection signal S2_N+1 from the (N+1)th stage shift register is input to the SET terminal 351 of the latch circuit 350. The latch circuit 350 outputs a light emission control signal Em_N to the Nth stage pixel circuit row from the Q terminal 353. When the threshold compensation period is (p-1)*H, a selection signal S2 from the (N-(p-1))th stage shift register is input to the RST terminal 352 of the latch circuit 350.

[0075] 10A is a schematic diagram showing an example of the configuration of a shift register circuit and a latch circuit group and an example of the layout of wiring for generating the light emission control signal Em. This makes it easier to design a circuit for generating the light emission control signal Em.

[0076] The shift register circuit 451 includes a plurality of shift register units 452 connected in series. Only one shift register unit is indicated by the reference numeral 452. The configuration of the shift register unit 452 is the same as that of the shift register unit 400. The shift register circuit 451 does not directly output a signal to the pixel circuit, but outputs only to the latch circuit group 461.

[0077] The latch circuit group 461 includes latch circuits 350 corresponding to each pixel circuit row. The latch circuit is designated by the reference numeral 350. The configuration of the latch circuit group 461 is similar to the configuration described with reference to Fig. 8. Compared to the configuration of Fig. 8, the connection wiring 471 between the shift register circuit 451 and the latch circuit group 461 is different.

[0078] 10A shows the (N-6)th stage shift register unit 452 and latch circuit 350 to the (N+3)th stage shift register unit 452 and latch circuit 350. The latch circuit 350 corresponds to the pixel circuit row in the same stage. The number of shift register units 452 is greater than the number of pixel circuit rows.

[0079] The two inputs of each latch circuit 350 are connected to the outputs of different shift register units 452. Specifically, the output from the earlier-stage shift register unit 452 is input to the RST terminal, and the output from the later-stage shift register unit 452 is input to the SET terminal. In the configuration example shown in Fig. 10A, the output of the (N-5)th stage shift register unit 452 is input to the RST terminal of the Nth stage latch circuit 350, and the output of the (N+1)th stage shift register unit 452 is input to the SET terminal of the Nth stage latch circuit 350.

[0080] The Nth stage shift register unit 452 outputs a control signal to the SET terminal of the (N-1)th stage latch circuit 350 and the RST terminal of the (N+5)th stage latch circuit 350. The Nth stage shift register unit 452 outputs a signal pulse to these simultaneously.

[0081] The Nth stage latch circuit 350 outputs a light emission control signal Em to the Nth stage pixel circuit row from a Q terminal. The Nth stage latch circuit 350 starts the pulse of the light emission control signal Em in response to the signal pulse from the (N-5)th stage shift register unit 452, and ends the pulse in response to the signal pulse from the (N+1)th stage shift register unit 452.

[0082] The direction (electric potential level) of the pulse of the light emission control signal Em is opposite to that of the selection signal S1. The timing chart of each signal is as shown in FIG. 10B. The pulse from the latch circuit 350 is the first signal pulse, and the pulse from the shift register unit 452 is the second signal pulse.

[0083] The above description of the Nth stage shift register unit 452 and the Nth stage latch circuit 350 can be applied to other stages of latch circuits 350 corresponding to each of the pixel circuit rows and their corresponding shift register units 452. Also, in the above example, the latch circuit 350 is controlled by output from two shift register units 452 that are six stages apart, but the positional relationship of the shift register units 452 that control the latch circuit 350 is determined according to the pulse width of the light emission control signal Em.

[0084] More generally, the output of the Nth stage latch circuit is reset by a pulse from the Kth stage shift register unit and set by a signal pulse from the (K+p)th stage shift register unit. In the above example, K is (N-5) and p is 6.

[0085] The output of the (N+q)th stage latch circuit is reset by a signal pulse from the (K+q)th stage shift register unit, and is set by a signal pulse from the (K+q+p)th stage shift register unit. The pulse from the latch circuit 350 has a pulse width of p*H. In addition, the pulse from the (N+q)th stage latch circuit 350 has a time delay of q*H with respect to the pulse from the Nth stage latch circuit 350. As described above, the period during which the current supply to the OLED element E1 is turned off is p*H.

[0086] 10A, a combination of a shift register circuit and a latch circuit group generates and outputs only the emission control signal Em without generating the selection signal S2. Another configuration example may generate and output the selection signal S2 in addition to the emission control signal Em. In this case, the OLED display device includes a shift register that generates the selection signal S1 and outputs it without passing through a latch circuit.

[0087] The circuit that generates the selection signal S2 and the emission control signal Em adds a control signal line from the output of the shift register unit 452 to the corresponding pixel circuit row to the configuration example of Figure 10A. The shift register unit 452 connected to the pixel circuit row outputs a signal pulse to the pixel circuit row in the same stage as well as the two latch circuits described with reference to Figure 10A. The driving method of the present invention is not limited to the two embodiments described above, and is a highly versatile method that can generate pulses of any time width by changing the time sequence and time interval of the SET signals and RST signals input to the latch circuits.

[0088] 11 shows an example of a configuration in which the signal line 131 that transmits the selection signal S1 from the latch circuit 300 is connected to the power supply potential VOFF, thereby preventing the S1 signal line from floating during the light emission period.

[0089] During the light emission period, the transistors M23 and M24 connected to the S1 signal line are in an off state, so that the S1 signal line is in an electrically floating state. The potential of the S1 signal line is maintained by the electrical capacitance of the entire signal line, but fluctuates due to feed-through noise via the coupling capacitance between the S1 signal line and the data lines that intersect with it in the display area. If this potential fluctuation is large, it may degrade image quality. For this reason, it is more desirable to fix the potential of the S1 signal line during the light emission period.

[0090] 11 includes a reset switch (switch transistor) 501 that turns on / off the connection between the S1 signal line 131 and a power line with a power supply potential VOFF. In the configuration example of FIG. 11, the reset switch 501 is a P-type TFT. The reset switch 501 is mounted on each of the S1 signal lines 131. The power supply potential VOFF is a potential opposite to the pulse potential of the selection signal S1, and is a High potential level in the configuration examples described with reference to FIGS. 2 to 10.

[0091] The ON / OFF of the reset switch 501 is controlled by a light emission control signal Em output from the shift register circuit 115. The light emission control signal is a signal that controls whether or not a drive current is supplied to the OLED element E1. Specifically, the reset switch 501 that turns ON / OFF the supply of the power supply potential VOFF to the Nth stage S1 signal line 131 is turned ON / OFF by the same Nth stage light emission control signal Em_N.

[0092] Fig. 12 shows a timing chart of control signals in the circuit shown in Fig. 11. The following mainly describes the differences from the timing chart shown in Fig. 3. The light emission control signal Em_N changes from low level to high level at time T0, which is 1H before time T1. When the light emission control signal Em_N is low level, the reset switch 501 is ON, and the potential of the S1 signal line 131 of the Nth stage is fixed to the power supply potential VOFF.

[0093] In response to the change of the light emission control signal Em_N to a high level, the reset switch 501 is turned off. The S1 signal line 131 is in a floating state. At time T1, the latch circuit 300 starts outputting a low level signal to the selection signal S1_N. The light emission control signal Em_N is at a high level, and the transistor M15 is turned off. A reset potential Vrst is applied to the anode of the OLED element E1, and is not applied to the gate of the drive transistor M11.

[0094] At time T5, which is 1H after time T4, the light emission control signal Em_N changes from a high level to a low level. In response to the change of the light emission control signal Em_N to a low level, the reset switch 501 turns ON. The reset switch 501 turns ON, and the potential of the S1 signal line 131 of the Nth stage is fixed to the power supply potential VOFF.

[0095] Fig. 13 shows another example of a configuration in which the power supply potential VOFF is applied to the potential of the S1 signal line. In the example of the configuration shown in Fig. 13, a signal VRESET for controlling a reset switch 501 is generated and output by combining a shift register circuit 503 and a latch circuit group. Fig. 13 shows an example of an Nth stage latch circuit 505, but latch circuits 505 corresponding to the S1 signal lines of all stages are implemented. The output of the latch circuit 505 is input to the gate of the reset switch 501 of the same stage. The pulse period of the shift register unit is 1H.

[0096] 13, the output of the (N-6)th stage shift register unit is input to the RST terminal of the Nth stage latch circuit 505, and the output of the Nth stage shift register unit is input to the SET terminal. The Nth stage latch circuit 505 outputs a control signal VRESET from a Q terminal to the gate of the Nth stage reset switch 501.

[0097] Fig. 14 shows a timing chart of control signals in the configuration example shown in Fig. 13. Differences from the timing chart shown in Fig. 3 will be mainly described. As shown in Fig. 14, the control signal VRESET of the Nth stage reset switch 501 changes complementarily to the Nth stage selection signal S1. In other words, when one is at a High or Low level, the other is at a Low or High level. This makes it possible to stabilize the potential of the S1 signal line.

[0098] At time T1, the output of the latch circuit 505 changes from logical H to logical L due to the pulse of the control signal R_N-6 to the RST terminal of the latch circuit 505. That is, the output VRESET of the latch circuit 505 changes from a low potential level to a high potential level. This turns off the reset switch 501.

[0099] After that, at time T3, the output of the latch circuit 505 changes from logical L to logical H due to a pulse of the control signal R_N to the SET terminal of the latch circuit 505. That is, the output VRESET of the latch circuit 505 changes from a high potential level to a low potential level. This turns on the reset switch 501, and the power supply potential VOFF is applied to the S1 signal line.

[0100] As described with reference to Figures 11 to 14, the wiring that transmits the pulse from each latch circuit to the pixel circuit row is connected to a power supply line with a high level potential after the pulse ends. This makes it possible to stabilize the wiring potential. Note that the potential level supplied to the wiring is the reference potential level of the pulse, and may be low depending on the waveform of the S1 signal.

[0101] 13 and 14 includes a second shift register circuit 503 and a plurality of second latch circuits 505. Each latch circuit 505 outputs a signal pulse to the corresponding reset switch 501.

[0102] The shift register circuit 503 sequentially outputs signal pulses. A signal pulse from one shift register unit of the shift register circuit 503 and a signal pulse from a shift register unit in a subsequent stage are input to each latch circuit 505. The signal pulse from each latch circuit 505 starts in response to the signal pulse from the shift register unit in the previous stage and ends in response to the signal pulse from the shift register unit in the subsequent stage.

[0103] Each latch circuit 505 controls the corresponding reset switch 501 by a signal pulse synchronized with the S1 signal pulse, and connects the wiring that transmits the S1 signal line pulse to the pixel circuit row to a power supply line at a high level potential after the S1 signal pulse ends.

[0104] [Other pixel circuit configurations] 15 shows another example of the configuration of a pixel circuit. The pixel circuit 550 includes a P-type TFT and an N-type TFT. The P-type TFT is, for example, a low-temperature polysilicon TFT, and the N-type TFT is, for example, an oxide semiconductor TFT. The pixel circuit 550 includes seven transistors (TFTs) M51 to M57. In this example, the transistors M51, M53, and M56 are P-type TFTs, and the transistors M52, M54, M55, and M57 are N-type TFTs.

[0105] The transistor M53 is a drive transistor that controls the amount of current to the OLED element E1. The drive transistor M53 controls the amount of current provided to the OLED element E1 from the anode power supply according to the voltage held by the storage capacitor Cst. The cathode of the OLED element E1 is connected to the cathode power supply. The storage capacitor Cst holds the gate-source voltage of the drive transistor M53.

[0106] The transistors M51 and M56 control whether or not the OLED element E1 emits light. The source terminal of the transistor M51 is connected to an anode power supply, and the transistor M51 turns on / off the current supply to the drive transistor M53 connected to the drain terminal. The source terminal of the transistor M56 is connected to the drain terminal of the drive transistor M53, and the transistor M51 turns on / off the current supply to the OLED element E1 connected to the drain terminal. The transistors M51 and M56 are controlled by a light emission control signal Em.

[0107] The transistor M57 operates to supply a reset potential to the anode of the OLED element E1. When the transistor M57 is turned on by a selection signal S2 input to the gate, the transistor M57 supplies a reset potential Vrst from a reset power supply to the anode of the OLED element E1. The other end of the reset power supply is connected to GND.

[0108] The transistor M55 controls whether or not a reset potential is supplied to the gate of the drive transistor M53. When the transistor M55 is turned ON by a selection signal S1 input to its gate, the reset potential Vrst is supplied to the gate of the drive transistor M53 from a reset power supply connected to its source / drain. The other end of the reset power supply is connected to GND. Note that the reset potential to the anode of the OLED element E1 and the reset potential to the gate of the drive transistor M53 may be different.

[0109] The transistor M52 is a selection transistor for selecting the pixel circuit 550 to which a data signal is to be supplied. The gate voltage of the transistor M52 is controlled by a selection signal S2. When the selection transistor M52 is ON, the selection transistor M52 supplies a data signal Vdata supplied from the driver IC 117 via a data line to the gate (storage capacitance Cst) of the drive transistor M53.

[0110] In this example, the selection transistor M52 is connected between the data line and the source of the driving transistor M53, and the transistor M54 is connected between the drain and gate of the driving transistor M53.

[0111] The transistor M54 operates to correct the threshold voltage of the driving transistor M53. When the transistor M54 is ON, the driving transistor M53 constitutes a diode-connected transistor. The data signal Vdata from the data line is applied to the storage capacitor Cst via the selection transistor M52, which is ON, the driving transistor M53, and the channel (source and drain) of the transistor M54.

[0112] The storage capacitor Cst holds the gate-source voltage of the drive transistor M53, and has one end connected to the gate of the drive transistor M53 and the other end connected to a node between the source of the transistor M51 and the anode power supply. The storage capacitor Cst holds a data signal (voltage) corrected according to the threshold voltage Vth of the drive transistor M53.

[0113] Fig. 16 shows a timing chart of signals controlling pixel circuit 550 shown in Fig. 15 during one frame period. Fig. 16 shows a timing chart for selecting the Nth pixel circuit row and writing data signal Vdata to pixel circuit 550. Specifically, Fig. 16 shows changes in light emission control signal Em_N, selection signal S1_N, and selection signal S2_N during one frame.

[0114] At time T11, the light emission control signal Em_N changes from a low level to a high level. The transistors M51 and M56 are turned off. At time T11, the selection signals S1_N and S2_N are low. In response to these control signals, the transistors M52, M54, M55, and M57 are turned off. These transistor states are maintained until time T12, which is after time T11.

[0115] At time T12, the selection signal S1_N changes from a low level to a high level. At time T12, the light emission control signal Em_N is high and the selection signal S2_N is low. In response to the change in the selection signal S1_N, the transistor M55 turns ON. The transistors M51, M52, M54, M56, and M57 are OFF.

[0116] When the transistor M55 is turned on, the gate potential of the driving transistor M53 changes to the reset potential Vrst. The reset potential Vrst is applied to the gate of the driving transistor M53 from time T12 to time T13. By applying the reset potential to the gate of the driving transistor M53, the influence of the history effect can be reduced.

[0117] At time T13, the selection signal S1_N changes from High level to Low level, and the selection signal S2_N changes from Low level to High level. The light emission control signal Em_N is High. In response to the change in the selection signal S1_N, the transistor M55 turns OFF. In response to the change in the selection signal S2_N, the transistors M52, M54, and M57 turn ON. The transistors M51 and M56 are OFF.

[0118] When the transistor M57 is turned on, the reset potential Vrst of the reset power supply is applied to the anode of the OLED element E1. Since the transistor M54 is turned on, the drive transistor M53 is diode-connected. Since the transistor M52 is turned on, the data signal Vdata from the data line is written to the storage capacitor Cst via the transistors M52, M53, and M54.

[0119] The voltage written to the storage capacitor Cst is a voltage obtained by correcting the data signal Vdata for the threshold voltage Vth of the drive transistor M53. In the period from time T13 to time T14, the data signal Vdata is written to the pixel circuit 550 and its threshold is compensated.

[0120] At time T14, the level of the selection signal S2 changes from High to Low. At time T14, the light emission control signal Em_N is at High level, and the selection signal S1_N is at Low level. In response to the change in the selection signal S2_N, the transistors M52, M54, and M57 are turned OFF. The transistors M51, M52, M54 to M57 are OFF. From time T14 to time T15, the states of the control signals and transistors are maintained.

[0121] At time T15, the light emission control signal Em_N changes from a high level to a low level, and the transistors M51 and M56 change from OFF to ON. The selection signals S1_N and S2_N are at a low level, and the transistors M52, M54, M55 and M57 remain OFF.

[0122] The driving transistor M53 controls the driving current to be provided to the OLED element E1 based on the corrected data signal stored in the storage capacitor Cst. That is, the OLED element E1 emits light. In the timing chart of Fig. 16, the periods from time T11 to T12, from time T12 to T13, from time T13 to T14, and from time T14 to T15 are each 1H. In the configuration examples shown in Figs. 15 and 16, threshold compensation and data writing are performed in the same period and are not separated.

[0123] In the following, a method for generating and outputting the control signals S1, S2, and Em in the configuration example shown in Figures 15 and 16 by combining a shift register circuit and a latch circuit group will be described. Figure 17 shows a configuration example of a latch circuit 380 used in the latch circuit group. Although Figure 17 shows an N-th stage latch circuit 380, the latch circuits in the other stages also have a similar configuration.

[0124] The latch circuit 380 is composed of four transistors and one capacitance element. The four transistors M61 to M64 are N-type transistors. The transistor M61 is in a diode-connected state, and its drain receives an input from a SET terminal 381. The transistor M62 is connected between the transistor M61 and a power supply that provides a power supply potential PVEE, and its gate receives an input from a RST terminal 382.

[0125] The transistor M63 is connected between a power supply providing a power supply potential PVDD and the Q terminal 383, and its gate is connected to an intermediate node between the transistors M61 and M62. The transistor M64 is connected between the transistor M63 and a power supply providing a power supply potential PVEE, and its gate receives the RST input. The capacitance element Cd is connected between the gate of the transistor M63 and the Q terminal 383. The intermediate node between the transistors M63 and M64 is connected to the Q terminal 383.

[0126] 18 shows a timing chart of input and output signals of the latch circuit 380. In the latch circuit 380, when the logical level of a signal is H, the potential level is High. The truth table of the latch circuit 380 is as shown in FIG.

[0127] When the SET signal and the RST signal are both at low potential levels, the Q output is at low potential level. When the SET input changes to high potential level, the Q output changes to high potential level. After that, even if the SET input changes to low potential level, the Q output maintains high potential level. After that, when the RST input changes to high potential level, the Q output changes to low potential level. After that, the RST input changes to low potential level, and the Q output is at low potential level.

[0128] Fig. 19 shows a schematic circuit configuration example in which the control signals S1, S2, and Em are generated and output by a combination of a shift register circuit and a latch circuit group. Fig. 19 shows a shift register circuit 507 and one latch circuit 380 in the latch circuit group. The shift register circuit 507 includes a plurality of shift register units connected in series, similar to the shift register circuit 111. The circuit configuration of the shift register circuit 507 is arbitrary. In one embodiment of the present specification, all the transistors included in the shift register circuit 507 are N-type TFTs.

[0129] The multiple register units sequentially output signal pulses. The potential level of the signal pulses is High. The output S_N of the Nth stage shift register unit is input to the S2 signal line of the Nth stage pixel circuit row, the S1 signal line of the (N+1)th stage pixel circuit row, the RST terminal of the (N-2)th stage latch circuit 380, and the SET terminal of the (N+2)th stage latch circuit 380. The S1 and S2 signal lines are first control lines.

[0130] The shift register unit outputs selection signals S1 and S2 to the two pixel circuit rows, respectively, and further outputs a RST signal and a SET signal to the two latch circuits 380, respectively. In this manner, the output pulse from each shift register unit is an S2 signal pulse for one corresponding pixel circuit row and an S1 signal pulse (third signal pulse) for the other corresponding pixel circuit row.

[0131] For example, the selection signal S1_N of the Nth pixel circuit row is the output signal S_N-1 of the (N-1)th shift register unit, and the selection signal S2_N of the Nth pixel circuit row is the output signal S_N of the Nth shift register unit.

[0132] As described above, the output signal S_N-2 of the (N-2)th stage shift register unit is input to the SET terminal of the Nth stage latch circuit 380, and the output signal S_N+2 from the (N+2)th stage shift register unit is input to the RST terminal. The Nth stage latch circuit 380 outputs a light emission control signal Em_N for the Nth stage pixel circuit row from the Q terminal. The output of the Q terminal is controlled by signal pulses to the SET terminal and RST terminal. The Em signal line that transmits the light emission control signal is the second control line.

[0133] In this manner, in this configuration example, a light emission control signal Em_N for the Nth row is generated from the shift register signals for the rows two rows before and two rows after. The period of the light emission control signal Em is 4H. In this configuration example, the light emission control signal Em is supplied to the gates of the P-type transistors 51 and 56, and therefore becomes a pulse signal having the same polarity as the selection signals S1 and S2.

[0134] Here, the same polarity means that the time when the pulse is at a high level is significantly shorter than the time when the pulse is at a low level. A circuit that generates such a signal can be configured with fewer TFTs when using N-type TFTs than when using P-type TFTs, and the circuit area can be reduced. In one embodiment of this specification, the transistors included in the latch circuit and the shift register circuit are all N-type TFTs.

[0135] As described above, in the pixel circuit 550 described with reference to FIG. 15, the emission control transistors M56, M51 and the drive transistor M53 are P-type (second conductivity type) TFTs. The switch transistors M52, M54, M55 and M57 are N-type (first conductivity type) TFTs. As described with reference to FIG. 19, the control line (first control line) from the shift register circuit 507 transmits the selection signal S, and the control line (second control line) from the latch circuit 308 transmits the emission control signal Em. In addition, all the transistors included in the shift register circuit 507 and the latch circuit 308 are N-type (first conductivity type) TFTs.

[0136] In this manner, in this configuration example, the selection signals S1 and S2 and the light emission control signal Em longer than 1H can be generated and output by the shift register circuit and latch circuit group composed of N-type TFTs. Note that by changing the conductivity type of the transistors in the pixel circuit 550 to the opposite conductivity type and configuring the shift register circuit and latch circuit with P-type TFTs, the shift register circuit and latch circuit can be configured with transistors of one conductivity type.

[0137] [Device structure of latch circuit] An example of the device structure of the latch circuit will be described below. Fig. 20 is a plan view showing a schematic layout example of the latch circuit 300. As described with reference to Fig. 7, the latch circuit 300 includes transistors M21 to M24 and a capacitive element Cb. In Fig. 20, the same material layers are painted in the same pattern. Specifically, the latch circuit 300 includes a semiconductor layer SC, a first metal layer MT1, and a second metal layer MT2.

[0138] Fig. 21 shows a schematic cross-sectional structure taken along line XXI-XXI in Fig. 20. Fig. 21 shows a cross-sectional structure of a transistor M22. An undercoat film UC is formed on an insulating substrate SUB. The undercoat film UC is, for example, a silicon nitride film.

[0139] A semiconductor layer SC is formed on the undercoat film UC. The semiconductor layer SC is, for example, polysilicon. When the TFT is an N-type, for example, an oxide semiconductor can be used. The semiconductor layer SC is covered with a gate insulating film GI. The gate insulating film GI is, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof.

[0140] A gate electrode GT and a first wiring ML1, which are included in a first metal layer MT1, are formed on the gate insulating film GI. Examples of materials that can be used for the first metal layer MT1 include Mo, W, Nb, and Al.

[0141] The first metal layer MT1 and the gate insulating film GI where the first metal layer MT1 is exposed are covered with an interlayer insulating film ILD. The interlayer insulating film ILD is, for example, a silicon nitride film or a silicon oxide film. A second wiring ML2 included in a second metal layer MT2 is formed on the interlayer insulating film ILD.

[0142] A part of the second wiring ML2 is in contact with the semiconductor layer SC through a contact hole formed in the interlayer insulating film ILD and the gate insulating film GI. A part of the second wiring ML2 is in contact with the semiconductor layer SC through a contact hole formed in the interlayer insulating film ILD and the gate insulating film GI, and is further in contact with the first wiring ML1 through a contact hole formed in the interlayer insulating film ILD. The entire latch circuit 300 is covered with a protective insulating film PV. The protective insulating film PV is, for example, an inorganic film such as a silicon nitride film or a silicon oxide film.

[0143] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

[0144] Several aspects of the present disclosure are described below. (1) a display area including a plurality of rows of pixel circuits; a shift register including a plurality of concatenated shift register units; a plurality of latch circuits that output signal pulses to the plurality of pixel circuit rows in response to a signal input from the shift register; Including, Each latch circuit of the plurality of latch circuits outputs a first signal pulse to a corresponding pixel circuit row; The plurality of shift register units sequentially output second signal pulses; the second signal pulse from a first shift register unit and the second signal pulse from a second shift register unit in a stage subsequent to the first shift register unit are input to each latch circuit of the plurality of latch circuits; The first signal pulse from each latch circuit of the plurality of latch circuits is changing from a first potential level to a second potential level in response to the second signal pulse from the first shift register unit; changing from the second potential level to the first potential level in response to the second signal pulse from the second shift register unit; Display device. (2) The display device according to (1), N is an integer, K is an integer, p is an integer greater than or equal to 2, q is an integer greater than or equal to 1, and H is the pulse width from the shift register; an output of the N-th stage latch circuit is set by the second signal pulse from the K-th stage shift register unit, and is reset by the second signal pulse from the (K+p)-th stage shift register unit; an output of the (N+q)th stage latch circuit is set by the second signal pulse from the (K+q)th stage shift register unit and reset by the second signal pulse from the (K+q+p)th stage shift register unit; the first signal pulse from each latch circuit has a pulse width of H*p; the first signal pulse from the (N+q)th stage latch circuit has a time delay of H*q with respect to the first signal pulse from the Nth stage latch circuit; Display device. (3) The display device according to (1), N is an integer, K is an integer, p is an integer greater than or equal to 2, q is an integer greater than or equal to 1, and H is the pulse width from the shift register; an output of the N-th stage latch circuit is reset by the second signal pulse from the K-th stage shift register unit, and is set by the second signal pulse from the (K+p)-th stage shift register unit; an output of the (N+q)th stage latch circuit is reset by the second signal pulse from the (K+q)th stage shift register unit, and is set by the second signal pulse from the (K+q+p)th stage shift register unit; the first signal pulse from each latch circuit has a pulse width of H*p; the first signal pulse from the (N+q)th stage latch circuit has a time delay of H*q with respect to the first signal pulse from the Nth stage latch circuit; Display device. (4) The display device according to (1), Each shift register unit of the plurality of shift register units outputs the second signal pulse to a corresponding row of pixel circuits; the shift register sequentially outputs the second signal pulse to the plurality of pixel circuit rows; Display device. (5) The display device according to (4), The first signal pulse controls a threshold compensation period of a driving transistor of a pixel circuit; The second signal pulse controls a period during which data is written to the pixel circuit. Display device. (6) The display device according to (4), the first signal pulse controls whether or not a drive current is supplied to a light emitting element included in a pixel circuit; The second signal pulse controls a period during which data is written to the pixel circuit. Display device. (7) The display device according to (5), a wiring for transmitting the first signal pulse from each latch circuit to the pixel circuit row is connected to a power supply line having a potential of the first potential level after the first signal pulse ends. Display device. (8) The display device according to (7), a switch transistor between the wiring and the power supply line that supplies a potential of the first potential level; The switch transistor is turned on / off by a signal that controls whether or not a drive current is supplied to a light-emitting element included in the pixel circuit. Display device. (9) The display device according to (1), the latch circuit is disposed between the shift register and the display area; Display device. (10) The display device according to (6), an output pulse from each shift register unit of the plurality of shift register units is the second signal pulse of a corresponding pixel circuit row and a third signal pulse of a corresponding other pixel circuit row; Display device. [Explanation of symbols]

[0145] 1 OLED display device 101 Display area 107,555 pixel circuit 111, 115, 451, 503, 507 Shift register circuit 112, 471 Wiring 113, 461 Latch circuits 131 S1 signal line 132 S2 signal line 133 Emission signal line 300, 350, 380, 505 Latch circuit 400, 452 Shift Register Unit 501 Reset switch CK, CKB clock signals E1 OLED element M11-M15, M21-M24, M51-M57, M61-M64 transistors

Claims

1. A display area; A drive circuit for the display area is disposed outside the display area; Including, The display area is A plurality of pixel circuits; a plurality of first control lines, a plurality of second control lines, a plurality of signal lines, and a plurality of power supply lines connected to the plurality of pixel circuits; Including, Each pixel circuit of the plurality of pixel circuits comprises: A light-emitting element; a plurality of switch transistors having a first conductivity type; a light emission control transistor having a second conductivity type and controlling ON / OFF of light emission of the light emitting element; a driving transistor having the second conductivity type and controlling an amount of current to the light emitting element; a storage capacitor connected to the driving transistor; Including, the first control lines each transmit a first control signal from the drive circuit to the first conductivity type switch transistors; the second control lines each transmit a second control signal from the drive circuit to a light emission control transistor having the second conductivity type; the drive circuit includes a plurality of transistors, a plurality of capacitors, and a connection wiring; All transistors included in the driving circuit are transistors of the first conductivity type. Display device.

2. The display device according to claim 1 , the driving circuit includes a plurality of shift register units and a plurality of latch circuits; Each latch circuit of the plurality of latch circuits outputs a first signal pulse to a corresponding pixel circuit row; the plurality of shift register units sequentially output second signal pulses; the second signal pulse from a first shift register unit and the second signal pulse from a second shift register unit in a stage subsequent to the first shift register unit are input to each of the latch circuits of the plurality of latch circuits; The first signal pulse from each latch circuit of the plurality of latch circuits is changing from a first potential level to a second potential level in response to the second signal pulse from the first shift register unit; changing from the second potential level to the first potential level in response to the second signal pulse from the second shift register unit; Display device.

3. The display device according to claim 2, the plurality of shift register units sequentially output the second signal pulses in accordance with an input clock signal; a signal pulse input to each latch circuit of the plurality of latch circuits is only the second signal pulse from the first shift register unit and the second signal pulse from the second shift register unit; Display device.

4. The display device according to claim 1 , The first conductivity type is N-type and the second conductivity type is P-type. Display device.

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