Nonvolatile memory device

Abstract

To provide a nonvolatile memory device capable of performing erase on a memory element further efficiently.SOLUTION: A nonvolatile memory device (1) includes: memory elements (Md1, Md2) capable of executing a program operation by trapping a hot carrier to a side wall; a first negative voltage generating unit (101) configured such that a first negative voltage (Vm1) that is applied to the gate of the memory element is generated when performing erase on the memory element; and a second negative voltage generating unit (102) configured such that a second negative voltage (Vm2) that is applied to the back gate of the memory element is generated when performing erase.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to non-volatile memory devices. [Background technology]

[0002] Conventionally, there is a non-volatile memory device that uses hot carrier injection into a transistor. This type of non-volatile memory device has a first and a second transistor as memory elements, whose characteristics are the same in the initial state, and injects hot carriers into only one of the transistors to change the characteristics of the transistor. In a subsequent read operation, it is read whether data "0" or data "1" is stored based on the magnitude relationship of the drain currents when a common gate voltage is supplied to the first and the second transistors. For example, a state in which the drain current of the first transistor is smaller (a state in which the characteristics of the first transistor have changed) corresponds to a state in which data "0" is stored, and a state in which the drain current of the second transistor is smaller (a state in which the characteristics of the second transistor have changed) corresponds to a state in which data "1" is stored.

[0003] The technology related to the above is disclosed in, for example, Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2011-103158 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the nonvolatile memory device described above, it is possible to perform a program for injecting hot carriers as well as an erase process for removing the hot carriers. However, there is a problem in that erasing can be performed more efficiently.

[0006] An object of the present disclosure is to provide a non-volatile memory device capable of more efficiently erasing a memory element. [Means for solving the problem]

[0007] For example, a non-volatile memory device according to the present disclosure may include A memory element capable of performing a program operation by trapping hot carriers in a sidewall; a first negative voltage generating unit configured to generate a first negative voltage to be applied to a gate of the memory element when erasing the memory element; a second negative voltage generating unit configured to generate a second negative voltage to be applied to a back gate of the memory element during the erase; The configuration is provided with the following. Effect of the Invention

[0008] According to the nonvolatile memory device according to the present disclosure, erasing can be performed on the memory elements more efficiently. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of voltage application to a memory element during programming according to a comparative example. [Diagram 2] FIG. 2 is a cross-sectional view of the vertical structure of a memory element corresponding to FIG. [Diagram 3] FIG. 3 is a diagram showing an example of voltage application to a memory element during erasing according to a comparative example. [Figure 4] FIG. 4 is a cross-sectional view of the vertical structure of a memory element corresponding to FIG. [Diagram 5] FIG. 5 is a diagram showing an example of voltage application to a memory element during erasing according to the present disclosure. [Figure 6] FIG. 6 is a cross-sectional view of the vertical structure of a memory element corresponding to FIG. [Figure 7]FIG. 7 is a graph showing an example of the relationship between the gate voltage and the drain current in each of the initial state, the erased state, and the programmed state. [Figure 8] FIG. 8 is a diagram showing a configuration of the nonvolatile memory device according to the first embodiment. [Figure 9] FIG. 9 is a timing chart showing an example of a drive signal in the charge pump. [Figure 10] FIG. 10 is a diagram showing schematic examples of waveforms of a positive voltage, a negative voltage, and a back gate voltage during programming and erasing, respectively. [Figure 11] FIG. 11 is a diagram showing a configuration of a nonvolatile memory device according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing a configuration of a nonvolatile memory device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Exemplary embodiments will now be described with reference to the drawings. Note that the non-volatile memory device described below may be configured as a semiconductor integrated circuit.

[0011] <1. How to erase> 1 is a diagram showing voltage application to a memory element MT during programming in a comparative example. The memory element MT is composed of an NMOS transistor (N-channel MOSFET (metal-oxide-semiconductor field-effect transistor)). FIG 2 is a vertical structural cross-sectional view of the memory element MT corresponding to FIG 1.

[0012] In the memory element MT, a gate voltage Vg can be applied to the gate, a drain voltage Vd to the drain, a source voltage Vs to the source, and a back gate voltage Vgt to the back gate. As shown in Figures 1 and 2, during programming, Vg=high voltage (e.g., +5V), Vs=high voltage (e.g., +5V), Vd=0V, and Vgt=0V are applied.

[0013] Such voltage application generates hot carriers (electrons) that flow from the drain D to the source S directly below the gate G, as shown by the arrow in Fig. 2. The hot carriers are attracted to the high voltage (positive voltage) applied to the gate G, and are trapped in the sidewall SSw on the source S side provided along the side of the gate G (trapped hot carriers E are shown in Fig. 2).

[0014] On the other hand, Fig. 3 is a diagram showing voltage application to the memory element MT during erasing in a comparative example. Fig. 2 is a vertical structure cross-sectional view of the memory element MT corresponding to Fig. 3 in Fig. 4. As shown in Figs. 3 and 4, during erasing, Vg=first negative voltage (e.g., -7V), Vs=high voltage (e.g., +5V), Vd=0V, and Vgt=0V are applied.

[0015] By applying such a voltage, hot carriers E are pulled out from the sidewall SSw as indicated by the arrows in FIG.

[0016] Here, the upper part of FIG. 7 is a graph showing an example of the relationship between the gate voltage Vg and the drain current Ids in the initial state (Ini) of the memory element MT, the erased state (ERS) according to the comparative example, and the programmed state (PRG) according to the comparative example. Thus, when programming is performed, Vth (threshold voltage) becomes higher than in the initial state, and the drain current Ids becomes less likely to flow for the same gate voltage Vg. However, even if erasing is performed from the programmed state, the erased state does not return to the initial state. This is because hot carriers are not sufficiently extracted from the sidewall.

[0017] Therefore, as an embodiment of the present disclosure, the following voltages are applied to the memory element MT during erasing. FIG. 5 is a diagram showing voltage application to the memory element MT during erasing according to an exemplary embodiment of the present disclosure. FIG. 6 is a vertical structure cross-sectional view of the memory element MT corresponding to FIG. 5. As shown in FIGS. 5 and 6, during erasing, Vg=first negative voltage (e.g., −7V), Vs=high voltage (e.g., +5V), Vd=0V, and Vgt=second negative voltage (e.g., −2V) are applied. That is, a difference from the above comparative example is that a negative voltage bias is applied to the back gate.

[0018] The lower part of FIG. 7 is a graph showing an example of the relationship between the gate voltage Vg and the drain current Ids in the initial state (Ini) of the memory element MT, the erased state (ERS) according to the present disclosure, and the programmed state (PRG) according to the comparative example. As described above, it can be seen that the erased state is closer to the initial state by the erase according to the present disclosure. This is because hot carriers are sufficiently extracted from the sidewall by applying a negative voltage bias to the back gate. Thus, the voltage application during the erase according to the present disclosure allows the erase to be performed more efficiently.

[0019] 2. First embodiment A more specific embodiment of the present disclosure will be described below. Fig. 8 is a diagram showing the configuration of a nonvolatile memory device 1 according to a first embodiment of the present disclosure. Note that the specific voltage values ​​described below are merely examples.

[0020] <2-1. Data element> The nonvolatile memory device 1 includes a first data element Md1, a second data element Md2, and a sense amplifier SAP.

[0021] The first data element Md1 and the second data element Md2 each have the same configuration as the memory element MT described above. By setting one of the first data element Md1 and the second data element Md2 to the program state and the other to the erase state, a difference in Vth is created between the first data element Md1 and the second data element Md2, and the drain current flowing through the data element set to the program state becomes smaller.

[0022] For example, when the first data element Md1 is in the program state and the second data element Md2 is in the erase state, the drain current Ids1 flowing through the first data element Md1 and the drain current Ids2 flowing through the second data element Md2 satisfy Ids1 < Ids2, indicating that the data "0" is stored. On the other hand, when the first data element Md1 is in the erase state and the second data element Md2 is in the program state, Ids1 > Ids2, indicating that the data "1" is stored. The sense amplifier SAP can read the data by detecting such a magnitude relationship of the drain currents. Note that the voltage application method during readout will be described later.

[0023] <2-2. First Negative Voltage Generation Unit> As shown in FIG. 8, the non-volatile memory device 1 includes a first negative voltage generation unit 101. The first negative voltage generation unit 101 is a circuit for generating a first negative voltage Vm1 to be applied to each gate of the data elements Md1 and Md2 during erasure. The first negative voltage Vm1 is generated on the line Ln1 where the negative voltage VM is generated.

[0024] The first negative voltage generation unit 101 includes a constant current source 2, a capacitor 3, an error amplifier 4, a charge pump 5, a switch 6, a drive signal generation unit 7, and resistors R1 to R4.

[0025] One end of the capacitor 3 is connected to the application terminal of the reference voltage VREF. The constant current source 2 is connected between the other end of the capacitor 3 and the application terminal of the ground potential (GND). The other end of the capacitor 3 is connected to the first inverting input terminal (-) of the error amplifier 4.

[0026] The resistors R1 and R2 are connected in series between a reference voltage VREF and a terminal to which a ground potential is applied. Here, VREF is +2 V, for example. A power supply voltage VDD, which will be described later, is greater than VREF, and VDD is +5 V, for example.

[0027] A node N1 to which the resistors R1 and R2 are connected is connected to a second inverting input terminal (−) of the error amplifier 4.

[0028] The resistors R3 and R4 are connected in series between the application terminal of the reference voltage VREF and the application terminal of the negative voltage VM. A node N2 to which the resistors R3 and R4 are connected is connected to the non-inverting input terminal (+) of the error amplifier 4. The error amplifier 4 is supplied with a power supply voltage VDD.

[0029] The charge pump 5 is an example of a negative boost circuit. The charge pump 5 includes inverters 5A to 5E, capacitors 5F to 5J, and NMOS transistors 5K to 5M. The output terminal of the inverter 5A is connected to the gate of the NMOS transistor 5K via a capacitor 5F. The drain of the NMOS transistor 5K is connected to an application terminal of the ground potential. The output terminal of the inverter 5B is connected to the source of the NMOS transistor 5K via a capacitor 5I. The source of the NMOS transistor 5K is connected to the drain of the NMOS transistor 5L. The output terminal of the inverter 5C is connected to the gate of the NMOS transistor 5L via a capacitor 5G. The output terminal of the inverter 5D is connected to the source of the NMOS transistor 5L via a capacitor 5J. The source of the NMOS transistor 5L is connected to the drain of the NMOS transistor 5M. The output terminal of the inverter 5E is connected to the gate of the NMOS transistor 5M via a capacitor 5H. The source of the NMOS transistor 5M is connected to an application terminal of the negative voltage VM.

[0030] Capacitors 5F, 5G, and 5H are used for level shifting for switching of NMOS transistors 5K, 5L, and 5M. The output of the error amplifier 4 is supplied to inverters 5A to 5E. The inverters 5A to 5E are driven based on a drive signal output from a drive signal generating unit 7.

[0031] FIG. 9 is a timing chart showing an example of the drive signals SA to SE output from each of the inverters 5A to 5C. The drive signals SA to SE are pulse signals. As shown in FIG. 9, when the drive signals SA, SE, and SC are at a low level and the transistors 5K, 5M, and 5L are in an off state, the drive signal SB switches to a high level and the drive signal SD switches to a low level. Then, the drive signals SA and SE switch to a high level, and the transistors 5K and 5M are in an on state. As a result, a charge is accumulated in the capacitor 5I, and a negative voltage VM is output from the capacitor 5J. Then, the drive signals SA and SE switch to a low level, and the transistors 5K and 5M are in an off state. Then, the drive signal SB switches to a low level and the drive signal SD switches to a high level. Then, the drive signal SC switches to a high level, and the transistor 5L is in an on state. As a result, a charge is accumulated in the capacitor 5J. Then, the drive signal SC switches to a low level, and the transistor 5L is in an off state. The output of the error amplifier 4 is negatively boosted to generate VM=a first negative voltage Vm1. In the configuration of the charge pump 5 shown in Fig. 8, the output of the error amplifier 4 is negatively boosted by 2. However, the negative boost factor of the charge pump is not limited to 2. Also, the charge pump is not limited to the synchronous rectification type shown in Fig. 8, and may be configured using diodes.

[0032] The switch 6 is composed of an NMOS transistor. The switch 6 is connected between an application terminal of the ground potential and an application terminal of the negative voltage VM. The switch 6 can be switched between an on state and an off state. By turning the switch 6 on, the negative voltage VM can be set to 0V. At this time, the charge pump 5 is in a stopped state.

[0033] <2-3. Second negative voltage generating unit> 8, the nonvolatile memory device 1 includes a second negative voltage generation unit 102. The second negative voltage generation unit 102 is a circuit for generating a second negative voltage Vm2 as the back gate voltage Vgt to be applied to each back gate of the data elements Md1 and Md2 during erasing.

[0034] The second negative voltage generating unit 102 includes an error amplifier 8, resistors R11 to R14, and a switch SW1. The resistors R11 and R12 are connected in series between an application terminal of the reference voltage VREF and an application terminal of the ground potential. A node N11 to which the resistors R11 and R12 are connected is connected to a non-inverting input terminal of the error amplifier 8. The switch SW1 is connected between the application terminal of the reference voltage VREF and the node N11.

[0035] The resistors R13 and R14 are connected in series between the application terminal of the reference voltage VREF and the output terminal of the error amplifier 8. A node N12 to which the resistors R13 and R14 are connected is connected to the inverting input terminal of the error amplifier 8. A power supply voltage VDD and a negative voltage VM are supplied to the error amplifier 8. A backgate voltage Vgt is output from the output terminal of the error amplifier 8.

[0036] <2-3. Gate voltage generation section> 8, the nonvolatile memory device 1 includes a gate voltage generating unit 103. The gate voltage generating unit 103 is a circuit for generating a gate voltage Vgt to be applied to each gate of the data elements Md1, Md2.

[0037] The gate voltage generating unit 103 includes an error amplifier 9, a capacitor 10, a switch 11, and resistors R21 to R24. The resistors R21 and R22 are connected in series between an application terminal of the reference voltage VREF and an application terminal of the ground potential. A node N21 to which the resistors R21 and R22 are connected is connected to the non-inverting input terminal of the error amplifier 9.

[0038] Resistors R23 and R24 are connected in series between the application terminal of the positive voltage VP and the application terminal of the ground potential. A node N22 to which the resistors R23 and R24 are connected is connected to the inverting input terminal of the error amplifier 9. A switch SW2 is connected between the application terminal of the positive voltage VP and the node N22. The output terminal of the error amplifier 9 is connected to the application terminal of the positive voltage VP. The error amplifier 9 is supplied with a power supply voltage VDD.

[0039] The switch 11 is composed of an NMOS transistor. The switch 11 is connected between an application terminal of a positive voltage VP and an application terminal of a ground potential. The switch 11 can be switched between an on state and an off state. When the switch 11 is in the on state, the positive voltage VP can be set to the ground potential.

[0040] <2-4. Level shifter> The nonvolatile memory device 1 includes a level shifter LS. A positive voltage VP and a negative voltage VM are applied to the level shifter LS. The level shifter LS level-shifts an input signal Sin and outputs a gate voltage Vg. When the input signal Sin is at a high level, the gate voltage Vg is a positive voltage VP, and when the input signal Sin is at a low level, the gate voltage Vg is a negative voltage VM.

[0041] <2-5. Switch> The nonvolatile memory device 1 includes switches S1, S2, S3, and S4. The switch S1 is connected between the sources of the data elements Md1 and Md2 and a terminal to which a ground potential is applied. The switch S2 is connected between the sources of the data elements Md1 and Md2 and a terminal to which a power supply voltage VDD is applied. The switch S3 is connected between the drain of the data element Md1 and a terminal to which a ground potential is applied. The switch S4 is connected between the drain of the data element Md2 and a terminal to which a ground potential is applied.

[0042] <2-6. Programming Operation> Here, there will be described an operation during programming in the nonvolatile memory device 1. The upper part of Fig. 10 is a diagram showing schematic waveforms of the positive voltage VP, the negative voltage VM, and the back gate voltage Vgt during programming.

[0043] During programming, the switch 11 is in the off state, and the switch SW2 is in the off state. As a result, the feedback voltage Vfb3 generated at the node N22 is fixed to 0V, the error amplifier 9 is in the full-on state, and the positive voltage VP output from the error amplifier 9 is fixed to the power supply voltage VDD. In this case, since the input signal Sin is at a high level, VP=VDD is output from the level shifter LS as the gate voltage Vg. In other words, the power supply voltage VDD (=+5V) is applied to each gate of the data elements Md1 and Md2.

[0044] During programming, the switch 6 is on and the negative voltage VM is set to 0 V. The switch SW1 is off and the reference voltage Ref2 generated at the node N11 is set to 0 V. As a result, the backgate voltage Vgt output from the error amplifier 8 is set to 0 V. Note that when the error amplifier 8 is stopped and the output of the error amplifier 8 is fixed to a low level, the switch SW1 does not need to be provided.

[0045] During programming, switch S2 is turned on and power supply voltage VDD is applied to the sources of data elements Md1 and Md2. At this time, switch S3 or S4 corresponding to the data element Md1 or Md2 to be programmed is turned on and 0 V is applied to the drain. Switch S3 or S4 corresponding to the data element not to be programmed is off.

[0046] As a result of the above, the voltage application state as shown in FIG. 1 and FIG. 2 can be achieved, making programming possible.

[0047] <2-7. Operation when erasing> Next, a description will be given of the erase operation in the nonvolatile memory device 1. The lower part of Fig. 10 is a diagram showing schematic waveforms of the positive voltage VP, the negative voltage VM, and the back gate voltage Vgt during the erase operation.

[0048] During the erase operation, the switch 6 is in an off state and the charge pump 5 is active. Initially, the soft start voltage Vsf generated at the other end of the capacitor 3 is decreased in a ramp-like manner from the reference voltage VREF by the constant current source 2. The error amplifier 4 amplifies the difference between the higher of the voltages input to the two inverting input terminals and the feedback voltage Vfb1 generated at the node N2 by dividing the voltage difference between the reference voltage VREF and the negative voltage VM by the resistors R3 and R4. Initially, the soft start voltage Vsf is higher than the reference voltage Ref1 generated at the node N1 by dividing the reference voltage VREF by the voltage dividing resistors R1 and R2, so the negative voltage VM is controlled so that the feedback voltage Vfb coincides with the soft start voltage Vsf. As a result, the negative voltage VM gradually decreases as shown in the lower part of FIG. 10.

[0049] On the other hand, during erasing, the switch SW1 is in an on state, and in the second negative voltage generating unit 102, the feedback voltage Vfb2 generated at the node N12 by dividing the voltage difference between the reference voltage VREF and the output (backgate voltage Vgt) of the error amplifier 8 by the resistors R13 and R14 is controlled so as to match the reference voltage Ref2 generated at the node N11 by dividing the reference voltage VREF by the resistors R11 and R12. Initially, the backgate voltage Vgt matches the decreasing negative voltage VM.

[0050] The second negative voltage Vm2, which is the target value for controlling the backgate voltage Vgt, is determined by the reference voltage Ref2 and resistors R13 and R14. The second negative voltage Vm2 is set to -2V, for example. When the negative voltage VM drops and falls below the second negative voltage Vm2, the backgate voltage Vgt is controlled to the second negative voltage Vm2 and becomes constant. After that, the negative voltage VM continues to drop.

[0051] The first negative voltage Vm1, which is the target value for controlling the negative voltage VM, is determined by the reference voltage Ref1 and resistors R3 and R4, and is set to -7 V as an example. When the soft-start voltage Vsf falls below the reference voltage Ref1, the error amplifier 4 amplifies the difference between the reference voltage Ref1 and the feedback voltage Vfb1. As a result, the feedback voltage Vfb1 is controlled to match the reference voltage Ref1, and the negative voltage VM is controlled to be constant at the first negative voltage Vm1.

[0052] As described above, the back gate voltage Vgt controlled to the second negative voltage Vm2 (=-2V) is applied to each back gate of the data elements Md1, Md2. Also, since the input signal Sin is at a low level, the level shifter LS outputs the negative voltage VM controlled to the first negative voltage Vm1 (=-7V) as the gate voltage Vg. That is, the first negative voltage Vm1 is applied to each gate of the data elements Md1, Md2.

[0053] During erasing, the switch 11 is turned on, and the positive voltage VP becomes 0 V. This suppresses the voltage applied to the level shifter LS when controlled to VM=Vm1, thereby making it possible to lower the withstand voltage.

[0054] During erasing, a voltage is applied to the sources and drains of data elements Md1 and Md2 in the same manner as during programming.

[0055] As a result, the voltage application state shown in FIG. 5 and FIG. 6 can be achieved, enabling efficient erasing.

[0056] <2-8. Read operation> Next, the operation of the nonvolatile memory device 1 during reading will be described. During reading, as during programming, VM=Vgt=0V is controlled. Furthermore, since the switch 11 is in the off state and the switch SW2 is in the on state, the feedback voltage Vfb3 is controlled to match the reference voltage Ref3 generated at the node N21 by dividing the reference voltage VREF by the resistors R21 and R22. As a result, the positive voltage VP output from the error amplifier 9 is controlled to the read voltage Vrd defined by the reference voltage Ref3 and the resistors R23 and R24. The read voltage Vrd is, for example, +2V.

[0057] During reading, since the input signal Sin is at a high level, the level shifter LS outputs a gate voltage Vg as a positive voltage VP=Vrd, that is, the read voltage Vrd is applied to each gate of the data elements Md1 and Md2.

[0058] During reading, the switch S1 is on, the switch S2 is off, and the switches S11 and S12 are off, causing 0V to be applied to the sources of the data elements Md1 and Md2.

[0059] The voltage application state is controlled in this manner, and data can be read from the data elements Md1 and Md2 by the sense amplifier SAP.

[0060] 3. Second embodiment 11 is a diagram showing a configuration of a nonvolatile memory device 1X according to a second embodiment of the present disclosure. The nonvolatile memory device 1X differs from the first embodiment (FIG. 8) in the configuration of a first negative voltage generating unit 101.

[0061] Specifically, the first negative voltage generation unit 101 has a configuration excluding the charge pump 5 in FIG. 8 described above, and a negative voltage VM1 supplied from the outside as the lower power supply of the error amplifier 4 is used. Also, the output terminal of the error amplifier 4 is connected to one end of the resistor R4 on the side opposite to the node N2 side. A negative voltage VM2 is output from the error amplifier 4. The negative voltage VM2 serves as the lower power supply of the error amplifier 8 via the line Ln1. In this embodiment, since the charge pump is not provided in the non-volatile memory device 1X in this way, the circuit area can be reduced.

[0062] VM1 < VM2. For example, when VM1 = -10V, VM2 = -7V. Note that, instead of the negative voltage VM2, the negative voltage VM1 may be used as the lower power supply of the error amplifier 8.

[0063] Note that during erasure, the switch 6 is in the off state. Also, during programming and reading, the switch 6 is in the on state. Thereby, during programming and reading, VM2 = 0V, and the voltage applied to the level shifter LS can be suppressed.

[0064] <4. Third Embodiment> FIG. 12 is a diagram showing the configuration of a non-volatile memory device 1Y according to the third embodiment of the present disclosure. The difference from the first embodiment (FIG. 8) of the non-volatile memory device 1Y is the configuration of the gate voltage generation unit 103. Also, a buffer BF is provided.

[0065] The gate voltage generation unit 103 includes a PMOS transistor (P-channel MOSFET) P1, inverters IV1 and IV2, a parasitic capacitance C1, and a capacitor C2. The capacitance of the capacitor C2 is sufficiently larger than the parasitic capacitance C1.

[0066] One end of a parasitic capacitance C1 and one end of a capacitor C2 are connected to the source of the PMOS transistor P1. A clock signal CLK is input to an inverter IV1 together with the gate of the PMOS transistor P1. The output of the inverter IV1 is input to an inverter IV2. The output of the inverter IV2 is applied to the other end of the capacitor C2. An internal voltage VREG is applied to the drain of the PMOS transistor P1. The internal voltage VREG is used as the upper power supply for the inverters IV1 and IV2. A ground potential is used as the lower power supply for the inverters IV1 and IV2. An output voltage Vo is generated at the source of the PMOS transistor P1.

[0067] The output voltage Vo and the ground potential are supplied to the buffer BF. Depending on the input signal Sin2 input to the buffer BF, the output voltage Vo or the ground potential is output from the buffer BF as a positive voltage VP.

[0068] The clock signal CLK is a pulse signal consisting of a high level and a low level. When the clock signal CLK is at a low level, the PMOS transistor P1 is turned on, and the internal voltage VREG is applied to the source of the PMOS transistor P1, i.e., one end of the capacitor C2. At this time, the ground potential output from the inverter IV2 is applied to the other end of the capacitor C2. As a result, VREG is applied across the two ends of the capacitor C2, and the capacitor C2 is charged. After that, when the clock signal CLK becomes a high level, the PMOS transistor P1 is turned off, and the VREG output from the inverter IV2 is applied to the other end of the capacitor C2. As a result, the output voltage Vo=VREG+VREG=2×VREG.

[0069] During programming, an output voltage Vo (=2×VREG) is generated by the above-mentioned bootstrap configuration. At this time, the output voltage Vo is output from the buffer BF as a positive voltage VP, and the positive voltage VP is used as the gate voltage Vg. Such a bootstrap configuration is effective when the programming time is short. Note that during programming, one cycle consisting of low and high levels in the clock signal CLK may be generated only once, or one cycle may be repeated. If the amount of drop in the output voltage Vo during the high level period when only one cycle is generated, the drop in the output voltage Vo may be suppressed by repeating one cycle to repeat short high level periods.

[0070] During reading, the clock signal CLK is maintained at a low level, the output voltage Vo=VREG, and the gate voltage Vg=VREG via the buffer BF.

[0071] <5.Other> In addition to the above-mentioned embodiment, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-mentioned embodiment, but should be understood to include all modifications that fall within the meaning and scope equivalent to the scope of the claims.

[0072] <6. Notes> As described above, for example, the nonvolatile memory device (1) according to the present disclosure has: A memory element (Md1, Md2) capable of performing a program operation by trapping hot carriers in a sidewall; a first negative voltage generating unit (101) configured to generate a first negative voltage (Vm1) to be applied to a gate of the memory element when erasing the memory element; a second negative voltage generating unit (102) configured to generate a second negative voltage (Vm2) to be applied to a back gate of the memory element during the erase; (First configuration).

[0073] In the first configuration, the first negative voltage generating unit (101) a first voltage dividing resistor (R3, R4) connected in series between an application terminal of a first reference voltage (VREF) and an application terminal of a negative voltage (VM); a first error amplifier (4) including a first input terminal connected to an application terminal of a second reference voltage (Ref1) and a second input terminal connected to a first connection node (N2) of the first voltage dividing resistor; a boost circuit (5) configured to negatively boost the output of the first error amplifier; having The first negative voltage output from the boost circuit may be generated at an application terminal of the negative voltage (second configuration).

[0074] In the second configuration, the boost circuit (5) may be configured as a charge pump (third configuration).

[0075] In the second or third configuration, the first error amplifier (4) has a third input terminal, A soft-start voltage (Vsf) that drops in a ramp shape may be applied to the third input terminal (fourth configuration).

[0076] In the first configuration, the first negative voltage generating unit (101) is configured to generate the first negative voltage (VM2) from a first input voltage (VM1) that is input from an outside as a negative voltage, The first input voltage may be lower than the first negative voltage (fifth configuration).

[0077] In the fifth configuration, the second negative voltage generating unit (102) may be configured to generate the second negative voltage using the first negative voltage (VM2) as a power supply (sixth configuration).

[0078] In any one of the first to sixth configurations, the second negative voltage generating unit (102) A second error amplifier (8); a second voltage dividing resistor (R13, R14) connected in series between an application terminal of a third reference voltage (VREF) and an output terminal of the second error amplifier; having A first input terminal of the second error amplifier is connected to an application terminal of a fourth reference voltage (Ref2); a second input terminal of the second error amplifier is connected to a second connection node (N12) of the second voltage dividing resistor; The second error amplifier may be configured to be capable of receiving the first negative voltage (seventh configuration).

[0079] In the seventh configuration, the first negative voltage generating unit (101) has a first switch (6) connected between a first line (Ln1) on which the first negative voltage is generated and a terminal to which a ground potential is applied, The first switch may be in an on state when the memory element is programmed (eighth configuration).

[0080] In the eighth configuration, the second negative voltage generating unit (102) a third voltage dividing resistor (R11, R12) connected between the application terminal of the third reference voltage and the application terminal of the ground potential; a second switch (SW1) connected between the application terminal of the third reference voltage and a third connection node (N11) of the third voltage dividing resistor; having During the programming, the second switch may be in an off state (ninth configuration).

[0081] In any one of the first to ninth configurations, a gate voltage generating unit (103) for generating a gate voltage (Vg) to be applied to the gate of the memory element; a level shifter (LS) for outputting, as the gate voltage, either the positive voltage (VP) generated by the gate voltage generating unit or a voltage of a second line (Ln1) on which the first negative voltage is generated, in response to a first input signal (Sin); It may further comprise the following (tenth configuration).

[0082] In the tenth configuration, the gate voltage generating unit (103) has a third switch (11) connected between an application terminal of the positive voltage (VP) and an application terminal of a ground potential, The third switch may be in an on state during the erasing (eleventh configuration).

[0083] In the tenth or eleventh configuration, the gate voltage generating unit (103) a third error amplifier (9) including an output terminal connected to the application terminal of the positive voltage (VP); a fourth voltage dividing resistor (R23, R24) connected in series between the application terminal of the positive voltage and the application terminal of the ground potential; a fourth switch (SW2) connected between the application terminal of the positive voltage and a fourth connection node (N22) of the fourth voltage dividing resistor; having A first input terminal of the third error amplifier is connected to an application terminal of a fifth reference voltage (Ref3); a second input terminal of the third error amplifier is connected to the fourth connection node; The third error amplifier can be supplied with a first power supply voltage (VDD); When the memory element is read, the fourth switch is in an on state. The fourth switch may be in an off state when the memory element is being programmed (twelfth configuration).

[0084] In the tenth or eleventh configuration, the gate voltage generating unit (103) includes: a switch (P1) connected between an output terminal of the gate voltage generating unit and an application terminal of a second power supply voltage (VREG); an inverter (IV2) to which the second power supply voltage and a ground potential are supplied; a capacitor (C2) including a first terminal connected to the output terminal of the gate voltage generating unit and a second terminal connected to the output terminal of the inverter; having When the clock signal (CLK) is at a first level, the switch is in an on state and the output of the inverter is at ground potential. When the clock signal is at a second level, the switch may be in an off state, and the output of the inverter may be the second power supply voltage (a thirteenth configuration).

[0085] In addition, in any of the tenth to thirteenth configurations, the configuration may further include a buffer (BF) that outputs either the output voltage (Vo) of the gate voltage generating unit or a ground potential as the positive voltage in response to a second input signal (Sin2) (a fourteenth configuration). [Industrial Applicability]

[0086] The present disclosure can be used, for example, in nonvolatile memory devices mounted on various semiconductor devices. [Explanation of symbols]

[0087] 1,1X,1Y non-volatile memory device 2 constant current source 3. Capacitor 4 Error Amplifier 5 Charge Pump 5A~5E Inverter 5F~5J capacitor 5K~5M NMOS transistor 6 Switch 7. Drive signal generator 8 Error Amplifier 9 Error Amplifier 10 Capacitor 11 Switch 12,13 LDO 14 LDO 14A Error Amplifier 14B Output transistor 14C~14F resistance 15. Bootstrap 15A High Side Transistor 15B Low Side Transistor 15C High Side Driver 15D Low Side Driver 15E Capacitor 15F Diode 101 First negative voltage generating unit 102 Second negative voltage generating unit 103 Gate voltage generator BF Buffer C1 parasitic capacitance C2 Capacitor E Hot Carrier IV1,IV2 inverter LS Level Shifter MT memory element Md1 First data element Md2 Second data element P1 PMOS transistor R1~R4 resistance R11~R14 Resistors R21~R24 Resistor R23 resistance S1, S2, S11, S12 Switches SAP Sense Amplifier SSw Sidewall SW1, SW2 switches

Claims

1. A memory element capable of performing a program operation by trapping hot carriers in a sidewall; a first negative voltage generating unit configured to generate a first negative voltage to be applied to a gate of the memory element when erasing the memory element; a second negative voltage generating unit configured to generate a second negative voltage to be applied to a back gate of the memory element during the erase; A non-volatile memory device comprising:

2. The first negative voltage generating unit is a first voltage dividing resistor connected in series between the application terminal of the first reference voltage and the application terminal of the negative voltage; a first error amplifier including a first input terminal connected to an application terminal of a second reference voltage and a second input terminal connected to a first connection node of the first voltage dividing resistor; a boost circuit configured to negatively boost an output of the first error amplifier; having The non-volatile memory device according to claim 1 , wherein the first negative voltage output from the boost circuit is generated at an application terminal of the negative voltage.

3. The non-volatile memory device of claim 2 , wherein the boost circuit is configured as a charge pump.

4. the first error amplifier has a third input terminal; 3. The non-volatile memory device of claim 2, wherein a soft-start voltage that drops in a ramp pattern is applicable to the third input terminal.

5. the first negative voltage generating unit is configured to generate the first negative voltage from a first input voltage that is input from an outside as a negative voltage; The non-volatile memory device of claim 1 , wherein the first input voltage is lower than the first negative voltage.

6. The non-volatile memory device of claim 5 , wherein the second negative voltage generating unit is configured to generate the second negative voltage using the first negative voltage as a power supply.

7. The second negative voltage generating unit is A second error amplifier; a second voltage dividing resistor connected in series between an application terminal of a third reference voltage and an output terminal of the second error amplifier; having a first input terminal of the second error amplifier is connected to a fourth reference voltage application terminal; a second input end of the second error amplifier is connected to a second connection node of the second voltage dividing resistor; The non-volatile memory device of claim 1 , wherein the first negative voltage is supplied to the second error amplifier.

8. the first negative voltage generating unit has a first switch connected between a first line on which the first negative voltage is generated and an application terminal of a ground potential; The non-volatile memory device of claim 7 , wherein the first switch is in an on state when the memory element is being programmed.

9. The second negative voltage generating unit is a third voltage dividing resistor connected between an application terminal of the third reference voltage and an application terminal of a ground potential; a second switch connected between the application terminal of the third reference voltage and a third connection node of the third voltage dividing resistor; having The non-volatile memory device of claim 8 , wherein the second switch is in an off state during the programming.

10. a gate voltage generator for generating a gate voltage to be applied to a gate of the memory element; a level shifter that outputs, as the gate voltage, one of the positive voltage generated by the gate voltage generating unit and a voltage of a second line on which the first negative voltage is generated in response to an input signal; The non-volatile memory device of claim 1 further comprising:

11. the gate voltage generating unit has a third switch connected between an application terminal of the positive voltage and an application terminal of a ground potential, The nonvolatile memory device of claim 10 , wherein the third switch is in an on state during the erase operation.

12. The gate voltage generating unit is a third error amplifier including an output terminal connected to the application terminal of the positive voltage; a fourth voltage dividing resistor connected in series between the positive voltage application terminal and the ground potential application terminal; a fourth switch connected between the application terminal of the positive voltage and a fourth connection node of the fourth voltage dividing resistor; having a first input terminal of the third error amplifier is connected to a fifth reference voltage application terminal; a second input terminal of the third error amplifier is connected to the fourth connection node; The third error amplifier can be supplied with a first power supply voltage. When the memory element is read, the fourth switch is in an on state. The non-volatile memory device of claim 10 , wherein the fourth switch is in an off state when the memory element is being programmed.

13. The gate voltage generating unit includes a switch connected between an output terminal of the gate voltage generating unit and an application terminal of a second power supply voltage; an inverter to which the second power supply voltage and a ground potential are supplied; a capacitor including a first terminal connected to the output terminal of the gate voltage generating unit and a second terminal connected to the output terminal of the inverter; having When the clock signal is at a first level, the switch is in an on state and the output of the inverter is at ground potential; 11. The non-volatile memory device of claim 10, wherein when the clock signal is at a second level, the switch is in an off state and the output of the inverter is the second power supply voltage.

14. The non-volatile memory device of claim 10 , further comprising a buffer configured to output one of an output voltage of the gate voltage generating unit and a ground potential as the positive voltage in response to a second input signal.

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