Image sensor

Abstract

To provide an image sensor that can reduce light loss and ensure Auto Focus (AF) separation ratio.SOLUTION: An image sensor according to one embodiment includes a substrate that includes a first surface into which light enters and a second surface that is opposite the first surface, a pixel separation pattern defining adjacent unit pixels in the substrate, first and second photoelectric conversion layers arranged along a first direction in the pixel separation pattern, a first separation pattern defining the first and second photoelectric conversion layers in the substrate between the first and second photoelectric conversion layers, a first grid pattern placed on top of the pixel separation pattern, and a second grid pattern arranged on the first separation pattern and having a height lower than the height of the first grid pattern.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The technical idea of ​​the present disclosure relates to an image sensor, and more particularly, to an image sensor with reduced light loss. [Background technology]

[0002] An image sensor is a device that converts an optical image into an electrical signal. The image sensor can be classified into a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor (CIS) realized by a CMOS process. The CMOS image sensor can be abbreviated as CIS (CMOS Image Sensor).

[0003] The CIS can read image information by converting optical energy into electrical energy. Specifically, the CIS can be a device developed to transmit CMOS digital signals, unlike the CCD image sensor which transmits electric charges, by converting analog image signals received through a lens into electrical image signals.

[0004] More specifically, the CIS includes a plurality of pixels arranged two-dimensionally, and a plurality of transistors are used for each pixel, and a signal charge generated in a photodiode is converted into a voltage within each pixel and then output. Since such a CIS can be manufactured using the existing commercially available CMOS technology, research into an easy-to-manufacture CIS is currently being actively conducted.

[0005] In manufacturing the CIS, one pixel has a structure including two or more photodiodes, and light entering through a color filter is absorbed in a polysilicon region of a deep trench isolation (DTI), causing optical loss. Summary of the Invention [Problem to be solved by the invention]

[0006] The technical problem that the present disclosure seeks to solve is to provide an image sensor with reduced light loss.

[0007] Another technical problem to be solved by the present disclosure is to provide an image sensor that can ensure an auto focus (AF) separation ratio in addition to the above-mentioned advantages. [Means for solving the problem]

[0008] According to one embodiment of the present disclosure, an image sensor may include a substrate having a first surface onto which light is incident and a second surface opposite to the first surface; a pixel separation pattern within the substrate defining adjacent unit pixels; a first photoelectric conversion layer and a second photoelectric conversion layer arranged along a first direction within the pixel separation pattern; a first separation pattern within the substrate between the first photoelectric conversion layer and the second photoelectric conversion layer defining the first photoelectric conversion layer and the second photoelectric conversion layer; a first grid pattern disposed on the pixel separation pattern; and a second grid pattern disposed on the first separation pattern and having a height lower than a height of the first grid pattern.

[0009] In one embodiment, the height of the second grid pattern may satisfy a range of 1 / 10 to 1 / 4 of the height of the first grid pattern.

[0010] In one embodiment, a first color filter may be disposed over the first grid pattern and the second grid pattern and have a refractive index higher than that of the second grid pattern.

[0011] In one embodiment, the refractive index of the second grid pattern with respect to the refractive index of the first color filter disposed on the second grid pattern may satisfy 0.40 to 0.95, and in another embodiment, the refractive index of the second grid pattern may satisfy 1.0 to 1.6.

[0012] In one embodiment, the first grid pattern can include a lower first grid pattern and an upper first grid pattern disposed above the lower first grid pattern.

[0013] In one embodiment, the lower first grid pattern and the lower second grid pattern may have the same height.

[0014] In one embodiment, the lower first grid pattern and the upper first grid pattern can comprise different materials.

[0015] In one embodiment, the unit pixel further includes a third photoelectric conversion layer arranged adjacent to the first photoelectric conversion layer in the second direction, and a fourth photoelectric conversion layer arranged adjacent to the second photoelectric conversion layer in the second direction, and the third photoelectric conversion layer and the fourth photoelectric conversion layer can be defined by the first separation pattern.

[0016] In one embodiment, the first isolated pattern may be composed of a first isolated sub-pattern and a second isolated sub-pattern spaced apart by a predetermined distance.

[0017] In one embodiment, the second grid pattern may be larger than or equal to the area of ​​the first and second sub-isolated patterns.

[0018] In one embodiment, another unit pixel arranged at a distance from the unit pixel may include a first photoelectric conversion layer and a second photoelectric conversion layer arranged along a first direction within the pixel separation pattern, a first separation pattern defining the first photoelectric conversion layer and the second photoelectric conversion layer within the substrate between the first photoelectric conversion layer and the second photoelectric conversion layer, and a third grid pattern arranged on at least one of the first photoelectric conversion layer and the second photoelectric conversion layer.

[0019] In an embodiment, the third grid pattern may be disposed to completely cover one of the first photoelectric conversion layer and the second photoelectric conversion layer.

[0020] In one embodiment, the first isolated pattern is composed of a first isolated sub-pattern and a second isolated sub-pattern spaced apart by a predetermined distance, and the third grid pattern may be disposed on at least a portion of the first isolated sub-pattern or the second isolated sub-pattern.

[0021] In an embodiment, the third grid pattern may be disposed completely covering the first isolated sub-pattern and the second isolated sub-pattern.

[0022] According to another embodiment of the present disclosure, an image sensor may include a substrate having a first surface onto which light is incident and a second surface opposite to the first surface; a pixel separation pattern within the substrate defining adjacent unit pixels; a first photoelectric conversion layer and a second photoelectric conversion layer arranged along a first direction within the pixel separation pattern; a first separation pattern within the substrate between the first photoelectric conversion layer and the second photoelectric conversion layer defining the first photoelectric conversion layer and the second photoelectric conversion layer; and a third grid pattern disposed on at least one of the first photoelectric conversion layer and the second photoelectric conversion layer.

[0023] In one embodiment, the third grid pattern may cover at least a portion of the second grid pattern.

[0024] In one embodiment, a second grid pattern may be disposed between the first isolated pattern and the third grid pattern.

[0025] According to still another embodiment of the present disclosure, an image sensor includes a substrate including a first surface onto which light is incident and a second surface opposite to the first surface; a pixel separation pattern defining adjacent unit pixels within the substrate; a first photoelectric conversion layer and a second photoelectric conversion layer arranged along a first direction within the pixel separation pattern; a first separation pattern defining the first photoelectric conversion layer and the second photoelectric conversion layer within the substrate between the first photoelectric conversion layer and the second photoelectric conversion layer; a surface insulating film disposed on the pixel separation pattern, the first photoelectric conversion layer, the second photoelectric conversion layer, and the first separation pattern; a first grid pattern disposed on the surface insulating film disposed on the pixel separation pattern; a second grid pattern disposed on the surface insulating film disposed on the first separation pattern, the second grid pattern having a height lower than a height of the first grid pattern; and a color filter disposed on the first grid pattern and the second grid pattern; wherein a height of the second grid pattern may satisfy 1 / 10 to 1 / 4 of a height of the first grid pattern.

[0026] In one embodiment, at least one other unit pixel arranged at a distance from the unit pixel may include a first photoelectric conversion layer and a second photoelectric conversion layer arranged along a first direction within the pixel separation pattern, a first separation pattern defining the first photoelectric conversion layer and the second photoelectric conversion layer within the substrate between the first photoelectric conversion layer and the second photoelectric conversion layer, and a third grid pattern arranged on at least one of the first photoelectric conversion layer and the second photoelectric conversion layer. Effect of the Invention

[0027] According to one embodiment of the present disclosure, an image sensor provides an image sensor with reduced light loss by including a pixel isolation pattern and a first grid pattern and a second grid pattern over an isolation pattern that defines a photoelectric conversion layer.

[0028] According to another embodiment of the present disclosure, an image sensor not only has the above-mentioned advantages, but also provides an image sensor including a unit pixel in which a portion of a photoelectric conversion layer is light-shielded to ensure an auto focus (AF) separation ratio. [Brief description of the drawings]

[0029] [Figure 1] FIG. 1 is an exemplary block diagram of an image sensor according to one embodiment of the present disclosure. [Diagram 2] FIG. 2 is a circuit diagram illustrating a unit pixel area of ​​a pixel array according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is an exploded perspective view of an image sensor according to one embodiment of the present disclosure. [Figure 4] FIG. 2 is an exploded perspective view of an image sensor according to another embodiment of the present disclosure. [Diagram 5] FIG. 2 is an exemplary layout diagram for explaining an image sensor according to an embodiment of the present disclosure. [Figure 6] 6 is a cross-sectional view taken along line AA' of FIG. 5, showing a cross-sectional view of an image sensor according to one embodiment of the present disclosure. [Figure 7a] 7A-7C are enlarged views of various embodiments of the P1 region of FIG. 6. [Figure 7b] 7A-7C are enlarged views of various embodiments of the P1 region of FIG. 6. [Figure 8a] FIG. 7b is a plan view taken along line DD' of FIG. 7a, illustrating a pixel isolation pattern and a first isolation pattern according to one embodiment of the present disclosure. [Figure 8b] FIG. 7b is a plan view taken along line DD' of FIG. 7a, illustrating a pixel isolation pattern and a first isolation pattern according to one embodiment of the present disclosure. [Figure 8c] FIG. 7b is a plan view taken along line DD' of FIG. 7a, illustrating a pixel isolation pattern and a first isolation pattern according to one embodiment of the present disclosure. [Figure 9a]FIG. 7a is a plan view taken along line EE' of FIG. 7a, showing a plan view of first grid pattern 160A and second grid pattern 160B, according to one embodiment of the present disclosure. [Figure 9b] FIG. 7a is a plan view taken along line EE' of FIG. 7a, showing a plan view of first grid pattern 160A and second grid pattern 160B, according to one embodiment of the present disclosure. [Figure 9c] FIG. 7a is a plan view taken along line EE' of FIG. 7a, showing a plan view of first grid pattern 160A and second grid pattern 160B, according to one embodiment of the present disclosure. [Figure 9d] FIG. 7a is a plan view taken along line EE' of FIG. 7a, showing a plan view of first grid pattern 160A and second grid pattern 160B, according to one embodiment of the present disclosure. [Figure 10] 6 is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, taken along line BB' in FIG. 5. [Figure 11a] FIG. 11 is an enlarged view of the P2 and P3 regions of FIG. [Figure 11b] FIG. 11 is an enlarged view of the P2 and P3 regions of FIG. [Figure 12a] 11 is a plan view of the P2 region or the P3 region of FIG. 10 cut along the line EE'. [Figure 12b] 11 is a plan view of the P2 region or the P3 region of FIG. 10 cut along the line EE'. [Figure 12c] 11 is a plan view of the P2 region or the P3 region of FIG. 10 cut along the line EE'. [Figure 12d] 11 is a plan view of the P2 region or the P3 region of FIG. 10 cut along the line EE'. [Figure 12e] 11 is a plan view of the P2 region or the P3 region of FIG. 10 cut along the line EE'. [Figure 12f] 11 is a plan view of the P2 region or the P3 region of FIG. 10 cut along the line EE'. [Figure 13] 6 is a cross-sectional view of an image sensor according to an embodiment of the present disclosure, taken along line CC' in FIG. 5. [Figure 14a] 14 is a plan view of the P4 and P5 regions of FIG. 13 cut along line EE'. [Figure 14b] 14 is a plan view of the P4 and P5 regions of FIG. 13 cut along line EE'. [Figure 15a] 1 illustrates a method for manufacturing an image sensor according to one embodiment of the present disclosure. [Figure 15b] 1 illustrates a method for manufacturing an image sensor according to one embodiment of the present disclosure. [Figure 15c] 1 illustrates a method for manufacturing an image sensor according to one embodiment of the present disclosure. [Figure 15d] 1 illustrates a method for manufacturing an image sensor according to one embodiment of the present disclosure. [Figure 15e] 1 illustrates a method for manufacturing an image sensor according to one embodiment of the present disclosure. [Figure 15f] 1 illustrates a method for manufacturing an image sensor according to one embodiment of the present disclosure. [Figure 15g] 1 illustrates a method for manufacturing an image sensor according to one embodiment of the present disclosure. [Figure 15h] 1 illustrates a method for manufacturing an image sensor according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present disclosure may be embodied in various different forms and is not limited to the embodiments set forth herein.

[0031] In order to clearly explain the present invention, parts that are not necessary for the explanation will be omitted, and the same reference numerals will be used to refer to the same or similar components throughout the specification.

[0032] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, the thicknesses of various layers and regions are exaggerated to clearly express the layers and regions. In the drawings, the thicknesses of some layers and regions are exaggerated to facilitate explanation.

[0033] In addition, when a part such as a layer, film, region, or plate is said to be "on" or "above" another part, this includes not only the case where it is "directly on" another part, but also the case where there is another part in between. Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between. In addition, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" the opposite direction of gravity.

[0034] Additionally, throughout the specification, when a part is said to "comprise" a certain element, this means that it may further include other elements, but not excluding other elements, unless specifically stated to the contrary.

[0035] Also, throughout the specification, the term "in a plane" means when the subject part is viewed from above, and the term "in cross section" means when the subject part is cut vertically and viewed from the side.

[0036] The present disclosure may be embodied in various different forms and is not limited to the embodiments set forth herein.

[0037] FIG. 1 is an exemplary block diagram of an image sensor according to one embodiment of the present disclosure.

[0038] Referring to FIG. 1, a semiconductor chip including a pixel array 102 and a semiconductor chip including a logic circuit 202 may be stacked.

[0039] The pixel array 102 can convert incident light and generate an electrical signal. The pixel array 102 can include unit pixel regions arranged in a matrix form along a row direction and a column direction. Specifically, the pixel array 102 can be driven under the control of a logic circuit 202. More specifically, the logic circuit 202 can control a plurality of transistors included in the pixel array 102.

[0040] The logic circuit 202 can efficiently receive data from the pixel array 102 and generate an image frame. For example, the logic circuit 202 can use various types of shutters, such as a global shutter type in which all unit pixel areas are sensed simultaneously, a flutter shutter type in which an exposure time is adjusted to sense all unit pixel areas simultaneously, a rolling shutter type in which unit pixel areas are controlled by row, or a coded rolling shutter type.

[0041] The logic circuit 202 may include components such as a row decoder 21, a row driver 22, a timing generator 23, a correlated double sampler (CDS) 24, an analog to digital converter (ADC) 25, a latch unit (LATCH) 26, and a column decoder 27.

[0042] The row driver 22 may control the row-by-row pixel array 102 under the control of the timing generator 23. The row driver 22 may select at least one row of the pixel array 102 by a row address. The row driver 22 may decode the row address and connect the selection transistor, the reset transistor, and the source follower transistor. The pixel array 102 may be driven by a number of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, received from the row driver 22.

[0043] The timing generator 23 provides timing signals and control signals to the row decoder 21 and the column decoder 28. The row driver 22 provides a plurality of driving signals to the pixel array for driving a plurality of unit pixels according to the result of decoding by the row decoder 21. When a plurality of unit pixels are arranged in a matrix form, the row driver 22 provides a driving signal for each row of the matrix.

[0044] The correlated double sampler 24 receives, stores, and samples the output signal from the pixel array 102. Specifically, the correlated double sampler 24 double samples a specific noise level and a signal level according to the output signal, and outputs a difference level corresponding to the difference between the noise level and the signal level.

[0045] The analog-to-digital converter 25 converts an analog signal corresponding to the difference level into a digital signal and outputs the digital signal. Specifically, the analog-to-digital converter 25 can convert an analog signal received from the pixel array 102 through a column line into a digital signal. The number of analog-to-digital converters 25 can be determined according to the number of unit pixel regions arranged along one row and the number of column lines. As a non-limiting example, the number of analog-to-digital converters 25 may be at least one.

[0046] The analog-to-digital converter 25 may include a reference signal generator REF, a comparator CMP, a counter CNT, and a buffer BUF. The reference signal generator REF may generate a ramp signal having a specific slope and provide the ramp signal as a reference signal of the comparator. The comparator CMP may compare an analog signal with the ramp signal of the reference signal generator REF and output a comparison signal having a transition time point according to a valid signal component. The counter CNT may perform a counting operation to generate a counting signal and provide the counting signal to the buffer BUF. The buffer BUF may include a circuit of a latch unit 26 connected to each column line, and may latch the counting signal output from the counter CNT for each column in response to a transition of the comparison signal, and output the latched counting signal as data.

[0047] FIG. 2 is a circuit diagram illustrating a unit pixel area of ​​a pixel array according to one embodiment of the present disclosure.

[0048] Referring to FIG. 2, the pixel array may include a photoelectric conversion layer PD, a transfer transistor TX, a floating diffusion region FD, and a reset transistor RX.

[0049] The photoelectric conversion layer PD can generate charges in proportion to the amount of light incident from the outside. The photoelectric conversion layer PD may be a photodiode including an n-type impurity region and a p-type impurity region. The photoelectric conversion layer PD can be coupled to a transfer transistor TX that transfers the generated and accumulated charges to the floating diffusion region FD. The floating diffusion region FD has a parasitic capacitance that converts the charges into a voltage, and the charges can be accumulated and stored.

[0050] One end of the transfer transistor TX may be connected to the photoelectric conversion layer PD, and the other end of the transfer transistor TX may be connected to the floating diffusion region. The transfer transistor TX may be formed of a transistor driven by a transfer signal, which is a predetermined bias. The transfer signal may be applied through a transfer gate TG. Specifically, the transfer transistor TX may transfer charges generated from the photoelectric conversion layer to the floating diffusion region FD in response to the transfer signal.

[0051] The source follower transistor SX amplifies a change in the electric potential of the floating diffusion region FD that receives charges from the photoelectric conversion layer PD and outputs the amplified change to the output line Vout. A predetermined electric potential, for example, a power supply voltage VDD, provided to the drain of the source follower transistor SX can be transmitted to the drain region of the selection transistor. A source follower gate SF of the source follower transistor SX can be connected to the floating diffusion region FD.

[0052] The selection transistor can select a unit pixel area to be read out on a row-by-row basis. The selection transistor can be a transistor driven by a selection line that applies a predetermined bias, for example, a row selection signal. The row selection signal can be applied through a selection gate SEL.

[0053] The reset transistor RX can periodically reset the floating diffusion region FD. The reset transistor RX can be configured as a transistor driven by a reset line that applies a predetermined bias, for example, a reset signal. The reset signal can be applied through a reset gate RG. When the reset transistor RX is turned on by the reset signal, a predetermined electrical potential, for example, a power supply voltage VDD, provided to the drain of the reset transistor RX can be transmitted to the floating diffusion region FD.

[0054] In FIG. 2, the photoelectric conversion layer PD electrically shares one floating diffusion region FD, however, this is a non-limiting example, and one unit pixel area may have at least one of the photoelectric conversion layers and the floating diffusion region FD, as well as the transmission, source follower, selection, and reset transistors, and the reset transistor RX, the source follower transistor SX, or the selection transistor may be shared with adjacent unit pixel areas.

[0055] In one embodiment, the area of ​​the unit pixel region is reduced, so that the photoelectric conversion layer PD and the transfer transistor TX can be formed on one semiconductor chip, and the reset transistor, the source follower transistor, and the selection transistor can be formed on another semiconductor chip. The semiconductor chips can be aligned to form the unit pixel region.

[0056] FIG. 2 discloses a unit pixel including multiple photoelectric conversion layers PD, specifically, two photoelectric conversion layers PD, but this is a non-limiting example and the unit pixel may include multiple photoelectric conversion layers, such as two photoelectric conversion layers PD or four photoelectric conversion layers PD.

[0057] In one embodiment, the image sensor includes a plurality of unit pixels. Specifically, the unit pixels may be arranged in a matrix along a row direction or a column direction. Each of the unit pixels may include a photoelectric conversion layer PD, a floating diffusion region FD, a transfer transistor, a source follower transistor, a selection transistor, and a reset transistor, which are described in detail above.

[0058] FIG. 3 is an exploded perspective view of an image sensor according to one embodiment of the present disclosure.

[0059] 3, an image sensor according to an embodiment may include a first substrate structure 100 and a second substrate structure 200 that are stacked together. The first substrate structure 100 may have a plurality of unit pixels arranged in a two-dimensional array structure on a plane including an X-axis direction and a Y-axis direction. Specifically, the first substrate structure 100 may include a pixel array. The X-axis direction and the Y-axis direction may be perpendicular to each other (or may be orthogonal to each other).

[0060] The second substrate structure 200 may include a structure such as a logic region. The second substrate structure 200 may be disposed under the first substrate structure 100. The first substrate structure 100 and the second substrate structure 200 may be electrically connected. The second substrate structure 200 may allow pixel signals transmitted from the first substrate structure 100 to be transmitted to the logic region of the second substrate structure 200.

[0061] The second substrate structure 200 may include components such as a logic region. The second substrate structure 200 may be disposed under the first substrate structure 100. The first substrate structure 100 and the second substrate structure 200 may be electrically connected. The second substrate structure 200 may allow pixel signals transmitted from the first substrate structure 100 to be transmitted to the logic region of the second substrate structure 200.

[0062] A logic element may be disposed in the logic region of the second substrate structure 200. The logic element may include a circuit for processing a pixel signal received from a unit pixel.

[0063] The first substrate structure 100 and the second substrate structure 200 can be stacked in the Z-axis direction, which may be perpendicular to (orthogonal to) the X-axis direction and the Y-axis direction.

[0064] FIG. 4 is an exploded perspective view of an image sensor according to another embodiment of the present disclosure.

[0065] 4, in an embodiment, the image sensor may further include a third substrate structure 300. The first substrate structure 100, the second substrate structure 200, and the third substrate structure 300 may be sequentially stacked along the Z-axis direction. The third substrate structure 300 may be disposed below the second substrate structure 200. Specifically, the second substrate structure 200 may be disposed between the first substrate structure 100 and the third substrate structure 300. Detailed descriptions of the first substrate structure 100 and the second substrate structure 200 are the same as those of FIG. 3 above to the extent that they do not contradict.

[0066] The third substrate structure 300 may include a memory device. The third substrate structure 300 may include a volatile memory device such as a DRAM or an SRAM. The third substrate structure 300 may receive signals from the first substrate structure 100 and the second substrate structure 200 and process the signals through the memory device.

[0067] Fig. 5 is an exemplary layout diagram for explaining an image sensor according to an embodiment of the present disclosure, and Fig. 6 is a cross-sectional view taken along line AA' in Fig. 5.

[0068] 5 and 6, an image sensor according to an embodiment may include a first substrate structure 100 and a second substrate structure 200. The first substrate structure 100 and the second substrate structure 200 may be a sensor chip and a logic chip, respectively.

[0069] The first substrate structure 100 may include a light receiving region APS, a light blocking region OB, and a pad region PAD. A plurality of unit pixel regions PX arranged two-dimensionally, for example, in a matrix form, may be formed in the light receiving region APS and the light blocking region OB. The unit pixel regions PX may be arranged in a matrix form on a plane on which the first direction D1 and the second direction D2 extend. The unit pixel regions PX may be arranged in a matrix form on a plane on which the first direction D1 and the second direction D2 extend. The first direction D1 and the second direction D2 may cross each other. The first direction D1 and the second direction D2 may be substantially perpendicular. The third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2.

[0070] Active pixels that receive light and generate an active signal may be arranged in the light receiving region APS, and optical black pixels that block light and generate an optical black signal may be arranged in the light blocking region OB. As a non-limiting example, the light blocking region OB may be formed along the periphery of the light receiving region APS.

[0071] In one embodiment, a dummy unit pixel region may be formed in the light blocking region OB, and the dummy unit pixel region may be a pixel that does not generate an active signal.

[0072] The pad area PAD may be formed around the light blocking area OB. The pad area PAD may be formed adjacent to an edge of the image sensor, for example and without limitation. The pad area PAD may be configured to be connected to a member such as an external device and to transmit and receive electrical signals between the image sensor and the external device. Specifically, on the upper substrate 110B of the pad area PAD, a second pad pattern 455 may be connected to a member such as an external device.

[0073] In one embodiment, the image sensor may include a first substrate structure 100 including an upper substrate 110B and a lower substrate 110A, a pixel separating pattern 120A, a surface insulating film 150, a first color filter 170, a first grid pattern 160A, a microlens 180, and a second substrate structure 200 disposed below the first substrate structure 100 and including a second substrate 210.

[0074] The upper substrate 110B may be a semiconductor substrate. Specifically, the upper substrate 110B may be bulk silicon or silicon-on-insulator (SOI). The upper substrate 110B may be a silicon substrate. The upper substrate 110B may be a material including, for example, silicon, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In one embodiment, the upper substrate 110B may be an epitaxial layer formed on a base substrate.

[0075] The upper substrate 110B may include a first surface 112a and a second surface 112b facing each other. In one embodiment, the first surface 112a of the upper substrate 110B may be a light receiving surface through which light is incident. In one embodiment, the image sensor may be a backside illuminated (BSI) image sensor.

[0076] A plurality of unit pixel regions PX may be formed in the upper substrate 110B of the light receiving region APS and the light blocking region OB. Each unit pixel region PX may include a first photoelectric conversion layer PD1 and a second photoelectric conversion layer PD2. In an embodiment, the upper substrate 110B of the light blocking region OB may further include a dummy unit pixel region that does not include the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2, but is not limited thereto. A signal generated in the dummy unit pixel region may be used as information for removing process noise in the following steps.

[0077] Each unit pixel region PX may include a photoelectric conversion layer PD, a floating diffusion region FD, and a transmission transistor TX. Specifically, the photoelectric conversion layer PD1 or PD2 may be formed in the upper substrate 110B of the light receiving region APS and the light blocking region OB. The photoelectric conversion layer PD1 or PD2 may generate charges in proportion to the amount of light incident from the outside. The photoelectric conversion layer PD1 or PD2 may transmit the generated and accumulated charges to the floating diffusion region FD.

[0078] The floating diffusion region FD can be formed in the upper substrate 110B of the light receiving region APS and the light blocking region OB. The floating diffusion region FD can be formed in the second surface 112b of the upper substrate 110B. The charge transferred to the floating diffusion region FD can be applied to the source follower gate SF of FIG.

[0079] The transfer transistor TX may be embedded in the upper substrate 110B. One end of the transfer transistor TX may be connected to the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2, and the other end of the transfer transistor TX may be connected to the floating diffusion region FD. The transfer transistor TX may transfer charges generated from the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2 to the floating diffusion region FD.

[0080] The transfer transistor TX may include a transfer gate, a gate dielectric, and a gate spacer. The transfer gate may include a portion embedded in the upper substrate 110B. The gate dielectric may be disposed between the transfer gate and the upper substrate 110B. The gate spacers may be disposed on both side walls of the transfer gate.

[0081] The pixel separating pattern 120A may be formed in the upper substrate 110B. The pixel separating pattern 120A may be formed by filling a conductive material in a deep trench formed by patterning the upper substrate 110B, and a liner film, which is an insulating material, may be formed between the conductive material and the upper substrate 110B to provide insulation.

[0082] The pixel separating pattern 120A may penetrate the upper substrate 110B in a third direction D3. Specifically, the pixel separating pattern 120A may extend from the second surface 112b to the first surface 112a. More specifically, the pixel separating pattern 120A may be a Front Deep Trench Isolation (FDTI).

[0083] The pixel separating pattern 120A may define a plurality of unit pixel regions PX. In another embodiment, the pixel separating pattern 120A may define a plurality of unit pixel regions PX and a dummy unit pixel DP. The pixel separating pattern 120A may be formed in a lattice shape on a plane to separate the plurality of unit pixel regions PX from each other.

[0084] The pixel separating pattern 120A may define a plurality of unit pixel regions PX. In one embodiment, the pixel separating pattern 120A may define a plurality of unit pixel regions PX. The pixel separating pattern 120A may be formed in a lattice shape in a plan view to separate the plurality of unit pixel regions PX from each other. The pixel separating pattern 120A may be a lattice structure extending in a first direction D1 and a second direction D2.

[0085] In terms of cross-sectional area, the pixel isolation pattern 120A may penetrate the upper substrate 110B in the third direction D3. The pixel isolation pattern 120A may extend from the second surface 112b to the first surface 112a of the upper substrate 110B. The pixel isolation pattern 120A may be a deep trench isolation (DTI) film. The width of the pixel isolation pattern 120A in the second direction D2 may gradually decrease from the second surface 112b to the first surface 112a of the upper substrate 110B, or may have the same width. However, the technical idea of ​​the present invention is not limited thereto.

[0086] The pixel isolation pattern 120A may include a liner film 120L, a first pixel isolation filling film 120F1, and a capping film 120C. The liner film 120L may be disposed along the sidewall and bottom surface of the first trench t1. In one embodiment, the bottom surface of the first trench t1 refers to the surface facing the first surface 112a of the upper substrate 110B. The first pixel isolation filling film 120F1 may be disposed on the liner film 120L. The capping film 120C may be disposed on the first pixel isolation filling film 120F1.

[0087] The liner film 120L may include an oxide film having a lower refractive index than the upper substrate 110B. The liner film 120L may include, by way of non-limiting example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof.

[0088] The liner film 120L, which has a lower refractive index than the upper substrate 110B, can refract light obliquely incident on the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2. The liner film 120L can prevent photocharges generated in a specific unit pixel area PX by incident light from moving to an adjacent unit pixel area PX due to random drift. Specifically, the liner film 120L can improve the light receiving rate of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2, thereby improving the quality of the image sensor.

[0089] The first pixel isolation filling layer 120F1 may include an insulating material or a conductive material. The insulating material may include a silicon-based insulating material such as silicon nitride, silicon oxide, and silicon oxynitride, and a high dielectric material such as hafnium oxide, aluminum oxide, and tantalum oxide. In one embodiment, the first pixel isolation filling layer 120F1 may be a conductive material with low resistance. As a non-limiting example, the conductive material may include polysilicon (Poly Si), or silicon doped with arsenic (As), phosphorus (P), or carbon (C).

[0090] In one embodiment, a negative voltage can be applied to the first pixel isolation filling layer 120F1 including a conductive material, which can effectively prevent electrostatic discharge (ESD) bruises in the image sensor. The ESD bruises refer to a phenomenon in which charges generated by an ESD-like reaction accumulate on the surface of the substrate, for example, the first surface 112a, causing bruise-like spots on the image.

[0091] The capping film 120C may include an insulating material. For example, the capping film 120C may include a silicon-based insulating material such as silicon nitride, silicon oxide, and silicon oxynitride, and a high-k material such as hafnium oxide and aluminum oxide. As a non-limiting example, the capping film 120C may include the same material as the first capping pattern 375 and the second capping pattern 475.

[0092] In one embodiment, a first separation pattern 120B may be included in the substrate between the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2, defining the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2. The first separation pattern 120B may include a liner film 120L, a first separation filling film 120F2, and a capping film 120C. The liner film 120L may be disposed along the sidewall and bottom surface of the second trench t2. In one embodiment, the bottom surface of the second trench t2 refers to the surface facing the first surface 112a of the upper substrate 110B. The first separation filling film 120F2 may be disposed on the liner film 120L. The capping film 120C may be disposed on the first separation filling film 120F2. The first separation pattern 120B is the same as the pixel separation pattern 120A described above to the extent that it does not contradict, except that it separates the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 within the unit pixel region PX.

[0093] In one embodiment, an isolation pattern 105 may be provided. The isolation pattern 105 may be disposed in the upper substrate 110B. For example, the isolation pattern 105 may be disposed in a trench recessed from a portion of the upper substrate 110B. In particular, the trench may be recessed from the second surface 112b of the upper substrate 110B. The isolation pattern 105 may be a shallow trench isolation (STI) film. The isolation pattern 105 may define an active region.

[0094] The width of the device isolation pattern 105 in the first direction D1 or the second direction D2 may gradually decrease from the second surface 112b to the first surface 112a of the upper substrate 110B. The device isolation pattern 105 may overlap the pixel isolation pattern 120A in the second direction D2 or the first direction D1. The pixel isolation pattern 120A may penetrate the device isolation pattern 105 in the third direction D3. The device isolation pattern 105 may include an insulating material. The insulating material may include at least one of silicon nitride, silicon oxide, and silicon oxynitride, for example.

[0095] The isolation pattern 105 may define an active region. In a plan view, the active region may have a line shape extending in a second direction D2, for example and without limitation. A floating diffusion region FD, a transfer transistor TX, a selection transistor, a reset transistor RX, and a source follower transistor SX may be provided on the active region. Specifically, the transfer transistor TX may include a transfer gate TG.

[0096] In one embodiment, a floating diffusion region FD may be provided on one side of the transfer transistor TX. The floating diffusion region FD may have an opposite conductivity to the upper substrate 110B. For example, n-type impurities may be doped into the floating diffusion region FD. The floating diffusion region FD may cover the transfer gate TG of the transfer transistor TX.

[0097] In one embodiment, a portion of the unit pixel region PX may include a selection transistor and a source follower transistor SX. The selection transistor may include a selection gate SEL, and the source follower transistor SX may include a source follower gate SF. Another portion of the unit pixel region PX may include a reset transistor RX. The reset transistor RX may include a reset gate RG. However, the technical idea of ​​the present invention is not limited thereto, and the arrangement and number of transistors included in the unit pixel region PX may be changed as desired.

[0098] In an embodiment, the image sensor may further include first wiring insulating films 131, 132, 133, 134, 135, and 136. The first wiring insulating films 131, 132, 133, 134, 135, and 136 may cover the second surface 112b of the upper substrate 110B. The upper substrate 110B and the first wiring insulating films 131, 132, 133, 134, 135, and 136 may constitute a first substrate structure 100. In FIG. 6, the first wiring insulating films 131, 132, 133, 134, 135, and 136 are shown, but are not limited thereto, and the number of layers of the first wiring insulating film is not limited thereto.

[0099] The first wiring insulating films 131, 132, 133, 134, 135, and 136 may include, but are not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a lower dielectric constant than silicon oxide.

[0100] In one embodiment, the first wiring insulating film 136 is a wiring insulating film connecting the upper substrate 110A and the lower substrate 110B, and can be divided into an upper insulating film 136T and a lower insulating film 136B. The upper insulating film 136T and the lower insulating film 136B can be made of the same film quality and can be distinguished at the interface where the upper substrate 110A and the lower substrate 110B are connected.

[0101] A plurality of first contacts 141, 143 and a plurality of first wiring patterns 142, 144, 145 may be provided within the first wiring insulating films 131, 132, 133, 134, 135, 136. The plurality of first contacts 141, 143 may electrically connect the floating diffusion region FD to the plurality of first wiring patterns 142, 144, 145. Some of the plurality of first wiring patterns 142, 144, 145 may be connected to the first connecting structure 360. This is a non-limiting example, and in various forms, the plurality of first contacts 141, 143 may be connected to the plurality of first wiring patterns 142, 144, 145, and the number is not limited thereto.

[0102] Each of the plurality of first contacts 141, 143 and the first wiring patterns 142, 144, 145 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, as non-limiting examples.

[0103] The second substrate 210 is one of the configurations of the second substrate structure 200 disposed under the first substrate structure 100, and may be bulk silicon or silicon-on-insulator (SOI). The second substrate 210 may be a silicon substrate. The second substrate 210 may include, for example, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The second substrate 210 may be an epitaxial layer formed on a base substrate.

[0104] A plurality of transistors TR may be formed on an upper surface of the second substrate 210. The transistors TR may control a transfer transistor TX, a reset transistor RX, a selection transistor, and a source follower transistor SX.

[0105] A second wiring insulating film 230 may be formed on the second substrate 210. For example, the second wiring insulating film 230 may cover an upper surface of the second substrate 210. An upper surface of the second wiring insulating film 230 may be in contact with and coupled to a third surface 100c, which is a lower surface of the lower substrate 110A of the first substrate structure 100. The second wiring insulating film 230 may include, as a non-limiting example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide.

[0106] A second contact 241 and a plurality of second wiring patterns 242 may be disposed within the second wiring insulating film 230. The second contact 241 may connect the plurality of second wiring patterns 242, and each of the plurality of second wiring patterns 242 may be connected to a transistor TR and may also be connected to a floating diffusion region FD of the first substrate structure 100. For example, some of the plurality of second wiring patterns 242 may be connected to the first connecting structure 360. In addition, another portion of the plurality of second wiring patterns 242 may be connected to the second connecting structure 450.

[0107] The second contact 241 and the second wiring pattern 242 may each include, by way of non-limiting example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, but are not limited thereto.

[0108] The surface insulating film 150 may be formed on the first surface 112a of the upper substrate 110B. The surface insulating film 150 may extend along the second surface 112b of the upper substrate 110B. In one embodiment, at least a portion of the surface insulating film 150 may be in contact with the pixel separating pattern 120A and the first separating pattern 120B. In this case, the lower surface of the surface insulating film 150 may be in flat contact with the pixel separating pattern 120A and the first separating pattern 120B.

[0109] The surface insulating film 150 may include an insulating material, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, tantalum oxide, and combinations thereof.

[0110] The surface insulating film 150 functions as an anti-reflection film to prevent reflection of light incident on the upper substrate 110B and to facilitate (promote) the incidence of the incident light, thereby improving the light receiving rate of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2. The surface insulating film 150 also functions as a planarizing film to enable the first color filter 170 and the microlens 180, which will be described later, to be formed with a uniform height and without distortion.

[0111] The first color filters 170 may be formed on the surface insulating film 150 of the light receiving region APS. In one embodiment, the first color filters 170 may be formed on the surface insulating film 150 of the light receiving region APS. In one embodiment, the first color filters 170 may be arranged correspondingly on each unit pixel region PX. Specifically, the first color filters 170 may be arranged two-dimensionally, for example, in a matrix form.

[0112] The first color filter 170 may have various color filters according to the unit pixel area PX. For example, the first color filter 170 may be arranged in a Bayer pattern including a red color filter, a green color filter, and a blue color filter. As a non-limiting example, the first color filter 170 may include a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter.

[0113] The first grid pattern 160A may be formed on the surface insulating film 150. The first grid pattern 160A may be formed in a lattice shape on a plane and may be interposed between a plurality of first color filters 170. The first grid pattern 160A may improve the quality of the image sensor by refracting or reflecting light obliquely incident on the image sensor.

[0114] The first grid pattern 160A may include a metal material capable of reflecting light or a low refractive index material having a refractive index lower than that of silicon (Si). For example, the first grid pattern 160A may include at least one of tungsten metal, aluminum metal, titanium metal, titanium nitride metal, silicon oxide, silicon oxide containing an air gap, a low refractive index polymer material, and combinations thereof, but is not limited thereto. The first grid pattern 160A has a refractive index lower than that of silicon (Si), so that light can be prevented from being absorbed by the liner film 120L.

[0115] In one embodiment, the first grid pattern 160B may include a second grid pattern 160B disposed on the first isolated pattern 120B. Specifically, the second grid pattern 160B may include a metal material capable of reflecting light or a low refractive index material having a refractive index lower than that of silicon (Si). For example, the first grid pattern 160A may include at least one of tungsten metal, aluminum metal, titanium metal, titanium nitride metal, silicon oxide, silicon oxide with an air gap, a low refractive index polymer material, and combinations thereof, but is not limited thereto.

[0116] In one embodiment, the first grid pattern 160A may be made of the same or different material as the second grid pattern 160B. When the first grid pattern 160A and the second grid pattern 160B are made of the same material, when light incident from the first color filter 170 is reflected by the first grid pattern 160A and the second grid pattern 160B, the light can be reflected at the same angle so as to be easily incident on the photoelectric conversion layers PD1 and PD2.

[0117] When the first grid pattern 160A and the second grid pattern 160B are made of different materials, when the light input from the first color filter 170 is reflected by the first grid pattern 160A and the second grid pattern 160B, the angle can be changed to maximize the amount of light entering the photoelectric conversion layers PD1 and PD2.

[0118] In one embodiment, a first protective film 165 may be formed on the surface insulating film 150, the first grid pattern 160A, and the second grid pattern 160B. The first protective film 165 may be interposed between the surface insulating film 150 and the first color filter 170, and between the first grid pattern 160A, the second grid pattern 160B, and the first color filter 170. For example, the first protective film 165 may prevent damage to the surface insulating film 150, the first grid pattern 160A, and the second grid pattern 160B.

[0119] The microlenses 180 may be formed on the first color filter 170. The microlenses 180 may be arranged to correspond to each unit pixel area PX. For example, the microlenses 180 may be arranged two-dimensionally on a plane, for example, in a matrix form.

[0120] The microlens 180 may have a convex shape and a radius of curvature within a predetermined range. By having the radius of curvature within the predetermined range, the microlens 180 may condense light incident on the photoelectric conversion layers PD1 and PD2. The microlens 180 may include, for example, a light-transmitting resin, as a non-limiting example.

[0121] In one embodiment, a second protective film 185 may be formed on the microlens 180. The second protective film 185 may extend along the surface of the microlens 180. The second protective film 185 may include, for example, an inorganic oxide film. The second protective film 185 may include, for example, at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof, as non-limiting examples. In one embodiment, the second protective film 185 may include, for example, a low temperature oxide (LTO).

[0122] The second protective film 185 can protect the microlenses 180 from the outside. For example, the second protective film 185 can protect the microlenses 180 including an organic material by including an inorganic oxide film. In addition, the second protective film 185 can improve the light collecting ability of the microlenses 180. For example, the second protective film 185 can fill the spaces between the microlenses 180, thereby reducing reactions such as reflection, refraction, or scattering of incident light that reaches the spaces between the microlenses 180.

[0123] In an embodiment, the image sensor may further include a first connecting structure 360. The first connecting structure 360 ​​may be formed in the light blocking region OB. The first connecting structure 360 ​​may be disposed in the light blocking region OB to block light incident on the light blocking region OB. The first connecting structure 360 ​​may be formed on the surface insulating film 150 of the light blocking region OB. The first connecting structure 360 ​​may be in contact with the pixel separating pattern 120A.

[0124] A third trench t3 exposing the pixel separating pattern 120A may be formed in the upper substrate 110B and the surface insulating film 150 in the light blocking region OB. The first connecting structure 360 ​​may be formed in the third trench t3 and may be in contact with the pixel separating pattern 120A in the light blocking region OB. The first connecting structure 360 ​​may extend along the profile of the sidewall and bottom surface of the third trench t3.

[0125] The first connection structure 360 ​​may be electrically connected to the pixel separating pattern 120A. For example, the first connection structure 360 ​​may be connected to a conductive layer of the pixel separating pattern 120A. As a non-limiting example, the first connection structure may include a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film that are stacked in sequence.

[0126] In one embodiment, a first pad pattern 365 may be formed on the first connecting structure 360. The first pad pattern 365 may be made of a metal material that blocks light around the pixel array, and may fill the first connecting structure 360 ​​and the remaining second trench t2. A first voltage may be applied to the pixel isolation pattern 120A of the pixel isolation pattern 120A through the first pad pattern 365. For example, a negative voltage may be applied to the conductive layer through the first pad pattern 365 and the first connecting structure 360, which include a conductive material, so that charges generated by a reaction such as ESD can be discharged to the first pad pattern 365 through the pixel isolation pattern 120A, preventing ESD bruises.

[0127] The first pad pattern 365 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, as non-limiting examples.

[0128] In one embodiment, a third trench t3 may be formed in the upper substrate 110B in the light-shielding region OB. The third trench t3 may expose a portion of the first wiring pattern 145 of the first substrate structure 100. For example, the third trench t3 may represent a through silicon via structure.

[0129] The third trench t3 may expose a portion of the second wiring pattern 242 and the third wiring pattern 243 of the second substrate structure 200. The first connection structure 360 ​​may be formed in the third trench t3 to connect the second wiring pattern 242 and the third wiring pattern 243. The first connection structure 360 ​​may extend along the sidewalls and bottom surface of the third trench t3.

[0130] In one embodiment, a first filling insulating layer 370 may be formed on the first connection structure 360. The first filling insulating layer 370 may include, by way of non-limiting example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof.

[0131] In one embodiment, a first capping pattern 375 may be formed on the first filling insulating layer 370. The first capping pattern 375 may include a silicon-based insulating material such as silicon nitride, silicon oxide, and silicon oxynitride, and a high dielectric material such as hafnium oxide and aluminum oxide. The first capping pattern 375 may include the same material as the capping layer 120C, but is not limited thereto.

[0132] In an embodiment, a second color filter 170C may be formed on the first connection structure 360. The second color filter 170C may be formed to cover a portion of the first protective film 165 in the light blocking region OB. As a non-limiting example, the second color filter 170C may include a blue color filter.

[0133] In an embodiment, a third protective film 380 may be formed on the second color filter 170C. For example, the third protective film 380 may be formed to cover a portion of the first protective film 165 in the light blocking region OB. In an embodiment, the second protective film 185 may extend along the surface of the third protective film 380. The third protective film 380 may include, as a non-limiting example, a light-transmitting resin. In an embodiment, the third protective film 380 may include the same material as the microlens 180.

[0134] The third connection structure 450 may be formed in the pad region PAD. The second connection structure 450 may be formed on the surface insulating film 150 in the pad region PAD. In one embodiment, a fifth trench t5 may be formed in the first substrate structure 100 in the pad region PAD. The second connection structure 450 may be formed along the sidewalls and bottom surface of the fifth trench t5.

[0135] A sixth trench t6 exposing the second wiring pattern 242 may be formed in the second substrate structure 200 in the pad area PAD. The third connection structure 457 may be formed along a bottom surface of a sidewall of the sixth trench t6.

[0136] The third connection structure 457 may be formed in the sixth trench t6 and may be in contact with a portion of the second wiring pattern 242. The third connection structure 457 may electrically connect a portion of the second wiring pattern 242 to the second pad pattern 455. The third connection structure 457 may be, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film that are sequentially stacked.

[0137] A second pad pattern 455 may be formed on the second connection structure 450. The second pad pattern 455 may fill the fifth trench t5 remaining after filling the third connection structure 450. The second pad pattern 455 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, as non-limiting examples.

[0138] In an embodiment, a portion of the second pad pattern 455 may be exposed. In an embodiment, an exposure opening may be formed to expose the second pad pattern 455. Thus, the second pad pattern 455 may be connected to an external device to transmit and receive electrical signals between the image sensor according to an embodiment and the external device.

[0139] A second filling insulating layer 470 may be formed on the third connecting structure 457 to fill the sixth trench t6 remaining after filling the third connecting structure 450. The second filling insulating layer 470 may include, but is not limited to, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof.

[0140] In one embodiment, a second capping pattern 475 may be formed on the second filling insulating layer 470. The second capping pattern 475 may include a silicon-based insulating material, such as silicon nitride, silicon oxide, or silicon oxynitride, and a high dielectric material, such as hafnium oxide or aluminum oxide. In particular, the second capping pattern 475 may include the same material as the capping layer 120C, as a non-limiting example.

[0141] In one embodiment, a fourth protective film 480 may be formed on the third connection structure 457 in the pad area PAD. For example, the fourth protective film 480 may be formed to cover a portion of the first protective film 165 in the pad area PAD. In one embodiment, the second protective film 185 may extend along a surface of the fourth protective film 480. The fourth protective film 480 may include, for example, but is not limited to, a light-transmitting resin. In one embodiment, the fourth protective film 480 may include the same material as the microlenses 180.

[0142] In an embodiment, the image sensor may further include a fifth connection structure (not shown). The fifth connection structure may be further formed in the light-shielding region OB. The fifth connection structure may be formed in the light-shielding region OB to block incident light. The fifth connection structure may be formed on the surface insulating film 150 of the light-shielding region OB.

[0143] The fifth connecting structure may be in contact with at least a portion of pixel separating pattern 120A. The fifth connecting structure may be in contact with at least a portion of a conductive layer of pixel separating pattern 120A. The fifth connecting structure may refer to first connecting structure 360 ​​to the extent not inconsistent.

[0144] In one embodiment, a seventh trench (not shown) exposing the pixel separating pattern 120A may be formed in the upper substrate 110B and the surface insulating film 150 in the light blocking region OB. The fifth connecting structure may be formed in the seventh trench and may contact at least a portion of the pixel separating pattern 120A in the light blocking region OB. The fifth connecting structure may extend along the profile of the sidewall and bottom surface of the seventh trench.

[0145] The fifth connection structure may be electrically connected to the pixel separating pattern 120A. Specifically, the fifth connection structure may include, as a non-limiting example, a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer that are sequentially stacked.

[0146] In one embodiment, an additional pad pattern (not shown) may be formed on the fifth connecting structure. The additional pad pattern may fill the fifth connecting structure and the remaining seventh trench. A voltage may be applied to the pixel isolation pattern 120A through the additional pad pattern and the fifth connecting structure, which may include a conductive material. For example, the voltage may be a well bias voltage.

[0147] The additional pad pattern may include, by way of non-limiting example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

[0148] 7a and 7b are enlarged views of various embodiments of the P1 region of FIG.

[0149] 7a, an image sensor according to an embodiment may include a first grid pattern 160A disposed on a pixel separating pattern 120A, and a second grid pattern 160B disposed on the first separating pattern 120B and having a height lower than that of the first grid pattern 160A. Specifically, a height H1 of the first grid pattern may be different from a height H2 of the second grid pattern.

[0150] In an embodiment, the height H1 of the first grid pattern may be higher than the height H2 of the second grid pattern. Specifically, the height H2 of the second grid pattern may be in the range of 1 / 10 to 1 / 4 of the height H1 of the first grid pattern. Specifically, the range may be 1 / 8 to 1 / 5. When the height H2 of the second grid pattern is in the above range of the height H1 of the first grid pattern, the incident light can be controlled to be easily incident on the photoelectric conversion layers PD1 and PD2 when the light is incident due to a shift.

[0151] If the upper limit of the range is exceeded, the light may be reflected by the second grid pattern 160B during shifting, making it difficult to reflect the light to the photoelectric conversion layers PD1 and PD2. If the lower limit of the range is exceeded, the light yield effect of the second grid pattern 160B may be insufficient (deteriorated).

[0152] In one embodiment, the second grid pattern 160B may have a refractive index lower than that of the first color filter 170. Since the refractive index of the first color filter 170 is higher than that of the second grid pattern 160B, light incident on the first color filter 170 can be refracted or reflected through the second grid pattern 160B and easily incident on the photoelectric conversion layers PD1 and PD2.

[0153] In an embodiment, the refractive index of the second grid pattern 160B relative to the refractive index of the first color filter 170 may satisfy a range of 0.40 to 0.95. Specifically, the range may satisfy 0.43 to 0.90.

[0154] By satisfying this range, light incident on the first color filter 170 can be easily incident on the photoelectric conversion layers PD1 and PD2 to increase the light yield. If the range is not satisfied, there is a problem that the incident light is reflected instead of being incident on the photoelectric conversion layers PD1 and PD2, or is absorbed by the liner film 120L in the pixel separating pattern 120A.

[0155] In an embodiment, the refractive index of the first color filter 170 may be in the range of 1.7 to 2.5. In an embodiment, the refractive index of the second grid pattern 160B may be in the range of 1.0 to 1.6. More specifically, the range may be in the range of 1.2 to 1.5.

[0156] Since the refractive index of the first color filter 170 is higher than that of the second grid pattern 160B, the angle of refraction becomes larger than the angle of incidence as the light travels from a dense medium to a sparse medium, resulting in total reflection.

[0157] 7b, the first grid pattern 160A may include a lower first grid pattern 160AB and an upper first grid pattern 160AT disposed on the lower first grid pattern 160AB. Specifically, the first grid pattern 160A may have a stack structure. The stack structure may be a structure that is realized in a process step of stacking the first grid pattern 160A and the second grid pattern 160B.

[0158] In one embodiment, the lower first grid pattern 160AB and the lower second grid pattern 160B may have the same or different refractive indexes. When the lower first grid pattern 160AB and the lower second grid pattern 160B are made of materials having the same refractive index, it is advantageous that the step of forming the first grid pattern 160A and the lower second grid pattern 160B can be easily performed in the process of manufacturing the image sensor. When the lower first grid pattern 160AB and the lower second grid pattern 160B are made of materials having different refractive indexes, it is advantageous that the refraction or reflection of incident light can be controlled according to a design to increase light yield.

[0159] In one embodiment, the lower first grid pattern 160AB and the second grid pattern 160B may have the same height. In this manner, by arranging the first grid pattern 160A in a stack structure, the lower first grid pattern 160AB and the second grid pattern 160B having the same height are simultaneously formed, and then the upper first grid pattern 160AT is formed, thereby simplifying the process.

[0160] 8a-8c are plan views taken along line DD' of FIG. 7a, illustrating a pixel isolation pattern 120A and a first isolation pattern 120B according to one embodiment of the present disclosure.

[0161] 8a and 8b, in one embodiment, the first separation pattern 120B may be composed of a first sub-separation pattern 120BT and a second sub-separation pattern 120BB. Specifically, the first sub-separation pattern 120BT may protrude from one side of the pixel separation pattern 120A, and the second sub-separation pattern 120BB may protrude from the other side opposite to the one side of the pixel separation pattern 120A.

[0162] The width of the first sub-separated pattern 120BT and the second sub-separated pattern 120BB may be, for example, 10 nm to 500 nm. Although Fig. 8a shows only the case where the widths of the first sub-separated pattern 120BT and the second sub-separated pattern 120BB are the same, this is merely an example and may include the case where the widths are different from each other.

[0163] In an embodiment, the first and second sub-isolated patterns 120BT and 120BB may be spaced apart by a predetermined distance DC. The predetermined distance may be, for example, 100 nm to 1,000 nm.

[0164] The first sub-isolation pattern 120BT and the second sub-isolation pattern 120BB are spaced apart by a predetermined distance DC, so that an overflow path is formed between the photoelectric conversion layers PD1 and PD2, thereby preventing loss of optical signals. As such, as shown in Figures 8a and 8c, the predetermined distance DC between the first sub-isolation pattern 120BT and the second sub-isolation pattern 120BB can be appropriately changed in design within a range in which an overflow path is formed.

[0165] 8c, the image sensor according to an embodiment of the present disclosure may further include a third photoelectric conversion layer PD3 disposed adjacent to the first photoelectric conversion layer PD1 in the second direction D2 within a unit pixel, and a fourth photoelectric conversion layer PD4 disposed adjacent to the second photoelectric conversion layer PD2 in the second direction D2. Specifically, FIG. 8b illustrates that one unit pixel may include the first to fourth photoelectric conversion layers PD1, PD2, PD3, and PD4.

[0166] In one embodiment, the third photoelectric conversion layer PD3 and the fourth photoelectric conversion layer PD4 may be defined by the first separation pattern 120B. Specifically, the third photoelectric conversion layer PD3 may be separated from the first photoelectric conversion layer PD1 by a third sub-separation pattern 120BL of the first separation pattern 120B, and the fourth photoelectric conversion layer PD4 may be separated from the second photoelectric conversion layer PD2 by a fourth sub-separation pattern 120BR of the first separation pattern 120B.

[0167] In one embodiment, the third sub-separation pattern 120BL and the fourth sub-separation pattern 120BR may be spaced apart by a predetermined distance DC'. For a detailed description of the predetermined distance DC', please refer to the description of the predetermined distance DC described above for the first sub-separation pattern 120BB and the second sub-separation pattern 120BT, to the extent that it does not contradict. In FIG. 8c, the predetermined distance DC of the first sub-separation pattern 120BB and the second sub-separation pattern 120BT and the predetermined distance DC' of the third sub-separation pattern 120BL and the fourth sub-separation pattern 120BR are illustrated as being the same, but this is a non-limiting example and may include cases where the distances are different.

[0168] In one embodiment, the image sensor may perform an auto focus (AF) function using a first photoelectric conversion layer PD1 and a second photoelectric conversion layer PD2. Each unit pixel may perform a phase detection auto focus (PDAF) function using a pair of divided photoelectric conversion layers PD1 and PD2.

[0169] The photoelectric conversion layer in the unit pixel may be divided and arranged in another direction. Specifically, the unit pixel may include a third photoelectric conversion layer PD3 arranged adjacent to the first photoelectric conversion layer PD1 in the second direction D2, and a fourth photoelectric conversion layer PD4 arranged adjacent to the second photoelectric conversion layer PD2 in the second direction D2. This allows the image sensor to perform an autofocus function in both the first direction D1 and the second direction D2.

[0170] 9a-9d are plan views taken along line EE' of FIG. 7a, illustrating a plan view of first grid pattern 160A and second grid pattern 160B, according to one embodiment of the present disclosure.

[0171] 9a to 9d, the interval at which the second grid pattern 160B is arranged can be seen based on the predetermined interval DC between the first sub-isolated pattern 120BB and the second sub-isolated pattern 120BT.

[0172] 9a, a first grid pattern 160A may be disposed on the pixel separation pattern 120A, and a second grid pattern 160B may be disposed on the first separation pattern 120B. By disposing the first grid pattern 160A and the second grid pattern 160B on the pixel separation pattern 120A and the first separation pattern 120B, light incident on the linear film 120L including polysilicon in the pixel separation pattern 120A and the first separation pattern 120B may be prevented from being absorbed, thereby preventing light loss.

[0173] In one embodiment, the second grid pattern 160B may have the same area as the first sub-separated pattern 120BB and the second sub-separated pattern 120BT in the first separated pattern 120B. The second grid pattern 160B has the same length and width as the first sub-separated pattern 120BB and the second sub-separated pattern 120BT, and covers the first sub-separated pattern 120BB and the second sub-separated pattern 120BT to prevent the light entering from the first color filter 170 from being absorbed by the liner film 120L.

[0174] 9b, in one embodiment, the second grid pattern 160B may be larger than the area of ​​the first sub-separation pattern 120BB and the second sub-separation pattern 120BT in the first separation pattern 120B. Specifically, the second grid pattern 160B may be separated with a second grid pattern separation distance GD that is narrower than the predetermined distance DC between the first sub-separation pattern 120BB and the second sub-separation pattern 120BT. By having the second grid pattern separation distance GD shorter than the predetermined distance DC between the first sub-separation pattern 120BB and the second sub-separation pattern 120BT, it is possible to more efficiently prevent the light entering from the first color filter 170 from being absorbed by the liner film 120L.

[0175] 9c, in one embodiment, the second grid pattern 160B may completely cover a predetermined distance DC between the first sub-isolated pattern 120BB and the second sub-isolated pattern 120BT in the first isolation pattern 120B. Specifically, the second grid pattern 160B may seal the first sub-isolated pattern 120BB and the second sub-isolated pattern 120BT to more efficiently prevent light entering from the first color filter 170 from being absorbed by the liner film 120L.

[0176] Referring to FIG. 9d, when the pixel separation pattern 120A and the first separation pattern 120B have four photoelectric conversion layers PD1, PD2, PD3, and PD4 as in FIG. 8b, a second grid pattern 160B covering the four photoelectric conversion layers PD1, PD2, PD3, and PD4 may be provided.

[0177] In Figures 9a to 9d, the width of the second grid pattern 160B is shown to have the same spacing as the width of the first sub-separated pattern 120BB and the second sub-separated pattern 120BT, but this is a non-limiting example and may include cases where the width of the second grid pattern 160B has a wider spacing than the width of the first sub-separated pattern 120BB and the second sub-separated pattern 120BT.

[0178] FIG. 10 is a cross-sectional view taken along line BB' in FIG. 5, illustrating an image sensor according to another embodiment of the present disclosure.

[0179] Referring to FIG. 10, an image sensor according to another embodiment of the present disclosure may include a substrate 100 including a first surface 112a through which light is incident and a second surface 112b opposite to the first surface 112a, a pixel separation pattern 120A defining adjacent unit pixels within the substrate 100, a first photoelectric conversion layer PD1 and a second photoelectric conversion layer PD2 arranged along a first direction D1 within the pixel separation pattern 120A, and a first separation pattern 120B defining the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 within the substrate 100 between the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2, and a third grid pattern 160C arranged on at least one of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2.

[0180] The third grid pattern 160C may be disposed on the first photoelectric conversion layer PD1 in a unit pixel region PX, and on the second photoelectric conversion layer PD2 in another unit pixel region PX. Specifically, the third grid pattern 160C may block either the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2, thereby quickly detecting an optical signal and performing autofocus more quickly.

[0181] For example, in a unit pixel area PX where the third grid pattern 160C blocks the first photoelectric conversion layer PD1, the optical signal of the second photoelectric conversion layer PD2 can be detected more quickly from the light that enters the second photoelectric conversion layer PD2, and in other unit pixel areas PX, the optical signal of the first photoelectric conversion layer PD1 can be detected more quickly from the light that enters the first photoelectric conversion layer PD1, thereby increasing the auto focus contrast in the image sensor.

[0182] Although Figure 10 illustrates the third grid pattern 160C shading the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 in adjacent unit pixel regions PX, this does not limit the present disclosure and may also include cases where the third grid pattern 160C shading the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 in spaced-apart unit pixel regions PX.

[0183] 11a and 11b are enlarged views of areas P2 and P3 in FIG. 10, respectively.

[0184] 11a and 11b, in one embodiment, the third grid pattern 160C may completely cover the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2. The third grid pattern 160C covers the first photoelectric conversion layer PD1 in a unit pixel region PX, and the third grid pattern 160C covers the second photoelectric conversion layer PD2 in another unit pixel region PX, thereby quickly determining the optical signal entering the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2 in each unit pixel region PX, thereby improving the auto focus contrast in the image sensor.

[0185] 12a to 12f are plan views of the P2 region or the P3 region of FIG. 10 cut along the line EE'.

[0186] Referring to Figures 12a and 12b, the third grid pattern 160C may be disposed on the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2, and may not be disposed on the first sub-isolated pattern 120BT and the second sub-isolated pattern 120BB.

[0187] 12c and 12d, the third grid pattern 160C may be disposed on the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2, and may be disposed on at least a portion of the first sub-isolated pattern 120BT and the second sub-isolated pattern 120BB. Specifically, the third grid pattern 160C may cover at least a portion of the width DCW of the first sub-isolated pattern 120BT and the second sub-isolated pattern 120BB.

[0188] 12e and 12f, the third grid pattern 160C may be disposed on the first photoelectric conversion layer PD1 or the second photoelectric conversion layer PD2, and may be disposed to completely cover the first sub-isolated pattern 120BT and the second sub-isolated pattern 120BB.

[0189] 12a to 12f, the third grid pattern 160C completely covers the first sub-isolated pattern 120BT and the second sub-isolated pattern 120BB, thereby preventing the incident light from being absorbed by the liner film 120L of the first sub-isolated pattern 120BT and the second sub-isolated pattern 120BB.

[0190] FIG. 13 is a part of a cross-sectional view taken along line CC' in FIG. 5, showing a cross-sectional view of an image sensor according to one embodiment of the present disclosure.

[0191] Referring to FIG. 13, in one embodiment, the third grid pattern 160C can simultaneously block a portion of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2.

[0192] 14a and 14b are plan views of the P4 and P5 regions of FIG. 13 taken along line EE'.

[0193] Referring to Fig. 14a, the third grid pattern 160C may light-shield the first and second photoelectric conversion layers PD1 and PD2 and the second sub-isolated pattern 120BB. Referring to Fig. 14b, the third grid pattern 160C may light-shield the first and second photoelectric conversion layers PD1 and PD2 and the first sub-isolated pattern 120BT.

[0194] Specifically, the third grid pattern 160C allows the coexistence of unit pixels in which a portion of the first photoelectric conversion layer PD1 and a portion of the second photoelectric conversion layer PD2, for example, the lower or upper region within the unit pixel region PX, is light-shielded, thereby enabling the optical signals for the lower and upper regions within the unit pixel region PX to be detected more quickly, thereby enabling autofocus to be performed more quickly.

[0195] Although Figures 14a and 14b show the third grid pattern 160C completely covering the first sub-isolated pattern 120BT and the second sub-isolated pattern 120BB, this is a non-limiting example, and the third grid pattern 160C may also be arranged to have the same length as the first sub-isolated pattern 120BT and the second sub-isolated pattern 120BB.

[0196] According to another embodiment of the present disclosure, an image sensor includes a substrate 100 including a first surface 112a on which light is incident and a second surface 112b opposite to the first surface 112a, a pixel separation pattern 120A defining adjacent unit pixels in the substrate 100, a first photoelectric conversion layer PD1 and a second photoelectric conversion layer PD2 arranged along a first direction in the pixel separation pattern 120A, a first separation pattern 120B defining the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 in the substrate 100 between the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2, a first grid pattern 160A and a first separation pattern 120B disposed on the pixel separation pattern 120A, The unit pixel may include a second grid pattern 160B arranged on the unit pixel 120B and having a height lower than that of the first grid pattern 160A, and another unit pixel arranged apart from the unit pixel may include a first photoelectric conversion layer PD1 and a second photoelectric conversion layer PD2 arranged along a first direction in the pixel separation pattern 120A, a first separation pattern 120B separating the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 in the substrate 100 between the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2, and a third grid pattern 160C arranged on at least one of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2.

[0197] In one embodiment, the second grid pattern 160B may be disposed between the first isolated pattern 120B and the third grid pattern 160C. Specifically, the third grid pattern 160C may cover at least a portion of the second grid pattern 160B. For example, the third grid pattern 160C may cover a portion of the second grid pattern 160B, or may cover the entire second grid pattern 160B.

[0198] Specifically, some unit pixels in the image sensor include a second grid pattern 160B, and other unit pixels arranged adjacent to or spaced apart from the unit pixels include a structure in which at least a portion of the first photoelectric conversion layer PD1 and the second photoelectric conversion layer PD2 are light-shielded, thereby enabling autofocus to be performed more quickly from the unit pixels having the light-shielded structure, and at the same time increasing the photosensitivity from the unit pixels including the second grid pattern 160B, thereby ensuring a high autofocus separation ratio.

[0199] 15a-15h illustrate a method of manufacturing an image sensor according to one embodiment of the present disclosure.

[0200] 15a, a first substrate 100 may be provided that includes a second surface 112b and a third surface 110c facing each other. An isolation pattern 105 may be formed in the first substrate 110. A trench may be formed in the first substrate 110, the trench being partially recessed from the second surface 112b of the first substrate 100. An isolation pattern 105 may be formed in the trench. The isolation pattern 105 may define an active region.

[0201] 15b, a first mask film M1 may be formed on the second surface 112b of the first substrate 110. The first mask film M1 may have openings that roughly define the positions of the first trench t1 and the second trench t2. The first mask film M1 may be formed of at least one of a photoresist film, an amorphous carbon layer (ACL), a spin on hardmask (SOH), a spin on carbon (SOC), a silicon oxide film, and a silicon nitride film. Then, a first trench t1 may be formed using the first mask film M1 as an etching mask. The first trench t1 may penetrate the isolation pattern 105.

[0202] 15c, a pre-liner film 120Lp may be formed along the sidewalls and bottom surfaces of the first trench t1 and the second trench t2, and a pre-pixel isolation filling film 120Fp may be formed on the pre-liner film 121Lp.

[0203] The pre-liner film 121Lp may extend along the upper surface of the first mask film M1. The pre-liner film 121Lp may include an insulating material. As non-limiting examples, the pre-liner film 121Lp may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof.

[0204] The pre-pixel isolation filling layer 120Fp may include an insulating material or a conductive material. The insulating material may include silicon-based insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride, and high-k materials such as hafnium oxide, aluminum oxide, and tantalum oxide. The conductive material may include, but is not limited to, polysilicon (Poly Si), or silicon doped with bismuth (As), phosphorus (P), boron (B), or carbon (C).

[0205] The pre-pixel isolation filling film 120Fp is formed deep in the direction from the second surface 110a to the third surface 110c to form a front deep trench isolation (FDTI), and the pre-pixel isolation filling film 120Fp can be filled into the first trench t1 and the second trench t2 to form the first isolation pattern 120B and the pixel isolation pattern 120A, respectively.

[0206] 15d, a pixel isolation pattern 120A and a first isolation pattern 120B may be formed. The pixel isolation pattern 120A may include a liner film 120L, a first pixel isolation filling film 120F1, and a capping film 120C. The first isolation pattern 120B may include a liner film 120L, a first isolation filling film 120F2, and a capping film 120C.

[0207] First, a portion of the pre-pixel isolation filling film 120Fp may be etched to form a first pixel isolation filling film 120F1 and a first isolation filling film 120F2. The first pixel isolation filling film 120F1 and the first isolation filling film 120F2 may be formed through an etch-back process. Then, a pre-capping film (not shown) may be formed on the first pixel isolation filling film 120F1 and the first isolation filling film 120F2. Then, a portion of the pre-capping film, a portion of the pre-liner film 121Lp, and the first mask film M1 may be removed to form the liner film 121L and the capping film 120C. A portion of the pre-capping film, a portion of the pre-liner film 121Lp, and the first mask film M1 may be removed to expose the first surface 110b of the first substrate 110.

[0208] 15e, the first surface 112a may be formed by polishing the third surface 110c, which is the rear surface of the first substrate 110. Various polishing methods, such as, but not limited to, CMP (Chemical Mechanical Polishing), may be used to polish the third surface 110c. Through the polishing method, polishing is performed such that portions of the first pixel isolation filling layer 120F1 and the first isolation filling layer 120F2 are exposed in the same line as the first surface 112a.

[0209] Thereafter, a step of cleaning the first surface 112a of the substrate 110 may be performed. As a non-limiting example, the step of cleaning the first surface 112a of the substrate 110 may be performed using a material such as HF.

[0210] 15f, a surface insulating film 150 may be applied on the cleaned first surface 112a. The surface insulating film 150 may include an insulating material. For example, the surface insulating film 150 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, titanium oxide, and combinations thereof.

[0211] 15g, a step of forming a first lower grid pattern 160AB and a second lower grid pattern 160B on the surface insulating layer 150. The first lower grid pattern 160AB and the second lower grid pattern 160B may be made of the same material and may be formed, for example, through a deposition or coating step. In one embodiment, the first lower grid pattern 160AB and the second lower grid pattern 160B may be deposited or coated to the same height.

[0212] 15h, a step of forming an upper first grid pattern 160AT on the lower first grid pattern 160AB may be performed. Since the upper first grid pattern 160AB is deposited or coated on the lower first grid pattern 160AB, the first grid pattern 160A including the upper first grid pattern 160AT and the lower first grid pattern 160AB is formed higher than the second grid pattern 160B, so that when light is incident due to a shift, the incident light can be controlled to easily enter the photoelectric conversion layers PD1 and PD2.

[0213] As described above, the first grid pattern 160A and the second grid pattern 160B are formed in a stack structure, which has an advantage that the process can be simplified and an image sensor with high light yield can be efficiently manufactured.

[0214] The present disclosure is not limited to the above-mentioned embodiment, and can be manufactured in various different forms, and a person having ordinary skill in the art to which the present disclosure pertains can understand that the present disclosure can be embodied in other specific forms without changing the technical idea or essential features of the present disclosure. Therefore, it should be understood that the above-described embodiment is illustrative and not limiting in all respects. [Explanation of symbols]

[0215] 100: First substrate structure 200: Second board structure PX: unit pixel area 120A: Pixel separation pattern 120B: First separation pattern 150: Surface insulating film 160A: First grid pattern 160B: Second grid pattern 160C: 3rd grid pattern

Claims

1. a substrate including a first surface onto which light is incident and a second surface opposite the first surface; a pixel separation pattern defining adjacent unit pixels within the substrate; a first photoelectric conversion layer and a second photoelectric conversion layer arranged along a first direction in the pixel separating pattern; a first isolation pattern defining the first photoelectric conversion layer and the second photoelectric conversion layer within the substrate between the first photoelectric conversion layer and the second photoelectric conversion layer; a first grid pattern disposed over the pixel separating pattern; and The image sensor includes a second grid pattern disposed over the first isolation pattern and having a height less than a height of the first grid pattern.

2. 2. The image sensor of claim 1, wherein the height of the second grid pattern is in the range of 1 / 10 to 1 / 4 of the height of the first grid pattern.

3. 2. The image sensor of claim 1, further comprising a first color filter disposed over the first grid pattern and the second grid pattern, the first color filter having a refractive index higher than a refractive index of the second grid pattern.

4. The image sensor of claim 1 , wherein the first grid pattern includes a lower first grid pattern and an upper first grid pattern disposed over the lower first grid pattern.

5. The image sensor of claim 4 , wherein the lower first grid pattern and the lower second grid pattern have the same height.

6. a third photoelectric conversion layer disposed adjacent to the first photoelectric conversion layer in a second direction within the unit pixel; and Further comprising a fourth photoelectric conversion layer disposed adjacent to the second photoelectric conversion layer in the second direction, The image sensor of claim 1 , wherein the third photoelectric conversion layer and the fourth photoelectric conversion layer are defined by the first isolation pattern.

7. 2. The image sensor of claim 1, wherein the first separation pattern comprises a first sub-separation pattern and a second sub-separation pattern spaced apart by a predetermined distance.

8. The image sensor of claim 7 , wherein the second grid pattern is greater than or equal to an area of ​​the first sub-isolation pattern and the second sub-isolation pattern.

9. Another unit pixel disposed apart from the unit pixel is a first photoelectric conversion layer and a second photoelectric conversion layer arranged along a first direction in the pixel separating pattern; a first isolation pattern within the substrate between the first photovoltaic conversion layer and the second photovoltaic conversion layer, the first isolation pattern defining the first photovoltaic conversion layer and the second photovoltaic conversion layer; and The image sensor of claim 1 , further comprising a third grid pattern disposed on at least one of the first photoelectric conversion layer and the second photoelectric conversion layer.

10. a substrate including a first surface onto which light is incident and a second surface opposite the first surface; a pixel separation pattern defining adjacent unit pixels within the substrate; a first photoelectric conversion layer and a second photoelectric conversion layer arranged along a first direction in the pixel separating pattern; a first isolation pattern defining the first photoelectric conversion layer and the second photoelectric conversion layer within the substrate between the first photoelectric conversion layer and the second photoelectric conversion layer; a surface insulating film disposed on the pixel separating pattern, the first photoelectric conversion layer, the second photoelectric conversion layer, and the first separating pattern; a first grid pattern disposed on the surface insulating film disposed on the pixel separating pattern; a second grid pattern disposed on the surface insulating film disposed on the first isolation pattern and having a height lower than a height of the first grid pattern; and a color filter disposed over the first grid pattern and the second grid pattern; a height of the second grid pattern satisfies 1 / 10 to 1 / 4 of a height of the first grid pattern.

Images