Semiconductor device

Abstract

To provide a semiconductor device and an electronic system including the same that improve reliability and performance.SOLUTION: A semiconductor device 10 includes a gate stack structure 120 including a first stack structure 120a and a second stack structure 120b that are sequentially stacked, respectively including a plurality of gate electrodes 130, a channel structure CH penetrating the gate stack structure, a plurality of gate contact portions 184 respectively connected to the plurality of gate electrodes in first and second pad regions formed in each stack structure, and a buffer insulating portion 132p formed in the first stack structure including a boundary part of the first stack structure adjacent to the second stack structure in a part where the second pad region is located. The buffer insulating portion includes an inner region, a first region located on one side of the inner region in an extension direction of the plurality of gate electrodes, and a second region located on the other side, and the first and second regions are each longer in the extension direction at an upper portion than at a lower portion, and a difference between the length at the upper portion and the length at the lower portion is larger in the second region than in the first region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and an electronic system including the same. [Background technology]

[0002] In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing a large amount of data. To this end, methods for increasing the data storage capacity of semiconductor devices have been researched. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] The embodiments provide a semiconductor device and an electronic system including the same that can improve reliability and performance. [Means for solving the problem]

[0004] The semiconductor device according to the embodiment includes a gate stack structure including a first stack structure and a second stack structure stacked in sequence, each of which includes a plurality of gate electrodes; a channel structure penetrating the gate stack structure; a plurality of gate contact portions respectively connected to the plurality of gate electrodes in first and second pad regions formed in the first and second stack structures, respectively; and a buffer insulating portion formed in the first stack structure including a boundary portion of the first stack structure adjacent to the second stack structure where the second pad region is located.

[0005] In this case, the buffer insulating portion includes an inner region, a first region located on one side of the inner region in an extension direction of the plurality of gate electrodes, and a second region located on the other side of the inner region in the extension direction. The first region and the second region each have a longer length in the extension direction at an upper portion than at a lower portion. The difference between the length at the upper portion and the length at the lower portion is larger in the second region than in the first region.

[0006] Alternatively, at least one of the first and second pad regions includes a pad region to which the gate electrodes and the gate contacts are respectively connected, and an upper region located on the pad region. The buffer insulating portion includes an inner region, a first region located on one side of the inner region in an extension direction of the gate electrodes, and a second region located on the other side of the inner region in the extension direction. A first distance between one of the gate electrodes and the inner region in the first region, and a second distance between one of the gate electrodes and the inner region in the second region are each greater than a third distance. The third distance is a distance between one gate electrode and the upper region in the upper region, or a distance between one gate electrode and the inner region of the upper region.

[0007] An electronic system according to an embodiment includes a main board, the above-described semiconductor device located on the main board, and a controller electrically connected to the semiconductor device on the main board. Effect of the Invention

[0008] According to the embodiment, the problem of the gate electrode being damaged due to the detachment or misalignment of the gate contact portion can be essentially prevented by the buffer insulating portion provided in the lower structure. At this time, since the side area of ​​the buffer insulating portion has a gentle slope, defects or failures due to gaps occurring in the buffer insulating portion near the corners of the buffer insulating portion can be prevented. As a result, the reliability and performance of the semiconductor device can be improved. Since the buffer insulating portion has a shape corresponding to or a symmetrical shape of the pad insulating portion provided in at least a part of the pad region, the buffer insulating portion can be formed by a simple process. [Brief description of the drawings]

[0009] [Figure 1] 1 is a partial plan view showing a semiconductor device according to an embodiment; [Diagram 2] 2 is a partial cross-sectional view of the semiconductor device taken along lines AA', BB', and CC' in FIG. [Diagram 3] 2 is a partial cross-sectional view showing an example of a channel structure included in the semiconductor device shown in FIG. [Figure 4] 2 is a schematic partial cross-sectional view of the semiconductor device taken along line DD' in FIG. [Diagram 5] 2 is a partial plan view showing an upper surface of a second stacked structure in the semiconductor device shown in FIG. 1. [Figure 6] 5 is an enlarged view of a portion corresponding to part A in FIG. 4 where no gate contact portion is provided. [Figure 7a] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7b] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7c] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7d] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7e] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7f] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7g] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7h] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7i] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] FIG. 11 is a partial cross-sectional view showing a schematic configuration of a semiconductor device according to another embodiment. [Figure 9] FIG. 11 is a partial cross-sectional view showing a schematic configuration of a semiconductor device according to another embodiment. [Figure 10] 10 is an enlarged view of a portion of the semiconductor device shown in FIG. 9. [Figure 11] FIG. 11 is a partial cross-sectional view showing a schematic configuration of a semiconductor device according to another embodiment. [Figure 12] FIG. 11 is a partial cross-sectional view showing a schematic configuration of a semiconductor device according to another embodiment. [Figure 13] 11 is a schematic partial cross-sectional view of a semiconductor device according to a further embodiment; FIG. [Figure 14] 1 is a diagram illustrating an electronic system including a semiconductor device according to an exemplary embodiment; [Figure 15] 1 is a perspective view showing a schematic diagram of an electronic system including a semiconductor device according to an exemplary embodiment; [Figure 16] 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. [Figure 17] 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art may realize, the embodiments may be realized in many different forms and are not limited to the embodiments set forth herein.

[0011] In order to clearly explain the present disclosure, parts not necessary for the explanation will be omitted, and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0012] In addition, the size and thickness of each component shown in the drawings are merely shown arbitrarily for convenience of explanation, and the present disclosure is not limited to the drawings. For convenience of explanation and / or easy illustration, the thickness of some layers and regions are enlarged or exaggerated.

[0013] In addition, when a part such as a layer, film, region, or plate is said to be "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between. In addition, being "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" the opposite direction to gravity.

[0014] Furthermore, throughout the specification, when a part is said to "comprise" a certain element, this does not mean that it excludes other elements and may further include other elements, unless specifically stated to the contrary.

[0015] Additionally, throughout the specification, "on a plane" or "when viewed in a plane" means when the target part is viewed from above, and "on a cross section" or "when viewed in cross section" means when the target part is cut vertically and viewed from the side.

[0016] A semiconductor device and a method for manufacturing the same according to an embodiment will be described in detail below with reference to FIGS. 1 to 6 and 7a to 7i.

[0017] Fig. 1 is a partial plan view showing a semiconductor device according to an embodiment, and Fig. 2 is a partial cross-sectional view of the semiconductor device taken along lines A-A', B-B', and C-C' in Fig. 1. Fig. 3 is a partial cross-sectional view showing an example of a channel structure included in the semiconductor device shown in Fig. 1.

[0018] For the sake of simple illustration and clear understanding, FIG 1 omits the illustration of the second wiring portion 180 and focuses on the channel structure CH and the gate contact portion 184. In FIG 1, two consecutive dotted or solid lines may represent dummy areas (reference symbol DS in FIG 4) in each pad area PA. For the sake of simple illustration, FIG 1 and the corresponding FIG 5 show the same intervals between the gate contact portions 184.

[0019] 1 to 3, a semiconductor device 10 according to an embodiment may include a cell region 100 in which a memory cell structure is provided, and a circuit region 200 in which a peripheral circuit structure for controlling the operation of the memory cell structure is provided. As an example, the circuit region 200 and the cell region 100 may be parts corresponding to a first structure 1100F and a second structure 1100S of a semiconductor device 1100 included in an electronic system 1000 shown in FIG. 14, respectively. Alternatively, the circuit region 200 and the cell region 100 may be parts including a first structure 3100 and a second structure 3200 of a semiconductor chip 2200 shown in FIG. 16, respectively.

[0020] Here, the circuit region 200 may include a peripheral circuit structure formed on the first substrate 210, and the cell region 100 may include a gate stack structure 120 and a channel structure CH formed on the cell array region 102 of the second substrate 110 as a memory cell structure. The circuit region 200 may include a first wiring unit 230, and the cell region 100 may include a second wiring unit 180 electrically connected to the memory cell structure.

[0021] In an exemplary embodiment, the cell region 100 may be located on the circuit region 200. This eliminates the need to secure an area corresponding to the circuit region 200 separately from the cell region 100, thereby reducing the area of ​​the semiconductor device 10. However, the embodiment is not limited thereto, and the circuit region 200 may be located to the side of the cell region 100. Various other modifications are possible.

[0022] The circuit region 200 may include a first substrate 210 , and a circuit element 220 and a first wiring portion 230 formed on the first substrate 210 .

[0023] The first substrate 210 may be a semiconductor substrate including a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate made of a semiconductor material, or may be a semiconductor substrate in which a semiconductor layer is formed on a base substrate. For example, the first substrate 210 may be made of single crystal or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like.

[0024] The circuit elements 220 formed on the first substrate 210 may include various circuit elements that control the operation of the memory cell structures included in the cell region 100. As an example, the circuit elements 220 may constitute peripheral circuit structures such as a decoder circuit (reference numeral 1110 in FIG. 14), a page buffer (reference numeral 1120 in FIG. 14), and a logic circuit (reference numeral 1130 in FIG. 14).

[0025] The circuit element 220 may include, but is not limited to, a transistor, for example, and may include passive elements such as a capacitor, a resistor, an inductor, and the like, in addition to active elements such as a transistor.

[0026] The first wiring unit 230 located on the first substrate 210 may be electrically connected to the circuit element 220. In an exemplary embodiment, the first wiring unit 230 may include a plurality of wiring layers 236 spaced apart from each other by a first insulating layer 232 and connected to form a desired path by a contact via 234. The wiring layers 236 or the contact vias 234 may include various conductive materials, and the first insulating layer 232 may include various insulating materials. As an example, the uppermost wiring layer 236 located adjacent to the cell region 100 among the plurality of wiring layers 236 may include or form a pad portion to which the gate contact portion 184, the through plug 188, etc. are connected.

[0027] The cell region 100 may include a cell array region 102 and a connection region 104. In the cell array region 102, a gate stack structure 120 and a channel structure CH may be formed on a second substrate 110. A structure for connecting the gate stack structure 120 and / or the channel structure CH formed in the cell array region 102 to a circuit region 200 or an external circuit may be located in the cell array region 102 and / or the connection region 104.

[0028] In an embodiment, the second substrate 110 may include a semiconductor layer including a semiconductor material. For example, the second substrate 110 may be a semiconductor substrate made of a semiconductor material, or may be a substrate having a semiconductor layer formed on a base substrate. For example, the second substrate 110 may be made of silicon, germanium, silicon-germanium, silicon-on-insulator, or germanium-on-insulator. Here, the semiconductor layer included in the second substrate 110 may be doped with p-type or n-type impurities, for example, n-type impurities (e.g., phosphorus (P), arsenic (As), etc.). The second substrate 110 may include a substrate insulating portion 110i in a region through which the gate contact portion 184 passes. However, the embodiment is not limited to the material of the second substrate 110, the conductive type of the impurities doped in the semiconductor layer, the material, and the like.

[0029] In the cell array region 102, a gate stack structure 120 including cell insulating layers 132 and gate electrodes 130 alternately stacked on a first surface (for example, a front or top surface) of the second substrate 110, and a channel structure CH extending through the gate stack structure 120 in a direction intersecting the second substrate 110 may be formed.

[0030] In an exemplary embodiment, horizontal conductive layers 112 and 114 may be provided between the second substrate 110 and the gate stack structure 120 in the cell array region 102. The horizontal conductive layers 112 and 114 serve to electrically connect the channel structure CH to the second substrate 110. As an example, the horizontal conductive layers 112 and 114 may include a first horizontal conductive layer 112 located on a first surface of the second substrate 110, and may further include a second horizontal conductive layer 114 located on the first horizontal conductive layer 112. The first horizontal conductive layer 112 may not be provided between the second substrate 110 and the gate stack structure 120 in a portion of the connection region 104, and a horizontal insulating layer 116 may be provided instead. In a manufacturing process, a portion of the horizontal insulating layer 116 may be replaced by the first horizontal conductive layer 112, but another portion of the horizontal insulating layer 116 located in the connection region 104 may remain in the connection region 104.

[0031] The first horizontal conductive layer 112 may function as a part of a common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 may function as a common source line together with the second substrate 110. As shown in the enlarged view of FIG. 3 , the channel structure CH may extend through the horizontal conductive layers 112, 114 to reach the second substrate 110, and the gate dielectric layer 150 may be removed where the first horizontal conductive layer 112 is located, so that the first horizontal conductive layer 112 may be directly connected to the channel layer 140 around the channel layer 140.

[0032] The first and second horizontal conductive layers 112, 114 may include a semiconductor material (e.g., polycrystalline silicon). For example, the first horizontal conductive layer 112 may be a polycrystalline silicon layer doped with impurities, and the second horizontal conductive layer 114 may be a polycrystalline silicon layer doped with impurities or a layer containing impurities diffused from the first horizontal conductive layer 112. However, the embodiment is not limited thereto, and the second horizontal conductive layer 114 may be made of an insulating material. Alternatively, the second horizontal conductive layer 114 may not be provided separately.

[0033] A gate stack structure 120 in which cell insulating layers 132 and gate electrodes 130 are alternately stacked may be located on the second substrate 110 (for example, on the first and second horizontal conductive layers 112, 114 formed on the second substrate 110).

[0034] In the gate stack structure 120, the gate electrode 130 may include a lower gate electrode, a memory cell gate electrode, and an upper gate electrode, which are sequentially arranged from above the second substrate 110. The lower gate electrode may be used as a gate electrode of a ground selection transistor, the memory cell gate electrode may constitute a memory cell, and the upper gate electrode may be used as a gate electrode of a string selection transistor. The number of memory cell gate electrodes may be determined according to the data storage capacity of the semiconductor device 10. Depending on the embodiment, the lower gate electrode and the upper gate electrode may each be one or more than two, and may have the same structure as or a different structure from the memory cell gate electrode. In addition, a part of the gate electrode 130, for example, the memory cell gate electrode adjacent to the lower gate electrode and the upper gate electrode, may be a dummy gate electrode.

[0035] The cell insulating layer 132 may include an interlayer insulating layer 132m located between two adjacent gate electrodes 130 in each of the gate stack structures 120a, 120b, and 120c, and upper insulating layers 132a, 132b, and 132c located on each of the gate stack structures 120a, 120b, and 120c. The cell insulating layer 132 may further include a pad insulating portion 132i formed by filling a recess portion RP provided in the pad region PA, and a buffer insulating portion 132p formed by filling a buffer recess portion BR. The pad insulating portion 132i and / or the buffer insulating portion 132p may form a part of the upper insulating layer 132a, 132b, and 132c, or may be formed as a part of the upper insulating layer 132a, 132b, and 132c. Alternatively, the pad insulation portion 132i and / or the buffer insulation portion 132p may be provided separately from the upper insulation layers 132a, 132b, 132c.

[0036] In the embodiment, the thicknesses of the cell insulating layers 132 may not all be the same. For example, the thicknesses of the upper insulating layers 132a, 132b, and 132c may be greater than the thickness of the interlayer insulating layer 132m. For simplicity of illustration, the drawings show an example in which one cell insulating layer 132 is provided without boundaries in the connection region 104. However, one or more insulating layers may have various stacked structures in the connection region 104. The shape and structure of the cell insulating layer 132 may be variously modified depending on the embodiment.

[0037] The gate electrode 130 may include various conductive materials. For example, the gate electrode 130 may include metal materials such as tungsten (W), copper (Cu), aluminum (Al), polycrystalline silicon, metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or combinations thereof. As shown in the enlarged view of FIG. 3, a part (e.g., a first blocking layer 156a) of the blocking layer 156 made of an insulating material may be located outside the gate electrode 130. The cell insulating layer 132 may include various insulating materials. For example, the cell insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant smaller than that of silicon oxide, or a combination thereof.

[0038] In one embodiment, a channel structure CH may be formed that extends through the gate stack 120 in a direction intersecting the second substrate 110 (for example, a vertical direction perpendicular to the second substrate 110) (Z-axis direction in the drawing).

[0039] The channel structure CH may include a channel layer 140 and a gate dielectric layer 150 located on the channel layer 140 between the gate electrode 130 and the channel layer 140. The channel structure CH may further include a core insulating layer 142 located inside the channel layer 140, or, as an alternative example, the core insulating layer 142 may not be provided. The channel structure CH may further include a channel pad 144 disposed on the channel layer 140 and / or the gate dielectric layer 150. The gate dielectric layer 150 located between the gate electrode 130 and the channel layer 140 may include a tunneling layer 152, a charge storage layer 154, and a blocking layer 156 sequentially formed on the channel layer 140.

[0040] Each channel structure CH forms one memory cell string, and a plurality of channel structures CH may be arranged in rows and columns on a plane, spaced apart from each other. For example, a plurality of channel structures CH may be arranged in various patterns, such as a lattice pattern or a zigzag pattern, on a plane. The channel structures CH may have a columnar shape. For example, when viewed in cross section, the channel structures CH may have inclined sides such that the width becomes narrower as they approach the second substrate 110 according to the aspect ratio. However, the embodiment is not limited thereto, and the arrangement, structure, shape, and the like of the channel structures CH may be modified in various ways.

[0041] The channel layer 140 may include a semiconductor material, such as polycrystalline silicon. The core insulating layer 142 may include a variety of insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0042] The tunneling layer 152 may include an insulating material (e.g., silicon oxide, silicon oxynitride, etc.) that allows tunneling of charges. The charge storage layer 154 is used as a data storage region, and may include polycrystalline silicon, silicon nitride, etc. The blocking layer 156 may include an insulating material that can prevent unintentional flow of charges into the gate electrode 130. For example, the blocking layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. In one embodiment, the blocking layer 156 may include a first blocking layer 156a including a portion extending horizontally along the gate electrode 130, and a second blocking layer 156b extending vertically between the first blocking layer 156a and the charge storage layer 154.

[0043] However, the materials and stacked structures of the channel layer 140, the core insulating layer 142, and the gate dielectric layer 150 can be modified in various ways, and the embodiment is not limited thereto.

[0044] A channel pad 144 may be disposed to cover an upper surface of the core insulating layer 142 and to be electrically connected to the channel layer 140. The channel pad 144 may include a conductive material, for example, but is not limited to, polysilicon doped with impurities.

[0045] In an exemplary embodiment, the gate stack structure 120 may include a plurality of gate stack structures 120a, 120b, and 120c sequentially stacked on the second substrate 110. This allows the number of stacked gate electrodes 130 to be increased, thereby increasing the number of memory cells with a stable structure. FIG. 2 illustrates an example in which the gate stack structure 120 includes first to third stack structures 120a, 120b, and 120c. However, the embodiment is not limited thereto, and the gate stack structure 120 may be composed of two or four or more gate stack structures.

[0046] When the plurality of gate stack structures 120a, 120b, and 120c are provided as described above, the channel structure CH may include a plurality of channel structures CH1, CH2, and CH3 that penetrate the plurality of gate stack structures 120a, 120b, and 120c, respectively. The plurality of channel structures CH1, CH2, and CH3 may have a shape connected to each other. The plurality of channel structures CH1, CH2, and CH3 may have inclined sides so that the width becomes narrower toward the second substrate 110 according to the aspect ratio when viewed in cross section, and a bent part due to the difference in width may be provided at the connection part of the plurality of channel structures CH1, CH2, and CH). As another example, the plurality of channel structures CH1, CH2, and CH3 may have inclined sides that are continuously connected without a bent part. FIG. 3 illustrates an example in which the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel structures CH1, CH2, and CH3 extend to each other to have an integral structure. However, the embodiment is not limited thereto, and the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the channel structures CH1, CH2, and CH3 may be formed separately and electrically connected to each other. Also, a separate channel pad may be additionally provided at the connection portion of the channel structures CH1, CH2, and CH3. Thus, the embodiment is not limited to the form of the channel structures CH1, CH2, and CH3.

[0047] In one embodiment, the gate stack structure 120 may be divided into a plurality of sections on a plane by isolation structures 146 extending in a direction intersecting the second substrate 110 (for example, a vertical direction, the Z-axis direction in the drawing) and penetrating the gate stack structure 120. An upper isolation region 148 may be formed on the upper part of the gate stack structure 120. The isolation structures 146 and / or upper isolation regions 148 may be provided in a plurality of sections on a plane, extending in a first direction (the Y-axis direction in the drawing) and spaced apart from each other at a predetermined interval in a second direction intersecting the first direction (the X-axis direction in the drawing).

[0048] The isolation structures 146 allow the gate stack structures 120 to extend in a first direction (Y-axis direction in the drawing) and be spaced apart from each other at a predetermined interval in a second direction (X-axis direction in the drawing) on ​​a plane. The gate stack structures 120 partitioned by the isolation structures 146 may constitute one memory cell block. However, the embodiment is not limited thereto, and the scope of the memory cell block is not limited thereto.

[0049] For example, the isolation structures 146 may extend through the gate stack 120 to the second substrate 110, and the upper isolation regions 148 may separate only one or a portion of the gate electrodes 130 from each other. The upper isolation regions 148 may be located between the isolation structures 146.

[0050] As an example, the separation structure 146 has an inclined side surface with a width gradually decreasing toward the second substrate 110 when viewed in cross section due to a high aspect ratio, but the embodiment is not limited thereto. The side surface of the separation structure 146 may be perpendicular to the second substrate 110 or may include a bent portion at a connection portion of the multiple laminated structures 120a, 120b, and 120c.

[0051] The isolation structure 146 or the upper isolation region 148 may be filled with various insulating materials. For example, the isolation structure 146 or the upper isolation region 148 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, the embodiment is not limited thereto, and the structure, shape, material, and the like of the isolation structure 146 or the upper isolation region 148 may be modified in various ways.

[0052] A connection region 104 and a second wiring unit 180 may be provided to connect the gate stack structure 120 and the channel structure CH provided in the cell array region 102 to the circuit region 200 or an external circuit. The connection region 104 may be disposed on the periphery of the cell array region 102, and a portion of the second wiring unit 180 may be located therein.

[0053] Here, the second wiring unit 180 may include all of the gate electrode 130, the channel structure CH, the horizontal conductive layers 112, 114, and / or the components that electrically connect the second substrate 110 to the circuit region 200 or an external circuit. For example, the second wiring unit 180 may include a bit line 182, a gate contact unit 184, a source contact unit 186, a through plug 188, contact vias 180a connected thereto, and a connecting wire 190 connecting these together.

[0054] The bit lines 182 may be positioned on the cell insulating layer 132 of the gate stack structure 120 formed in the cell array region 102. The bit lines 182 may extend in a direction (X-axis direction in the drawing) intersecting one direction in which the gate electrodes 130 extend. The bit lines 182 may be electrically connected to a channel structure CH, e.g., a channel pad 144, through contact vias 180a, e.g., bit line contact vias.

[0055] In one embodiment, the gate electrodes 130 and the interlayer insulating layer 132m of the plurality of stacked structures 120a, 120b, and 120c may extend in a first direction (the Y-axis direction in the drawing) in the connection region 104. The connection region 104 may also include a plurality of pad regions PA to which the gate contact parts 184 and the gate electrodes 130 are connected.

[0056] In the pad region PA, the gate electrode 130 is removed to form a recess RP, and pad portions PP1 and PP2 of the plurality of connection gate electrodes 130c may be exposed at the top. The pad portions PP1 and PP2 may be located at ends of the connection gate electrodes 130c far away from the cell array region 102 and may have a greater thickness than other portions. The recess RP in the pad region PA may be filled with a pad insulating portion 132i.

[0057] In the drawings, the pad portions PP1 and PP2 provided in one pad area PA are illustrated as having a first pad portion PP1 having a relatively short length and a second pad portion PP2 having a relatively long length. Such second pad portion PP2 may be formed in consideration of the arrangement of the first wiring part 230 and the manufacturing process of the semiconductor device 10. The second pad portion PP2 may be periodically positioned with a plurality of first pad portions PP1 therebetween, but the embodiment is not limited thereto.

[0058] In each pad region PA, the gate contact portion 184 is electrically connected to a connecting gate electrode 130c having pad portions PP1 and PP2 among the multiple gate electrodes 130 included in the gate stack structure 120, and can be insulated from the remaining gate electrodes 130r by an insulating pattern 184i therebetween.

[0059] For example, the gate contact portion 184 may penetrate the pad portions PP1 and PP2 of the connection gate electrode 130c and be connected to the inner surfaces of the pad portions PP1 and PP2. For example, the gate contact portion 184 may include a connection portion 184c that protrudes from the inner surfaces of the pad portions PP1 and PP2 and directly contacts the pad portions PP1 and PP2. The width of the insulating pattern 184i in the horizontal direction may be greater than the thickness of the remaining gate electrode 130r in the vertical or thickness direction. This can effectively insulate the remaining gate electrode 130r from the gate contact portion 184, but the embodiment is not limited thereto.

[0060] The gate contact portion 184 may extend through the gate stack structure 120 and the like to a pad portion provided on the uppermost portion of the wiring layers 236 of the circuit region 200 and be connected to the pad portion. As a result, the gate contact portion 184 is connected to the circuit region 200 without passing through the connecting wire 190 and the like, thereby improving the design freedom of the second wiring portion 180. However, the manner of connecting the gate contact portion 184 to the circuit region 200 may be modified in various ways. As another example, as shown in FIG. 13, the gate contact portion 184 may be connected to the circuit region (reference numeral 200a in FIG. 13) through the connecting wire 190 and the second junction structure 194. This will be described in detail below with reference to FIG. 13.

[0061] The gate contact portion 184 may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and may further include a diffusion barrier layer. However, the embodiment is not limited to the material of the gate contact portion 184.

[0062] In the connection region 104, the source contact portion 186 may penetrate the cell insulating layer 132 to be electrically connected to the horizontal conductive layers 112, 114 and / or the second substrate 110, and the through plug 188 may penetrate the gate stack structure 120 or be disposed outside the gate stack structure 120 to be electrically connected to the first wiring portion 230 of the circuit region 200.

[0063] A dummy structure (not shown) may be further provided in the connection region 104. The dummy structure serves to reduce stress that may be applied to the gate stack structure 120. The dummy structure may have the same or similar structure or shape as the channel structure CH, but is not electrically connected to the bit line 182. The dummy structure may be formed in the same process as the channel structure CH and may have the same structure, shape, material, etc., or may be formed in a separate process from the channel structure CH and may have a different structure, shape, material, etc., from the channel structure CH. In an exemplary embodiment, the dummy structure may have a planar size larger than that of the channel structure CH. However, the embodiment is not limited thereto, and the shape, position, arrangement, number, etc. of the dummy structure may be variously modified.

[0064] The connecting wires 190 may be located in the cell array region 102 and / or the connecting region 104. The bit lines 182, the source contact portions 186 and / or the through plugs 188 may be electrically connected to the connecting wires 190. For example, the source contact portions 186 and / or the through plugs 188 may be connected to the connecting wires 190 through contact vias 180a. In an exemplary embodiment, the contact vias 180a and the connecting wires 190 connected to the gate contact portions 184 are not provided, which may improve the design freedom of the second wiring portion 180. However, the contact vias 180a and the connecting wires 190 connected to the gate contact portions 184 may be provided according to an embodiment.

[0065] 1 shows an example in which the connecting wire 190 is provided as a single layer located on the same plane as the bit line 182, and the second insulating layer 192 is located in a portion other than the second wiring portion 180. However, this is merely a simplified illustration for convenience. Therefore, the connecting wire 190 may include multiple wiring layers for electrical connection with the bit line 182, the gate contact portion 184, the source contact portion 186, and / or the through plug 188, and may further include contact vias.

[0066] In this manner, the second wiring unit 180 and the first wiring unit 230 may electrically connect the bit line 182, the gate electrode 130, the horizontal conductive layers 112, 114 and / or the second substrate 110 connected to the channel structure CH to the circuit element 220 in the circuit region 200.

[0067] 2, the gate contact portion 184, the source contact portion 186 and / or the through plug 188 have inclined sides that narrow toward the second substrate 110 according to the aspect ratio when viewed in cross section, and have a bent portion at the boundary portion 120p of the plurality of stacked structures 120a, 120b, 120c. However, the embodiment is not limited thereto. It is also possible that the source contact portion 186 and / or the through plug 188 does not have a bent portion at the boundary portion 120p of the plurality of stacked structures 120a, 120b, 120c. Various other modifications are possible.

[0068] In this embodiment, a buffer insulating portion 132p is provided adjacent to a boundary portion 120p between the plurality of stacked structures 120a, 120b, and 120c to prevent problems caused by detachment or misalignment of the gate contact portion 184 that may occur at the boundary portion 120p. The pad region PA, the pad insulating portion 132i formed therein, and the buffer insulating portion 132p will be described in more detail with reference to FIGS. 1 and 2 as well as FIGS. 4 to 6.

[0069] Fig. 4 is a schematic partial cross-sectional view of the semiconductor device 10 taken along line D-D' in Fig. 1. Fig. 5 is a partial plan view showing the upper surface of the second stacked structure 120b in the semiconductor device 10 shown in Fig. 1. For simplified illustration and clear understanding, Fig. 4 omits illustration of the second wiring portion 180 and only shows the shape of the gate contact portion 184. Fig. 5 mainly illustrates the channel structure CH, the gate contact portion 184, etc., corresponding to Fig. 1, and is illustrated with respect to the upper surface of the gate electrode 130 located at the top.

[0070] 1, 2, 4 and 5, in one embodiment, a plurality of pad areas PA may be provided to electrically connect a plurality of gate electrodes 130 included in a plurality of stacked structures 120a, 120b, and 120c to a plurality of gate contact portions 184, respectively. Here, the plurality of pad areas PA may include a first pad area PA1 in which the gate electrode 130 of the first stacked structure 120a is connected to the gate contact portion 184, a second pad area PA2 in which the gate electrode 130 of the second stacked structure 120b is connected to the gate contact portion 184, and a third pad area PA3 in which the third gate electrode 130 of the third stacked structure 120c is connected to the gate contact portion 184.

[0071] In this case, the first to third pad regions PA1, PA2, and PA3 may each include an upper pad region PU in which the gate electrode 130 located in the upper portion of the multiple stacked structures 120a, 120b, and 120c is connected to the gate contact portion 184, and a lower pad region PL in which the gate electrode 130 located in the lower portion of the multiple stacked structures 120a, 120b, and 120c is connected to the gate contact portion 184.

[0072] By separately providing the upper pad region PU and the lower pad region PL in this manner, the process of forming the pad region PA can be simplified, but the embodiment is not limited thereto, and each of the gate stack structures 120a, 120b, and 120c may have one or more pad regions PA.

[0073] 4 illustrates an example in which a first upper pad region PU1, a second upper pad region PU2, a third upper pad region PU3, a second lower pad region PL2, a third lower pad region PL3, and a first lower pad region PL1 are sequentially arranged in a direction away from the cell array region 102. However, this is merely an example, and the embodiment is not limited thereto.

[0074] The upper pad region PU may include a pad area PS and a dummy area DS, and the lower pad region PL may include a pad area PS, a dummy area DS, and an upper area US, where the pad area PS is located on one side of the pad region PA and is an area where the gate electrodes 130 and the gate contact parts 184 are respectively connected, and the dummy area DS may be an area located on the other side of the pad region PA. The upper area US may be a portion located on the upper part of the pad area PS and the dummy area DS.

[0075] More specifically, in the pad region PS, the gate electrodes 130 may be sequentially removed by the recess portion RP. As an example, in the pad region PS, the length of the gate electrodes 130 may be gradually increased as they descend downward in a direction away from the cell array region 102. For example, in the pad region PS, the gate electrodes 130 may have a stepped shape descending downward in a direction away from the cell array region 102. In this case, the gate electrodes 130 may have a stepped shape in one direction or in multiple directions. As a result, the pad portions PP1 and PP2 of the connection gate electrodes 130c may be exposed to the upper part in the pad region PS.

[0076] In the dummy region DS, the plurality of gate electrodes 130 may be sequentially removed by the recess portion RP. As an example, in the dummy region DS, the length of the plurality of gate electrodes 130 may gradually increase as it descends downward toward the cell array region 102. For example, in the dummy region DS, the plurality of gate electrodes 130 may have a stepped shape that descends downward toward the cell array region 102. The stepped shape of the plurality of gate electrodes 130 in the dummy region DS may have a steeper slope than the stepped shape of the plurality of gate electrodes 130 in the pad region PS, but the embodiment is not limited thereto.

[0077] Thus, the pad insulating part 132i provided in the dummy area DS is located on one surface (top surface in FIG. 3) of the gate electrodes 130 in the first direction (Y-axis direction in the drawing), has a dummy length (reference symbol D1 in FIG. 6), and may include a plurality of dummy parts DP sequentially arranged in the first direction. The pad insulating part 132i provided in the pad area PS is located on one surface (top surface in FIG. 6) of the gate electrodes 130 in the first direction, and may include a plurality of parts. Here, the plurality of parts may include a first part having a first bottom length (reference symbol D2 in FIG. 6, the same applies below) and a second part having a second bottom length (reference symbol D3 in FIG. 6) greater than the first bottom length D2.

[0078] In the upper region US, the plurality of gate electrodes 130 may be removed by the recess portion RP. As an embodiment, one side and the other side of the upper region US may be configured as a vertical surface perpendicular to the second substrate 110 or the first direction, or an inclined surface inclined toward the second substrate 110 or the first direction and decreasing in length from the top to the bottom. In this case, the inclined surface may have a steep inclination. Here, the length may mean the length in the first direction (Y-axis direction in the drawing). This can prevent the overall length of the upper pad region PU from increasing due to the upper region US. However, the embodiment is not limited thereto.

[0079] The recessed portion RP of the pad region PA described above is sufficient as long as it has a shape or profile for sequentially exposing the pad portions PP1, PP2 of the connecting gate electrodes 130c in each pad region PA. The shapes or profiles of the recessed portion RP or the gate electrodes 130 in the pad region PS, the dummy region DS and / or the upper region US of each pad region PA may be the same or similar.

[0080] The pad insulating portion 132i may have a shape in which a recess portion RP in which the gate electrodes 130 are removed in each pad region PA is filled with an insulating material.

[0081] In one embodiment, a buffer insulating portion 132p may be formed in a portion of the lower structure adjacent to the boundary portion 120p. A separate insulating structure may be further provided in consideration of possible detachment or misalignment of the gate contact portion 184 in the portion adjacent to the boundary portion 120p. This allows the insulating structure of the gate contact portion 184 to be stably realized at the boundary portion 120p.

[0082] Here, a gate stack structure located at the lower part of one boundary portion 120p may be referred to as a lower structure, and a gate stack structure located at the upper part may be referred to as an upper structure. In the first and second stack structures 120a and 120b, the first stack structure 120a may be the lower structure, and the second stack structure 120b may be the upper structure. In the second and third stack structures 120b and 120c, the second stack structure 120b may be the lower structure, and the third stack structure 120c may be the upper structure. In each pad region PA, a gate stack structure having a connecting gate electrode 130c may be referred to as a connecting structure, and a gate stack structure not having a connecting gate electrode 130c may be referred to as an insulating structure.

[0083] When the upper structure is a connecting structure and the lower structure is an insulating structure, the buffer insulating portion 132p may be formed in the lower structure including the boundary portion 120p of the lower structure. The buffer insulating portion 132p may have a form in which an insulating material is filled in a buffer recess portion BR in which one or more gate electrodes 130 of the lower structure are removed.

[0084] In the embodiment, a wiring through hole (reference symbol OH in FIG. 7g, the same applies below) for forming the gate contact part 184 may be formed by performing an etching process on the gate stack structure 120 and / or the pad insulating part 132i. However, there is a difference in etching speed or etching form in the etching process between the part where the gate stack structure 120 is located and the part where the pad insulating part 132i is located. For example, the etching speed may be faster in the part where the pad insulating part 132i is located than in the part where the gate stack structure 120 is located, so that the area or size of the wiring through hole OH may be larger in the part where the pad insulating part 132i is located. That is, when the upper structure is a connecting structure, the wiring through hole OH has a relatively large area or size at the boundary part 120p of the lower structure, so that the gate contact part 184 formed in the upper structure at the boundary part 120p of the lower structure may also have a large area or size. As a result, there may be a high possibility of a problem occurring due to the gate contact part 184 falling off or misalignment at the boundary part 120p. In consideration of this, a buffer insulating portion 132p is formed in a region including the boundary portion 120p in the lower structure located under the connecting structure.

[0085] FIG. 5 shows an example in which the gate electrode 130 is entirely removed in the second direction (X-axis direction in the drawing) or width direction in a lower structure located under the connecting structure, and the buffer insulating portion 132p is formed in the part. That is, the buffer insulating portion 132p is entirely formed in the second direction or width direction. This can effectively prevent the gate contact portion 184 from falling off or being misaligned. However, the embodiment is not limited thereto. As another example, the gate electrode 130 is partially removed in the second direction (X-axis direction in the drawing) or width direction in a lower structure located under the connecting structure, and the buffer insulating portion 132p is formed in the part. That is, the buffer insulating portion 132p can be partially formed in the second direction or width direction. This can maintain the electrical connection path in the part where the buffer insulating portion 132p is located. Therefore, the buffer insulating portion 132p can be located in various positions regardless of the arrangement of the plurality of pad regions PA. Various other modifications are possible.

[0086] The buffer insulator 132p may be made of the same insulating material as the pad insulator 132i. Alternatively, the buffer insulator 132p may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a dielectric constant lower than that of silicon oxide, or a combination thereof. However, the embodiment is not limited thereto. For example, the buffer insulator 132p may be made of a different material than the pad insulator 132i, or may include an insulating material different from the above-mentioned materials.

[0087] The shape of the buffer insulating portion 132p will be described in more detail with reference to Fig. 6. Fig. 6 corresponds to part A of Fig. 4, and is an enlarged view of a portion where the gate contact portion 184 is not provided.

[0088] 4 and 6, in one embodiment, the buffer insulating part 132p may include an inner area IS, a first area SS1 located on one side of the inner area IS, and a second area SS2 located on the other side of the inner area IS. In this case, the first area SS1 and the second area SS2 may each have a longer length in the first direction (Y-axis direction in the drawings) at the upper part than at the lower part.

[0089] The inner region IS may be located between the first region SS1 and the second region SS2 in the first direction, and may refer to a portion having a substantially identical length L0 in the first direction. In this specification, substantially identical may refer to a portion having a difference within a process error (e.g., a difference within 10%). The first region SS1 and the second region SS2 may be side regions located on one side and the other side of the inner region IS in the first direction, respectively.

[0090] A bottom gate electrode 1310 or a cell insulating layer 132 may be entirely located under the inner region IS, so that the lower surface of the inner region IS may be configured as a flat surface.

[0091] In an exemplary embodiment, the length of each of the first and second regions SS1 and SS2 in the first direction (Y-axis direction in the drawing) may be successively smaller from the top to the bottom. For example, a plurality of gate electrodes 130 may be located at the bottom of each of the first and second regions SS1 and SS2, and the bottom surface or side surface of each of the first and second regions SS1 and SS2 may have a staircase shape formed by one surface (top surface in FIG. 6) and side surfaces of the plurality of gate electrodes 130.

[0092] First, the first area SS1 will be described in detail, and then the second area SS2 will be described in detail. In this specification, the term "length" may refer to the length in a first direction (the Y-axis direction in the drawing) or the extension direction of the gate electrode 130.

[0093] The first region SS1 may have a first length L11 at an upper portion of the first region SS1. At this time, the upper portion of the first region SS1 may be based on one surface (the upper surface in FIG. 6) of the first gate electrode 1301. More specifically, the first region SS1 may have the first length L11 between the boundary between the inner region IS and a side of the first gate electrode 1301 located at the upper portion and the interlayer insulating layer 132m located thereunder.

[0094] The first region SS1 may have a second length L12 smaller than the first length L11 between the boundary between the inner region IS and the side of the second gate electrode 1302 located under the first gate electrode 1301 and the interlayer insulating layer 132m located thereunder. The first region SS1 may have a third length L13 smaller than the second length L12 between the boundary between the inner region IS and the side of the third gate electrode 1303 located under the second gate electrode 1302 and the interlayer insulating layer 132m located thereunder. The first region SS1 may have a fourth length L14 smaller than the third length L13 between the boundary between the inner region IS and the side of the fourth gate electrode 1304 located under the third gate electrode 1303 and the interlayer insulating layer 132m located thereunder. This pattern may be repeated until the bottom gate electrode 1310 or the cell insulating layer 132 located under the inner region IS is reached. For example, the length at the bottom of the first region SS1 may be substantially zero (0).

[0095] The second region SS2 may have a fifth length L21 at an upper portion of the second region SS2. In this case, the upper portion of the first region SS1 may be based on one surface (the upper surface in FIG. 6) of the first gate electrode 1301. More specifically, the second region SS2 may have a fifth length L21 between a side of the upper first gate electrode 1301 and the interlayer insulating layer 132m located thereunder and a boundary between the inner region IS and the side.

[0096] The second region SS2 may have a sixth length L22 smaller than the fifth length L21 between the boundary between the side of the second gate electrode 1302 and the interlayer insulating layer 132m located thereunder and the internal region IS. The second region SS2 may have a seventh length L23 smaller than the sixth length L22 between the boundary between the side of the third gate electrode 1303 and the interlayer insulating layer 132m located thereunder and the internal region IS. The second region SS2 may have an eighth length L24 smaller than the seventh length L23 between the side of the fourth gate electrode 1304 and the interlayer insulating layer 132m located thereunder and the internal region IS. This form may be repeated until the bottom gate electrode 1310 or the cell insulating layer 132 located at the bottom of the internal region IS is reached. For example, the length at the bottom of the second region SS2 may be substantially zero (0).

[0097] In the embodiment, the difference between the length at the top (hereinafter, top length) and the length at the bottom (hereinafter, bottom length) in the first section SS1 and the second section SS2 as described above, or the reference length change amount in the first section SS1 and the second section SS2, can be controlled to prevent defects occurring near the corners of the buffer insulating portion 132p. This will be described in more detail.

[0098] The distance or interval between one surface (top surface in FIG. 6) of adjacent gate electrodes 130 among the plurality of gate electrodes 130 in the third direction (Z-axis direction in the drawing) may be the reference thickness SD2. For example, the distance or interval between one surface of the first gate electrode 1301 and one surface of the second gate electrode 1302, or the distance or interval between one surface of the second gate electrode 1302 and one surface of the third gate electrode 1303, or the distance or interval between one surface of the third gate electrode 1303 and one surface of the fourth gate electrode 1304 may be the reference thickness SD2.

[0099] The length change of the upper region US provided in the first or second region SS1, SS2 or lower pad region PL at the reference thickness SD2 may be the reference length change. For example, the reference length change in the first region SS1 may mean the difference between the first length L11 and the second length L12, the difference between the second length L12 and the third length L13, or the difference between the third length L13 and the fourth length L14. For example, the reference length change in the second region SS2 may mean the difference between the fifth length L21 and the sixth length L22, the difference between the sixth length L22 and the seventh length L23, or the difference between the seventh length L23 and the eighth length L24. For example, the length difference on one surface of two adjacent gate electrodes 130 in the upper region US may be the reference length change DV2 in the upper region US.

[0100] When the amount of change in the reference length is large, the region can be considered to have a relatively gentle slope, and when the amount of change in the reference length is small, the region can be considered to have a relatively steep slope. The amount of change in the reference length can correspond to the reciprocal of the slope.

[0101] In one embodiment, the difference between the top length and the bottom length may be greater in the first section SS1 and the second section SS2 than on one or the other side of the top section US provided in the lower pad area PL2. The difference between the top length and the bottom length in the first section SS1 may be a first length L11, and the difference between the top length and the bottom length in the second section SS2 may be a fifth length L21. The difference between the top length and the bottom length on one or the other side of the top section US provided in the lower pad area PL2 may be a length DV1 that is smaller than the first length L11 and the fifth length L21.

[0102] For example, the difference between the upper length and the lower length on one or the other side of the first region SS1, the second region SS2, or the upper region US may be determined based on a thickness corresponding to the thickness SD1 of the buffer insulating portion 132p. Here, the thickness SD1 of the buffer insulating portion 132p may refer to the distance in the third direction (the Z-axis direction in the drawing) between the upper surface of the buffer insulating portion 132p located on the same plane as the upper surface of the gate electrode 130 and the upper surface of the bottom gate electrode 1310 or the cell insulating layer 132 located at the bottom of the internal region IS.

[0103] The first distance between one gate electrode 130 and the inner area IS in the first area SS1 and the second distance between the one gate electrode 130 and the inner area IS in the second area SS2 may be greater than the third distance. The third distance may be the distance between one gate electrode 130 and the upper area US, or the distance between one gate electrode 130 and the inner area of ​​the upper area US. The inner area of ​​the upper area US may mean a portion of the upper area US having substantially the same length in the first direction, except for the side area. For example, the first distance may be the maximum distance between the gate electrode 130 and the inner area IS in the first area SS1, or the distance between the top gate electrode and the inner area IS in the portion where the first area SS1 is located. In this case, the second distance may be the maximum distance between the gate electrode 130 and the inner area IS in the second area SS2, or the maximum distance between the top gate electrode and the inner area IS in the portion where the second area SS2 is located. In this case, the third distance may mean the maximum distance between the gate electrode 130 and the upper area US (e.g., an inner area of ​​the upper area US) in the upper area US, or the distance between the top gate electrode and the upper area US (e.g., an inner area of ​​the upper area US) in the portion where the upper area US is located.

[0104] Alternatively, the reference length change amount in the first section SS1 and the reference length change amount in the second section SS2 may be greater than the reference length change amount DV2 at one or the other side of the upper section US provided in the lower pad region PL2. For example, the ratio of the reference length change amount in the first section SS1 or the second section SS2 to the reference length change amount DV2 at one or the other side of the upper section US may be 2 times or more. More specifically, the ratio of the reference length change amount in the first section SS1 or the second section SS2 to the reference length change amount DV2 at one or the other side of the upper section US may be 2 times to 100 times. When the ratio is 2 times or more, the side section may have a gentle slope. When the ratio is 100 times or less, the entire length L of the buffer insulating part 132p may be prevented from becoming larger than a certain level. However, the embodiment is not limited thereto. Therefore, the ratio of the reference length change amount in the first section SS1 or the second section SS2 to the reference length change amount DV2 on one side or the other side of the upper section US may be less than two times or may exceed 100 times.

[0105] In this manner, when the first section SS1 and the second section SS2 have a gentler slope than one or the other side of the upper section US, defects that may occur near the corners of the buffer insulating portion 132p (i.e., near the corners formed where the lower surfaces or side surfaces of the first and / or second sections SS1, SS2 meet the bottom surface of the internal section IS) can be prevented.

[0106] For reference, unlike the embodiment, if the first and / or second regions have a relatively small difference between the top length and bottom length or a small reference length change amount and have a steep slope, the bonding portion of the insulating layer formed near the corner of the buffer insulating portion may not be solid. As a result, defects may occur in which gaps are formed in the insulating layer constituting the buffer insulating portion near the corner of the buffer insulating portion. If such defects occur, various problems may occur in subsequent processes. For example, metal residues may be sandwiched and remain in the gaps formed in the insulating layer, degrading the characteristics of the semiconductor device. On the other hand, the embodiment can prevent defects near the corners of the buffer insulating portion 132p as described above, thereby improving the characteristics of the semiconductor device.

[0107] At this time, one or the other side of the upper region US of the lower pad region PL may be formed as a vertical surface perpendicular to the second substrate 110 or an inclined surface having a steep slope. In the embodiment, the lower surface or side of the first region SS1 and / or the second region SS2 may have a stepped shape, so that the lower surface or side of the first region SS1 and / or the second region SS2 may have a more stable and gentle slope than the upper region US formed as a vertical surface or a steeply inclined surface. This makes it possible to effectively prevent defects near the corners of the buffer insulating portion 132p.

[0108] In one embodiment, the length L0 of the internal region IS in the first direction (Y-axis direction in the drawing) may be equal to or smaller than the sum of the overall length of the first region SS1 and the overall length of the second region SS2. Here, the overall length of the first region SS1 may mean the longest length among the lengths of the first region SS1 in the first direction, for example, the first length L11 which is the length of the upper part of the first region SS1. The overall length of the second region SS2 may mean the longest length among the lengths of the second region SS2 in the first direction, for example, the fifth length L21 which is the length of the upper part of the second region SS2. In this way, the overall lengths of the first region SS1 and the second region SS2 which are side regions can be sufficiently secured to have a gentle slope.

[0109] For example, the ratio of the length L0 of the inner region IS to the entire length L of the buffer insulating part 132p in the first direction (Y-axis direction in the drawing) may be 10% to 50%. Here, the entire length L of the buffer insulating part 132p may mean the longest length of the buffer insulating part 132p in the first direction. When the ratio is 50% or less, the side region may have a gentle slope. When the ratio is 10% or more, the process stability may be improved. However, the embodiment is not limited thereto, and the ratio (L0 / L) of the length L0 of the inner region IS to the entire length L of the buffer insulating part 132p in the first direction may be less than 10% or more than 50%.

[0110] In an embodiment, the difference between the upper length and the lower length with respect to the thickness SD1 of the buffer insulating part 132p may be larger in the second region SS2 than in the first region SS1. In this case, the difference between the upper length and the lower length in the first region SS1 may be a first length L11, and the difference between the upper length and the lower length in the second region SS2 may be a fifth length L21. Thus, the fifth length L21 may be larger than the first length L11. Alternatively, the reference length change amount in the second region SS2 may be larger than the reference length change amount in the first region SS1. In other words, the buffer insulating part 132p may have an asymmetric structure in the first direction (Y-axis direction in the drawing), and the first region SS1 and the second region SS2 may have an asymmetric structure with respect to the inner region IS in the first direction.

[0111] In this manner, when the second section SS2 has a gentler slope than the first section SS1, it is possible to more effectively prevent defects from occurring in the buffer insulating portion 132p on the second section SS2 side. Also, by making the upper length of the second section SS2 (e.g., the first length L11) relatively short, it is possible to prevent the overall length L of the buffer insulating portion 132p from becoming larger than a certain level.

[0112] Here, the first region SS1 may be located on one surface (top surface in FIG. 6) of the gate electrodes in a first direction (Y-axis direction in the drawing), have a dummy length LD1, and may include a plurality of dummy portions DB sequentially located in the first direction. For example, the side or bottom surface of the first region SS1 may have a stepped shape having the same length. For example, the dummy length LD1 of the first region SS1 may be substantially the same as the dummy length D1 of the pad insulating portion 132i provided in the dummy region DS.

[0113] For example, the thickness of the dummy portions DB may be gradually decreased or the height of the bottom surface may be gradually increased as the dummy portions DB are spaced from the inner region IS in the first direction. The dummy length LD1 may correspond to a reference length change amount in the first region SS1. In this manner, the first region SS1 includes the dummy portions DB having substantially the same reference length change amount or dummy length LD1, and the overall length L of the buffer insulating portion 132p may be prevented from becoming longer than a certain level.

[0114] The second regions SS2 are located on one surface (top surface in FIG. 6) of the gate electrodes 130 in the first direction (Y-axis direction in the drawing) and may include a first portion BP1 having a first bottom length LD2 and a second portion BP2 having a second bottom length LD3 longer than the first bottom length LD2. The first and second bottom lengths LD2 and LD3 may be greater than the dummy length LD1. For example, the first and second bottom lengths LD2 and LD3 of the second region SS2 may be substantially equal to the first and second bottom lengths D2 and D3 of the pad insulating portion 132i provided in the pad region PS.

[0115] The second portions BP2 may be arranged periodically with respect to a plurality of first portions BP1 in the first direction. In this case, the order or arrangement of the first portions BP1 and the second portions BP2 may have the same or corresponding shape as or a symmetric shape to the order or arrangement of the first pad portions PP1 and the second pad portions PP2 in at least a part of the pad area PA. The symmetric shape may mean a shape that is symmetrical in the first direction.

[0116] For example, the first and second portions BP1, BP2 may have a thickness that is gradually reduced or a height that is gradually increased as the portions are farther from the inner region IS in the first direction. The first and second bottom lengths LD2, LD3 may correspond to the reference length change amount in the second region SS2. The second region SS2 may have a gentler slope by including the first and second portions BP1, BP2 having the first and second bottom lengths LD2, LD3, respectively. However, the embodiment is not limited thereto. Thus, at least one of the first and second bottom lengths LD2, LD3 in the second region SS2 may be equal to or smaller than the dummy length LD1.

[0117] In one embodiment, the buffer insulating portion 132p may have a shape corresponding to or a symmetrical shape of the pad insulating portion 132i provided in at least a part of the pad region PA. The symmetrical shape may mean a shape symmetrical in the first direction. For example, the reference length change amount of the dummy insulating portion 132d of the pad insulating portion 132i provided in at least a part of the dummy region DS may be substantially the same as the reference length change amount of the first region SS1 of the buffer insulating portion 132p, and the reference length change amount of the pad insulating portion 132e of the pad insulating portion 132i provided in at least a part of the pad region PA may be substantially the same as the reference length change amount of the second region SS2 and the inner region IS. Alternatively, the first region SS1 may have the same shape as the dummy insulating portion 132d of the pad insulating portion 132i or a symmetrical shape. And the inner region IS and the second region SS2 may have a shape corresponding to or a symmetrical shape of the pad insulating portion 132e. Here, the corresponding shape may mean that the gate electrode 130 does not have a thicker portion in the portion where the internal region IS and the second region SS2 are located, and that the pad portions PP1 and PP2 have a thicker thickness than other portions in the pad insulating portion 132e, and the symmetrical shape may mean that the corresponding shape has a symmetrical shape. This is because a process of selectively increasing the thickness of only the pad portions PP1 and PP2 is performed after the recess portion RP and the buffer recess portion BR are formed.

[0118] As an example, the buffer insulating portion 132p may have substantially the same size as at least a portion of the pad region PA. Here, having substantially the same size may mean having a size within a process error. For example, the overall length L of the buffer insulating portion 132p may be 90% to 110% of the overall length of at least one of the pad regions PA. However, the embodiment is not limited thereto. Therefore, the buffer insulating portion 132p may have a different size than at least a portion of the pad region PA or may be formed in a process separate from the pad region PA.

[0119] For example, the buffer insulating portion 132p having the above-mentioned shape can be formed using the same process conditions as those for forming the pad insulating portion 132i located in the pad region PA, which will be described in more detail later in the method for manufacturing the semiconductor device 10.

[0120] In one embodiment, the first area SS1 may be located adjacent to the cell array region 102, and the second area SS2 may be located away from the cell array region 102. The buffer insulating part 132p may be located on the upper part of the lower stack structure and may be configured as an upper pattern including the inner area IS, the first area SS1, and the second area SS2. As an example, the buffer insulating part 132p may have a symmetric shape in the first direction (Y-axis direction in the drawing) with the pad insulating part 132i located in at least a part of the pad area PA (e.g., the upper pad area PU). Different embodiments will be described in more detail below with reference to FIGS. 8 to 11.

[0121] In this manner, when the buffer insulating portion 132p has a symmetrical shape to the pad insulating portion 132i provided in at least a portion of the pad region PA, the first region SS1 and the inner region IS may be located under the pad region PS where the gate electrode 130 and the gate contact portion 184 are connected in the pad region PA. That is, in the lower structure, the gate contact portion 184 may be located in the first region SS1 and the inner region IS where a relatively large amount of insulating material is located. This makes it possible to effectively prevent problems such as falling off or misalignment of the gate contact portion 184.

[0122] In one embodiment, one buffer insulating portion 132p may be formed in the second stacked structure 120b including the boundary portion 120p of the second stacked structure 120b in the third pad region PA3 (e.g., third lower pad region PL3). And another buffer insulating portion 132p may be formed in the first stacked structure 120a including the boundary portion 120p of the first stacked structure 120a in the second pad region PA2 (e.g., second lower pad region PL2). This is because the pad insulating portion 132i is formed to have a large thickness including the upper region US in the lower pad region PL, and therefore the gate contact portion 184 may have a large area or size at the boundary portion 120p of the lower structure located therein.

[0123] However, the embodiment is not limited thereto. When the upper pad region PU is provided in the upper structure, the buffer insulating part 132p may be provided in the lower structure located below the upper pad region PU. Also, when the upper structure is an insulating structure and the lower structure is an insulating structure, the buffer insulating part 132p may be provided in the lower structure. This will be described in detail later with reference to FIG. 12. As another example, only one buffer insulating part 132p may be provided, and various other modifications are possible.

[0124] According to the embodiment, a buffer insulating portion 132p is formed in a lower structure located below a boundary portion 120p where a bonded portion of the gate contact portion 184 is located in the connection region 104. As a result, even if a detachment phenomenon of the gate contact portion 184 occurs at the boundary portion 120p, a portion of the gate contact portion 184 located in the upper structure is located at a portion of the gate contact portion 184 located in the lower structure and the buffer insulating portion 132p. In other words, the buffer insulating portion 132p allows the gate contact portion 184 to have a sufficient distance from the gate electrode 130. As a result, the buffer insulating portion 132p can fundamentally prevent a problem in which the gate electrode 130 is damaged due to detachment or misalignment of the gate contact portion 184.

[0125] At this time, since the side areas of the buffer insulating portion 132p have a gentle slope, defects or failures that would occur in the buffer insulating portion 132p near the corners of the buffer insulating portion 132p can be prevented, thereby improving the reliability and performance of the semiconductor device 10. Since the buffer insulating portion 132p has a shape corresponding to or a symmetrical shape of the pad insulating portion 132i provided in at least a part of the pad area PA, the buffer insulating portion 132p can be formed through a simple process.

[0126] In the above embodiment, the difference between the upper length and the lower length is larger in the second section SS2 than in the first section SS1, and the reference length change amount in the second section SS2 is larger than the reference length change amount in the first section SS1. However, the embodiment is not limited to this. Therefore, the difference between the upper length and the lower length may be the same in the first section SS1 and the second section SS2, or the reference length change amount in the first section SS1 and the reference length change amount in the second section SS2 may be the same. In this case, the difference between the upper length and the lower length may be larger in the first and / or second sections SS1, SS2 than on one or the other side of the upper section US. Alternatively, the reference length change amount in the first and / or second sections SS1, SS2 may be larger than the reference length change amount DV2 on one or the other side of the upper section US. In this way, defects that may occur near the corners of the buffer insulating portion 132p can be prevented. Various other modifications are possible.

[0127] An example of a method for manufacturing the semiconductor device 10 having the above-mentioned structure will be described in detail with reference to Figures 7a to 7i as well as Figures 1 to 6. Detailed description of the parts that have already been described will be omitted, and parts that have not been described will be described in detail.

[0128] 7a to 7i are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. Figures 7a to 7i are partial cross-sectional views of the semiconductor device 10 taken along line D-D' in Figure 1. Hereinafter, the method for manufacturing the semiconductor device 10 will be described focusing on the gate stack structure 120, the channel structure CH, the gate contact portion 184, the cell insulating layer 132 including the buffer insulating portion 132p, and the isolation structure 146.

[0129] As shown in Figures 7a to 7f, a plurality of sacrificial insulating layers 130s and a plurality of cell insulating layers 132 may be alternately stacked on a circuit region 200 including a peripheral circuit structure to form a laminated structure 120s. Here, the cell insulating layer 132 may include a pad insulating portion 132i and a buffer insulating portion 132p. A second substrate 110, a horizontal insulating layer 116, a second horizontal conductive layer 114, etc. may be further formed between the circuit region 200 and the laminated structure 120s. Then, a channel sacrificial layer 124s and a wiring sacrificial layer 184s may be formed penetrating the laminated structure 120s.

[0130] For ease of explanation and clear understanding, the drawings and description illustrate an example in which the laminated structure 120s includes a plurality of laminated structures 120d, 120e, and 120f including a first laminated structure 120d, a second laminated structure 120e, and a third laminated structure 120f. However, the embodiment is not limited thereto, and the laminated structure 120s may include two or four or more laminated structures.

[0131] First, as shown in Fig. 7a, a horizontal insulating layer 116 and a second horizontal conductive layer 114 may be formed on a second substrate 110 to form a first laminated structure 120d. That is, cell insulating layers 132 and sacrificial insulating layers 130s may be alternately laminated. A first upper insulating layer 132a may be positioned on the top of the first laminated structure 120d.

[0132] Here, the sacrificial insulating layer 130s may be a layer that replaces the gate electrode (reference number 130 in FIG. 7i, the same hereinafter) in a subsequent process, and at least a portion of the horizontal insulating layer 116 may be a layer that replaces the first horizontal conductive layer (reference number 112 in FIG. 7i, the same hereinafter) in a subsequent process. That is, the sacrificial insulating layer 130s may be formed to correspond to a portion where the gate electrode 130 is to be formed, and the horizontal insulating layer 116 may be formed to include a portion where the first horizontal conductive layer 112 is to be formed.

[0133] The horizontal insulating layer 116 and / or the sacrificial insulating layer 130s may be formed of a different material than the interlayer insulating layer 132m and / or the first upper insulating layer 132a. For example, the interlayer insulating layer 132m or the first upper insulating layer 132a may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material, etc. For example, the sacrificial insulating layer 130s may include one of silicon, silicon oxide, silicon carbide, silicon nitride, etc., and may be formed of a different material than the interlayer insulating layer 132m.

[0134] In one embodiment, an etch stop layer 136 may be formed on the first upper insulating layer 132a. The etch stop layer 136 may be a layer for protecting the first stacked structure 120d during an etching process, and may be, for example, a hard mask layer.

[0135] Next, as shown in Fig. 7b to Fig. 7d, a recess portion RP and a buffer recess portion BR may be formed in the first laminate structure 120d. Here, the recess portion RP may be formed to correspond to the first upper pad region PU1 and the first lower pad region PL1, or may be formed to correspond to the pad insulating portion 132i provided therein. The buffer recess portion BR may be formed to correspond to the buffer insulating portion 132p. As an example, the buffer recess portion BR is positioned to correspond to the second lower pad region PL2, but the embodiment is not limited thereto. The recess portion RP and the buffer recess portion BR may be formed by sequential etching processes using mask layers 138a, 138b, and 138c.

[0136] More specifically, as shown in FIG. 7b, a first mask layer 138a is formed, and a first etching process is performed to form a part of the recess portion RP and a part of the buffer recess portion BR in the first laminate structure 120d exposed thereby. For example, the first mask layer 138a may be a photoresist layer and may be formed by a photolithography process. A trim process using the first mask layer 138a may be repeated to form a part of the recess portion RP and a part of the buffer recess portion BR. For example, a stepwise etching process may be performed on the sacrificial insulating layer 130s and the cell insulating layer 132 while sequentially increasing the area exposed using the first mask layer 138a, thereby forming a part of the recess portion RP and a part of the buffer recess portion BR.

[0137] In this case, the first region A1 of the first mask layer 138a for forming the recess portion RP and the second region A2 of the first mask layer 138a for forming the buffer recess portion BR may have a symmetrical structure. In this case, the process conditions for forming the part of the recess portion RP constituting a part of the pad region PS in the first etching process may be the same as the process conditions for forming the part of the buffer recess portion BR constituting a part of the second region SS2. In this case, the recess portion RP and the buffer recess portion BR have a symmetrical shape. Thus, the process conditions for one side of the recess portion RP may be the same as the process conditions for the other side of the buffer recess portion BR, and the process conditions for the other side of the recess portion RP may be the same as the process conditions for one side of the buffer recess portion BR.

[0138] Next, as shown in FIG. 7c, a second mask layer 138b is formed, and a second etching process is performed to form another part of the recess portion RP and another part of the buffer recess portion BR in the first laminate structure 120d exposed thereby. For example, the second mask layer 138b may be a photoresist layer and may be formed by a photolithography process. The trim process using the second mask layer 138b may be repeated to form another part of the recess portion RP and another part of the buffer recess portion BR. For example, the other part of the recess portion RP and another part of the buffer recess portion BR may be formed by performing a stepwise etching process on the sacrificial insulating layer 130s and the cell insulating layer 132 while sequentially increasing the area exposed using the second mask layer 138b.

[0139] In this case, the third region A3 of the second mask layer 138b for forming the recess portion RP and the fourth region A4 of the second mask layer 138b for forming the buffer recess portion BR may have a symmetrical structure. In this case, the process conditions for forming the other part of the recess portion RP constituting a part of the pad region PS in the second etching process may be the same as the process conditions for forming the other part of the buffer recess portion BR constituting a part of the second region SS2. In this case, the recess portion RP and the buffer recess portion BR have a symmetrical shape. Thus, the process conditions for one side of the recess portion RP may be the same as the process conditions for the other side of the buffer recess portion BR, and the process conditions for the other side of the recess portion RP may be the same as the process conditions for one side of the buffer recess portion BR.

[0140] As a result, a recess portion RP may be formed in the upper portion of the first laminate structure 120d in the first upper pad region PU1 and the first lower pad region PL1. A buffer recess portion BR having an inner region IS, a first area SS1, and a second area SS2 may be formed in the upper portion of the first laminate structure 120d in the second lower pad region PL2. Although the above description has been given using the first and second etching processes, the embodiment is not limited thereto. One etching process or three or more etching processes may be used.

[0141] 7d, a recess RP corresponding to the first lower pad region PL1 including the upper region US may be formed using a third mask layer 138c. The first lower pad region PL1 may be exposed using the third mask layer 138c and etched downward by an amount corresponding to the upper region US.

[0142] Next, as shown in FIG. 7e, a pad insulator 132i and a buffer insulator 132p may be formed, and a channel sacrificial layer 124s and a wiring sacrificial layer 184s may be formed.

[0143] Before forming the pad insulating portion 132i and the buffer insulating portion 132p, the thickness of the sacrificial insulating layer 130s may be partially increased and the etching stop layer 136 may be removed. That is, the thickness of the sacrificial insulating layer 130s may be increased in the portions corresponding to the pad portions (reference symbols PP1 and PP2 in FIG. 7i, the same hereinafter) of the gate electrode 130 compared to other portions. For example, after forming an additional sacrificial insulating layer, the thickness of the sacrificial insulating layer 130s may be partially increased by patterning so that the additional sacrificial insulating layer remains only on the pad portions PP1 and PP2. At this time, the thickness of the sacrificial insulating layer 130s located in the recess portion RP may be increased, and the thickness of the sacrificial insulating layer 130s located in the buffer recess portion BR may be maintained as it is without being increased. The etching stop layer 136 may be formed before or after the thickness increasing process.

[0144] Next, the pad insulating portion 132i and the buffer insulating portion 132p may be formed to fill the recess portion RP and the buffer recess portion BR, respectively. As an example, the pad insulating portion 132i and the buffer insulating portion 132p may be formed together using the same process. According to an embodiment, in the first laminated structure 120d, the pad insulating portion 132i and the buffer insulating portion 132p may be formed before or after a process of forming the first upper insulating layer 132a separately from the first upper insulating layer 132a, or may be formed as a part of the first upper insulating layer 132a.

[0145] Next, a channel sacrificial layer 124s penetrating the first stacked structure 120d may be formed in the cell array region 102, and a wiring sacrificial layer 184s penetrating the first stacked structure 120d may be formed in the connection region 104. For example, after forming a through portion penetrating the first stacked structure 120d, a sacrificial material may be deposited to form the channel sacrificial layer 124s and the wiring sacrificial layer 184s. For example, the through portion may be formed by an etching process (e.g., a plasma etching process), and the sacrificial material may include polycrystalline silicon, tungsten, and the like.

[0146] A second laminate structure 120e and a third laminate structure 120f may then be formed as shown in FIG. 7f.

[0147] More specifically, the second laminated structure 120e may be formed by alternately stacking the cell insulating layer 132 and the sacrificial insulating layer 130s on the first laminated structure 120d. At this time, the cell insulating layer 132 may include a pad insulating portion 132i and a buffer insulating portion 132p, and may include a second upper insulating layer 132b located on the upper portion of the second laminated structure 120e. Then, a channel sacrificial layer 124s and a wiring sacrificial layer 184s penetrating the second laminated structure 120e may be formed. The manufacturing process of the sacrificial insulating layer 130s, the cell insulating layer 132, the channel sacrificial layer 124s, and the wiring sacrificial layer 184s of the second laminated structure 120e may be the same as that described for the first laminated structure 120d, and therefore a detailed description thereof will be omitted.

[0148] Next, the cell insulating layer 132 and the sacrificial insulating layer 130s may be alternately stacked on the second stacked structure 120e to form a third stacked structure 120f. At this time, the cell insulating layer 132 may include a pad insulating portion 132i and may include a third upper insulating layer 132c located on the upper portion of the third stacked structure 120f. Then, a channel sacrificial layer 124s and a wiring sacrificial layer 184s may be formed penetrating the third stacked structure 120f. The manufacturing process of the sacrificial insulating layer 130s, the cell insulating layer 132, the channel sacrificial layer 124s, and the wiring sacrificial layer 184s of the third stacked structure 120f may be directly applied to the description related to the first stacked structure 120d, so detailed description will be omitted.

[0149] In one embodiment, the channel sacrificial layer 124s may be formed to correspond to a channel structure (reference numeral CH in FIG. 7g, the same applies below). The wiring sacrificial layer 184s may be formed to correspond to a gate contact portion (reference numeral 184 in FIG. 7i).

[0150] Next, as shown in FIGS. 7g to 7i, the channel sacrificial layer 124s and the wiring sacrificial layer 184s can be removed, and the channel structure CH, the gate contact portion 184, and the gate electrode 130 can be formed.

[0151] More specifically, as shown in Fig. 7g, a channel structure CH may be formed, and a wiring through hole OH may be formed. An upper isolation region 148 may be further formed in a portion of the second stacked structure 120e. The upper isolation region (reference numeral 148 in Fig. 2, the same applies hereinafter) may be formed by forming an upper isolation opening by an etching process using a mask layer, and depositing an insulating material in the upper isolation opening.

[0152] That is, the channel structure CH can be formed in the through-hole formed by removing the channel sacrificial layer (reference number 124s in FIG. 7f). For example, the gate dielectric layer (reference number 150 in FIG. 3, the same hereinafter), the channel layer (reference number 140 in FIG. 3, the same hereinafter), and the core insulating layer (reference number 142 in FIG. 3, the same hereinafter) are sequentially formed to fill the through-hole, and a channel pad (reference number 144 in FIG. 3, the same hereinafter) is formed on the channel layer 140 to form the channel structure CH. In this case, the first blocking layer (reference number 156a in FIG. 3, the same hereinafter) of the gate dielectric layer 150 is not formed, but can be formed in a subsequent process.

[0153] Then, the wiring sacrificial layer (reference numeral 184s in FIG. 7f) may be removed to form the wiring through-portion OH. Before forming the wiring through-portion OH, a portion of the cell insulating layer 132 covering the channel structure CH may be further formed. The wiring through-portion OH may penetrate the stacked structure 120s and the substrate insulating portion 110i of the second substrate 110 to extend to the circuit region 200. The wiring through-portion OH may be formed to expose a pad portion of the circuit region 200.

[0154] Next, as shown in FIG. 7h, a tunnel portion can be formed through the wiring through portion OH, and a preliminary insulating layer 184j and a vertical sacrificial layer 183c can be formed.

[0155] More specifically, a portion of the sacrificial insulating layer 130s exposed through the wiring through-hole OH may be removed in a horizontal direction to form the tunnel portion TL. When an etching material is introduced through the wiring through-hole OH, the sacrificial insulating layer 130s adjacent to the wiring through-hole OH may be etched in a horizontal direction to form the tunnel portion TL. At this time, etching may also be performed in the upper and lower directions of the sacrificial insulating layer 130s to form the tunnel portion TL to a thickness slightly thicker than that of the sacrificial insulating layer 130s. Since the tunnel portion TL is formed by etching in a horizontal direction through the wiring through-hole OH, the side of the tunnel portion TL may have a relatively small slope or may include a convex or rounded portion.

[0156] The tunnels TL and the wiring openings OH can then be filled with a preliminary insulating layer 184j and a vertical sacrificial layer 183c.

[0157] The preliminary insulating layer 184j may be a layer in which a portion thereof remains to form an insulating pattern (reference numeral 184i in FIG. 2, the same hereinafter). The preliminary insulating layer 184j may not completely fill the tunnel portion TL formed corresponding to the pad portions PP1 and PP2 of the connecting gate electrode (reference numeral 130c in FIG. 2, the same hereinafter) having a relatively large thickness, but may be formed to fill the tunnel portion TL formed corresponding to the remaining gate electrode (reference numeral 130r in FIG. 2, the same hereinafter). This may be due to a relative thickness difference. The vertical sacrificial layer 183c may be formed to fill the remaining space in the wiring through portion OH.

[0158] The preliminary insulating layer 184j may be made of the same material as that of the insulating pattern 184i. The vertical sacrificial layer 183c may include a different material from that of the preliminary insulating layer 184j, for example, polycrystalline silicon, tungsten, etc. However, the embodiment is not limited thereto, and the material of the preliminary insulating layer 184j and / or the vertical sacrificial layer 183c may be variously modified.

[0159] Next, as shown in FIG. 7i, a sacrificial insulating layer (reference numeral 130s in FIGS. 7f and 7g, the same applies below) can be replaced with the gate electrode 130, and a gate contact portion 184 can be formed.

[0160] First, an opening may be formed in a region corresponding to an isolation structure (reference numeral 146 in FIG. 2, the same below) so as to penetrate the stack structure (reference numeral 120s in FIG. 7f). The sacrificial insulating layer 130s may be selectively removed by an etching process (e.g., a wet etching process) through the opening. Then, the gate electrode 130 may be formed by filling a conductive material constituting the gate electrode 130 in the portion from which the sacrificial insulating layer 130s has been removed. In this way, the gate stack structure 120 may be formed in place of the gate electrode 130 in the region where the sacrificial insulating layer 130s is located. In this case, a process of forming a first blocking layer 156a may be further performed before the process of filling the conductive material constituting the gate electrode 130.

[0161] According to an embodiment, an opening may be formed to expose the horizontal insulating layer 116. An etching process through the opening may be performed to remove at least a portion of the horizontal insulating layer 116 and a portion of the gate dielectric layer 150, and a material constituting the first horizontal conductive layer 112 may be filled to form the first horizontal conductive layer 112. Then, an insulating material may be filled into the opening to form the isolation structure 146.

[0162] Next, the vertical sacrificial layer (reference numeral 183c in FIG. 7h, the same below) and a portion of the preliminary insulating layer (reference numeral 184j in FIG. 7h, the same below) can be removed and a conductive material can be embedded to form the gate contact portion 184.

[0163] More specifically, after selectively removing the vertical sacrificial layer 183c, a portion of the preliminary insulating layer 184j may be removed. At this time, the preliminary insulating layer 184j formed on the pad portions PP1 and PP2 of the connection gate electrode 130c may be entirely removed, and the preliminary insulating layer 184j formed on the tunnel portion TL of the remaining gate electrode 130r may remain to form the insulating pattern 184i.

[0164] Next, a conductive material may be deposited in the wiring through-hole OH to form the gate contact part 184. The gate contact part 184 may include a connection part 184c protruding from the inner side of the pad parts PP1 and PP2. Then, a second wiring part 180 connected to the channel structure CH may be further formed.

[0165] According to the embodiment, the buffer insulating portion 132p may be formed to have a shape corresponding to or a symmetrical shape of the pad insulating portion 132i provided in at least a portion of the pad region PA, using process conditions for forming the pad insulating portion 132i. As a result, the semiconductor device 10 having excellent reliability and performance and including the buffer insulating portion 132p may be manufactured through a simple process.

[0166] Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment different from the above-described embodiment will be described in more detail with reference to Figures 8 to 13. Detailed descriptions of parts that are the same as or very similar to those already described will be omitted, and only different parts will be described in detail.

[0167] 8 is a schematic partial cross-sectional view of a semiconductor device according to another embodiment of the present invention, which shows a portion corresponding to that shown in FIG.

[0168] 8, in an embodiment, at least one of the buffer insulating parts 132p may be formed of an extension pattern including an inner area IS, a first area SS1, a second area SS2, and an upper buffer area UB located thereon. For example, in FIG. 8, the first area SS1 is located adjacent to the cell array region 102, and the second area SS2 is located away from the cell array region 102, and the buffer insulating part 132p has a symmetrical shape with the pad insulating part 132i provided in the second lower pad region PL2. Other examples will be described below with reference to FIGS. 9 to 11.

[0169] 8, the second laminated structure 120b constituting the lower structure in the third lower pad region PL3 is provided with the buffer insulating portion 132p formed with the extension pattern, and the first laminated structure 120a constituting the lower structure in the second lower pad region PL2 is provided with the buffer insulating portion 132p formed with the upper pattern. However, the embodiment is not limited thereto. For example, the first laminated structure 120a and / or the second laminated structure 120b may be provided with one or more buffer insulating portions 132p formed with the extension pattern. The number and arrangement of the buffer insulating portions 132p formed with the extension pattern and the buffer insulating portions 132p formed with the upper pattern may be modified in various ways.

[0170] In one embodiment, the difference between the upper length and the lower length may be larger in the first section SS1 and the second section SS2 than in one or the other side of the upper buffer area UB. Alternatively, the reference length change amount in the first section SS1 and the second section SS2 may be larger than the reference length change amount in one or the other side of the upper buffer area UB. For example, one or the other side of the upper buffer area UB may be configured as a vertical surface perpendicular to the second substrate 110 or an inclined surface having a steep slope.

[0171] In one embodiment, the buffer insulating portion 132p having the extension pattern may be formed using the same process conditions as the process of forming the pad insulating portion 132i located in the upper pad region PU having the upper area US. For example, the buffer recess portion BR corresponding to the upper buffer area UB may be formed in the process of forming the recess portion RP corresponding to the upper area US of the upper pad region PU.

[0172] For example, the upper length, the lower length, the side slope, etc. of the upper buffer region UB may be substantially the same as the upper length, the lower length, the side slope, etc. of the upper region US of the upper pad region PU, thereby preventing the overall length of the buffer insulating part 132p configured as an extension pattern having the upper buffer region UB from becoming larger than a certain level.

[0173] In this manner, when the upper buffer region UB is further included, the buffer insulating portion 132p may have a relatively large thickness at the boundary portion 120p of the lower structure, thereby effectively preventing the gate contact portion 184 from falling off or being misaligned at the boundary portion 120p.

[0174] In one embodiment, the buffer insulating portion 132p having the upper buffer area UB may have a shape corresponding to or a symmetrical shape of the pad insulating portion 132i provided in at least a portion of the pad area PA.

[0175] Fig. 9 is a partial cross-sectional view showing a schematic configuration of a semiconductor device according to another embodiment, and Fig. 10 is an enlarged view of a portion of the semiconductor device shown in Fig. 9. Fig. 9 shows a portion corresponding to Fig. 4, and Fig. 10 shows a portion corresponding to Fig. 6.

[0176] 9 and 10, in one embodiment, the first area SS1 may be located away from the cell array region 102, and the second area SS2 may be located adjacent to the cell array region 102. As an example, the buffer insulating part 132p may have a shape corresponding to the pad insulating part 132i provided in at least a part of the pad region PA in the first direction (the Y-axis direction in the drawings).

[0177] Accordingly, the second area SS2 may be located below where the gate electrode 130 and the gate contact portion 184 are connected in the pad region PA. Then, the thickness of the buffer insulating portion 132p in the lower structure may be proportional to the thickness of the pad insulating portion 132i in the upper structure. As a result, problems such as detachment and misalignment of the gate contact portion 184 may be effectively prevented.

[0178] 11 is a schematic partial cross-sectional view of a semiconductor device according to another embodiment of the present invention, which shows a portion corresponding to that shown in FIG.

[0179] 11, in an embodiment, at least one of the buffer insulating parts 132p may be configured in an extended pattern including an inner area IS, a first area SS1, a second area SS2, and an upper buffer area UB located thereon. In an embodiment, the buffer insulating part 132p including the upper buffer area UB may have a shape corresponding to or a symmetrical shape of the pad insulating part 132i provided in at least a part of the pad area PA. For example, in FIG. 11, the first area SS1 is located farther from the cell array region 102, the second area SS2 is located adjacent to the cell array region 102, and the buffer insulating part 132p has a shape corresponding to the pad insulating part 132i provided in the second lower pad area PL2.

[0180] 11, the second laminated structure 120b constituting the lower structure in the third lower pad region PL3 is provided with a buffer insulating portion 132p formed with an extension pattern, and the first laminated structure 120a constituting the lower structure in the second lower pad region PL2 is provided with a buffer insulating portion 132p formed with an upper pattern. However, the embodiment is not limited thereto. For example, the first laminated structure 120a and / or the second laminated structure 120b may be provided with one or more buffer insulating portions 132p formed with an extension pattern. The number and arrangement of the buffer insulating portions 132p formed with the extension pattern and the buffer insulating portions 132p formed with the upper pattern may be modified in various ways.

[0181] In this manner, when the upper buffer region UB is further included, the buffer insulating portion 132p may have a relatively large thickness at the boundary portion 120p of the lower structure, thereby effectively preventing the gate contact portion 184 from falling off or being misaligned at the boundary portion 120p.

[0182] 12 is a schematic partial cross-sectional view of a semiconductor device according to another embodiment of the present invention, which shows a portion corresponding to that shown in FIG.

[0183] 12 illustrates an example in which the buffer insulating portion 132p is formed in the second upper pad region PU2, the third upper pad region PU3, the second lower pad region PL2, and the third lower pad region PL3 of the first laminated structure 120a, and in the third upper pad region PU3, the third lower pad region PL3, and the first lower pad region PL1 of the second laminated structure 120b. Also, in FIG. 12, the buffer insulating portion 132p is formed by an upper pattern, and has a symmetrical shape with the pad insulating portion 132i provided in the upper pad region PU.

[0184] However, the embodiment is not limited thereto. At least one buffer insulating portion 132p may be provided in one or more pad areas PA to include the boundary portion 120p in the first and / or second stacked structures 120a and 120b.

[0185] 12 illustrates an example in which the buffer insulating portion 132p is not provided with the extended pattern and is provided with the upper pattern, but the embodiment is not limited thereto. According to an embodiment, at least one of the buffer insulating portions 132p may be an upper pattern including the inner area IS, the first area SS1, and the second area SS2, and / or at least one of the buffer insulating portions 132p may be an extended pattern including the inner area IS, the first area SS1, the second area SS2, and the upper buffer area UB. Alternatively, the buffer insulating portion 132p may not be provided with the upper pattern and may be provided with the extended pattern.

[0186] According to an embodiment, the buffer insulating portion 132p may have a shape corresponding to or a symmetrical shape of the pad insulating portion 132i provided in at least a part of the pad region PA, for example, the upper pad region PU or the lower pad region PL. In this manner, the buffer insulating portion 132p may have various structures, arrangements, shapes, etc.

[0187] In the above embodiment, the gate stack 120 includes three gate stacks 120a, 120b, and 120c, but the embodiment is not limited thereto. Even when the gate stack 120 includes two gate stacks or four or more gate stacks, the buffer insulating portion 132p may be provided in the lower structure.

[0188] The additional embodiment will be described in detail with reference to Fig. 13. The description of the previous embodiment may be applied to the same or similar reference numerals as those in the previous embodiment unless otherwise stated. The following description will focus on the differences from the description of the previous embodiment.

[0189] FIG. 13 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a further embodiment.

[0190] 13, the semiconductor device according to the embodiment may have a chip-to-chip (C2C) structure bonded by a wafer bonding method. That is, a lower chip including a circuit region 200a formed on a first substrate 210a is manufactured, an upper chip including a cell region 100a formed on a second substrate 110a is manufactured, and then the two are bonded to manufacture a semiconductor device.

[0191] The circuit region 200a may include a first substrate 210a, a circuit element 220, a first wiring unit 230, and a first junction structure 238 electrically connected to the first wiring unit 230 and located on a surface facing the cell region 100a. A first insulating layer 232 may cover an area other than the first junction structure 238 on the surface facing the cell region 100a.

[0192] The cell region 100a may include a second substrate 110a, a gate stack structure 120, a channel structure CH, a second wiring portion 180, and a second junction structure 194 electrically connected to the second wiring portion 180 and located on a surface facing the circuit region 200a. The area other than the second junction structure 194 may be covered with an insulating layer 196.

[0193] In the embodiment, the second substrate 110a may be a semiconductor substrate including a semiconductor material. For example, the second substrate 110a may be a semiconductor substrate including a semiconductor material, or a semiconductor substrate including a semiconductor layer formed on a base substrate. For example, the second substrate 110a may be made of single crystal or polycrystalline silicon, germanium, silicon-germanium, silicon-on-insulator, or germanium-on-insulator. Alternatively, the second substrate 110a may be made of a support member including an insulating layer or an insulating material. This is because, after bonding the cell region 100a to the circuit region 200a, the semiconductor substrate included in the cell region 100a may be removed to form a support member including an insulating layer or an insulating material.

[0194] In one embodiment, the gate stack 120 may be stacked in sequence under the second substrate 110a in the drawing, and may be arranged in a structure obtained by upside down the gate stack 120 shown in FIG. 2. The channel structure CH stacked in sequence through the gate stack 120 may have a structure obtained by upside down the channel structure CH shown in FIG. 2 or 3. As a result, the channel structure CH may have a side surface that is inclined so that its width narrows from the circuit region 200a toward the second substrate 110a when viewed in cross section. The channel pad 144 and the second wiring unit 180 located on the gate stack 120 may be located adjacent to the circuit region 200a.

[0195] For example, the first bond structure 238 and / or the second bond structure 194 can be made of aluminum, copper, tungsten, or an alloy including the same. As an example, the first and second bond structures 238, 194 can include copper, and the cell region 100a and the circuit region 200a can be bonded (for example, bonded in direct contact) by a copper-to-copper bond.

[0196] 13 illustrates an example in which the gate stack structure 120 includes three gate stack structures 120a, 120b, and 120c, but may include two or four gate stack structures. Unless otherwise noted, the description of the gate stack structure 120 and the channel structure CH described with reference to FIGS. 1 to 6, 7a to 7i, and 8 to 12 may be applied as is. In FIG. 13, the electrical connection structure between the channel structure CH and the horizontal conductive layers 112, 114 and / or the second substrate 110 is the same as that in FIG. 2. However, the embodiment is not limited thereto, and the electrical connection structure between the channel structure CH and the horizontal conductive layers 112, 114 and / or the second substrate 110a may be modified in various ways.

[0197] According to an example, the semiconductor device 20 may include an I / O pad (not shown) and an I / O connection wire (not shown) electrically connected thereto. The I / O connection wire may be electrically connected to a portion of the second junction structure 194. The I / O pad may be located, for example, on an insulating film 198b covering an outer surface of the second substrate 110a. According to an embodiment, a separate I / O pad may be provided that is electrically connected to the circuit region 200a.

[0198] As an example, the circuit region 200a and the cell region 100a may be parts corresponding to the first structure 1100F and the second structure 1100S of the semiconductor device 1100 included in the electronic system 1000 shown in Fig. 14. Alternatively, the circuit region 200a and the cell region 100a may be regions including the first structure 4100 and the second structure 4200 of the semiconductor chip 2200a shown in Fig. 17.

[0199] An example of an electronic system including the above-mentioned semiconductor device will now be described in detail.

[0200] FIG. 14 is a diagram illustrating an electronic system including a semiconductor device according to an exemplary embodiment.

[0201] 14, an electronic system 1000 according to an exemplary embodiment may include a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0202] The semiconductor device 1100 may be a non-volatile memory device, for example, a NAND flash memory device as described with reference to FIGS. 1 to 6, 7a to 7i, and 8 to 13. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed to the side of the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1, UL2, first and second gate lower lines LL1, LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0203] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The numbers of the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2 may be variously modified according to the embodiment.

[0204] In an exemplary embodiment, the lower transistors LT1 and LT2 may include ground selection transistors, and the upper transistors UT1 and UT2 may include string selection transistors. The first and second gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0205] The common source line CSL, the first and second gate lower lines LL1, LL2, the word line WL, and the first and second gate upper lines UL1, UL2 may be electrically connected to the decoder circuit 1110 through a first connecting wire 1115 extending to the second structure 1100S in the first structure 1100F. The bit line BL may be electrically connected to the page buffer 1120 through a second connecting wire 1125 extending to the second structure 1100S in the first structure 1100F.

[0206] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one memory cell transistor selected from the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an I / O pad 1101 electrically connected to the logic circuit 1130. The I / O pad 1101 may be electrically connected to the logic circuit 1130 through an I / O connection wiring 1135 extending to the second structure 1100S in the first structure 1100F.

[0207] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an embodiment, the electronic system 1000 may include multiple semiconductor devices 1100, in which case the controller 1200 may control the multiple semiconductor devices 1100.

[0208] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 for processing communication with the semiconductor device 1100. A control command for controlling the semiconductor device 1100, data to be written in the memory cell transistor MCT of the semiconductor device 1100, data to be read from the memory cell transistor MCT of the semiconductor device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0209] FIG. 15 is a perspective view that illustrates a schematic diagram of an electronic system including a semiconductor device according to an exemplary embodiment.

[0210] 15, an electronic system 2000 according to an exemplary embodiment may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 may be connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0211] The main board 2001 may include a connector 2006 including a plurality of pins to be coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on a communication interface between the electronic system 2000 and the external host. In an exemplary embodiment, the electronic system 2000 may communicate with the external host through any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the electronic system 2000 may operate with power supplied from the external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0212] The controller 2002 can record data to and read data from the semiconductor package 2003 , thereby improving the operating speed of the electronic system 2000 .

[0213] The DRAM 2004 may be a buffer memory for mitigating the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a type of cache memory and provide space for temporarily storing data in a control operation for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0214] The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. The first and second semiconductor packages 2003a and 2003b may each be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of each of the semiconductor chips 2200, a connection structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0215] The package substrate 2100 may be a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 may include an I / O pad 2210. The I / O pad 2210 may correspond to the I / O pad 1101 of FIG. 14. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. The semiconductor chips 2200 may include the semiconductor devices described with reference to FIGS. 1 to 6, 7a to 7i, and 8 to 13, respectively.

[0216] In an exemplary embodiment, the connection structure 2400 may be a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Thus, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected by a connection structure including a through silicon via (TSV) instead of the bonding wire type connection structure 2400.

[0217] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0218] 16 and 17 are cross-sectional views each illustrating a semiconductor package according to an exemplary embodiment. Each of FIG. 16 and FIG. 17 illustrates an exemplary embodiment of the semiconductor package 2003 of FIG. 15 and conceptually illustrates a region of the semiconductor package 2003 of FIG. 15 cut along the cutting line II'.

[0219] 16, in the semiconductor package 2003, a package substrate 2100 may be a printed substrate. The package substrate 2100 may include a package substrate body part 2120, a package upper pad 2130 disposed on an upper surface of the package substrate body part 2120, a lower pad 2125 disposed on or exposed through a lower surface of the package substrate body part 2120, and an internal wiring 2135 electrically connecting the upper pad 2130 and the lower pad 2125 inside the package substrate body part 2120. The upper pad 2130 may be electrically connected to a connection structure 2400. The lower pad 2125 may be connected to a wiring pattern 2005 of a main substrate 2001 of an electronic system 2000 through a conductive connection part 2800 as shown in FIG.

[0220] The semiconductor chip 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and an isolation structure 3230 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a gate connecting wiring electrically connected to a word line (WL in FIG. 14) of the gate stack structure 3210.

[0221] In the semiconductor chip 2200 or the semiconductor device according to the embodiment, the buffer insulating portion 132p is provided, so that the performance of the semiconductor chip 2200 or the semiconductor device can be improved.

[0222] Each of the semiconductor chips 2200 may include a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may pass through the gate stack structure 3210 and may be further disposed outside the gate stack structure 3210. Each of the semiconductor chips 2200 may further include an input / output connecting wiring 3265 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200, and an input / output pad 2210 electrically connected to the input / output connecting wiring 3265.

[0223] In an exemplary embodiment, a plurality of semiconductor chips 2200 in a semiconductor package 2003 may be electrically connected to each other by a bonding wire type connecting structure 2400. As another example, a plurality of semiconductor chips 2200 or a plurality of parts constituting the plurality of semiconductor chips 2200 may be electrically connected to each other by a connecting structure including a through silicon via (TSV).

[0224] Referring to FIG. 17, in the semiconductor package 2003A, each of the semiconductor chips 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 on the first structure 4100 by a wafer bonding method.

[0225] The first structure 4100 may include a peripheral circuit region including a peripheral wiring 4110 and a first junction structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 and an isolation structure 4230 penetrating the gate stack structure 4210, and a second junction structure 4250 electrically connected to the channel structure 4220 and the word line (WL in FIG. 14, the same hereinafter) of the gate stack structure 4210. For example, the second junction structure 4250 may be electrically connected to the channel structure 4220 and the word line WL through a bit line 4240 electrically connected to the channel structure 4220 and a gate connecting wiring electrically connected to the word line WL. The first joint structure 4150 of the first structure 4100 and the second joint structure 4250 of the second structure 4200 may be in contact with each other and joined. The joined portions of the first joint structure 4150 and the second joint structure 4250 may be formed of, for example, copper (Cu).

[0226] In the semiconductor chip 2200a or the semiconductor device according to the embodiment, the buffer insulating portion 132p is provided, so that the performance of the semiconductor chip 2200a or the semiconductor device can be improved.

[0227] Each of the semiconductor chips 2200a may further include an I / O pad 2210 and an I / O connecting wire 4265 below the I / O pad 2210. The I / O connecting wire 4265 may be electrically connected to a portion of the second joint structure 4250.

[0228] In one embodiment, a plurality of semiconductor chips 2200a in a semiconductor package 2003A may be electrically connected to each other by a bonding wire type connecting structure 2400. As another example, a plurality of semiconductor chips 2200 or a plurality of parts constituting the plurality of semiconductor chips 2200 may be electrically connected to each other by a connecting structure including a through electrode.

[0229] Although the embodiments have been described in detail above, the scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the claims may also fall within the scope of the present invention. [Explanation of symbols]

[0230] 100: Cell area 200: Circuit area 120: Gate stack structure 130: Gate electrode CH: Channel structure 132: Cell insulation layer 132i: Pad insulation part 132p: Buffer insulation part

Claims

1. a gate stack structure including a first stack structure and a second stack structure that are stacked in sequence, each of the first stack structure and the second stack structure including a plurality of gate electrodes; a channel structure extending through the gate stack; a plurality of gate contact portions respectively connected to the plurality of gate electrodes in first and second pad regions formed in the first and second stacked structures, respectively; a buffer insulating portion formed in the first stacked structure including a boundary portion of the first stacked structure adjacent to the second stacked structure where the second pad region is located; Including, the buffer insulating portion includes an inner region, a first region located on one side of the inner region in an extension direction of the gate electrodes, and a second region located on the other side of the inner region in the extension direction; The first region and the second region each have a longer length in the extension direction at an upper portion than at a lower portion, A semiconductor device in which the difference between the length at the upper portion and the length at the lower portion is greater in the second area than in the first area.

2. When a distance between one surface of adjacent gate electrodes among the plurality of gate electrodes is defined as a reference thickness, and a change in length of the first or second region in the extension direction relative to the reference thickness is defined as a reference length change amount, 2. The semiconductor device according to claim 1, wherein said reference length change amount in said second section is larger than said reference length change amount in said first section.

3. 2. The semiconductor device according to claim 1, wherein a length of said inner region in said extension direction is equal to or smaller than a sum of an overall length of said first region and an overall length of said second region.

4. At least one of the first and second pad regions includes a pad area to which the gate electrodes and the gate contact portions are respectively connected, and an upper area located on an upper portion of the pad area; When a distance between one surface of adjacent gate electrodes among the plurality of gate electrodes is defined as a reference thickness, and a change in length of the upper region or the first or second region in the extension direction relative to the reference thickness is defined as a reference length change amount, 2. The semiconductor device according to claim 1, wherein the reference length change in the first section and the reference length change in the second section are each greater than the reference length change on one side of the upper section.

5. The one side surface of the upper section is formed of a vertical surface or an inclined surface, The semiconductor device according to claim 4 , wherein at least one side or bottom surface of the first region and the second region is configured in a stepped shape.

6. The semiconductor device according to claim 1 , wherein the buffer insulating portion has a shape corresponding to or a symmetrical shape of a pad insulating portion provided in at least a part of the first pad region.

7. the buffer insulating portion is located on the top of the first laminate structure and is configured with an upper pattern including the inner region, the first region, and the second region; or The semiconductor device of claim 1 , wherein the buffer insulation portion is configured in an extended pattern further including an upper buffer area located on top of the inner area, the first area, and the second area.

8. The buffer insulating portion is formed of the extension pattern, When a distance between one surface of adjacent gate electrodes among the plurality of gate electrodes is defined as a reference thickness, and a change in length of the upper buffer region or the first or second region in the extension direction relative to the reference thickness is defined as a reference length change amount, The semiconductor device of claim 7 , wherein the reference length change in the first section and the reference length change in the second section are greater than the reference length change on one side of the upper buffer section.

9. a gate stack structure including a first stack structure and a second stack structure that are stacked in sequence, each of the first stack structure and the second stack structure including a plurality of gate electrodes; a channel structure extending through the gate stack; a plurality of gate contact portions respectively connected to the plurality of gate electrodes in first and second pad regions formed in the first and second stacked structures, respectively; a buffer insulating portion formed in the first stacked structure including a boundary portion of the first stacked structure adjacent to the second stacked structure where the second pad region is located; Including, At least one of the first and second pad regions includes a pad area to which the gate electrodes and the gate contact portions are respectively connected, and an upper area located on an upper portion of the pad area; the buffer insulating portion includes an inner region, a first region located on one side of the inner region in an extension direction of the gate electrodes, and a second region located on the other side of the inner region in the extension direction; a first distance between one of the plurality of gate electrodes and the inner area in the first area, and a second distance between the one gate electrode and the inner area in the second area are each greater than a third distance; The third distance is a distance between the one gate electrode and the upper region in the upper region or a distance between the one gate electrode and an inner region of the upper region.

10. When a distance between one surface of adjacent gate electrodes among the plurality of gate electrodes is defined as a reference thickness, and a change in length of the upper region or the first or second region in the extension direction relative to the reference thickness is defined as a reference length change amount, the reference length change amount in the first section and the reference length change amount in the second section are each greater than the reference length change amount in one side of the upper section, 10. The semiconductor device of claim 9, wherein a ratio of the reference length change in the first region or the reference length change in the second region to the reference length change on the one side of the upper region is equal to or greater than two.

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