Semiconductor device

Abstract

To provide a semiconductor device capable of preventing quality deterioration.SOLUTION: A semiconductor device comprises: a plurality of trenches 4 containing extension parts extended in a first direction and arranged with an interval in a second direction; a gate insulation film 5 that is provided inside the trench 4; and a p-type protection region that is provided under the trench 4 and contains a first protection layer 11a and a second protection layer 11b. The semiconductor device further comprises: first conductive type first main electrode regions (source regions) 7a and 7b that contain parts provided along a side wall of the first trench 4 as one of the trenches 4; second conductive type base regions 3a and 3b that are provided under the first main electrode regions 7a and 7b. In a depth direction, the concentration of an impurity element in a second protection layer 11b provided between the first protection layer 11a and a bottom part of the first trench 4 is lower than a peak concentration in a first region along a side wall of the first trench 4 of the base regions 3a and 3b. The first protection layer 11a has a concentration of the impurity element that is higher than those in the base regions 3a and 3b.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In trench-type MOSFETs using silicon carbide (SiC) semiconductors, when a reverse bias voltage is applied during turn-off (hereinafter simply referred to as "off"), a high voltage is applied between the drain and source, which can cause the quality of the gate insulating film to deteriorate. When a reverse bias voltage is applied, the part of the gate insulating film at the bottom of the trench is most susceptible to damage.

[0003] As a technique for protecting the gate insulating film at the bottom of the trench, for example, Patent Document 1 discloses a technique in which a high-concentration p-type electric field shield region is placed directly under the trench to protect the gate insulating film from high voltage when the device is off. However, in the case of the technique of Patent Document 1, when the device is turned on (hereinafter also simply referred to as "on"), the path of the main current is blocked by the electric field shield region. This causes a problem in that the increased component of the on-resistance (JFET resistance) increases due to the junction field effect transistor (JFET) effect in which a depletion layer extends from an adjacent channel region to narrow the path of the main current. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4738562 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned problems, and has an object to provide a semiconductor device capable of preventing quality deterioration. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, one aspect of the semiconductor device of the present invention is a semiconductor device comprising: a trench including an extension portion extending in a first direction, the extension portions being arranged at intervals in a second direction; an insulating film provided inside the trench; and a p-type protective region provided below the trench and including a first protective layer and a second protective layer, further comprising: a first main electrode region of a first conductivity type including a portion provided along a sidewall of a first trench which is one of the trenches; and a base region of a second conductivity type provided below the first main electrode region, wherein in the depth direction, the concentration of an impurity element in the second protective layer provided between the first protective layer and a bottom of the first trench is lower than the peak concentration in a first region of the base region along the sidewall of the first trench, and the first protective layer has a higher concentration of an impurity element than the base region.

[0007] In order to solve the above-mentioned problems, one aspect of the semiconductor device of the present invention is a semiconductor device comprising: a trench including an extension portion extending in a first direction, the extension portions being arranged at intervals in a second direction; an insulating film provided inside the trench; and a p-type protection region provided below the trench and including a first protection layer and a second protection layer, further comprising: a first main electrode region of a first conductivity type including a portion provided along a sidewall of a first trench, which is one of the trenches; and a base region of a second conductivity type provided below the first main electrode region, wherein the protection region is composed of three or more layers, and the second protection layer is provided in contact with the bottom of the first trench. Effect of the Invention

[0008] According to the present invention, it is possible to provide a semiconductor device capable of preventing quality deterioration. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view for explaining an outline of a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a cross-sectional view for explaining an outline of a state of a main current flowing in a semiconductor device according to an embodiment of the present invention; [Diagram 3]10 is a cross-sectional view for explaining an outline of a state of a main current flowing in a semiconductor device according to a comparative example; FIG. [Figure 4] 1A to 1C are partially enlarged cross-sectional views for explaining in schematic form the outline of the state of a main current flowing in the semiconductor device according to the embodiment of the present invention and in the semiconductor device according to the comparative example. [Diagram 5] 1 is a graph showing the relationship between the concentration of the conductive path forming layer below the bottom of the trench and the on-resistance of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views (part 1) for illustrating a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 5A to 5C are cross-sectional views (part 2) for illustrating a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 4A to 4C are cross-sectional views (part 3) for illustrating a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 4 is a cross-sectional view (part 4) for illustrating a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 10] 5 is a cross-sectional view (part 5) for illustrating a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. [Figure 11] 6 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. [Figure 12] 7 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. [Figure 13] 8 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. [Figure 14] 9 is a cross-sectional view for illustrating a schematic method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. [Figure 15] 1A to 1C are cross-sectional views (part 1) illustrating a schematic diagram of a method for manufacturing a semiconductor device according to a first modified example of the embodiment of the present invention. [Figure 16] 5A to 5C are cross-sectional views (part 2) illustrating a schematic diagram of a method for manufacturing a semiconductor device according to a first modified example of the embodiment of the present invention. [Figure 17] 11A to 11C are cross-sectional views (part 3) illustrating a schematic diagram of a method for manufacturing a semiconductor device according to a first modified example of the embodiment of the present invention. [Figure 18] 4 is a cross-sectional view (part 4) illustrating a schematic diagram of a method for manufacturing a semiconductor device according to a first modified example of the embodiment of the present invention. FIG. [Figure 19] FIG. 11 is a partially enlarged cross-sectional view illustrating an outline of a configuration of a semiconductor device according to a second modified example of the embodiment of the present invention. [Figure 20] FIG. 11 is a partially enlarged cross-sectional view for explaining an outline of a state of a main current flowing in a semiconductor device according to a second modified example of the embodiment of the present invention. [Figure 21] FIG. 11 is a partially enlarged cross-sectional view illustrating an outline of a configuration of a semiconductor device according to a third modified example of the embodiment of the present invention. [Figure 22] FIG. 11 is a partially enlarged cross-sectional view for explaining an outline of a state of a main current flowing in a semiconductor device according to a third modified example of the embodiment of the present invention. [Figure 23] FIG. 13 is a partially enlarged cross-sectional view illustrating an outline of a configuration of a semiconductor device according to a fourth modified example of the embodiment of the present invention. [Figure 24] FIG. 11 is a partially enlarged cross-sectional view for explaining an outline of a state of a main current flowing in a semiconductor device according to a fourth modified example of the embodiment of the present invention. [Diagram 25] FIG. 13 is a partially enlarged cross-sectional view illustrating an outline of a configuration of a semiconductor device according to a fifth modified example of the embodiment of the present invention. [Figure 26] FIG. 13 is a partially enlarged cross-sectional view for explaining an outline of a state of a main current flowing in a semiconductor device according to a fifth modified example of the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The following describes an embodiment of the present invention. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, and the like differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description. In addition, it goes without saying that the drawings include parts whose dimensional relationships and ratios differ from each other.

[0011] In addition, the directions of "left and right" and "up and down" in the following description are merely definitions for the convenience of explanation and do not limit the technical idea of ​​the present invention. Therefore, for example, if the paper is rotated 90 degrees, "left and right" and "up and down" are read interchangeably, and if the paper is rotated 180 degrees, "left" becomes "right" and "right" becomes "left". In addition, in the following description, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example, but the conductivity types may be selected in the opposite relationship, with the first conductivity type being p-type and the second conductivity type being n-type. In addition, + and - added to n and p mean that the semiconductor region has a relatively high or low impurity element concentration, respectively, compared to a semiconductor region without + and -.

[0012] In this specification, the term "first main electrode region" refers to a semiconductor region that becomes either a source region or a drain layer in a field effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), the term "second main electrode region" refers to a semiconductor region that becomes either a source region or a drain layer that is not the first main electrode region in a FET or an SIT, and to a region that becomes either an emitter region or a collector region that is not the first main electrode region in an IGBT.

[0013] <Semiconductor device> 1, a semiconductor device according to an embodiment of the present invention is a MOSFET including an n-type drift region 2 using a SiC semiconductor substrate, and a plurality of p-type base regions 3a, 3b provided in an upper portion of the drift region 2. A trench 4 is provided in an upper portion of the drift region 2, extending from the base regions 3a, 3b to the drift region 2.

[0014] The semiconductor device shown in Fig. 1 focuses on one trench 4 and the region surrounding this trench 4 in a semiconductor device according to an embodiment of the present invention. In reality, a plurality of trenches 4 are provided, and each trench extends parallel to each other at intervals along a direction penetrating the paper on which the drawing is drawn. The semiconductor device according to the embodiment of the present invention is configured by repeatedly forming and integrating a structure such as that shown in Fig. 1 on both the left and right sides of Fig. 1.

[0015] 1 also includes a gate insulating film 5 provided inside the trench 4, a gate electrode 6 provided inside the trench 4 via the gate insulating film 5, and an interlayer insulating film 8 provided on the surface of the gate electrode 6. The concentration of impurity elements in the base regions 3a and 3b--the impurity density--is, for example, 4.0×10 17 cm -3 When a predetermined gate voltage is applied to the gate electrode 6 while a positive bias is applied to the channel region, the conductivity type of the channel region is inverted.

[0016] In the upper part of the inner part of the plurality of p-type base regions 3a and 3b, a plurality of p + In addition, directly below the base regions 3a and 3b located below the base contact regions 12a and 12b, first contact under base regions 13a and 13b and second contact under base regions 14a and 14b, both of which are p-type, are laminated from bottom to top in this order.

[0017] The semiconductor device shown in FIG. 1 has a plurality of n-type junctions selectively provided in the upper part of the p-type base regions 3a and 3b. +The semiconductor device includes source regions 7a, 7b and a source electrode 9 provided on the source regions 7a, 7b via a barrier metal layer 15. The source regions 7a, 7b correspond to the "first main electrode region" of the present invention. The source electrode 9 is connected to the source regions 7a, 7b. The barrier metal layer 15 has a three-layer structure of titanium (Ti), titanium nitride (TiN), etc., provided on the drift region 2 over the interlayer insulating film 8, the upper surfaces of the source regions 7a, 7b, and the base contact regions 12a, 12b. The barrier metal layer 15 suppresses the growth of silicon (Si) nodules or the diffusion of aluminum (Al) contained in the source electrode 9. An ohmic contact is formed by providing a nickel silicide layer (not shown) at the contact portion between the barrier metal layer 15 and the source regions 7a, 7b and the base contact regions 12a, 12b.

[0018] A passivation film such as polyimide is deposited as the outermost layer on the upper surface of the source electrode 9, and the main surface of the lower source electrode 9 is exposed in a window--an opening--formed in the passivation film. The exposed main surface of the source electrode 9 can be used as a source bonding pad. Similarly, a wiring layer connected to the gate electrode 6 is exposed in a window formed in the passivation film in a location separate from the source electrode 9. The exposed portion of the wiring layer can be used as a gate bonding pad. Illustrations of the passivation film, bonding pads, etc. are omitted.

[0019] The semiconductor device shown in FIG. 1 also has a n + The semiconductor device includes a drain region 1 of a semiconductor device type, and a drain electrode 10 provided under and connected to the drain region 1. The drain region corresponds to the "second main electrode region" of the present invention.

[0020] Further provided below the trench 4 within the drift region 2 are a p-type protective layer 11a that protrudes outward beyond the width of the trench 4, and a p-type conductive path-forming layer 11b that is provided between the protective layer 11a and the bottom of the trench 4. The conductive path-forming layer 11b is provided so as to protrude outward by a certain amount beyond the width of the trench 4, and the concentration and thickness of the impurity element in the protruding region are set so as to be inverted to n-type when on. A two-layer protective conductive region (11a, 11b) is realized by the protective layer 11a and the conductive path-forming layer 11b.

[0021] The protective conductive regions (11a, 11b) are provided at approximately the same height as the first-contact under base regions 13a, 13b below the base contact regions 12a, 12b. The protective conductive regions (11a, 11b) have approximately the same thickness t as the first-contact under base regions 13a, 13b, and their upper surfaces are in contact with the lower surface of the gate insulating film 5 at the bottom of the trench 4. The protective layer 11a and the conductive path forming layer 11b of the protective conductive regions (11a, 11b) both have a rectangular cross-sectional shape shown in FIG. 1 and extend parallel to the trench 4 that extends in the drift region 2 in a direction penetrating the page.

[0022] The protective layer 11a is formed of a 5.0×10 18 cm -3 At high concentrations of p + The protective layer 11a is formed to have a rectangular shape. The protruding width w of both ends of the rectangular shape of the protective layer 11a is longer than the protruding width of both ends of the rectangular shape of the conductive path-forming layer 11b. Therefore, the overall cross-sectional shape of the protective conductive region (11a, 11b) consisting of the protective layer 11a and the conductive path-forming layer 11b has a stepped shape at both ends from the lower side to the upper side and from the outside to the inside of the trench 4.

[0023] The conductive path forming layer 11b is provided directly on the protective layer 11a, and an inversion layer is formed when the conductive path forming layer 11b is on. The upper limit of the p-type impurity element concentration of the conductive path forming layer 11b is set to a concentration that allows the thickness of the conductive path forming layer 11b to be inverted to n-type when an on-voltage is applied. As an example of inverting the conductive path forming layer 11b to n-type, it is preferable to set the impurity element concentration of the conductive path forming layer 11b lower than the impurity element concentration of the base regions 3a and 3b. On the other hand, the lower limit of the p-type impurity element concentration of the conductive path forming layer 11b is set to at least the impurity element concentration of the n-type drift region 2 so that the conductivity type can be maintained as p-type when the conductive path forming layer 11b is off. Specifically, if the semiconductor device is a 1200V class, the upper limit of the p-type impurity element concentration is set to, for example, 8.0×10 15 cm -3 The impurity element concentration in the protective layer 11a and the impurity element concentration in the conductive path forming layer 11b may be set to be the same.

[0024] The conductive path forming layer 11b of the semiconductor device according to the embodiment of the present invention is set in thickness as well as concentration so as to more reliably realize an inversion layer formed when the semiconductor device is on. Specifically, the overhang width of both ends of the conductive path forming layer 11b is about 0.1 μm to 0.5 μm. If the overhang width and thickness exceed their respective upper limits, there is a concern that the inversion layer may not be formed sufficiently.

[0025] The total thickness t of the protective conductive regions (11a, 11b) is set so as to achieve both the realization of an inversion layer in the conductive path forming layer 11b and the protection of the gate insulating film 5 by the protective layer 11a.

[0026] As shown in FIG. 2, in the semiconductor device according to the embodiment of the present invention, when the drain region 1 is biased to a positive potential, an inversion layer 11b, in which the conductivity type is inverted from p type to n type, is formed inside the conductive path forming layer 11b in the on-state. inv Then, a main current I flows from the drain region 1 toward the source regions 7a and 7b along the left and right side walls of the trench 4. L 1,I R 1 flows. The main current I L 1,I RThe flow of the main current I1 rises along the side of the protective layer 11a in the n-type drift region 2, reaches the upper side of the protective layer 11a, and then changes direction by about 90 degrees so as to flow along the upper surface of the end of the protective layer 11a. L 1,I R 1 is the inversion layer 11b inv The end of the tube is inserted into the tube.

[0027] Then, the main current I L 1,I R 1 is the inversion layer 11b inv Inside the trench 4, the direction of the main current I L 1,I R 1 is the inversion layer 11b inv Then, the main current I L 1,I R The flow of 1 flows upward along the sidewall of trench 4, passes through the inversion layers of channel regions 3a1, 3b1 formed in base regions 3a, 3b, and reaches source regions 7a, 7b.

[0028] That is, the main current I L 1,I R 1 does not flow along the shape of the corners of the end of the conductive path forming layer 11b in the protective conductive region (11a, 11b), but flows along the inversion layer 11b of the conductive path forming layer 11b. inv 2, the hatching of the inversion layer portions of the channel regions 3a1 and 3b1 is omitted for ease of viewing.

[0029] <Comparative Example> On the other hand, as shown in FIG. 3, in the case of the semiconductor device according to the comparative example that does not have a conductive path forming layer, the main current I L z,I Rz flows along the step shape of the end of protective layer 11z. The semiconductor device of the comparative example differs from the semiconductor device of the embodiment of the present invention in that it does not have a two-layer protective conductive region (11a, 11b) including conductive path forming layer 11b, but only has a single-layer protective layer 11z. That is, the shape of the outer edge of protective layer 11z of the semiconductor device of the comparative example is equivalent to the shape of the outer edge of protective conductive region (11a, 11b) of the semiconductor device of the embodiment of the present invention, but the inner conductivity type is high concentration p + Only the type is formed, and no inversion layer is formed. The concentration of the impurity element in the protective layer 11z of the semiconductor device according to the comparative example is, for example, 5.0×10 18 cm -3 On the other hand, the impurity element concentration of the conductive path forming layer 11b of the protective conductive region (11a, 11b) of the semiconductor device according to the embodiment of the present invention is about 4.0×10 17 cm -3 It is set fairly low.

[0030] In FIG. 4, a main current I L 1,I R 1 and the main current I L z,I R 4, the flow of the main current I in the semiconductor device according to the embodiment of the present invention is shown by a solid line. L 1,I R 1 is the inversion layer 11b inv After entering the inside of the trench 4 from the side end face, the tip approaches the side wall of the trench 4 while smoothly curving.

[0031] On the other hand, in the comparative example illustrated by the dashed line, the main current I L z,I R The main current I z cannot pass through the inside of the protective layer 11 z in the path from the upper side of the protective layer 11 z to the side wall of the trench 4. L z,I RThe main current Iz is forced to travel along a greatly bent path that is longer than the path in the embodiment of the present invention, along the stepped shape of the outer edge of the protective layer 11z. L 1,I R Since the overall path length can be shortened, the on-resistance can be reduced accordingly.

[0032] 5 shows the relationship between the impurity element concentration of the conductive path forming layer 11b in the protective conductive region (11a, 11b) and the on-resistance Ron of the semiconductor device. It can be seen that the on-resistance Ron decreases as the impurity element concentration of the conductive path forming layer 11b decreases. th 1, the peak concentration of the channel regions 3a1 and 3b1 of the semiconductor device is 3.0×10 17 cm -3 1 visually shows the positions where the threshold voltages of the channel regions 3a1 and 3b1 exist in the case of FIG.

[0033] The solid vertical line L in Figure 5 th In the range to the left of 1, the on-resistance Ron is th As the impurity element concentration in the conductive path forming layer 11b decreases, the locus of the solid line connecting the plot points indicated by the white circles becomes flatter. th In the range to the right of 1, the on-resistance Ron is th As the impurity element concentration in the conductive path formation layer 11b increases, the locus of the solid line connecting the plot points approaches a flat line.

[0034] Also, the dashed vertical line L in Fig. 5 th 2, the peak concentration of the channel regions 3a1 and 3b1 of the semiconductor device is 4.0×10 17 cm -3 In this case, the position where the threshold voltage of the channel regions 3a1 and 3b1 exists is visually indicated. th In the range to the left of 2, the peak concentration of the channel regions 3a1 and 3b1 is 3.0×10 17 cm -3As in the case of th As the impurity element concentration in the conductive path forming layer 11b decreases, the locus of the solid line connecting the plotted points indicated by the white circles becomes flat. th In the range to the right of 2, the on-resistance Ron is th 2 is higher overall than the range to the left of 2, and as the impurity element concentration in the conductive path formation layer 11b increases, the dotted line connecting the plot points approaches a flat line.

[0035] In the semiconductor device according to the embodiment of the present invention, a conductive path forming layer 11b in which an inversion layer is formed when the device is on is provided on the protective layer 11a that protects the gate insulating film 5 at the bottom of the trench 4. Therefore, the main current I L 1,I R 1 through inversion layer 11b inv By inducing the main current I L 1,I R Therefore, it is possible to realize a semiconductor device that can protect the gate insulating film 5 at the bottom of the trench 4 and reduce the on-resistance at the same time.

[0036] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. + 4H-SiC semiconductor substrate 1 sub A semiconductor substrate 1 is prepared by epitaxial growth. sub An n-type 4H-SiC semiconductor layer is epitaxially grown on top of the drift region 2 to form the drift region 2. Next, a first mask film 16 is deposited to a predetermined thickness on the upper surface of the drift region 2. As the first mask film 16, a silicon oxide (SiO2) film or a silicon nitride (Si3N4) film formed by thermal oxidation or deposited by a chemical vapor deposition (CVD) method or the like can be used.

[0037] Next, a photoresist film is applied onto the first mask film 16 by photolithography, etching, or the like, and the photoresist film is patterned. Then, as shown in Fig. 7, using the patterned photoresist film as a mask, the portion of the first mask film 16 located above the region where the trench 4 is to be formed is selectively removed to form a window portion. The window portion can be formed by an etching technique such as reactive ion etching (RIE).

[0038] After removing the photoresist film, impurity element ions such as Al are implanted into the drift region 2 by multi-stage ion implantation or the like using the first mask 16p having the window as an ion implantation mask to form the protective layer intended region 11a0. Note that the photoresist film used in etching the first mask coating 16 may be left on the drift region 2 without being removed, and used as an ion implantation mask together with the first mask 16p.

[0039] Next, as shown in FIG. sub The structure having a semiconductor substrate 1 at the bottom (hereinafter, simply referred to as "semiconductor substrate 1") sub The protective layer-planned region 11a0 is activated by vacuum annealing or the like, and p + A protective layer 11a for the mold is formed. The protective layer 11a is formed so that both ends extend outward by a certain width w beyond the width of the trench 4 to be formed later.

[0040] 9, a first mask 16p having a window is continuously used to dig the drift region 2 by etching such as RIE to form a trench 4. The position of the trench 4 is controlled so that the distance between the bottom surface and the lower surface of the protective layer 11a is equal to the thickness t of the protective conductive region (11a, 11b) to be formed later.

[0041] Next, semiconductor substrate 1 subAfter cleaning and removing the first mask 16p, a second mask film 17 is deposited to a predetermined thickness on the exposed upper surface of the drift region 2 as shown in Fig. 10. As the second mask film 17, for example, a protective film such as a SiO2 film deposited by a plasma CVD method or the like can be used.

[0042] Next, a photoresist film is applied onto the second mask film 17 by photolithography, etching, or the like, and the photoresist film is patterned. Then, using the patterned photoresist film as a mask, the portion of the second mask film 17 located above the trench 4 is selectively removed by RIE or the like to form a window portion, exposing the bottom of the trench 4 as shown in Fig. 11. At this time, the opening dimensions of the window portion are adjusted so that the sidewall portion of the second mask film 17 on the trench 4 remains.

[0043] 12, ion implantation is performed through a second mask 17p having a window formed therein to form a conductive path formation layer region 11b0 between the protective layer 11a and the bottom of the trench 4 inside the drift region 2. The ion implantation is performed by controlling the implantation depth of p-type impurity element ions such as Al. During the ion implantation, the sidewall portion of the trench 4 is protected by the second mask 17p.

[0044] Next, semiconductor substrate 1 sub The conductive path formation layer planned region 11b0 is activated by vacuum annealing or the like. Through activation, the conductive path formation layer 11b, which is the second layer of the protective conductive region (11a, 11b), is formed to have a protruding width planned to shorten the path length of the main current. Then, the second mask 17p remaining on the structure is removed by full surface etching or the like to expose the upper surface of the drift region 2 and the sidewall of the trench 4 as shown in FIG. 13, and the semiconductor substrate 1 is exposed. sub The material is then subjected to cleaning and other processing.

[0045] Next, as shown in Fig. 14, an insulating film such as a SiO2 film is deposited on the surface of the drift region 2, including the inside of the trench 4, by thermal oxidation or the like. The deposited insulating film is then patterned using photolithography and dry etching techniques to form a gate insulating film 5. A doped polysilicon film doped with an n-type impurity element is then deposited on the entire upper surface of the drift region 2 by low-pressure CVD or the like. Thereafter, the doped polysilicon film is embedded inside the trench 4 by etch-back or chemical mechanical polishing (CMP) or the like to form a gate electrode 6.

[0046] Thereafter, the first contact under base regions 13a, 13b and the second contact under base regions 14a, 14b are provided in a predetermined pattern in this order in the region between the trenches 4 inside the drift region 2 using photolithography technology, etching technology, ion implantation technology, etc. Next, the base regions 3a, 3b are similarly provided in the region between the trenches 4 inside the drift region 2. When the base regions 3a, 3b are formed by implanting p-type impurity element ions such as Al, the ion implantation is performed so that the peak dose of the implanted ions is higher than the dose of the impurity element ions when the conductive path formation layer 11b is formed.

[0047] In other words, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, the ion dose during formation of the conductive path-forming layer 11b is lower than the peak ion dose during formation of the base regions 3a, 3b. By controlling the respective doses, the concentration of the impurity element during formation of the conductive path-forming layer 11b is realized to be lower than the peak concentration of the impurity element in the channel regions 3a1, 3b1, as shown in FIG.

[0048] Thereafter, the base contact regions 12a, 12b and the source regions 7a, 7b are provided in a predetermined pattern inside the base regions 3a, 3b by using photolithography, etching, ion implantation, etc. Then, an interlayer insulating film 8 such as a SiO2 film is deposited over the gate electrode 6, the base contact regions 12a, 12b, and the source regions 7a, 7b by using a CVD method or the like.sub The bottom surface of the drain region 1 is thinned and flattened by CMP or the like to form the drain region 1. A metal film such as nickel (Ni) is then formed under the drain region 1, and the formed metal film is patterned to form the drain electrode 10.

[0049] Then, after performing a predetermined annealing or the like as necessary, a barrier metal layer 15 having three metal layers, for example, a Ti layer, a TiN layer, and a Ti layer, is formed by vacuum deposition, sputtering, a CVD method, etc. The barrier metal layer 15 is provided over the interlayer insulating film 8, the source regions 7a and 7b, and the base contact regions 12a and 12b.

[0050] Then, for example, an alloy film containing Al as a main component element is deposited on the barrier metal layer 15, and patterned into a predetermined shape by photolithography technology, etching technology, etc. to form the source electrode 9. Thereafter, a sintering process by annealing, etc. is performed. Through the above series of steps, the semiconductor device according to the embodiment of the present invention can be obtained.

[0051] According to the manufacturing method of a semiconductor device of an embodiment of the present invention, by providing a protective layer 11a and a conductive path forming layer 11b, a semiconductor device can be manufactured that can simultaneously protect the gate insulating film 5 at the bottom of the trench 4 and reduce the on-resistance.

[0052] In the manufacturing method of the semiconductor device according to the embodiment of the present invention, the protective layer 11a is formed longer than the width of the trench 4 so that both ends extend outward from the trench 4 by a certain width w. It is possible to align the length of the protective layer 11a with the length of the trench 4. However, in a manufacturing site of a semiconductor device where photolithography technology is frequently used, if the width of the protective layer 11a is set to the same value as the width of the trench 4, transfer misalignment caused by the current limit of alignment accuracy may not be avoided. If a portion where the protective layer 11a and the trench 4 do not overlap due to the transfer misalignment is formed, the gate insulating film 5 may not be sufficiently protected. In the semiconductor device according to the embodiment of the present invention, the width of the protective layer 11a is intentionally secured to be sufficiently longer than the width of the trench 4, so that the gate insulating film 5 at the bottom of the trench 4 is reliably protected even if a transfer misalignment occurs.

[0053] In the method for manufacturing a semiconductor device according to the embodiment of the present invention, the trench 4 is first excavated, and then ions are injected through the space inside the excavated trench 4 to form the conductive path forming layer 11b. This allows the ion implantation to be shallow and simple while suppressing an increase in processing energy. In addition, the conductive path forming layer 11b is formed shallowly just below the trench 4 so that the upper surface of the conductive path forming layer 11b contacts the lower surface of the gate insulating film 5, so that the ion implantation can be performed even more easily.

[0054] In the method for manufacturing a semiconductor device according to an embodiment of the present invention, each ion implantation is controlled so that the dose of the impurity element ion when forming the conductive path formation layer 11b is lower than the peak dose of the impurity element ion when forming the base regions 3a, 3b. Since ion implantation equipment that is widely used as existing manufacturing equipment can be used as is, the burden of new equipment investment can be suppressed and the semiconductor device according to the embodiment of the present invention can be manufactured.

[0055] Furthermore, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, the same first mask 16p is used in both the process for digging the trench 4 and the ion implantation process for forming the protective layer 11a. Since there is no need to change masks between the two processes, the manufacturing process can be simplified and the burden can be reduced.

[0056] In the manufacturing method of the semiconductor device according to the embodiment of the present invention, the protective layer 11a and the conductive path-forming layer 11b are formed by controlling the concentration and thickness t separately from the first under-contact base regions 13a, 13b located at the same depth as the protective conductive regions (11a, 11b). Therefore, the concentration and thickness of the impurity elements in the protective layer 11a and the conductive path-forming layer 11b can be formed with higher accuracy.

[0057] In the method for manufacturing a semiconductor device according to the embodiment of the present invention, the sidewall portion of trench 4 is protected by second mask 17p during ion implantation for conductive path-forming layer 11. This makes it possible to prevent quality degradation of channel regions 3a1, 3b1 of base regions 3a, 3b corresponding to the sidewall of trench 4.

[0058] -First modified example- Next, a method for manufacturing a semiconductor device according to a first modification of the embodiment of the present invention will be described with reference to FIGS. + 4H-SiC semiconductor substrate 1 sub A semiconductor substrate 1 is prepared by epitaxial growth. sub An n-type 4H—SiC semiconductor layer is epitaxially grown on top of the drift region 2 to form the drift region 2. Next, a first mask film 16 is deposited to a predetermined thickness on the upper surface of the drift region 2. As the first mask film 16, a SiO2 film or Si3N4 film formed by thermal oxidation or deposited by a CVD method or the like can be used. The process up to this point is the same as that described above with reference to FIG. 6.

[0059] Next, a photoresist film is applied onto the first mask film 16 by photolithography, etching, or the like, and the photoresist film is patterned. Then, as shown in Fig. 15, using the patterned photoresist film as a mask, a portion of the first mask film 16 located above the region where the trench 4 is to be formed is selectively removed to form a window portion. The window portion can be formed by an etching technique such as RIE.

[0060] After removing the photoresist film, impurity element ions such as Al are implanted into the drift region 2 by multi-stage ion implantation or the like using the first mask 16p with the window as an ion implantation mask. The protection layer-planned region 11a1 and the conductive path formation layer-planned region 11b3 are formed with different heights so that they have the same impurity element concentration by the implantation. The photoresist film used in etching the first mask coating 16 may be left on the drift region 2 without being removed, and used as an ion implantation mask together with the first mask 16p.

[0061] Next, as shown in FIG. sub The protective layer-planned region 11a1 and the conductive path-formation layer-planned region 11b3 are activated by vacuum annealing or the like to form a p-type protective layer 11a2 and a conductive path-formation layer 11b4 that will become protective conductive regions. The protective layer 11a2 and the conductive path-formation layer 11b4 are formed so that both ends extend outward by a certain width w beyond the groove width of the trench 4 that will be formed later.

[0062] 17, a first mask 16p having a window is continuously used to dig the drift region 2 by etching such as RIE to form a trench 4. The position of the trench 4 is controlled so that the distance between the position of the bottom surface and the position of the lower surface of the protective layer 11a2 is a predetermined thickness t.

[0063] Next, semiconductor substrate 1 subAfter cleaning and removing the first mask 16p, as shown in FIG. 18, an insulating film such as a SiO2 film is deposited on the surface of the drift region 2 including the inside of the trench 4 by thermal oxidation or the like. The deposited insulating film is then patterned by photolithography and dry etching techniques to form a gate insulating film 5. A doped polysilicon film doped with an n-type impurity element is then deposited on the entire upper surface of the drift region 2 by low-pressure CVD or the like. Thereafter, the doped polysilicon film is embedded inside the trench 4 by etch-back or chemical mechanical polishing (CMP) or the like to form a gate electrode 6.

[0064] Thereafter, the first contact under base regions 13a, 13b and the second contact under base regions 14a, 14b are provided in a predetermined pattern in this order in the region between the trenches 4 inside the drift region 2 using photolithography technology, etching technology, ion implantation technology, etc. Next, the base regions 3a, 3b are similarly provided in the region between the trenches 4 inside the drift region 2. When the base regions 3a, 3b are formed by implanting p-type impurity element ions such as Al, the ion implantation is performed so that the peak dose of the implanted ions is higher than the dose of the impurity element ions when the conductive path formation layer 11b is formed.

[0065] In other words, in the method for manufacturing a semiconductor device according to the first modified example of the embodiment of the present invention, the ion dose during the formation of the conductive path-forming layer 11b4 and the protective layer 11a2 is lower than the peak ion dose during the formation of the base regions 3a, 3b. By controlling the respective doses, the concentration of the impurity element during the formation of the conductive path-forming layer 11b4 is realized to be lower than the peak concentration of the impurity element in the channel regions 3a1, 3b1.

[0066] Thereafter, the base contact regions 12a, 12b and the source regions 7a, 7b are provided in a predetermined pattern inside the base regions 3a, 3b by using photolithography, etching, ion implantation, etc. Then, an interlayer insulating film 8 such as a SiO2 film is deposited over the gate electrode 6, the base contact regions 12a, 12b, and the source regions 7a, 7b by using a CVD method or the like. sub The bottom surface of the drain region 1 is thinned and flattened by CMP or the like to form the drain region 1. A metal film of Ni or the like is then formed under the drain region 1, and the formed metal film is patterned to form the drain electrode 10.

[0067] Then, after performing a predetermined annealing or the like as necessary, a barrier metal layer 15 having three metal layers, for example, a Ti layer, a TiN layer, and a Ti layer, is formed by vacuum deposition, sputtering, CVD, or the like. The barrier metal layer 15 is provided over the interlayer insulating film 8, the source regions 7a, 7b, and the base contact regions 12a, 12b. A nickel silicide layer (not shown) is provided between the barrier metal layer 15 and the source regions 7a, 7b and the base contact regions 12a, 12b.

[0068] Then, for example, an alloy film containing Al as a main component element is deposited on the barrier metal layer 15, and patterned into a predetermined shape by photolithography technology, etching technology, etc. to form the source electrode 9. Thereafter, a sintering process by annealing, etc. is performed. Through the above series of steps, the semiconductor device according to the embodiment of the present invention can be obtained.

[0069] According to the method for manufacturing a semiconductor device according to the first modified example of the embodiment of the present invention, by providing the protective layer 11a2 and the conductive path-forming layer 11b4, it is possible to manufacture a semiconductor device capable of both protecting the gate insulating film 5 at the bottom of the trench 4 and reducing the on-resistance. The protective layer 11a2 and the conductive path-forming layer 11b4 have the same concentration of impurity elements, but by making the concentration lower than that of the base regions 3a, 3b, for example, the conductive path-forming layer 11b4 at the bottom of the trench 4 can be inverted when on.

[0070] Furthermore, in the semiconductor device according to the first modified example of the embodiment of the present invention, the protective layer 11a2 and the conductive path formation layer 11b4 can be formed using the same mask, so that no transfer misalignment occurs.

[0071] -Second modified version- Next, a semiconductor device according to a modification of the embodiment of the present invention will be described with reference to Fig. 19 to Fig. 26. As in the semiconductor device according to the second modification shown in Fig. 19, the impurity element concentration inside the p-type conductive path forming layer (21b1-21b3) whose upper surface is provided in contact with the bottom of the trench 4 may be made different for each region along the width direction of the trench 4. The protective conductive region (21a, 21b1-21b3) of the semiconductor device according to the second modification has a two-layer structure made up of the protective layer 21a and the conductive path forming layer (21b1-21b3).

[0072] The conductive path formation layers (21b1 to 21b3) of the semiconductor device according to the second modification have a high concentration p + The central protection region 21b1 has a low concentration of p - The left conductive path forming region 21b2 and the right conductive path forming region 21b3 of the mold are provided with approximately the same thickness.

[0073] The central protection region 21b1 is provided on the protection layer 21a directly below the trench 4, and has approximately the same width as the groove width of the trench 4, and extends in the direction of the trench 4, which is the direction penetrating the paper on which the drawing is drawn. The impurity element concentration of the central protection region 21b1 is set so that the conductivity type is not inverted and the p-type is maintained even in the on state.

[0074] The left conductive path-forming region 21b2 has approximately the same thickness as the central protection region 21b1, and, like the central protection region 21b1, extends along the extension direction of the trench 4. The impurity element concentration of the left conductive path-forming region 21b2 is set to a low concentration that inverts the conductivity type to n-type in the on state.

[0075] The right-side conductive path-forming region 21b3 is provided so as to be symmetrical with the left-side conductive path-forming region 21b2 with respect to the central protection region 21b1. The impurity element concentration of the right-side conductive path-forming region 21b3 is set to a low concentration such that the conductivity type is inverted to n-type in the on-state, similar to the left-side conductive path-forming region 21b2. The structure of the semiconductor device according to the second modified example other than the conductive path-forming layers (21b1 to 21b3) is equivalent to the members of the same name in the semiconductor device according to the embodiment of the present invention shown in FIG. 1, and therefore a duplicated description will be omitted.

[0076] As shown in FIG. 20, in the semiconductor device according to the second modification, when a gate voltage is applied in the on-state, an inversion layer 21b1 is formed in the left-side conductive path-forming region 21b2, similarly to the channel regions 3a1 and 3b1. inv In addition, an inversion layer 21b2 is formed in the right-side conductive path forming region 21b3. inv is formed. inv and inversion layer 21b2 inv is an inversion layer 11b1 of the conductive path forming layer 11b in the semiconductor device shown in FIG. inv As in the case of L 1,I R 1 forms a conductive path.

[0077] In the semiconductor device according to the second modification, the main current I L 1,I R 1 flows from the bottom of the drift region 2 toward the channel regions 3a1 and 3b1. The main current I L 1,I R In the second modification, both ends of the conductive path-forming layers (21b1 to 21b3) are located at positions that interfere with the path of the main current I. In the second modification, the left conductive path-forming region 21b2 and the right conductive path-forming region 21b3, whose conductivity type is inverted when the main current I L 1,I R Since the electron 1 is guided to the side wall of the trench 4 and can pass through a shorter path, the on-resistance of the semiconductor device can be reduced.

[0078] In the first modification in which the concentration of impurity elements in the conductive path formation layers (21b1-21b3) decreases in the direction from the center to the outside, the high-concentration central protection region 21b1 can be disposed directly below the bottom of the trench 4. This can further improve protection of the gate insulating film 5 when the device is off. Other effects of the semiconductor device according to the second modification are similar to those of the semiconductor device according to the embodiment of the present invention shown in FIG.

[0079] -Third modified version- 21, the impurity element concentration inside the p-type conductive path-forming layer (31b1-31b5) whose upper surface is provided in contact with the bottom of the trench 4 may be varied in more stages than in the second modified example along the groove width direction of the trench 4. The protective conductive region (31a, 31b1-31b5) of the semiconductor device according to the third modified example has a two-layer structure consisting of the protective layer 31a and the conductive path-forming layer (31b1-31b5).

[0080] The conductive path-forming layer (31b1 to 31b5) of the semiconductor device according to the third modification has a central protection region 31b1 provided in the center, and a first left-side conductive path-forming region 31b2 provided on the left side of the central protection region 31b1 in contact with the central protection region 31b1. A second left-side conductive path-forming region 31b4 is provided next to the first left-side conductive path-forming region 31b2 on the side opposite to the central protection region 31b1 of the first left-side conductive path-forming region 31b2.

[0081] The conductive path-forming layer (31b1 to 31b5) also has a right-side first conductive path-forming region 31b3 provided on the right side of the central protection region 31b1 in contact with the central protection region 31b1. A right-side second conductive path-forming region 31b5 is provided next to the right-side first conductive path-forming region 31b3 on the side opposite to the central protection region 31b1 of the right-side first conductive path-forming region 31b3. The central protection region 31b1, the left-side first conductive path-forming region 31b2, the left-side second conductive path-forming region 31b4, the right-side first conductive path-forming region 31b3 and the right-side second conductive path-forming region 31b5 all have approximately the same thickness and the same conductivity type, that is, p-type.

[0082] The central protection region 31b1 is provided on the protection layer 31a directly below the trench 4, and has a width substantially equal to the groove width of the trench 4 and extends in the direction in which the trench 4 extends. The impurity element concentration of the central protection region 31b1 is high p + The type is set to be maintained.

[0083] The left first conductive path-forming region 31b2 and the left second conductive path-forming region 31b4 extend in the same direction as the trench 4, similar to the central protection region 31b1. The impurity element concentration of the left first conductive path-forming region 31b2 is set to a low concentration p-type such that the conductivity type is inverted to n-type in the on state. The impurity element concentration of the left second conductive path-forming region 31b4 is set to an even lower concentration p-type than that of the left first conductive path-forming region 31b2 such that the conductivity type is inverted to n-type in the on state. - Set to type It has been done.

[0084] The right-side first conductive path-forming region 31b3 and the right-side second conductive path-forming region 31b5 are provided symmetrically with the left-side first conductive path-forming region 31b2 and the left-side second conductive path-forming region 31b4 with respect to the central protection region 31b1. The impurity element concentrations of the right-side first conductive path-forming region 31b3 and the right-side second conductive path-forming region 31b5 are mirror-symmetric with the left-side first conductive path-forming region 31b2 and the left-side second conductive path-forming region 31b4, and are low-concentration p-type and p-type impurities. - The right-side first-conductive-path-forming region 31b3 and the right-side second-conductive-path-forming region 31b5 are also inverted in conductivity type to n-type in the on state, similar to the left-side first-conductive-path-forming region 31b2 and the left-side second-conductive-path-forming region 31b4. The structures of the semiconductor device according to the third modified example other than the conductive path-forming layers (31b1 to 31b5) are equivalent to the members of the same names in the semiconductor device shown in FIG. 1, and therefore repeated explanations will be omitted.

[0085] As shown in FIG. 22, in the semiconductor device according to the third modification, when a gate voltage is applied in the on-state, an inversion layer 31b2 is formed in the left first conductive path forming region 31b2, similarly to the channel regions 3a1 and 3b1. invIn addition, an inversion layer 31b4 is formed in the left second conductive path forming region 31b4. inv At the same time, an inversion layer 31b3 is formed in the right first conductive path forming region 31b3. inv However, an inversion layer 31b5 is formed in the right second conductive path forming region 31b5. inv are formed. inv , inversion layer 31b3 inv , inversion layer 31b4 in and inversion layer 31b5 inv is an inversion layer 11b1 of the conductive path forming layer 11b in the semiconductor device shown in FIG. inv As in the case of L 1,I R 1 forms a conductive path.

[0086] In the semiconductor device according to the third modification, the main current I L 1,I R 1 flows from the lower side of the drift region 2 toward the channel regions 3a1 and 3b1. The main current I L 1,I R In the second modified example, both ends of the conductive path-forming layers (31b1-31b5) are located at positions that interfere with the path of the first conductive path-forming region 31b2 on the left side and the second conductive path-forming region 31b4 on the left side of the conductive path-forming layers (31b1-31b5). Also, a first right side conductive path-forming region 31b3 on the right side and the second right side conductive path-forming region 31b5 on the right side of the conductive path-forming layers (31b1-31b5). The conductivity types of the first left side conductive path-forming region 31b2, the second left side conductive path-forming region 31b4, the first right side conductive path-forming region 31b3 and the second right side conductive path-forming region 31b5 are all inverted when on. Therefore, when on, the main current I L 1,I R Since the electron 1 is guided to the side wall of the trench 4 and can pass through a shorter path, the on-resistance of the semiconductor device can be reduced.

[0087] In the second modification in which the concentration of impurity elements in the conductive path formation layers (31b1-31b5) decreases in the direction from the center to the outside, the high-concentration central protection region 21b1 can be disposed directly below the bottom of the trench 4. Therefore, similar to the first modification, protection of the gate insulating film 5 during off-time can be further enhanced. Other effects of the semiconductor device according to the third modification are similar to those of the semiconductor device according to the embodiment of the present invention shown in FIG.

[0088] -Fourth Variation- In the second and third modified examples, the conductive path forming layer having a plurality of regions therein is set so that the impurity element concentration is highest in the central region corresponding to the center of the trench 4 and the concentration decreases along the direction from the center to the outside. However, as in the semiconductor device according to the fourth modified example shown in Fig. 23, the impurity element concentration inside the p-type conductive path forming layer (41b1, 41b2) whose upper surface is provided in contact with the bottom of the trench 4 may be made to vary along the depth direction of the trench 4. The protective conductive region (41a, 41b1, 41b2) of the semiconductor device according to the fourth modified example has a two-layer structure consisting of a protective layer 41a and a conductive path forming layer (41b1, 41b2).

[0089] The conductive path forming layers (41b1, 41b2) are composed of a p-type lower conductive path forming region 41b1 located below two layers provided on the protective layer 41a, and a low-concentration p - The lower conductive path forming region 41b1 has both ends protruding outward from the trench 4 and extends along the direction in which the trench 4 extends.

[0090] The impurity element concentration of the lower conductive path-forming region 41b1 is set to a low concentration such that the conductivity type is inverted to n-type in the on state. The upper conductive path-forming region 41b2 has approximately the same thickness as the lower conductive path-forming region 41b1, and extends along the extension direction of the trench 4 like the lower conductive path-forming region 41b1. The impurity element concentration of the upper conductive path-forming region 41b2 is set to an even lower concentration than that of the lower conductive path-forming region 41b1 such that the conductivity type is inverted to n-type in the on state. The structure of the semiconductor device according to the fourth modification other than the conductive path-forming layers (41b1, 41b2) is equivalent to the members of the same name in the semiconductor device shown in FIG. 1, so that repeated explanations will be omitted.

[0091] As shown in FIG. 24, in the semiconductor device according to the fourth modification, when a gate voltage is applied in the on-state, an inversion layer 41b1 is formed in the lower conductive path forming region 41b1, similarly to the channel regions 3a1 and 3b1. inv In addition, an inversion layer 41b2 is formed in the upper conductive path forming region 41b2. inv is formed. inv and inversion layer 41b2 inv is an inversion layer 11b1 of the conductive path forming layer 11b in the semiconductor device shown in FIG. inv As in the case of L 1,I R 1 forms a conductive path.

[0092] In the semiconductor device according to the fourth modification, the main current I L 1,I R The two ends of the conductive path forming layers (41b1, 41b2) are located at positions interfering with the path of the main current I L 1,I R The main current I1 flows from the lower side of the drift region 2 toward the channel regions 3a1 and 3b1. In the fourth modification, a lower conductive path forming region 41b1 and an upper conductive path forming region 41b2, whose conductivity type is inverted when the transistor is turned on, are provided at both ends of the conductive path forming layer (41b1, 41b2). L 1,I R Since the electron 1 is guided to the side wall of the trench 4 and can pass through a shorter path, the on-resistance of the semiconductor device can be reduced.

[0093] In addition, the concentration of the impurity element in the conductive path forming layer (41b1, 41b2) becomes higher from the position contacting the bottom of the trench 4 toward the lower side, so that it is possible to increase the concentration of the entire p-type semiconductor region located on the side below the trench 4. Therefore, the protection of the gate insulating film 5 at the off time can be further strengthened. Other effects of the semiconductor device according to the fourth modification are the same as those of the semiconductor device according to the embodiment of the present invention shown in FIG. 1. The structure of the conductive path forming layer, the inside of which is divided into multiple parts in the vertical direction, is not limited to the two-layer structure shown in the fourth modification. It is also possible to realize a conductive path forming layer with multiple regions of three or more layers, in which the impurity element concentration of each region becomes higher as the position becomes deeper.

[0094] -Fifth Variation- 25, the overhang width of the protective layer 51a and the overhang width of the conductive path forming layer 51b may be equal, and the outer edge of the cross-sectional shape of the protective conductive region (51a, 51b) consisting of the protective layer 51a and the conductive path forming layer 51b may be rectangular. The impurity element concentration of the conductive path forming layer 51b may be a low concentration p-type that inverts the conductivity type to n-type in the on-state. - The structures of the semiconductor device according to the fifth modification, other than the conductive path formation layer 51b, are equivalent to the members of the same names in the semiconductor device shown in FIG.

[0095] As shown in FIG. 26, in the semiconductor device according to the fifth modification, when a gate voltage is applied in the on-state, an inversion layer 51b is formed in the conductive path-forming layer 51b in the same manner as in the channel regions 3a1 and 3b1. inv is formed. Inversion layer 51b inv is the inversion layer 11b of the conductive path forming layer 11b in the semiconductor device shown in FIG. inv As in the case of L 2,I R 2 is the conducting Make a road.

[0096] In the semiconductor device according to the fifth modification, the main current I L2,I R The two ends of the conductive path forming layer 51b are located at positions where they interfere with the path of the main current I L 2,I R In the case of the fifth modification, when the transistor is turned on, the inversion layer 51b includes both ends of the conductive path forming layer 51b. inv Therefore, the main current I L 2,I R Since the current 2 is guided to the side wall of the trench 4 and can pass through a shorter path, the on-resistance of the semiconductor device can be reduced. Other effects of the semiconductor device according to the fifth modification are similar to those of the semiconductor device according to the embodiment of the present invention shown in FIG.

[0097] In addition, as in the semiconductor device according to the fifth modification, the main current I L 1,I R As long as an inversion layer is formed at a position interfering with the path through which 1 flows when turned on, the overall shape of the protective conduction region is not limited to one having stepped ends and can be modified as appropriate.

[0098] <Other embodiments> Although the present invention has been described by the above disclosed embodiment, the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. It should be considered that various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art from this disclosure.

[0099] The structure of the semiconductor device according to the present invention is not limited to the above, and can be appropriately changed according to the desired specifications. For example, in addition to the structure of the semiconductor device shown in FIG. 1, a high-concentration n-type region can be provided as a counter-doped layer below the base regions 3a, 3b inside the drift region 2 at a depth including the protective conductive regions (11a, 11b). By providing the high-concentration counter-doped layer, electric field concentration is intentionally generated not on the trench 4 side but on the counter-doped layer to induce an avalanche current, thereby further strengthening the protection of the gate insulating film 5 at the bottom of the trench 4. When the high-concentration n-type region is provided, the concentration of the p-type impurity element added is set to a value equal to or higher than the concentration of the impurity element in the high-concentration n-type region so that the conductive path forming layer 11b can maintain the p-type when it is off.

[0100] Furthermore, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, when forming conductive path-forming layer 11b by ion implantation, the region of second mask film 17 corresponding to the bottom of trench 4 is removed. However, the present invention is not limited to this, and it is also possible to form conductive path-forming layer 11b by performing ion implantation while leaving the region corresponding to the bottom of trench 4 in place without removing it. By eliminating the step of partially removing second mask film 17, the manufacturing process can be simplified.

[0101] In the method for manufacturing a semiconductor device according to the embodiment of the present invention, as shown in FIG. 7 and FIG. 12, the protective layer 11a and the conductive path forming layer 11b are formed by vertical ion implantation. However, in the present invention, the ion implantation direction is not limited to the vertical direction, and oblique ion implantation can also be performed. For example, even if the diffusion coefficient of impurities in SiC is very small and the planned protrusion widths of the protective layer 11a and the conductive path forming layer 11b cannot be sufficiently achieved by vertical ion implantation alone, the desired protrusion width can be achieved by oblique ion implantation. In addition, when performing oblique ion implantation, the sidewall of the trench is protected by a mask or the like to prevent ion irradiation to the sidewall portion, and quality deterioration can be suppressed.

[0102] In addition, for example, during diffusion in forming the protective layer 11a or the conductive path forming layer 11b, the diffusion can be promoted by photoexcitation effect by irradiating ultraviolet light from an excimer laser or the like at an inclination angle similar to that in the case of oblique ion implantation. Promotion of diffusion by photoexcitation effect or the like is effective in cases where the diffusion coefficient of impurities in SiC is so small that the protective layer 11a and the conductive path forming layer 11b cannot be sufficiently diffused by heat treatment alone.

[0103] In the method for manufacturing a semiconductor device according to the embodiment of the present invention, the base regions 3a, 3b are formed by ion implantation, but the method is not limited to ion implantation and they can be formed by epitaxial growth, etc. In the case of epitaxial growth, the doping epi concentration in the channel region of the base region is adjusted to be higher than the concentration of the impurity element ions in the conductive path-forming layer, and a low concentration is realized so that an inversion layer is formed when the conductive path-forming layer is on.

[0104] The semiconductor device according to the present invention can also be realized by partially combining the structures of the semiconductor devices shown in Figures 1 to 26. As described above, the present invention includes various embodiments not described above, and the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0105] 1 Drain region 1 sub Semiconductor Substrate 2. Drift Region 3a, 3b Base region 3a1,3b1 Channel region 4. Trench 5 Gate insulating film 6 Gate electrode 7a,7b Source region 8 Interlayer insulating film 9 Source Electrode 10 Drain electrode 11a,11a2 Protective layer 11a0, 11a1 Protective layer area 11b,11b4 Conductive path forming layer 11b0, 11b3 Conductive path forming layer planned area 11b1 First conductive path formation area 11b1 inv Inversion Layer 11b2 Second conductive path forming area 11b2 inv Inversion Layer 11b inv Inversion Layer 11c Central protection area 11z protective layer 12a, 12b Base contact region 13a, 13b First contact lower base region 14a, 14b Second contact lower base region 15 Barrier metal layer 16 First mask coating 16p 1st Mask 17 Second mask membrane 17p 2nd Mask 21a Protective layer 21b1 Central protection area 21b1 inv Inversion Layer 21b2 Left side conductive path formation area 21b2 inv Inversion Layer 21b3 Right side conductive path formation area 31a Protective layer 31b1 Central protection area 31b2 Left side first conductive path formation area 31b2 inv Inversion Layer 31b3 Right side first conductive path formation area 31b3 inv Inversion Layer 31b4 Left side second conductive path formation area 31b4 inv Inversion Layer 31b5 Second conductive path formation area on the right side 31b5 inv Inversion Layer 41a Protective layer 41b1 Lower conductive path formation area 41b2 Upper conductive path formation area 41b1 inv Inversion Layer 41b2 inv Inversion Layer 51a Protective layer 51b Conductive path forming layer 51b inv Inversion Layer I L 1,I R 1 Main current I L 2,I R 2 Main current I L z,I R z Main current d Thickness w width

Claims

1. A semiconductor device comprising: a trench including an extension portion extending in a first direction, the extension portion being arranged in a second direction at intervals; an insulating film provided inside the trench; and a p-type protection region provided under the trench, the p-type protection region including a first protection layer and a second protection layer, a first main electrode region of a first conductivity type including a portion provided along a sidewall of a first trench, the first trench being one of the trenches; a base region of a second conductivity type provided under the first main electrode region; Further comprising: In a depth direction, a concentration of an impurity element in the second protective layer provided between the first protective layer and a bottom portion of the first trench is lower than a peak concentration of an impurity element in a first region of the base region along a sidewall of the first trench; The first protective layer has a higher concentration of an impurity element than the base region. Semiconductor device.

2. The peak concentration is 3×10 17 cm -3 ~4×10 17 cm -3 is The semiconductor device according to claim 1 .

3. The first protective layer has a cross-sectional shape in which the width in the second direction is greater than that of the second protective layer.

3. The semiconductor device according to claim 1 or 2.

4. The first protective layer and the second protective layer have a cross-sectional shape that is provided to an outer side than a bottom of the first trench in the second direction. The semiconductor device according to claim 1 .

5. The protection area is composed of three or more layers, The second protective layer is provided in contact with a bottom portion of the first trench. The semiconductor device according to claim 1 .

6. A semiconductor device comprising: a trench including an extension portion extending in a first direction, the extension portion being arranged in a second direction at intervals; an insulating film provided inside the trench; and a p-type protection region provided under the trench, the p-type protection region including a first protection layer and a second protection layer, a first main electrode region of a first conductivity type including a portion provided along a sidewall of a first trench, the first trench being one of the trenches; a base region of a second conductivity type provided under the first main electrode region; Further comprising: The protection area is composed of three or more layers, The second protective layer is provided in contact with a bottom portion of the first trench. Semiconductor device.

7. the protective region includes a third protective layer below the second protective layer, the third protective layer having a higher concentration of an impurity element than the second protective layer; The first protective layer is provided under the third protective layer and has a higher concentration of an impurity element than the third protective layer.

7. The semiconductor device according to claim 5.

8. The concentration of the impurity element in the second protective layer is 8.0×10 15 cm -3 That's all. The semiconductor device according to claim 1 .

9. a second trench, the second trench being adjacent to the first trench; a p-type base contact region provided between the first trench and the second trench; Equipped with The base contact region has a higher concentration of an impurity element than the base region and the second protective layer. The semiconductor device according to claim 1 .

10. a polysilicon film electrode is provided on the inside of the insulating film; The semiconductor device is a trench type SiC-MOSFET. The semiconductor device according to claim 1 .

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