Semiconductor device

Abstract

To make a semiconductor device compact.SOLUTION: A semiconductor device 10 includes: a body region 42 formed on a drift region 40; a body contact region 48 formed on the body region 42; a gate trench 14 formed penetrating both the body region 42 and body contact region 48 to reach the drift region 40, and including a side wall 14A and a bottom wall 14B; a gate electrode 50 arranged in the gate trench 14; a sound region 44 formed along a part of the side wall 14A and contacting both the body region 42 and body contact region 48; and source wiring 28 arranged straddling both the gate trench 14 and body region 42 in plan view. The source region 44 includes a source contact region 46 contacting the source wiring 28. The source wiring 28 contacts both a side face of the source contact region 46 and a front surface 48A of the body contact region 48.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a metal insulator semiconductor field effect transistor (MISFET) having a split gate structure.

[0003] The MISFET of Patent Document 1 includes a contact trench that penetrates a source region between multiple trenches in a semiconductor layer and reaches a body region, a contact region formed on a bottom wall of the contact trench, and a source contact embedded in the contact trench. A source wiring of this MISFET is electrically connected to the source contact. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2022-146898 A

[0005] [overview] However, when a contact trench is formed between a plurality of trenches in a semiconductor layer, it is difficult to arrange the plurality of trenches close to each other, which makes it difficult to miniaturize the semiconductor device.

[0006] A semiconductor device according to one aspect of the present disclosure includes a drift region, a body region formed on the drift region, a body contact region formed on the body region, a gate trench formed to penetrate both the body region and the body contact region to reach the drift region and including a sidewall and a bottom wall, an insulating layer formed in the gate trench, a gate electrode disposed in the gate trench and separated from the sidewall by the insulating layer, a source region formed along a portion of the sidewall and in contact with both the body region and the body contact region, and a source wiring disposed across both the gate trench and the body region when viewed in a depth direction of the gate trench, wherein the source region includes a source contact region in contact with the source wiring, and the source wiring is in contact with both a side surface of the source contact region and a surface of the body contact region. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line F2-F2 in FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view showing an enlarged view of one gate trench and its periphery in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an enlarged mesa region and its periphery in FIG. [Diagram 5] 5A to 5C are schematic cross-sectional views illustrating an exemplary manufacturing process of a semiconductor device according to an embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view of an exemplary semiconductor device according to a modified example. [Figure 22] FIG. 22 is a schematic cross-sectional view of an exemplary semiconductor device according to a modified example.

[0008] [Detailed Description] Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] [Plane structure of semiconductor device] The planar structure of a semiconductor device according to one embodiment will be described with reference to FIG. Fig. 1 shows a schematic planar structure of an exemplary semiconductor device 10 according to one embodiment. Note that the term "planar view" used in the present disclosure refers to viewing the semiconductor device 10 in the Z direction of the mutually orthogonal XYZ axes shown in Fig. 1. Unless otherwise expressly stated, "planar view" refers to viewing the semiconductor device 10 from above along the Z axis.

[0011] The semiconductor device 10 is, for example, a MISFET having a split gate structure. The semiconductor device 10 includes a semiconductor layer 12, a gate trench 14 formed in the semiconductor layer 12, and an insulating layer 16 formed in the gate trench 14.

[0012] The semiconductor layer 12 can be formed of, for example, silicon (Si). The semiconductor layer 12 includes a first surface 12A and a second surface 12B (see FIG. 2) opposite to the first surface 12A, and has a thickness in a direction perpendicular to the first surface 12A (Z direction). In other words, the Z direction can be said to be the "thickness direction of the semiconductor layer 12."

[0013] The gate trench 14 has an opening in the second surface 12B of the semiconductor layer 12, and has a depth in the Z direction. Therefore, it can be said that the gate trench 14 is formed in the second surface 12B. Furthermore, the gate trench 14 extends in the Y direction in a plan view, and has a width in the X direction. In this specification, the Z direction is also referred to as the "depth direction of the gate trench 14," and the X direction is also referred to as the "width direction of the gate trench 14."

[0014] The semiconductor device 10 includes a plurality of gate trenches 14 (four in the example of FIG. 1). The plurality of gate trenches 14 may be aligned in a stripe shape. In one example, the plurality of gate trenches 14 may be arranged at equal intervals in the X direction in a plan view. A gate electrode 50 and a field plate electrode 52, which will be described later with reference to FIG. 2, may be disposed in the gate trenches 14. Each gate trench 14 has a first end 14P and a second end 14Q as both ends in the Y direction. Here, the field plate electrode 52 is an example of a "buried electrode."

[0015] The semiconductor device 10 may further include a peripheral trench 18 formed in the semiconductor layer 12. The peripheral trench 18 can be formed to be spaced apart from the gate trenches 14 and to surround the gate trenches 14 in a plan view. In the example shown in Fig. 1, the peripheral trench 18 is formed in a rectangular frame shape with the X direction being the short side direction and the Y direction being the long side direction. A peripheral electrode (not shown) formed along the shape of the peripheral trench 18 can be disposed in the peripheral trench 18.

[0016] As shown in FIG. 1, the second surface 12B of the semiconductor layer 12 is an n-type impurity-containing - A p-type region 20 and a p-type region - A p-type region 22 and a p-type region + A region 24 containing n-type impurities + and a mold region 25. - The mold region 20 may surround the peripheral trench 18. - type region 22, p + Type region 24, and n + The type region 25 may be surrounded by a peripheral trench 18. - Type region 20 and p - type region 22, p + Type region 24, and n + The mold region 25 is defined by a peripheral trench 18 .

[0017] p - Type 22 and p +The mold regions 24 are arranged side by side in the Y direction. - A plurality of mold regions 22 (two in the example of FIG. 1) may be provided. - The type region 22 is, for example, p + The mold region 24 is provided on both sides in the Y direction. + The mold region 24 has two p - It can be located between the mold areas 22.

[0018] n + The type region 25 is p + It is arranged at a position overlapping with the mold region 24. + The mold region 25 has a shape of p + It is disposed closer to the first surface 12A than the mold region 24. + A plurality of mold regions 25 are formed. + The mold regions 25 are arranged apart from each other in the X direction. In the example shown in FIG. + The mold regions 25 extend along the Y direction on both sides in the X direction of each gate trench 14 .

[0019] Each gate trench 14 is p - Type 22 and p + The first end 14P of the gate trench 14 can be disposed adjacent to both of the p-type regions 25. - The second end 14Q of the gate trench 14 may be adjacent to one of the p-type regions 22. - The middle portion of the gate trench 14 may be adjacent to the remaining one of the p + It may be adjacent to the mold area 24 .

[0020] The insulating layer 16 is formed on the p-type second surface 12B of the semiconductor layer 12. + The insulating layer 16 covers the region other than the region 24, and is embedded in the gate trench 14 and the peripheral trench 18. The insulating layer 16 is a layer that insulates the gate electrode 50 and the field plate electrode 52 from the semiconductor layer 12.

[0021] The semiconductor device 10 may further include a gate wiring 26 and a source wiring 28 formed on the insulating layer 16. Each of the gate wiring 26 and the source wiring 28 may be disposed so as to cover a part of the gate trench 14 and a part of the peripheral trench 18. The gate wiring 26 may include two p - The source wiring 28 can be disposed so as to at least partially overlap one of the p-type regions 22. - The source wiring 28 can be disposed so as to at least partially overlap the other of the two type regions 22. The source wiring 28 can be disposed so as to be spaced apart from the gate wiring 26 and at least + It may cover the entire mould area 24 .

[0022] The gate wiring 26 and the source wiring 28 can be formed from a material including at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a Cu alloy, and an Al alloy.

[0023] The semiconductor device 10 may further include a plurality of gate contact portions 30. Each gate contact portion 30 may connect a gate electrode 50 (see FIG. 2) disposed in each gate trench 14 to the gate wiring 26. The gate contact portion 30 may extend in the Z direction so as to penetrate the insulating layer 16 located between the gate electrode 50 and the gate wiring 26. The gate contact portion 30 may be disposed in a region where the gate trench 14 and the gate wiring 26 overlap in a plan view. More specifically, the gate contact portion 30 may be disposed in a region where the first end 14P of the gate trench 14 and the gate wiring 26 overlap in a plan view.

[0024] The semiconductor device 10 may further include a plurality of source contact portions 32. Each source contact portion 32 may connect a field plate electrode 52 disposed in each gate trench 14 to the source wiring 28. The source contact portion 32 may extend in the Z direction so as to penetrate the insulating layer 16 located between the field plate electrode 52 and the source wiring 28. The source contact portion 32 may be disposed in a region where the gate trench 14 and the source wiring 28 overlap in a plan view. More specifically, the source contact portion 32 may be disposed in a region where the second end 14Q of the gate trench 14 and the source wiring 28 overlap in a plan view.

[0025] The semiconductor device 10 may further include one or more contact parts 34 that connect a peripheral electrode (not shown) arranged in the peripheral trench 18 to the source wiring 28. The number and positions of the contact parts 34 are not limited to the example shown in FIG. 1 and can be changed arbitrarily.

[0026] The gate contact portion 30, the source contact portion 32, and the contact portion 34 may be formed of any metallic material. In one example, each of the contact portions 30, 32, and 34 may be formed of a material including at least one of tungsten (W), Ti, and titanium nitride (TiN).

[0027] [Cross-sectional structure of semiconductor device] The cross-sectional structure of the semiconductor device 10 will be described with reference to FIGS. Fig. 2 shows a schematic cross-sectional structure of the semiconductor device 10 of Fig. 1 taken along line F2-F2. Fig. 3 shows a schematic cross-sectional structure of one gate trench 14 and its periphery in Fig. 2 in an enlarged manner. Fig. 4 shows a schematic cross-sectional structure of the opening of the gate trench 14 of Fig. 3 and its periphery in an enlarged manner.

[0028] The semiconductor layer 12 may include a semiconductor substrate 36 including the first surface 12A of the semiconductor layer 12, and an epitaxial layer 38 formed on the semiconductor substrate 36 and including the second surface 12B of the semiconductor layer 12. The semiconductor substrate 36 may be formed of a material including Si. In one example, the semiconductor substrate 36 may be a Si substrate. The semiconductor substrate 36 may correspond to a drain region of the MISFET. For this reason, the semiconductor substrate 36 may be referred to as a "drain region 36". The epitaxial layer 38 may be a Si layer epitaxially grown on the Si substrate. The epitaxial layer 38 may include a drift region 40, a body region 42 formed on the drift region 40, and a source region 44 formed in a part of the body region 42.

[0029] The drain region 36 (semiconductor substrate 36) is an n-type + The n-type impurity concentration of the drain region 36 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The drain region 36 may have a thickness of, for example, 50 μm to 450 μm.

[0030] The drift region 40 has a lower concentration of n-type impurities than the drain region 36. - The n-type impurity concentration of the drift region 40 may be, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 40 may have a thickness of, for example, 1 μm to 25 μm.

[0031] The body region 42 is a p - The p-type impurity concentration of the body region 42 may be, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The body region 42 may have a thickness of, for example, not less than 0.5 μm and not more than 1.5 μm.

[0032] The source region 44 has a higher concentration of n-type impurities than the drift region 40. + The source region 44 may be an n-type region. The impurity concentration of the source region 44 may be higher than the impurity concentration of the body region 42. The n-type impurity concentration of the source region 44 may be, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 44 can be the n + 4. The source region 44 corresponds to the type region 25. In other words, the dimension of the source region 44 in the Y direction is smaller than the dimension of the gate trench 14 in the Y direction.

[0033] The body contact region 48 may include the second surface 12B of the semiconductor layer 12. The surface 48A (second surface 12B) of the body contact region 48 may be the p + The body contact region 48 corresponds to the type region 24. That is, the dimension in the Y direction of the body contact region 48 is smaller than the dimension in the Y direction of the gate trench 14. The dimension in the Y direction of the body contact region 48 is equal to the dimension in the Y direction of the source region 44.

[0034] The body contact region 48 is a p + The body contact region 48 may be a p-type region. The body contact region 48 is formed in a surface region of the body region 42. More specifically, the body contact region 48 is formed in the body region 42 between two gate trenches 14 adjacent to each other in the X direction. The p-type impurity concentration of the body contact region 48 is higher than that of the body region 42, and may be, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 It can be as follows:

[0035] In the present disclosure, n-type is also referred to as a first conductive type, and p-type is also referred to as a second conductive type. The n-type impurity may be, for example, phosphorus (P), arsenic (As), etc. The p-type impurity may be, for example, boron (B), aluminum (Al), etc.

[0036] The gate trench 14 has a sidewall 14A and a bottom wall 14B, and the bottom wall 14B is adjacent to the drift region 40. That is, the gate trench 14 penetrates the body region 42 of the semiconductor layer 12 to reach the drift region 40. The depth of the gate trench 14 may be, for example, 1 μm or more and 10 μm or less. The depth of the gate trench 14 can be defined as the distance in the Z direction from the second surface 12B of the semiconductor layer 12 to the bottom wall 14B of the gate trench 14 (the deepest part of the gate trench 14 when the bottom wall 14B is curved). Here, the Z direction corresponds to the "depth direction of the gate trench 14 (trench)".

[0037] The sidewall 14A of the gate trench 14 may be inclined with respect to the Z direction so that the width of the gate trench 14 decreases toward the bottom wall 14B. The sidewall 14A may extend in a direction (Z direction) perpendicular to the second surface 12B of the semiconductor layer 12. In the example shown in FIG. 2, the bottom wall 14B of the gate trench 14 includes a flat portion formed in the center in the X direction and curved portions formed on both sides of the flat portion in the X direction. The curved portions are portions that connect the flat portion and the sidewall 14A. The configuration of the bottom wall 14B can be changed arbitrarily, and may be entirely composed of flat portions or entirely composed of curved portions, for example.

[0038] The semiconductor device 10 may further include a gate electrode 50 disposed in the gate trench 14, and a field plate electrode 52 disposed in the gate trench 14 and spaced downward from the gate electrode 50 in the Z direction.

[0039] 3, the field plate electrode 52 includes an opposing surface 52A opposing the gate electrode 50 via the insulating layer 16, a bottom surface 52B opposing the bottom wall 14B of the gate trench 14 via the insulating layer 16, and a side surface 52C connecting the opposing surface 52A and the bottom surface 52B. The opposing surface 52A of the field plate electrode 52 is located closer to the bottom wall 14B of the gate trench 14 than the gate electrode 50 in the Z direction.

[0040] The gate electrode 50 may include a bottom surface 50A at least a part of which faces the facing surface 52A of the field plate electrode 52, a surface 50B opposite the bottom surface 50A, and a side surface 50C connecting the bottom surface 50A and the surface 50B. At least a part of the bottom surface 50A of the gate electrode 50 may face the facing surface 52A of the field plate electrode 52 in the Z direction. In one example, the surface 50B of the gate electrode 50 is located closer to the bottom wall 14B of the gate trench 14 than the second surface 12B of the semiconductor layer 12, for example.

[0041] The gate electrode 50 is disposed closer to the second surface 12B than the interface 41 between the body region 42 and the drift region 40. More specifically, a bottom surface 50A of the gate electrode 50 is disposed closer to the second surface 12B than the interface 41. The bottom surface 50A may be at the same position as the interface 41 in the Z direction, or may be closer to the bottom wall 14B than the interface 41.

[0042] The gate electrode 50 includes a bottom recess 51A and a surface recess 51B. The bottom recess 51A is recessed from the bottom 50A to the surface 50B at the center of the gate electrode 50 in the X direction. In other words, the bottom recess 51A opens toward the field plate electrode 52. The surface recess 51B is recessed from the surface 50B to the bottom 50A at the center of the gate electrode 50 in the X direction. The gate electrode 50 may have a width that decreases from the surface 50B to the bottom 50A, as shown in FIG. 3. In another example, the gate electrode 50 may have a substantially uniform width (dimension in the X direction).

[0043] The insulating layer 16 can be interposed between the gate electrode 50 and the semiconductor layer 12 to cover the sidewall 14A of the gate trench 14. The gate electrode 50 faces the semiconductor layer 12 in the X direction via the insulating layer 16. In other words, the gate electrode 50 is separated from the sidewall 14A by the insulating layer 16. When a predetermined voltage is applied to the gate electrode 50, the insulating layer 16 and the adjacent p - A channel is formed in the body region 42 of the n-type semiconductor device 10. + The source region 44 and n- The flow of electrons in the Z direction to and from the drift region 40 of the mold can be controlled.

[0044] The gate electrode 50 is disposed closer to the body region 42 than the drift region 40. In one example, the gate electrode 50 may be located such that its bottom surface 50A is not closer to the bottom wall 14B of the gate trench 14 in the Z direction than the interface 41 between the drift region 40 and the body region 42. In one example, the gate electrode 50 may be disposed such that its bottom surface 50A is at the same position in the Z direction as the interface 41 between the drift region 40 and the body region 42. In another example, the gate electrode 50 may be disposed such that its bottom surface 50A is closer to the second surface 12B of the semiconductor layer 12 than the interface 41 between the drift region 40 and the body region 42.

[0045] The field plate electrode 52 is disposed in the gate trench 14 between the bottom surface 50A of the gate electrode 50 and the bottom wall 14B of the gate trench 14. The field plate electrode 52 can be at the same potential as the source region 44. By applying a source voltage to the field plate electrode 52, the electric field concentration in the gate trench 14 is alleviated, so that the breakdown voltage of the semiconductor device 10 can be improved. The field plate electrode 52 is formed in a substantially rectangular shape with the Z direction being the length direction (longitudinal direction) and the X direction being the width direction (short direction) in the cross-sectional view of FIG. 3. In the example shown in FIG. 3, the field plate electrode 52 is formed in a tapered shape tapering from the opposing surface 52A toward the bottom surface 52B. The gate electrode 50 and the field plate electrode 52 can be formed of, for example, conductive polysilicon.

[0046] 2, the semiconductor device 10 may further include a drain electrode 54 formed on the first surface 12A of the semiconductor layer 12. The drain electrode 54 is electrically connected to the drain region 36. The drain electrode 54 may be formed of a material including at least one of Ti, Ni, Au, Ag, Cu, Al, a Cu alloy, and an Al alloy.

[0047] [Gate trench opening and surrounding structure] Next, the opening of the gate trench 14 and the surrounding structure will be described in more detail with reference to Figures 3 and 4. Please refer mainly to Figure 4 for the dimensional relationship between the components.

[0048] 3, the body region 42 is formed in a surface region (mesa region 60) of the semiconductor layer 12 in a region between two gate trenches 14 adjacent to each other in the X direction. The body contact region 48 is formed on the body region 42. The body contact region 48 is formed over the entire mesa region 60 in the X direction in the second surface 12B of the semiconductor layer 12. For this reason, it can be said that the body contact region 48 is also formed on the sidewall 14A of the gate trench 14. The body contact region 48 is formed in one of both end portions of the sidewall 14A of the gate trench 14 in the Z direction that is closer to the second surface 12B.

[0049] The entire surface 48A (second surface 12B) of the body contact region 48 is formed as a flat surface without any holes. In other words, the mesa region 60 does not have any holes extending in the Z direction from the surface 48A (second surface 12B) of the body contact region 48. It can be said that the body contact region 48 is formed on the body region 42. In one example, the surface 48A of the body contact region 48 is formed by a plane (XY plane) perpendicular to the Z direction. The depth dimension H2 of the body contact region 48 is smaller than the depth dimension H1 of the body region 42. The depth dimension H2 is ⅕ or less of the depth dimension H1.

[0050] The source region 44 is formed along a part of the sidewall 14A of the gate trench 14. That is, the source region 44 is formed at a position overlapping with the body contact region 48 in a plan view. The source region 44 is in contact with both the body region 42 and the body contact region 48. It can also be said that the source region 44 is formed in the mesa region 60.

[0051] The width dimension W1 of the source region 44 is smaller than 1 / 2 of the width dimension W2 of the body contact region 48. In one example, the width dimension W1 is 1 / 4 or less of the width dimension W2. In one example, the width dimension W1 is 1 / 10 or more of the width dimension W2. The width dimension W1 of the source region 44 is smaller than the depth dimension H3 of the source region 44. In this embodiment, since the body contact region 48 is formed over the entire mesa region 60 in the X direction, the width dimension W2 of the body contact region 48 is equal to the width dimension of the mesa region 60. Therefore, it can be said that the width dimension W1 of the source region 44 is smaller than 1 / 2 of the width dimension of the mesa region 60.

[0052] The source region 44 includes a source contact region 46 in contact with the source wiring 28. The source contact region 46 is a region of the source region 44 that is exposed from the insulating layer 16. The source contact region 46 is formed at one of both ends of the source region 44 in the Z direction that is closer to the second face 12B. Therefore, the source contact region 46 is in contact with the body contact region 48 in the Z direction. In addition, the source contact region 46 is in contact with the body region 42 in the X direction. A depth dimension H4 of the source contact region 46 is equal to or smaller than ½ of a depth dimension H3 of the source region 44.

[0053] The gate electrode 50 is disposed closer to the bottom wall 14B of the gate trench 14 in the Z direction than the body contact region 48. In one example, the surface 50B of the gate electrode 50 is located closer to the bottom wall 14B than the body contact region 48. In other words, the surface 50B of the gate electrode 50 is disposed at a position separated from the body contact region 48 in the Z direction.

[0054] The surface 50B of the gate electrode 50 may be located at the same position as the lower edge of the source region 44 in the Z direction. The lower edge of the source region 44 is the edge of the source region 44 that is farthest from the body contact region 48 in the Z direction. It can also be said that the lower edge of the source region 44 is the edge that is closer to the bottom wall 14B of the gate trench 14, among both ends of the source region 44 in the Z direction. The surface 50B of the gate electrode 50 may be closer to the bottom wall 14B or closer to the second surface 12B than the lower edge of the source region 44 in the Z direction.

[0055] The insulating layer 16 includes a first insulating layer 56 covering the side surface 50C of the gate electrode 50 and the area between the gate electrode 50 and the bottom wall 14B of the gate trench 14, and a second insulating layer 58 formed on the gate electrode 50. The first insulating layer 56 and the second insulating layer 58 are integrated to surround the gate electrode 50. The first insulating layer 56 and the second insulating layer 58 may be formed of the same insulating material, or may be formed of different insulating materials. The first insulating layer 56 and the second insulating layer 58 may be formed of an insulating material including, for example, silicon oxide (SiO) and silicon nitride (SiN). In one example, both the first insulating layer 56 and the second insulating layer 58 are formed of a SiO2 film.

[0056] The second insulating layer 58 covers the surface 50B of the gate electrode 50. The second insulating layer 58 is in contact with the surface 50B of the gate electrode 50 and a part of the sidewall 14A of the gate trench 14 in the Z direction. The second insulating layer 58 includes a surface 58A on the opposite side to the gate electrode 50. This surface 58A is disposed closer to the gate electrode 50 than the surface 48A (second surface 12B) of the body contact region 48. The surface 58A is disposed at the same position as the lower edge of the source contact region 46 in the Z direction. That is, the second insulating layer 58 covers a part of the source region 44, but does not cover the source contact region 46. Therefore, the source contact region 46 is exposed from the insulating layer 16. It can be said that the source contact region 46 is a region of the source region 44 that protrudes from the surface 58A of the second insulating layer 58 toward the second surface 12B in the Z direction. In addition, the body contact region 48 is not covered by the insulating layer 16. That is, the body contact region 48 is exposed from the insulating layer 16.

[0057] 3, a source wiring 28 is formed on the insulating layer 16. The source wiring 28 is disposed across both the gate trench 14 and the body region 42 in a plan view. The source wiring 28 is electrically connected to both the source contact region 46 and the body contact region 48.

[0058] The source interconnect 28 includes an interconnect body 28A and a contact plug 28B. In one example, the interconnect body 28A and the contact plug 28B are integrated together. Note that the interconnect body 28A and the contact plug 28B may be formed as separate bodies.

[0059] The wiring body 28A is a part of the source wiring 28 formed on the second surface 12B of the semiconductor layer 12. The wiring body 28A is in contact with the second surface 12B. In other words, the wiring body 28A is in contact with the surface 48A of the body contact region 48. This allows the source wiring 28 to be electrically connected to the body contact region 48. In one example, the wiring body 28A is in contact with the entire surface 48A of the body contact region 48. The body contact region 48 has a p+ Since it corresponds to the region 24, the source wiring 28 is + It can be said that the entire surface of the region 24 is in contact with the surface.

[0060] The contact plug 28B protrudes from the wiring body 28A toward the inside of each gate trench 14. The contact plug 28B is inserted between the surface 48A (second surface 12B) of the body contact region 48 in the gate trench 14 and the surface 58A of the second insulating layer 58. The contact plug 28B contacts a portion of the sidewall 14A of the gate trench 14 closer to the second surface 12B than the surface 58A of the second insulating layer 58. Both the side surface of the source contact region 46 and the side surface of the body contact region 48 are exposed in the portion of the sidewall 14A of the gate trench 14 closer to the second surface 12B than the surface 58A of the second insulating layer 58. Therefore, the contact plug 28B contacts both the side surface of the source contact region 46 and the side surface of the body contact region 48. As a result, the source wiring 28 is electrically connected to both the source contact region 46 (source region 44) and the body contact region 48. The contact plug 28B is in contact with the surface 58A of the second insulating layer 58.

[0061] Here, the side surface of the source contact region 46 is the surface of the source contact region 46 exposed from the sidewall 14A of the gate trench 14. The side surface of the body contact region 48 is the surface of the body contact region 48 exposed from the sidewall 14A of the gate trench 14. In one example, the side surface of the source contact region 46 and the side surface of the body contact region 48 are formed continuously in the Z direction. In one example, the side surface of the source contact region 46 and the side surface of the body contact region 48 are formed flush with each other.

[0062] The thickness dimension of the contact plug 28B in the Z direction (hereinafter, thickness dimension TC) is larger than the depth dimension H2 of the body contact region 48. Moreover, the thickness dimension TC is smaller than the depth dimension H3 of the source region 44. In one example, the thickness dimension TC is equal to or smaller than ½ of the distance DA between the surface 48A (second face 12B) of the body contact region 48 and the gate electrode 50 in the Z direction. In one example, the contact plug 28B is in contact with the entire side surface of the source contact region 46 in the Y direction. Therefore, the dimension of the contact plug 28B in the Y direction is equal to or larger than the dimension of the source contact region 46 in the Y direction.

[0063] [Method of manufacturing semiconductor device] An example of a method for manufacturing the semiconductor device 10 will be described with reference to FIGS. 5 to 19 are schematic cross-sectional views showing exemplary manufacturing processes for the semiconductor device 10. For ease of understanding, in Fig. 5 to Fig. 19, the same components as those in Fig. 2 to Fig. 4 are denoted by the same reference numerals.

[0064] 5, the method for manufacturing the semiconductor device 10 includes forming an epitaxial layer 38 on a semiconductor substrate 36. This forms a semiconductor layer 12 including the semiconductor substrate 36 and the epitaxial layer 38. The semiconductor substrate 36 may be a Si substrate containing n-type impurities. The epitaxial layer 38 is an n-type impurity that is epitaxially grown on the semiconductor substrate 36 while being doped with n-type impurities. - It may be a type Si layer.

[0065] 6, the method for manufacturing the semiconductor device 10 includes forming a gate trench 14 having a sidewall 14A and a bottom wall 14B in the semiconductor layer 12. In this step, a part of the epitaxial layer 38 is selectively removed by etching using a mask (not shown) of a predetermined pattern formed on the second surface 12B of the semiconductor layer 12. This makes it possible to form the gate trench 14 having an opening in the second surface 12B of the semiconductor layer 12. The gate trench 14 extends along the Y direction in a plan view.

[0066] As shown in FIG. 7, the method for manufacturing the semiconductor device 10 includes forming a first insulating layer 100 on the semiconductor layer 12. The first insulating layer 100 is an insulating layer constituting a part of the first insulating layer 56 (see FIG. 3) of the insulating layer 16. The first insulating layer 100 can be formed along the second surface 12B of the semiconductor layer 12 and the sidewall 14A and bottom wall 14B of the gate trench 14. In one example, the first insulating layer 100 may be SiO2 formed by a thermal oxidation method. In another example, the first insulating layer 100 may be SiO2 formed by a chemical vapor deposition (CVD) method. Thus, the first insulating layer 100 may be a SiO2 film.

[0067] As shown in FIGS. 8 and 9, the method for manufacturing the semiconductor device 10 includes forming a field plate electrode 52 (see FIG. 9) in the gate trench 14. 8, forming the field plate electrode 52 in the gate trench 14 includes forming a first conductive layer 102 on a first insulating layer 100. A portion of the first conductive layer 102 is filled in a recess space formed in the gate trench 14. This allows the gate trench 14 to be filled with the first insulating layer 100 and the first conductive layer 102. The first conductive layer 102 may be, for example, conductive polysilicon. The first conductive layer 102 may be formed by, for example, sputtering.

[0068] 9, forming the field plate electrode 52 in the gate trench 14 includes removing a portion of the first conductive layer 102 by etching. In this step, the first conductive layer 102 is etched to expose the first insulating layer 100 covering the second surface 12B of the semiconductor layer 12, while the upper surface of the first conductive layer 102 in the gate trench 14 can be positioned midway in the depth direction (Z direction) of the gate trench 14. Through the above steps, the field plate electrode 52 is formed.

[0069] As shown in FIG. 10, the manufacturing method of the semiconductor device 10 includes removing a part of the first insulating layer 100 by etching. In this step, a part of the first insulating layer 100 formed closer to the second surface 12B of the semiconductor layer 12 with respect to a part closer to the opposing surface 52A than the center of the field plate electrode 52 in the Z direction in the gate trench 14, and a part formed on the second surface 12B of the semiconductor layer 12 can be etched. As a result, the side surface 52C and the opposing surface 52A of the part closer to the opposing surface 52A than the center of the field plate electrode 52 in the Z direction can be exposed. In addition, a part of the side wall 14A of the gate trench 14 and the second surface 12B of the semiconductor layer 12 can be exposed.

[0070] As shown in FIG. 11, the manufacturing method of the semiconductor device 10 includes forming a second insulating layer 104 on the semiconductor layer 12. The second insulating layer 104 can be formed along the exposed portion of the field plate electrode 52, the exposed portion of the sidewall 14A of the gate trench 14, and the second surface 12B of the semiconductor layer 12. The second insulating layer 104 is an insulating layer that constitutes a part of the first insulating layer 56 of the insulating layer 16. In one example, the second insulating layer 104 may be SiO2 formed by a thermal oxidation method. In another example, the second insulating layer 104 may be SiO2 formed by a CVD method. In this manner, the second insulating layer 104 may be a SiO2 film. The second insulating layer 104 can be formed with a relatively thin thickness. In one example, the second insulating layer 104 may be formed with a thickness thinner than that of the first insulating layer 100.

[0071] As shown in FIGS. 12 and 13, the method for manufacturing the semiconductor device 10 includes forming a gate electrode 50 in the gate trench 14. As shown in FIG. 12, forming the gate electrode 50 in the gate trench 14 includes forming a second conductive layer 106 on the second insulating layer 104. A portion of the second conductive layer 106 is embedded in a recess space formed in the gate trench 14. A portion of the second conductive layer 106 may be formed on the second insulating layer 104 covering the second surface 12B of the semiconductor layer 12. The second conductive layer 106 may be, for example, conductive polysilicon. The second conductive layer 106 may be formed by, for example, sputtering.

[0072] 13, forming the gate electrode 50 in the gate trench 14 includes removing a portion of the second conductive layer 106 by etching. In this step, the second conductive layer 106 is etched to expose the second insulating layer 104 covering the second surface 12B of the semiconductor layer 12. Through the above steps, the gate electrode 50 is formed. The surface 50B of the gate electrode 50 is located closer to the bottom wall 14B of the gate trench 14 than the second surface 12B.

[0073] 14, the manufacturing method of the semiconductor device 10 includes removing a part of the second insulating layer 104 by etching. In this step, it is possible to etch a portion of the second insulating layer 104 closer to the second surface 12B than the surface 50B of the gate electrode 50, and a portion on the second surface 12B. As a result, it is possible to expose a portion of the sidewall 14A of the gate trench 14 closer to the second surface 12B than the surface 50B of the gate electrode 50, and the second surface 12B. Through the above steps, the first insulating layer 56 of the insulating layer 16 is formed.

[0074] 15, the method for manufacturing the semiconductor device 10 includes forming a source formation region 108 in the epitaxial layer 38. The source formation region 108 is formed in a region exposed from the second insulating layer 104 in the gate trench 14 and in the second surface 12B of the semiconductor layer 12. The source formation region 108 is an n +In this step, n-type impurities are implanted by ion implantation into the region exposed from the second insulating layer 104 in the gate trench 14, which is the surface of the epitaxial layer 38, which is an n-type Si layer, and into the second surface 12B.

[0075] As shown in FIG. 16, the method for manufacturing the semiconductor device 10 includes forming a third insulating layer 110 in the gate trench 14 and on the second surface 12B. The third insulating layer 110 is an insulating layer constituting the second insulating layer 58 (see FIG. 3) of the insulating layer 16. The third insulating layer 110 covers the source formation region 108. In one example, the second insulating layer 104 may be SiO2 formed by a CVD method. In another example, the second insulating layer 104 may be SiO2 formed by a thermal oxidation method. Thus, the second insulating layer 104 may be a SiO2 film.

[0076] 17, the method for manufacturing the semiconductor device 10 includes removing a portion of the third insulating layer 110 by etching. In this step, the portion of the third insulating layer 110 on the second surface 12B and the portion provided at the opening end of the gate trench 14 can be etched. Through the above steps, the second insulating layer 58 of the insulating layer 16 is formed.

[0077] 18, the method for manufacturing the semiconductor device 10 includes a step of grinding the second surface 12B of the semiconductor layer 12. In this step, the second surface 12B can be polished by, for example, chemical mechanical polishing (CMP). As a result, the source formation region 108 formed on the second surface 12B is removed. As a result, a region exposed from the second insulating layer 104 in the gate trench 14 remains as the source formation region 108.

[0078] 19, the method for manufacturing the semiconductor device 10 includes forming the body region 42 and forming the body contact region 48. P-type impurities are implanted into the surface region of the epitaxial layer 38 by ion implantation. This forms the body region 42. Then, p-type impurities are further implanted into the second surface 12B. This forms the body contact region 48.

[0079] 20, the manufacturing method of the semiconductor device 10 includes forming the source wiring 28. In this step, a third conductive layer 112 is formed on the second surface 12B of the semiconductor layer 12 and in the gate trench 14 by, for example, sputtering. An embedded portion 112A of the third conductive layer 112 embedded in the gate trench 14 constitutes a contact plug 28B of the source wiring 28. Next, the third conductive layer 112 is patterned to form a wiring main body 28A from the third conductive layer 112. Through the above steps, the source wiring 28 is formed.

[0080] Although not shown, the method for manufacturing the semiconductor device 10 includes forming a drain electrode 54 (see FIG. 3). Through the above steps, the semiconductor device 10 is manufactured. Note that although the method for manufacturing the semiconductor device 10 has been described above as including a number of manufacturing steps that are performed sequentially, it should be understood that some of the manufacturing steps may be performed in parallel or in a different order. Also, some manufacturing steps may be omitted, and any of the manufacturing steps may perform a process different from the above example.

[0081] [Effect] The operation of the semiconductor device 10 of this embodiment will now be described. For example, a commonly known configuration is one in which a part of a source wiring is embedded in a contact hole in a mesa region for contacting the body region, thereby electrically connecting the body region and the source wiring (hereinafter, referred to as a "comparative configuration"). In the comparative configuration, a body contact region is formed at the bottom of the contact hole.

[0082] In the comparative structure, since a contact hole is formed in the mesa region, it is difficult to reduce the dimension of the mesa region in the X direction. In addition, in the comparative structure, it is necessary to adjust the Z direction positions of the top surface of the gate electrode and the bottom of the contact hole. Both the gate electrode and the contact hole are formed separately by etching. For this reason, high processing accuracy is required for etching both the gate electrode and the contact hole.

[0083] In the semiconductor device 10 of this embodiment, the source wiring 28 is formed so as to contact the source contact region 46 formed on the sidewall 14A of the gate trench 14 and the body contact region 48 formed on the second surface 12B. Therefore, no contact hole is formed in the mesa region 60. This allows the dimension of the mesa region 60 in the X direction to be reduced. That is, the distance between adjacent gate trenches 14 in the X direction can be reduced. In addition, since it is not necessary to form a contact hole in the mesa region 60 and to adjust the position of the top surface of the gate electrode and the bottom of the contact hole in the Z direction, high processing accuracy is not required in etching.

[0084] [effect] According to the semiconductor device 10 of this embodiment, the following effects can be obtained. (1) The semiconductor device 10 includes a drift region 40, a body region 42 formed on the drift region 40, a body contact region 48 formed on the body region 42, a gate trench 14 formed to penetrate both the body region 42 and the body contact region 48 to reach the drift region 40 and including a sidewall 14A and a bottom wall 14B, an insulating layer 16 formed in the gate trench 14, a gate electrode 50 disposed in the gate trench 14 and separated from the sidewall 14A by the insulating layer 16, a source region 44 formed along a part of the sidewall 14A and in contact with both the body region 42 and the body contact region 48, and a source wiring 28 disposed across both the gate trench 14 and the body region 42 in a plan view. The source region 44 includes a source contact region 46 in contact with the source wiring 28. The source wiring 28 is in contact with both the side surface of the source contact region 46 and a surface 48A of the body contact region 48.

[0085] According to this configuration, the body contact region 48 is formed on the body region 42, the source region 44 including the source contact region 46 is formed on the sidewall 14A of the gate trench 14, and the source wiring 28 is in contact with both the side surface of the source contact region 46 and the surface 48A of the body contact region 48, so that it is not necessary to form a contact hole in the body region 42 for connecting the body region and the source wiring. Therefore, since no contact hole is formed, the semiconductor device 10 can be made smaller.

[0086] (2) The entire surface 48A (second surface 12B) of the body contact region 48 is formed as a flat surface that does not have any holes. This configuration facilitates surface contact between the surface 48A of the body contact region 48 and the source wiring 28.

[0087] (3) The source region 44 is formed to overlap the body contact region 48 in a plan view. According to this configuration, the source region 44 and the body contact region 48 are aligned in the X direction, thereby enabling the semiconductor device 10 to be made smaller in size in the X direction compared to a configuration in which the body contact region 48 and the source region 44 do not overlap in a planar view.

[0088] (4) The gate electrode 50 is disposed closer to the bottom wall 14B of the gate trench 14 in the Z direction than the body contact region 48. The source region 44 is formed between the body contact region 48 and the gate electrode 50 in the Z direction.

[0089] According to this configuration, the source region 44 is disposed closer to the body contact region 48 than the gate electrode 50, that is, the gate electrode 50 and the source region 44 do not face each other in the X direction, so that a decrease in the breakdown voltage between the gate electrode 50 and the source region 44 can be suppressed.

[0090] (5) In the Z direction, of both edge portions of the source region 44, the edge portion closer to the bottom wall 14B of the gate trench 14 is located at the same position as the surface of the gate electrode 50 (surface 50B). According to this configuration, when a gate voltage is applied to the gate electrode 50, a channel is formed up to one of both end edges of the source region 44 that is closer to the bottom wall 14B of the gate trench 14. This makes it easier for a drain current to flow to the source region 44.

[0091] (6) The source contact region 46 is formed in a position of the source region 44 adjacent to the body contact region 48 in the Z direction. According to this configuration, the distance between the source wiring 28 and the gate electrode 50 in the Z direction can be secured, so that a decrease in the breakdown voltage between the source wiring 28 and the gate electrode 50 can be suppressed.

[0092] (7) The insulating layer 16 includes a first insulating layer 56 covering the side surface 50C of the gate electrode 50 and the area between the gate electrode 50 and the bottom wall 14B of the gate trench 14, and a second insulating layer 58 formed on the gate electrode 50. A surface 58A of the second insulating layer 58 is disposed closer to the gate electrode 50 than a surface 48A (second face 12B) of the body contact region 48. The source wiring 28 includes a contact plug 28B that is inserted between the surface 48A (second face 12B) of the body contact region 48 in the gate trench 14 and the surface 58A of the second insulating layer 58 and is in contact with the source contact region 46.

[0093] According to this configuration, the source wiring 28 contacts both the surface 48A of the body contact region 48 and the side surface exposed from the sidewall 14A of the gate trench 14. This makes it possible to increase the contact area between the source wiring 28 and the body contact region 48.

[0094] (8) The thickness dimension TC of the contact plug 28B in the Z direction is greater than the depth dimension H2 of the body contact region 48 in the Z direction. This configuration allows the contact plug 28B and the source contact region 46 to form a region in which they face each other in the X-direction. This makes it easier for the contact plug 28B and the source contact region 46 to come into contact with each other.

[0095] (9) The thickness dimension TC of the contact plug 28B in the Z direction is smaller than the depth dimension H3 of the source region 44 in the Z direction. According to this configuration, the distance between the contact plug 28B and the gate electrode 50 in the Z direction can be secured, so that a decrease in the breakdown voltage between the source wiring 28 and the gate electrode 50 can be suppressed.

[0096] (10) The thickness dimension TC of the contact plug 28B in the Z direction is equal to or less than half the distance DA between the surface 48A (second face 12B) of the body contact region 48 and the gate electrode 50 in the Z direction.

[0097] According to this configuration, the distance between the contact plug 28B and the gate electrode 50 in the Z direction can be secured, so that a decrease in the breakdown voltage between the source wiring 28 and the gate electrode 50 can be suppressed. (11) The semiconductor device 10 includes a field plate electrode 52 disposed in the gate trench 14 closer to the bottom wall 14B than the gate electrode 50 and separated from the gate electrode 50, the sidewall 14A, and the bottom wall 14B by the insulating layer 16.

[0098] This configuration makes it possible to maintain the breakdown voltage even when the impurity concentration in the epitaxial layer 38 is increased in order to reduce the on-resistance of the semiconductor device 10. In addition, the gate-drain capacitance can be reduced, thereby improving the switching speed of the semiconductor device 10.

[0099] <Example of change> The above embodiment can be modified as follows: The following modifications can be combined with each other as long as no technical contradiction occurs.

[0100] The positional relationship between the source region 44 and the body contact region 48 can be changed arbitrarily. In one example, as shown in FIG. 21, the body contact region 48 may be formed between two source regions 44 spaced apart in the X direction. In this case, the body contact region 48 is in contact with the source region 44 in the X direction. That is, the body contact region 48 is not exposed from the sidewall 14A of the gate trench 14. Therefore, the width dimension W1 of the body contact region 48 is smaller than the width dimension of the mesa region 60. In addition, the thickness dimension TC of the contact plug 28B of the source wiring 28 is equal to the depth dimension H4 of the source contact region 46.

[0101] 21, the depth dimension H4 of the source contact region 46 is larger than the depth dimension H2 of the body contact region 48. The depth dimension H4 is, for example, more than twice the depth dimension H2. It can also be said that the thickness dimension TC of the contact plug 28B is more than twice the depth dimension H2.

[0102] 21, the position of the surface 58A of the second insulating layer 58 in the Z direction can be changed as desired, provided that the surface 58A is closer to the gate electrode 50 than the second surface 12B of the semiconductor layer 12. In one example, the surface 58A may be located at the same position as the interface between the body contact region 48 and the body region 42 in the Z direction. That is, the thickness of the second insulating layer 58 may be made thicker than in the example shown in FIG. 21. Accordingly, the depth dimension H4 of the source contact region 46 becomes smaller. This depth dimension H4 may be equal to the depth dimension H2 of the body contact region 48.

[0103] The position of the gate electrode 50 in the Z direction can be changed arbitrarily. In one example, the surface 50B of the gate electrode 50 may be disposed closer to the bottom wall 14B of the gate trench 14 than the source region 44 in the Z direction.

[0104] The relationship between the width dimension W1 and the depth dimension H3 of the source region 44 can be changed arbitrarily. In one example, the width dimension W1 may be equal to the depth dimension H3. In one example, the width dimension W1 may be greater than the depth dimension H3.

[0105] The relationship between the width dimension W1 of the source region 44 and the width dimension W2 of the body contact region 48 can be changed arbitrarily. In one example, the width dimension W1 may be equal to or greater than ½ of the width dimension W2. In one example, the width dimension W1 may be equal to or greater than the width dimension W2. In this case, the body contact region 48 is formed in a part of the mesa region 60 in the X direction.

[0106] The thickness dimension TC of the contact plug 28B of the source wiring 28 can be changed arbitrarily. In one example, the thickness dimension TC may be equal to the depth dimension H3 of the source region 44. In one example, the thickness dimension TC may be greater than the depth dimension H3. The thickness dimension TC may be greater than ½ of the distance DA between the surface 48A (second face 12B) of the body contact region 48 and the gate electrode 50. In one example, the thickness dimension TC of the contact plug 28B of the source wiring 28 may be equal to the depth dimension H2 of the body contact region 48. Also, the thickness dimension TC may be smaller than the depth dimension H2.

[0107] The cross-sectional shape of the gate electrode 50 cut in the XZ plane can be changed arbitrarily. In one example, at least one of the bottom side recess 51A and the front side recess 51B may be omitted from the gate electrode 50. When the bottom side recess 51A is omitted from the gate electrode 50, the bottom surface 50A of the gate electrode 50 may be flat or curved. When the front side recess 51B is omitted from the gate electrode 50, the front surface 50B of the gate electrode 50 may be flat or curved.

[0108] The field plate electrode 52 may be omitted from the semiconductor device 10. In this case, as shown in FIG. 22, the gate electrode 50 may extend in the Z direction. The first insulating layer 56 is formed so as to cover the side surface 50C and the bottom surface 50A of the gate electrode 50. In one example, the tip surface of the first insulating layer 56 is flush with the surface 50B of the gate electrode 50. In another example, the thickness of the first insulating layer 56 is constant. The second insulating layer 58 is formed so as to cover both the surface 50B of the gate electrode 50 and the tip surface of the first insulating layer 56. In this way, the insulating layer 16 covers the gate electrode 50.

[0109] In the example shown in FIG. 22, the body region 42, the source region 44, the source contact region 46, and the body contact region 48 are the same as those in the first embodiment. In one example, the edge of the source region 44 in the Z direction that is closer to the bottom wall 14B of the gate trench 14 is located at the same position as the surface 50B of the gate electrode 50. The contact plug 28B of the source wiring 28 is in contact with the source contact region 46 in the X direction. According to the modification example shown in FIG. 22, the same effects as those of the above-mentioned embodiments (1-1) to (1-10) can be obtained. The body region 42, the source region 44, the source contact region 46, and the body contact region 48 may be modified as in the modification example shown in FIG. 21.

[0110] The semiconductor layer 12 may be formed of, for example, SiC (silicon carbide) instead of Si. In this case, the semiconductor substrate 36 of the semiconductor layer 12 may be, for example, a SiC substrate. And the epitaxial layer 38 may be a SiC layer epitaxially grown on the SiC substrate.

[0111] One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0112] The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0113] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" of the vertical direction. For example, the X direction may be a vertical direction, or the Y direction may be a vertical direction.

[0114] <Additional Notes> The technical ideas that can be understood from the above embodiment and each modified example are described below. Note that the reference numerals of the components of the embodiment corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid in understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0115] [Appendix A1] a drift region (40); a body region (42) formed on the drift region (40); a body contact region (48) formed on the body region (42); a gate trench (14) formed to penetrate through both the body region (42) and the body contact region (48) to reach the drift region (40), the gate trench including a sidewall (14A) and a bottom wall (14B); an insulating layer (16) formed in the gate trench (14); a gate electrode (50) disposed within the gate trench (14) and spaced from the sidewall (14A) by the insulating layer (16); a source region (44) formed along a portion of the sidewall (14A) and in contact with both the body region (42) and the body contact region (48); a source wiring (28) arranged across both the gate trench (14) and the body region (42) when viewed from a depth direction (Z direction) of the gate trench (14); Including, The source region (44) includes a source contact region (46) that contacts a source wiring (28), The source wiring (28) is in contact with both the side surface of the source contact region (46) and the surface of the body contact region (48). A semiconductor device (10).

[0116] [Appendix A2] The entire surface of the body contact region (48) is formed as a flat surface without any holes. 13. The semiconductor device according to claim 12 .

[0117] [Appendix A3] The source region (44) is formed so as to overlap the body contact region (48) when viewed from the depth direction (Z direction). The semiconductor device according to appendix A1 or A2.

[0118] [Appendix A4] the gate electrode (50) is disposed closer to the bottom wall (14B) of the gate trench (14) than the body contact region (48) is in the depth direction (Z direction); The source region (44) is formed between the body contact region (48) and the gate electrode (50) in the depth direction (Z direction). 10. The semiconductor device according to claim 9,

[0119] [Appendix A5] In the depth direction (Z direction), of both end edges of the source region (44), the end edge closer to the bottom wall (14B) of the gate trench (14) is located at the same position as the surface (50B) of the gate electrode (50) or closer to the bottom wall (14B) than the surface (50B) of the gate electrode (50). The semiconductor device according to appended claim A4.

[0120] [Appendix A6] The source contact region (46) is formed at a position of the source region (44) adjacent to the body contact region (48) in the depth direction (Z direction). The semiconductor device according to appendix A4 or A5.

[0121] [Appendix A7] The impurity concentration of the source region (44) is higher than the impurity concentration of the body region (42). The semiconductor device according to any one of Appendix A1 to A6.

[0122] [Appendix A8] A width dimension (W1) of the source region (44) in the width direction (X direction) of the gate trench (14) is smaller than a depth dimension (H3) of the source region (44) in the depth direction (Z direction). The semiconductor device according to any one of Appendix A1 to A7.

[0123] [Appendix A9] A width dimension (W1) of the source region (44) in the width direction (X direction) is smaller than a width dimension (W2) of the body contact region (48) in the width direction (X direction). The semiconductor device according to Appendix A8.

[0124] [Appendix A10] The insulating layer (16) is a first insulating layer (56) covering a side surface (50C) of the gate electrode (50) and a portion between the gate electrode (50) and the bottom wall (14B); a second insulating layer (58) formed on the gate electrode (50); Including, a surface (58A) of the second insulating layer (58) is disposed closer to the gate electrode (50) than a surface of the body contact region (48); The source wiring (28) is inserted between a surface of the body contact region (48) in the gate trench (14) and a surface (58A) of the second insulating layer (58), and includes a contact plug (28B) in contact with the source contact region (46). The semiconductor device according to any one of Appendix A4 to A6.

[0125] [Appendix A11] A thickness dimension (TC) of the contact plug (28B) in the depth direction (Z direction) is greater than a depth dimension (H2) of the body contact region (48) in the depth direction (Z direction). The semiconductor device according to claim A10.

[0126] [Appendix A12] A thickness dimension (TC) of the contact plug (28B) in the depth direction (Z direction) is smaller than a depth dimension (H3) of the source region (44) in the depth direction (Z direction). The semiconductor device according to appendix A10 or A11.

[0127] [Appendix A13] A thickness dimension (TC) of the contact plug (28B) in the depth direction (Z direction) is equal to or less than half the distance (DA) between the surface of the body contact region (48) and the gate electrode (50) in the depth direction (Z direction). The semiconductor device according to any one of Appendix A10 to A12.

[0128] [Appendix A14] The gate electrode (50) is disposed closer to the body region (42) than to the drift region (40). The semiconductor device according to any one of Appendix A4 to A6.

[0129] [Appendix A15] The gate trench includes a buried electrode that is disposed closer to the bottom wall than the gate electrode and is separated from the gate electrode, the side wall, and the bottom wall by the insulating layer. The semiconductor device according to any one of Appendix A1 to A14.

[0130] [Appendix B1] forming a semiconductor layer (12) having a first surface (12A) and a second surface (12B) facing in a direction opposite to the first surface (12A); forming a gate trench (14) including a sidewall (14A) and a bottom wall (14B) in the semiconductor layer (12); forming a first insulating layer (56) in the gate trench (14); forming a gate electrode (50) in the gate trench (14); forming a second insulating layer (58) covering a surface (50B) of the gate electrode (50) in the gate trench (14); forming a source region (44) in a portion of the sidewall (14A) of the gate trench (14) closer to the second surface (12B) than the second insulating layer (58) by ion implantation; forming a body region (42) in the semiconductor layer (12) by ion implantation; forming a body contact region (48) in the body region (42) by ion implantation; and forming a source wiring (28) so as to be in contact with both the source region (44) and the body contact region (48); A method for manufacturing a semiconductor device (10), comprising:

[0131] [Appendix B2] Forming the source region (44) comprises: forming a source formation region (108) in the semiconductor layer (12) by ion implantation; and removing the source formation region (108) formed on the second surface (12B) of the semiconductor layer (12) by polishing the second surface (12B); Includes A method for manufacturing a semiconductor device according to Appendix B1.

[0132] [Appendix B3] The body contact region (48) is formed in the body region (42) after removing the source formation region (108) formed on the second surface (12B). A method for manufacturing a semiconductor device according to Appendix B2.

[0133] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0134] 10...Semiconductor device 12...Semiconductor layer 12A…Side 1 12B…Second side 14…Gate trench 14A…Side wall 14B…Bottom wall 14P...1st end 14Q…Second end 16…Insulating layer 18...Peripheral trench 20...n - type area 22...p - type area 24...p + type area 25...n + type area 26…Gate wiring 28…Source wiring 28A…Wiring body 28B…Contact plug 30…Gate contact section 32…Source contact section 34…Contact part 36...Semiconductor substrate (drain region) 38…Epitaxial layer 40…Drift region 41...interface 42…Body area 44…Source region 46…Source contact area 48…Body contact area 48A…Surface 50…Gate electrode 50A…Bottom 50B…Surface 50C…side 51A…Bottom recess 51B: Surface recess 52...Field plate electrode 52A…Facing surface 52B…Bottom 52C…side 54...Drain electrode 56…First insulating layer 58…Second insulating layer 58A…Surface 60…Mesa area 100...First insulating layer 102...First conductive layer 104...Second insulating layer 106...Second conductive layer 108...Source formation region 110...Third insulating layer 112...Third conductive layer 112A…embedded part H1: Depth dimension of body area H2: Depth dimension of body contact area H3: Depth dimension of source region H4: Depth dimension of source contact area W1: Width of source area W2: Width of body contact area TC: Thickness of the contact plug of the source wiring DA...Distance between the surface of the body contact region and the gate electrode in the Z direction

Claims

1. A drift region; a body region formed on the drift region; a body contact region formed on the body region; a gate trench formed to pass through both the body region and the body contact region and reach the drift region, the gate trench including a sidewall and a bottom wall; an insulating layer formed in the gate trench; a gate electrode disposed in the gate trench and spaced from the sidewalls by the insulating layer; a source region formed along a portion of the sidewall and in contact with both the body region and the body contact region; a source wiring arranged across both the gate trench and the body region when viewed from a depth direction of the gate trench; Including, the source region includes a source contact region in contact with the source wiring, The source wiring is in contact with both a side surface of the source contact region and a surface of the body contact region. Semiconductor device.

2. The entire surface of the body contact region is formed as a flat surface having no holes. The semiconductor device according to claim 1 .

3. The source region is formed so as to overlap the body contact region when viewed from the depth direction. The semiconductor device according to claim 1 .

4. the gate electrode is disposed closer to the bottom wall of the gate trench than the body contact region is in the depth direction; The source region is formed between the body contact region and the gate electrode in the depth direction. The semiconductor device according to claim 3 .

5. In the depth direction, one of both end edges of the source region closer to the bottom wall of the gate trench is located at the same position as the surface of the gate electrode or closer to the bottom wall than the surface of the gate electrode. The semiconductor device according to claim 4.

6. The source contact region is formed in a position of the source region adjacent to the body contact region in the depth direction. The semiconductor device according to claim 4.

7. The impurity concentration of the source region is higher than the impurity concentration of the body region. The semiconductor device according to claim 1 .

8. The width dimension of the source region in the width direction of the gate trench is smaller than the depth dimension of the source region in the depth direction. The semiconductor device according to claim 1 .

9. The width dimension of the source region in the width direction is smaller than the width dimension of the body contact region in the width direction. The semiconductor device according to claim 8.

10. The insulating layer is a first insulating layer covering a side surface of the gate electrode and a portion between the gate electrode and the bottom wall; a second insulating layer formed on the gate electrode; Including, a surface of the second insulating layer is disposed closer to the gate electrode than a surface of the body contact region; The source wiring includes a contact plug that is inserted between a surface of the body contact region and a surface of the second insulating layer in the gate trench and is in contact with the source contact region. The semiconductor device according to claim 4.

11. The thickness dimension of the contact plug in the depth direction is greater than the depth dimension of the body contact region in the depth direction. The semiconductor device according to claim 10.

12. The thickness dimension of the contact plug in the depth direction is smaller than the depth dimension of the source region in the depth direction. The semiconductor device according to claim 10.

13. The thickness dimension of the contact plug in the depth direction is equal to or less than half the distance in the depth direction between the surface of the body contact region and the gate electrode. The semiconductor device according to claim 10.

14. The gate electrode is disposed closer to the body region than the drift region. The semiconductor device according to claim 4.

15. a buried electrode disposed in the gate trench closer to the bottom wall than the gate electrode and separated from the gate electrode, the sidewall, and the bottom wall by the insulating layer; The semiconductor device according to any one of claims 1 to 14.

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