Delta sigma type modulator

Abstract

To provide a delta sigma modulator capable of improving a settling performance, and reducing noise.SOLUTION: In a delta sigma type modulator 1, a first chopping switch 9 is connected to an input side of a capacitive coupling amplifier 2, and a parallel circuit 12 is connected to an output side of the capacitive coupling amplifier. A second chopping switch 13 is connected to a subsequent stage of the parallel circuit, and a first integrator 3 is connected to a subsequent stage of the second chopping switch. A third chopping switch 14 is arranged between the second chopping switch and an input side of the first integrator, and signals modulated by the first chopping switch are demodulated by the second chopping switch. A filtering switch ΦDF is actuated at an operation frequency Fs of the integrator and the third chopping switch, and at a timing at which a phase is different by 180 degrees from that of the third chopping switch.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a delta-sigma modulator. [Background technology]

[0002] For example, Patent Document 1 discloses a configuration in which chopping is performed at the same frequency for the input / output of a part performing A / D conversion operation and the input / output of an integral capacitance in an integrator in a delta-sigma modulator. Also, Non-Patent Document 1 discloses a configuration in which dynamic filtering is performed by combining an RC filter and a switch between the output of an amplifier and a sampling input for A / D conversion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Publication 2022 / 0263520 Specification [Non-patent literature]

[0004] [Non-Patent Document 1] A 19 nV / √Hz Noise 2-μV Offset 75-μA Capacitive-Gain Amplifier With Switched-Capacitor ADC Driving CapabilityHanqing Wang, et. al., JSSC2017 (ADI) Summary of the Invention [Problem to be solved by the invention]

[0005] In the configuration of Patent Document 1, the polarity of the input value of the quantizer is inverted before and after chopping, so the polarity of the decision value of the quantizer is also inverted before and after chopping. Therefore, in order to properly control the output timing of the D / A converter before and after chopping, it is necessary to take into consideration all of the decision and output timing of the quantizer and the output timing of the D / A converter. The timing control becomes complicated.

[0006] In addition, the configuration of Non-Patent Document 1 has the advantage that the settling time is short when the switch is turned on, and the noise propagation to the subsequent stage is small due to the action of the resistor when the switch is turned off. However, the timing generation for performing dynamic filtering becomes complicated.

[0007] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a delta-sigma modulator that can improve settling performance and reduce noise with simpler timing control. [Means for solving the problem]

[0008] According to the delta-sigma modulator of claim 1, the first chopping switch (9) is connected to the input side of the capacitive coupling amplifier (2). A parallel circuit (12) of a resistive element (11) and a filter switch (ΦDF) is connected to the output side of the capacitive coupling amplifier. The second chopping switch (13) is connected to the rear stage of the parallel circuit. The correlated double sampling integrator (3) is connected to the rear stage of the second chopping switch. The third chopping switch (14) is disposed between the second chopping switch and the input side of the integrator. Then, the signal modulated by the chopping operation of the first chopping switch is demodulated by the chopping operation of the second chopping switch.

[0009] The operating frequency of the integrator and the third chopping switch is Fs, and the operating frequency of the first and second chopping switches is Fs / 2. The filter switch operates at the operating frequency Fs and with a phase difference of 180 degrees with respect to the third chopping switch.

[0010] By setting the operating frequency of the first chopping switch, which chops the voltage input to the capacitive coupling amplifier, to half that of the integrator, the amount of charge absorbed is reduced. Also, the filter switch, which performs dynamic filtering, is turned on at the timing when the voltage input to the second chopping switch changes in accordance with the phase transition of the sample / hold at the input of the integrator, which accompanies the on / off of the third chopping switch. This makes it possible to shorten the resistance element and speed up settling. Also, since the filter switch is turned off at a timing when the voltage does not change, the noise level generated in the previous stage can be reduced by the resistance value of the resistance element. In this way, the timing for controlling the filter switch is simplified.

[0011] The delta-sigma modulator (2, 33) of claim 2 has a configuration in which the third chopping switch is removed from the configuration of claim 1, and is similar in that a signal modulated by a chopping operation using the first chopping switch is demodulated by a chopping operation using the second chopping switch. The first and second chopping switches perform chopping operations at an operating frequency Fs / 2 relative to the operating frequency Fs of the integrator, and at timings that are 90 degrees out of phase with each other. The filter switch operates at an operating frequency Fs, and at timings that are 180 degrees out of phase with respect to a signal obtained by taking the exclusive OR of each signal for the first and second chopping switches.

[0012] With this configuration, the timing for controlling the filter switch has the same effect as in claim 1. And according to claim 2, the third chopping switch of claim 1 is also used as the second chopping switch, so the circuit scale can be made smaller. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a delta-sigma modulator according to a first embodiment. [Diagram 2] A timing chart showing the waveforms of signals that control each switch. [Diagram 3] FIG. 11 is a diagram showing a configuration of a delta-sigma modulator according to a second embodiment. [Figure 4] A timing chart showing the waveforms of signals that control each switch. [Diagram 5] FIG. 13 is a diagram showing a configuration of a delta-sigma modulator according to a third embodiment. [Figure 6] A timing chart showing signal waveforms for controlling each switch. [Figure 7] 1 is a timing chart showing input and output voltage waveforms of a capacitive coupling amplifier and waveforms of signals controlling a filter switch; [Figure 8] FIG. 13 is a diagram showing a configuration of a delta-sigma modulator according to a fourth embodiment. [Figure 9] Timing chart showing signal waveforms that control main switches DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] (First embodiment) As shown in Fig. 1, the delta-sigma modulator 1 of this embodiment is a differential type, and includes a capacitively coupled amplifier 2, a first integrator 3, a second integrator 4, and a quantizer 5. Although the reference characters "a" and "b" are attached to the respective sides of the differential configuration in the figure, the reference characters "a" and "b" are not attached unless there is a particular need to distinguish them because the configuration is symmetrical. A parallel circuit of a capacitor 7 and a resistor element 8 is connected between the input terminal and the output terminal of an operational amplifier 6 constituting the capacitively coupled amplifier 2. Voltages Vinp and Vinm are input to the input terminals of the operational amplifier 6 via a first chopping switch 9 and a capacitor 10.

[0015] The first chopping switch 9 has four switches, and there are two sets of switches Φ1din and Φ2din, one end of which is commonly connected. The names of the switches are the same as the names of the signals used for switching control. Each switch is turned on when the level of the control signal is high. Voltages Vinp and Vinm are input to the capacitor 10a via the switches Φ2din and Φ1din. Voltages Vinp and Vinm are input to the capacitor 10b via the switches Φ1din and Φ2din.

[0016] A parallel circuit 12 including a resistor element 11 and a filter switch ΦDF is connected to the output terminal of the capacitive coupling amplifier 2. A second chopping switch 13 and a third chopping switch 14 are connected in series to the parallel circuit 12. These chopping switches 13 and 14 also include four switches, and the second chopping switch 13 includes two pairs of switches Φ1dout and Φ2dout whose output sides are commonly connected. The input side of each switch Φ1dout is connected straight to the parallel circuit 12, and the input side of each switch Φ2dout is connected crosswise to the parallel circuit 12.

[0017] The third chopping switch 14 has two pairs of switches Φ1d and Φ2d whose output sides are commonly connected. The input side of each switch Φ1d is connected straight to the second chopping switch 13, and the input side of each switch Φ2d is connected crosswise to the second chopping switch 13.

[0018] The output side of the third chopping switch 14 is connected to the input terminal of an operational amplifier 16 constituting the first integrator 3 via a capacitor 15. A series circuit of a switch Φ2 and a capacitor 17 and a switch Φ1 are connected in parallel between the input terminal and the output terminal of the operational amplifier 16. The first integrator 3 is of a correlated double sampling type.

[0019] The output terminal of the operational amplifier 16 is connected to the input terminal of an operational amplifier 19 constituting the second integrator 4 via a series circuit of a switch Φ2d, a capacitor 18, and a switch Φ2. A switch Φ1d is connected between the common connection point of the switch Φ2d and the capacitor 18 and ground. A switch Φ1 is connected between the common connection point of the capacitor 18 and the switch Φ2 and ground.

[0020] A capacitor 20 is connected between the input terminal and output terminal of the operational amplifier 19. The output terminal of the operational amplifier 19 is connected to the input terminal of the quantizer 5. The output terminal of the quantizer 5 is connected to the input terminals of D / A converters 21 and 22. The output terminal of the D / A converter 21 is connected to the input terminal of the operational amplifier 16 via a series circuit of a switch Φ2d and a capacitor 23. The output terminal of the D / A converter 22 is connected to the common connection point of the switch Φ2d and the capacitor 18 on the input side of the second integrator 4 via a series circuit of a switch Φ2d and a capacitor 24.

[0021] Next, the operation of this embodiment will be described. As shown in Fig. 2, the operating frequency of signals Φ1 and Φ2 that control the on / off of the switches on the input side of the first integrator 3 and the second integrator 4 is Fs. The signals Φ1 and Φ2 are 180 degrees out of phase with each other. The signals Φ1d and Φ2d control the third chopping switch 14 and the switches on the output side of the D / A converters 21 and 22. The signals Φ1d and Φ2d are signals with a slight phase delay of the signals Φ1 and Φ2.

[0022] The signals Φ1din and Φ2din are signals that control the first chopping switch 9, and the signals Φ1dout and Φ2dout are signals that control the second chopping switch 13, and their frequencies are Fs / 2. The signals Φ1din and Φ2din are 180 degrees out of phase with each other, and the signals Φ1dout and Φ2dout are also 180 degrees out of phase with each other. The signals Φ1din and Φ1dout are in phase.

[0023] The frequency of the signal ΦDF that controls the switch of the parallel circuit 12 is Fs and is in phase with the signal Φ2. On the input side of the first integrator 3 and the second integrator 4, when the signals Φ1 and Φ1d are at a high level, the input signal is in a sample phase, and when the signals Φ2 and Φ2d are at a high level, the input signal is in a hold phase. Therefore, the filter switch ΦDF is turned off in the sample phase and turned on in the hold phase.

[0024] Delta-sigma modulator 1 generally performs A / D conversion, but its operating frequency is Fs. Capacitively coupled amplifier 2 operates at a frequency of Fs / 2, and amplifies input voltage Vin with a gain multiplied by the capacitance ratio of capacitors 10 and 7. This reduces the amount of charge absorbed. CCAOUT is the output point of the parallel circuit 12, and INT1IN is the input point of the capacitor 15. The filter switch ΦDF is turned off during a period in which the voltage of CCAOUT does not change, so that the output voltage of the capacitively coupled amplifier 2 is output to the next stage via the resistive element 11 of the parallel circuit 12. This reduces the level of noise generated in the capacitively coupled amplifier 2. In addition, the filter switch ΦDF is turned on at the timing when the voltage of CCAOUT changes, and shorts out the resistive element 11. This shortens the settling time.

[0025] As described above, according to this embodiment, in the delta-sigma modulator 1, the first chopping switch 9 is connected to the input side of the capacitively coupled amplifier 2. The parallel circuit 12 of the resistive element 11 and the filter switch ΦDF is connected to the output side of the capacitively coupled amplifier 2. The second chopping switch 13 is connected to the rear stage of the parallel circuit 12. The first integrator 3 is connected to the rear stage of the second chopping switch 13. The third chopping switch 14 is disposed between the second chopping switch 13 and the input side of the first integrator 3. Then, the signal modulated by the chopping operation by the first chopping switch 9 is demodulated by the chopping operation by the second chopping switch 13.

[0026] The operating frequency of the integrators 3 and 4 and the third chopping switch 14 is Fs, and the operating frequency of the first and second chopping switches 9 and 13 is Fs / 2. The filter switch ΦDF operates at the operating frequency Fs and at a timing that is 180 degrees out of phase with the third chopping switch 14.

[0027] This reduces the amount of charge absorbed on the input side of the capacitively coupled amplifier 2. Also, the filter switch ΦDF, which performs dynamic filtering, is turned on at the timing when the voltage input to the second chopping switch 13 fluctuates, so that the resistance element 11 can be shorted to hasten settling. Also, the filter switch ΦDF is turned off at the timing when the voltage does not fluctuate, so that the noise level generated in the previous stage can be reduced by the resistance value of the resistance element 11. In this way, the timing for controlling the filter switch ΦDF is simplified.

[0028] Second embodiment In the following, the same parts as in the first embodiment are denoted by the same reference numerals and their explanations are omitted, and only the different parts are explained. A delta-sigma modulator 31 of the second embodiment shown in Fig. 3 has a configuration in which the third chopping switch 14 is deleted from the delta-sigma modulator 1. The output side of the second chopping switch 13 is directly connected to the capacitor 15.

[0029] Next, the operation of the second embodiment will be described. As shown in FIG. 4, among the signals that control the switches, the phases of the signals Φ1dout and Φ2dout are different from those of the first embodiment. In the first embodiment, the signals Φ1din and Φ1dout, and the signals Φ2din and Φ2dout are in phase. In contrast, in the second embodiment, the signal Φ1dout leads the signal Φ1din by 90 degrees in phase, and the signal Φ2dout also leads the signal Φ2din by 90 degrees in phase. By controlling in this way, the third chopping switch 14 is not necessary. Therefore, according to the second embodiment, the circuit scale can be further reduced.

[0030] The pattern of the signal that controls the filter switch ΦDF is an inverted pattern of a signal obtained by taking the exclusive OR of the signals Φ1din and Φ1dout that control the first chopping switch 9, and the signals Φ2din and Φ2dout that control the second chopping switch 13.

[0031] Third embodiment As shown in Fig. 5, delta-sigma modulator 32 of the third embodiment is configured to use capacitively coupled amplifier 33 instead of capacitively coupled amplifier 2 of delta-sigma modulator 31. Capacitively coupled amplifier 33 is configured to replace resistive element 8 of capacitively coupled amplifier 2 with switch Φ0. As shown in Fig. 6, switch Φ0 has an operating frequency of Fs, is turned on at the rising edge of signal Φ1, and shorts out input and output terminals of operational amplifier 6.

[0032] As shown in Figs. 6 and 7, the polarity of the output voltage Vout of the capacitive coupling amplifier 33 changes at the timing when the switch Φ0 is turned on. When the output voltage Vout transitions from a negative value toward 0V or from a positive value toward 0V, even if the transition to 0V is not complete, the switch Φ0 is turned on to perform DC biasing. In the second embodiment, a direct current always flows through the resistance element 8, which causes a gain error of the output voltage. In addition, the resistance value of the resistance element 8 becomes high, so that DC biasing takes time. In contrast, according to the third embodiment, the switch Φ0 is turned on to perform DC biasing instantly without causing a gain error.

[0033] (Fourth embodiment) 8, in the delta-sigma modulator 41 of the fourth embodiment, in the delta-sigma modulator 32 of the third embodiment, input low speed chopping switches 42p, 42m are arranged in the stage preceding the first chopping switch 7, and an output low speed chopping switch 43 is arranged in the stage following the quantizer 5. In addition, capacitive low speed chopping switches 44, 45 are arranged across the capacitor 17 of the first integrator 3, and capacitive low speed chopping switches 46, 47 are arranged across the capacitor 20 of the second integrator 4.

[0034] 9, each of the low-speed chopping switches 42 to 47 performs chopping operation at a frequency fLF that is sufficiently lower than the frequency Fs and is lower than the other signals, thereby making it possible to further reduce the influence of the absorption of electric charges.

[0035] (Other embodiments) The configurations of the third and fourth embodiments may be applied to the first embodiment. Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0036] In the drawing, reference numeral 1 denotes a delta-sigma modulator, 2 denotes a capacitively coupled amplifier, 3 denotes a first integrator, 4 denotes a second integrator, 5 denotes a quantizer, 9 denotes a first chopping switch, 11 denotes a resistive element, ΦDF denotes a filter switch, 12 denotes a parallel circuit, 13 denotes a second chopping switch, and 14 denotes a third chopping switch.

Claims

1. A capacitively coupled amplifier (2); a first chopping switch (9) connected to the input side of the capacitively coupled amplifier; a parallel circuit (12) of a resistor element (11) and a filter switch (ΦDF) connected to the output side of the capacitive coupling amplifier; a second chopping switch (13) connected to the rear stage of the parallel circuit; a correlated double sampling integrator (3) connected to the rear stage of the second chopping switch; a third chopping switch (14) disposed between the second chopping switch and an input side of the integrator; demodulating a signal modulated by a chopping operation of the first chopping switch by a chopping operation of the second chopping switch; When the operating frequency of the integrator is Fs, The operating frequency of the third chopping switch is Fs, The operating frequency of the first and second chopping switches is Fs / 2; The filter switch is a delta-sigma modulator that operates at an operating frequency Fs and at a timing that is 180 degrees out of phase with the third chopping switch.

2. A capacitively coupled amplifier (2, 33); a first chopping switch (9) connected to the input side of the capacitively coupled amplifier; a parallel circuit (12) of a resistor element (11) and a filter switch (ΦDF) connected to the output side of the capacitive coupling amplifier; a second chopping switch (13) connected to the rear stage of the parallel circuit; a correlated double sampling integrator (3) connected to the rear stage of the second chopping switch; demodulating a signal modulated by a chopping operation of the first chopping switch by a chopping operation of the second chopping switch; When the operating frequency of the integrator is Fs, the first and second chopping switches perform chopping operations at an operating frequency of Fs / 2 and at timings that are out of phase with each other by 90 degrees, The filter switch is a delta-sigma modulator that operates at an operating frequency Fs and at a timing that is 180 degrees out of phase with a signal obtained by taking an exclusive OR of each signal for the first and second chopping switches.

3. a DC bias switch (Φ0) for short-circuiting between input and output terminals of the capacitive coupling amplifier (33); When the operating frequency of the switch constituting the integrator is Fs, 3. The delta-sigma modulator according to claim 1, wherein the DC bias switch is turned on at an operating frequency Fs for a time period shorter than the time period during which the switch constituting the integrator is turned on.

4. an input slow chopping switch (42) and an output slow chopping switch (43) connected to the input side of the first chopping switch and the output side of the integrator, respectively; 3. A delta-sigma modulator as claimed in claim 1 or 2, wherein the input and output slow chopping switches chop at a lower frequency than the first chopping switch.

5. a capacitance chopping switch (44 to 47) connected to both ends of a feedback capacitance constituting the integrator and chopped by the same signal as the input and output slow chopping switches; a quantizer (5) connected to the output side of the integrator; 5. The delta-sigma modulator according to claim 4, wherein the output slow chopping switch is connected to the output side of the quantizer.

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