Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor which is improved in productivity.SOLUTION: In a multilayer ceramic capacitor 1, an internal electrode layer 30 is divided into M pieces of groups G and independent, and N pieces are continued in a lamination direction T (M and N are natural numbers equal to or more than 2). On a cross section of a central part of a laminate 10 in a length direction L, regarding m-th group G ((m) is a natural number equal to or more than 1 and equal to or less than M-1) and a (m+1)th group, a deviation amount between an n-th ((n) is a natural number equal to or more than 1 and equal to or less than N-1) internal electrode layer and a (n+1)th internal electrode layer in a width direction W is within α1 and between the m-th group G and the (m+1)th group G, when a deviation amount in the width direction W which is adjacent to the lamination direction T is defined as β1, α1<β1 is satisfied. Regarding the m-th group G and the (m+1)th group, between the internal electrode layers connected to the same external electrode, a deviation amount of ends not connected thereto in the length direction is smaller than a deviation amount of ends not connected with the external electrode in the length direction between the most proximate internal electrode layers connected to the same external electrode between the m-th group G and the (m+1)th group.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Conventionally, a multilayer ceramic capacitor has been known that includes a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked in a stacking direction, and a pair of external electrodes that are arranged at both ends of the laminate in the longitudinal direction and connected to the internal electrode layers.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor comprising a laminated chip having a substantially rectangular parallelepiped shape in which dielectric layers mainly composed of ceramic and internal electrode layers are alternately laminated, with a plurality of the laminated internal electrode layers being exposed at two end faces that alternately face each other, and external electrodes formed on the two end faces, the external electrodes having a structure in which a plating layer is formed on a base layer, and at least a portion of the surface of the base layer includes a region in which the bottom-to-peak height is 0.4 μm or more and the average spacing between local peaks is 0.5 μm or less. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-182106 A Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, the capacity of multilayer ceramic capacitors has increased, resulting in a structure in which many internal electrode layers are laminated. In an example of Patent Document 1, it is described that 1,000 dielectric green sheets on which a conductive paste for forming internal electrodes is printed are stacked, and cover sheets made of a material with the same main component as the dielectric green sheets are stacked on top and bottom of the stack.

[0006] However, in the method of laminating 1,000 or more dielectric green sheets at once, if even one defect occurs, it is necessary to laminate 1,000 or more new dielectric green sheets, which results in a significant decrease in the productivity of multilayer ceramic capacitors.

[0007] The present invention has been made to solve the above problems, and an object of the present invention is to provide a multilayer ceramic capacitor that can be produced with excellent productivity. [Means for solving the problem]

[0008] The multilayer ceramic capacitor of the present invention includes a laminate including a plurality of dielectric layers and a plurality of internal electrode layers laminated in a lamination direction, and having a first main surface and a second main surface opposing each other in the lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction, and a pair of external electrodes arranged to cover the first end surface and the second end surface of the laminate, respectively, and connected to the internal electrode layers. The plurality of internal electrode layers are divided into M sets (M is a natural number of 2 or more). Each of the M sets independently includes N (N is a natural number of 2 or more) of the internal electrode layers continuously in the lamination direction. The total number of the internal electrode layers included in the first to Mth sets is 1000 or more. The thickness of the dielectric layer is 0.8 μm or more. When viewing a cross section including the width direction and the stacking direction at the center of the length direction in the laminate, in at least one pair of the mth (m is a natural number greater than or equal to 1 and less than or equal to M-1) set and the m+1th set, the widthwise deviation amount between the nth (n is a natural number greater than or equal to 1 and less than or equal to N-1) internal electrode layer and the n+1th internal electrode layer is within α1, and when the widthwise deviation amount of the internal electrode layers adjacent to each other in the stacking direction between the mth set and the m+1th set is β1, α1<β1 is satisfied. When viewing a cross section including the length direction and the stacking direction at the center of the width direction in the laminate, in the m-th set and the m+1-th set, the amount of deviation in the length direction of ends of the internal electrode layers connected to the same external electrode that are not connected to the external electrode is within α2, and when the amount of deviation in the length direction of ends of the closest internal electrode layers connected to the same external electrode between the m-th set and the m+1-th set is β2, α2<β2 is satisfied. Effect of the Invention

[0009] According to the present invention, a multilayer ceramic capacitor with excellent productivity can be provided. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a perspective view illustrating an example of a multilayer ceramic capacitor according to the present invention. [Diagram 2] FIG. 2 is an example of a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along line II-II, taken along a line WT including a width direction W and a lamination direction T. In FIG. [Diagram 3] FIG. 3 is an example of a LT cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along line III-III and including the length direction L and lamination direction T. [Figure 4] FIG. 4 is a cross-sectional view showing a schematic example of a state in which the ends in the width direction of the internal electrode layers are curved. [Diagram 5] FIG. 5 is a cross-sectional view showing a schematic example of a state in which the end portions in the longitudinal direction of the internal electrode layers are curved. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The multilayer ceramic capacitor of the present invention will be described below. Note that the present invention is not limited to the following embodiments, and can be modified as appropriate within the scope of the present invention. In addition, a combination of two or more of the individual preferred configurations described in the following embodiments also constitutes the present invention.

[0012] In this specification, terms indicating the relationship between elements (e.g., "vertical," "parallel," "orthogonal," etc.) and terms indicating the shapes of elements are not intended to be used in a strict sense, but are intended to include a range of substantial equivalence, for example, a difference of a few percent.

[0013] The drawings shown below are schematic diagrams, and the dimensions, scale of aspect ratio, etc. may differ from those of the actual product. In particular, the number of internal electrode layers does not reflect the actual product. In the drawings, the same reference numerals are used for the same or corresponding parts. In addition, the same reference numerals are used for the same elements in each drawing, and duplicate explanations are omitted.

[0014] FIG. 1 is a perspective view illustrating an example of a multilayer ceramic capacitor according to the present invention.

[0015] 1 includes a laminate 10 and a pair of external electrodes 11 and 12. In the laminate 1 and the laminate 10, the length direction, width direction and lamination direction are defined by double-headed arrows L, W and T, respectively.

[0016] (Laminate) The laminate 10 has a first main surface 10a and a second main surface 10b facing each other in a stacking direction T, a first side surface 10c and a second side surface 10d facing each other in a width direction W perpendicular to the stacking direction T, and a first end surface 10e and a second end surface 10f facing each other in a length direction L perpendicular to the stacking direction T and the width direction W. The laminate 10 has, for example, a rectangular parallelepiped shape.

[0017] At least one of the corners and ridges of the laminate 10 may be rounded. Here, a corner is a portion where three faces of the laminate 10 intersect, and a ridge is a portion where two faces of the laminate 10 intersect.

[0018] Fig. 2 is an example of a WT cross-sectional view including a width direction W and a stacking direction T along line II-II of the multilayer ceramic capacitor shown in Fig. 1. Fig. 3 is an example of an LT cross-sectional view including a length direction L and a stacking direction T along line III-III of the multilayer ceramic capacitor shown in Fig. 1.

[0019] The laminate 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in a stacking direction T.

[0020] The number of the dielectric layers 20 is 1000 or more.

[0021] The dielectric material constituting the dielectric layer 20 is, for example, BaTiO 3 , SrTiO 3A dielectric ceramic containing the above-mentioned components as main components is used. Furthermore, components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc., which are contained in smaller amounts than the main components, may be added to these main components.

[0022] The thickness of the dielectric layer 20 between the internal electrode layers 30 is, for example, 0.8 μm or more. On the other hand, the thickness of the dielectric layer 20 between the internal electrode layers 30 is, for example, 1.2 μm or less.

[0023] An outer layer portion 25 formed by laminating only the dielectric layers 20 may be provided on the outside of the plurality of dielectric layers 20 and the plurality of internal electrode layers 30 laminated in the lamination direction T. The outer layer portion 25 is a dielectric layer located on both main surface sides of the laminate 10 and located between the main surface and the internal electrode layer 30 closest to the main surface. On the other hand, the region sandwiched between both outer layer portions 25 can also be referred to as an inner layer portion.

[0024] The thickness of the outer layer portion 25 is preferably 30 μm or more and 200 μm or less.

[0025] The multiple internal electrode layers 30 include a first internal electrode layer 31 and a second internal electrode layer 32, as shown in FIG.

[0026] The first internal electrode layer 31 has a first opposing electrode portion 31a facing the second internal electrode layer 32 via the dielectric layer 20, and a first extraction electrode portion 31b extending from the first opposing electrode portion 31a to the first end face 10e of the laminate 10.

[0027] The second internal electrode layer 32 has a second opposing electrode portion 32a facing the first internal electrode layer 31 via the dielectric layer 20, and a second extraction electrode portion 32b extending from the second opposing electrode portion 32a to the second end face 10f of the laminate 10.

[0028] In the laminate 10, a W gap is formed between one end in the width direction W of the first opposing electrode portion 31a and the second opposing electrode portion 32a and the first side surface 10c, and between the other end in the width direction W of the first opposing electrode portion 31a and the second opposing electrode portion 32a and the second side surface 10d. Furthermore, in the laminate 10, an L gap is formed between an end of the first internal electrode layer 31 opposite to the first extraction electrode portion 31b and the second end surface 10f, and between an end of the second internal electrode layer 32 opposite to the second extraction electrode portion 32b and the first end surface 10e.

[0029] The dimension of the W gap in the width direction W of the laminate 10 is preferably 30 μm or more and 100 μm or less.

[0030] The dimension of the L gap of the laminate 10 in the length direction L is preferably 30 μm or more and 100 μm or less.

[0031] In this embodiment, in each opposing electrode portion, a capacitance is formed by the internal electrode layers 30 opposing each other via the dielectric layer 20. This allows the multilayer ceramic capacitor 1 to function as a capacitor.

[0032] 2 and 3, the internal electrode layers 30 are divided into M (M is a natural number of 2 or more) sets G. In the example shown in Fig. 2 and 3, the internal electrode layers 30 are divided into five sets G.

[0033] The number M of sets G may be 3 or more, 4 or more, 5 or more, 10 or more, etc. On the other hand, the number M of sets G may be, for example, 100 or less, 50 or less, 40 or less, 30 or less, 25 or less, 20 or less, 15 or less, etc.

[0034] Each of the M sets G independently includes N (N is a natural number of 2 or more) internal electrode layers 30 successively arranged in the stacking direction T. In the example shown in Fig. 2 and Fig. 3, five sets G include three or two internal electrode layers 30 successively arranged in the stacking direction T.

[0035] The total number of the internal electrode layers 30 included in the first to Mth sets G is 1000 or more. On the other hand, the total number of the internal electrode layers 30 included in the first to Mth sets G may be, for example, 10000 or less, 5000 or less, 4500 or less, 4000 or less, 3500 or less, 3000 or less, 2500 or less, or 2000 or less.

[0036] Each set G preferably includes 100 or more internal electrode layers 30. That is, the number N of the internal electrode layers 30 included in each set G is preferably 100 or more. On the other hand, the number N of the internal electrode layers 30 included in each set G may be, for example, 500 or less, 400 or less, 300 or less, 250 or less, 200 or less, 150 or less, etc.

[0037] As shown in FIG. 2, when looking at a cross section (i.e., a WT cross section) including the width direction W and the stacking direction T at the center of the length direction L of the laminate 10, in at least one pair of an mth (m is a natural number greater than or equal to 1 and less than or equal to M-1) set G and an m+1th set G, the amount of misalignment in the width direction W between the nth (n is a natural number greater than or equal to 1 and less than or equal to N-1) internal electrode layer 30 and the n+1th internal electrode layer 30 is within α1, and when the amount of misalignment in the width direction W of adjacent internal electrode layers 30 in the stacking direction T between the mth set G and the m+1th set G is β1, α1<β1 is satisfied.

[0038] In the M sets, it is sufficient that the above relationship is satisfied between at least one pair of sets G. Therefore, although there may be a pair of sets G that does not satisfy the above relationship, it is preferable that the above relationship is satisfied between all sets G. The same applies below.

[0039] In this embodiment, the mth and (m+1)th laminate blocks are prepared in advance and then compressed together. For ease of handling, it is preferable to laminate a dielectric sheet thicker than the dielectric sheet on which the internal electrode pattern is printed on the top and bottom layers of each laminate block. By preparing the multilayer ceramic capacitor 1 in this manner, for example, if a defect occurs in the mth laminate block, it is only necessary to re-stack only the mth laminate block, thereby improving the productivity of the multilayer ceramic capacitor 1.

[0040] The deviation amount α1 of the internal electrode layer 30 in the width direction W is, for example, not less than 0 μm and not more than 20 μm. Between different sets G, the deviation amount α1 of the internal electrode layer 30 in the width direction W may be the same or different.

[0041] The amount of deviation β1 of the internal electrode layers 30 in the width direction W is, for example, 100 μm or more and 500 μm or less. Between different sets G, the amount of deviation β1 of the internal electrode layers 30 in the width direction W may be the same or different.

[0042] Furthermore, as shown in Figure 3, when looking at a cross section (i.e., an LT cross section) of the laminate 10 including the length direction L and the stacking direction T at the center of the width direction W, in the mth set G and the m+1th set G, the amount of deviation in the length direction L of the ends not connected to the external electrode 11 or 12 between the internal electrode layers 30 connected to the same external electrode 11 or 12 is within α2, and when the amount of deviation in the length direction L of the ends not connected to the external electrode 11 or 12 between the closest internal electrode layers 30 connected to the same external electrode 11 or 12 between the mth set G and the m+1th set G is β2, α2<β2 is satisfied.

[0043] The deviation amount α2 in the length direction L of the internal electrode layer 30 is, for example, 0 μm or more and 20 μm or less. Between different sets G, the deviation amount α2 in the length direction L of the internal electrode layer 30 may be the same or different. The deviation amount α2 in the length direction L of the internal electrode layer 30 may be the same as the deviation amount α1 in the width direction W of the internal electrode layer 30, may be smaller than the deviation amount α1 in the width direction W of the internal electrode layer 30, or may be larger than the deviation amount α1 in the width direction W of the internal electrode layer 30.

[0044] The deviation amount β2 in the length direction L of the internal electrode layer 30 is, for example, 100 μm or more and 500 μm or less. Between different sets G, the deviation amount β2 in the length direction L of the internal electrode layer 30 may be the same or different. The deviation amount β2 in the length direction L of the internal electrode layer 30 may be the same as the deviation amount β1 in the width direction W of the internal electrode layer 30, may be smaller than the deviation amount β1 in the width direction W of the internal electrode layer 30, or may be larger than the deviation amount β1 in the width direction W of the internal electrode layer 30.

[0045] As described above, it is preferable that a dielectric layer 20 that can be independently handled is disposed on the outermost layer of each set G. Therefore, when the distance between the internal electrode layers 30 in the m-th set G is t1 and the distance between the internal electrode layers 30 between the m-th set G and the (m + 1)-th set G is t2, it is preferable to satisfy t1 < t2.

[0046] By increasing the thickness between the sets G, the strain in the stacking direction T due to the piezoelectric effect generated between the sets G can be absorbed, so that the reliability of the multilayer ceramic capacitor 1 is improved.

[0047] The distance t1 between the internal electrode layers 30 is, for example, 0.8 μm or more and 1.2 μm or less. Between different sets G, the distance t1 between the internal electrode layers 30 may be the same or different.

[0048] On the one hand, the distance t2 between the internal electrode layers 30 satisfies, for example, t1 < t2 and is 1.2 μm or more and 5 μm or less. For example, when t1 = 1.2 μm, it is preferable that t2 > 1.2 μm. The distance t2 between the internal electrode layers 30 may be the same or different between different sets G.

[0049] When the number of internal electrode layers 30 included in the m-th set G is N1 and the number of internal electrode layers 30 included in the (m + 1)-th set G is N2, N1 and N2 may be the same or different. Thus, the number of internal electrode layers 30 included in each set G may all be the same or at least some may be different.

[0050] When looking at a cross-section including the length direction L and the stacking direction T at the center of the width direction W in the laminate 10, the internal electrode layers 30 closest to each other between the m-th set G and the (m + 1)-th set G are preferably connected to the same external electrode 11 or 12. In this case, since electric strain is less likely to occur between the m-th set G and the (m + 1)-th set G, the reliability of the multilayer ceramic capacitor 1 is further improved.

[0051] In the m-th set G, at least one of the end portions in the width direction W and the end portions in the length direction L of the internal electrode layer 30 may be curved in the same direction in the stacking direction T. In this case, since the directions in which the end portions of the internal electrode layer 30 are curved are aligned, the reliability of the multilayer ceramic capacitor 1 is improved.

[0052] When the end of the internal electrode layer 30 in the width direction W is curved, one end in the width direction W may be curved in the same internal electrode layer 30, or both ends in the width direction W may be curved. When both ends are curved, it is preferable that both ends are curved in the same direction of the stacking direction T. In the same set G, internal electrode layers 30 with one end in the width direction W curved and internal electrode layers 30 with both ends in the width direction W curved may be mixed. In addition, in the same set G, internal electrode layers 30 with an end in the width direction W curved and internal electrode layers 30 with an end in the width direction W not curved may be mixed.

[0053] When the end of the internal electrode layer 30 in the length direction L is curved, it is sufficient that the end not connected to the external electrode 11 or 12 is curved. In this case, only the end not connected to the external electrode 11 may be curved, only the end not connected to the external electrode 12 may be curved, or both ends may be curved. When both ends are curved, it is preferable that both ends are curved in the same direction of the stacking direction T. In the same set G, internal electrode layers 30 whose ends in the length direction L are curved and internal electrode layers 30 whose ends in the length direction L are not curved may be mixed.

[0054] FIG. 4 is a cross-sectional view showing a schematic example of a state in which the ends in the width direction of the internal electrode layers are curved.

[0055] In the example shown in FIG. 4, the ends of the internal electrode layers 30 in the width direction W are curved in the same direction as the stacking direction T (downward in FIG. 4).

[0056] FIG. 5 is a cross-sectional view showing a schematic example of a state in which the end portions in the longitudinal direction of the internal electrode layers are curved.

[0057] In the example shown in FIG. 5, the end portions in the length direction L of the internal electrode layers 30 (for example, the first internal electrode layers 31) are curved in the same direction as the stacking direction T (downward in FIG. 5).

[0058] Although not shown in Figures 4 and 5, in the (m+1)th set G, at least one of the ends in the width direction W and the length direction L of the internal electrode layer 30 may be curved in the same direction of the stacking direction T.

[0059] In the above case, the direction in which the ends of the internal electrode layers 30 are curved may be the same between the m-th set G and the (m+1)-th set G. For example, the stacking direction of the m-th laminate block and the (m+1)-th laminate block may be the same.

[0060] Alternatively, the direction in which the end of the internal electrode layer 30 is curved may be different between the mth set G and the m+1th set G. For example, the stacking directions of the mth laminate block and the m+1th laminate block may be different. In some cases, making the stacking directions of the laminate blocks different can reduce distortion of the entire laminate block.

[0061] In addition, among the first to M-th sets G, the direction in which the end of the internal electrode layer 30 is curved may be the same in all sets G, or the direction in which the end of the internal electrode layer 30 is curved may be different in at least some sets G. Also, a set G in which the end of the internal electrode layer 30 is not curved may be included.

[0062] The amount of misalignment and the direction of curvature can be observed and measured using an optical microscope after polishing the laminate 10 so that each cross section is exposed.

[0063] (external electrode) A pair of external electrodes 11 and 12 are disposed so as to cover the first end face 10e and the second end face 10f of the laminate 10, respectively, and are connected to the internal electrode layer 30.

[0064] The external electrode 11 is disposed so as to cover the first end face 10e of the laminate 10, and is connected to the first internal electrode layer 31. The external electrode 11 may extend from the first end face 10e to the first main face 10a, the second main face 10b, the first side face 10c, and the second side face 10d.

[0065] The external electrode 12 is disposed so as to cover the second end face 10f of the laminate 10, and is connected to the second internal electrode layer 32. The external electrode 12 may extend from the second end face 10f to the first main face 10a, the second main face 10b, the first side face 10c, and the second side face 10d.

[0066] For example, each of the external electrodes 11 and 12 includes a base electrode layer and a plating layer disposed on the base electrode layer.

[0067] The base electrode layer includes at least one layer selected from, for example, a baked layer, a resin layer, a thin film layer, and the like.

[0068] The baked layers include, for example, glass and metal.

[0069] The baked layer contains at least one metal selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like.

[0070] The baked layer may be multiple layers.

[0071] The baked layer is a layer formed by applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be formed by simultaneous baking with the internal electrode layer, or may be formed by baking after baking the internal electrode layer.

[0072] The resin layer may include, for example, a resin layer containing conductive particles and a thermosetting resin. The resin layer may be formed directly on the laminate without forming a baked layer.

[0073] The resin layer may be a multi-layered layer.

[0074] The thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness in which metal particles are deposited.

[0075] The plating layer contains at least one metal selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like.

[0076] The plating layer may be a multi-layered layer. The plating layer preferably has a two-layer structure of a Ni plating layer and a Sn plating layer. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the multilayer ceramic capacitor, and the Sn plating layer can improve the wettability of the solder when mounting the multilayer ceramic capacitor, making it easy to mount.

[0077] The external electrodes 11 and 12 may each have a plating layer that is provided directly on the laminate 10 and directly connected to the internal electrode layer 30. However, a catalyst may be provided on the laminate 10 as a pretreatment.

[0078] The plating layer preferably includes a first plating layer and a second plating layer provided on the first plating layer.

[0079] The first plating layer and the second plating layer preferably include, for example, a plating of one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or a plating of an alloy containing at least one of the above metals.

[0080] For example, when Ni is used as the internal electrode layer 30, it is preferable to use Cu, which has good bonding properties with Ni, as the first plating layer. It is also preferable to use Sn or Au, which has good solder wettability, as the second plating layer, and it is preferable to use Ni, which has solder barrier properties, as the first plating layer.

[0081] The second plating layer is formed as necessary, and the external electrodes 11 and 12 may be composed of the first plating layer.

[0082] The second plating layer may be provided as the outermost plating layer, or another plating layer may be provided on the second plating layer.

[0083] The plating layer preferably does not contain glass.

[0084] The metal ratio per unit volume of the plating layer is preferably 99 volume % or more.

[0085] The plating layer is formed by grain growth along the thickness direction, and is preferably columnar.

[0086] (Internal electrode layer) The internal electrode layers 30 contain a metal such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.

[0087] The internal electrode layers 30 may further contain dielectric particles having the same composition as the ceramics contained in the dielectric layers 20 .

[0088] The number of the internal electrode layers 30 is preferably 1000 or more.

[0089] The thickness of the internal electrode layer 30 is preferably 0.8 μm or more and 1.2 μm or less.

[0090] (Multilayer ceramic capacitors) When the dimension in the longitudinal direction L of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 11 and 12 is defined as dimension L, the dimension L of the multilayer ceramic capacitor 1 is, for example, not less than 1.0 mm and not more than 3.2 mm.

[0091] When the dimension in the width direction W of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 11 and 12 is defined as dimension W, the dimension W of the multilayer ceramic capacitor 1 is, for example, not less than 0.5 mm and not more than 1.6 mm.

[0092] When the dimension in the lamination direction T of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 11 and 12 is defined as dimension T, the dimension T of the multilayer ceramic capacitor 1 is, for example, not less than 0.5 mm and not more than 1.6 mm.

[0093] The L dimension of the multilayer ceramic capacitor 1 may be the same as the W dimension or T dimension of the multilayer ceramic capacitor 1, may be larger than the W dimension or T dimension of the multilayer ceramic capacitor 1, or may be smaller than the W dimension or T dimension of the multilayer ceramic capacitor 1. The W dimension of the multilayer ceramic capacitor 1 may be the same as the T dimension of the multilayer ceramic capacitor 1, may be larger than the T dimension of the multilayer ceramic capacitor 1, or may be smaller than the T dimension of the multilayer ceramic capacitor 1.

[0094] Usually, these dimensions are values ​​that do not include tolerances, but in this specification, dimensions including tolerances are also included within the scope of the present invention.

[0095] The thickness of each of the plurality of dielectric layers 20 and the plurality of internal electrode layers 30 is measured as follows. First, the WT cross section of the laminate 10 exposed by polishing is observed with a scanning electron microscope. Next, the thickness is measured along a center line along the stacking direction T that passes through the center of the WT cross section of the laminate 10, and along two lines drawn equally spaced on each side of this center line, for a total of five lines. The average of these five measured values ​​is taken as the thickness of each layer. To obtain a more accurate thickness, the above five measured values ​​are obtained for each of the upper, middle, and lower parts in the stacking direction T, and the average of these measured values ​​is taken as the thickness of each layer.

[0096] (Manufacturing method of multilayer ceramic capacitors) The multilayer ceramic capacitor of the present invention is preferably produced by the following method.

[0097] (1) Prepare a dielectric sheet and a conductive paste for internal electrodes. The dielectric sheet and the conductive paste for internal electrodes contain a binder and a solvent, and known organic binders and organic solvents can be used.

[0098] (2) On a dielectric sheet, a conductive paste for internal electrodes is printed in a predetermined pattern by a method such as screen printing or gravure printing to form an internal electrode pattern.

[0099] (3) A predetermined number of dielectric sheets for outer layers on which no internal electrode pattern is printed are stacked, then dielectric sheets on which an internal electrode pattern is printed are stacked in sequence on top of the stacked dielectric sheets, and then a predetermined number of dielectric sheets for outer layers are stacked on top of the stacked dielectric sheets to produce a laminated sheet.

[0100] (4) The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block. Note that pressing is not essential.

[0101] The above steps (1) to (4) are repeated to prepare a plurality of laminate blocks. In this case, it is preferable to laminate only a plurality of dielectric sheets as outer layers on the top and bottom of the laminate block, since this makes it easier to handle in the subsequent steps.

[0102] The distortion of each laminated block is measured, and the blocks are stacked so that the overall distortion is minimized, and then pressed. When stacking, it is preferable to shift each block by a certain distance to increase reliability.

[0103] To improve adhesion, binder rich dielectric sheets may be placed between the stacked blocks.

[0104] (5) The laminated block is cut to a predetermined size to obtain laminated chips. At this time, the corners and edges of the laminated chips may be rounded by a method such as barrel polishing.

[0105] (6) The laminated chip is fired to produce a laminate. The firing temperature depends on the materials of the dielectric layers and the internal electrode layers, but is preferably 900° C. or higher and 1300° C. or lower.

[0106] (When the external electrodes are baked layers) (7) A conductive paste for external electrodes is applied to both end surfaces of the laminate, and then baked to form baked layers for the external electrodes. The baking temperature is preferably 700° C. or higher and 900° C. or lower.

[0107] (8) If necessary, the surface of the baked layer may be plated.

[0108] (When the external electrode is a plating electrode) A plated electrode may be formed directly on the surface of the laminate as an external electrode without providing a baked layer. In that case, the following steps (7') and (8') are carried out instead of the above steps (7) and (8).

[0109] (7') Plating is applied to both end surfaces of the laminate to form a base plating layer on the exposed portion of the internal electrode layer. Either electrolytic plating or electroless plating may be used for plating, but electroless plating has the disadvantage that it requires pretreatment with a catalyst or the like to improve the plating deposition speed, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. As a plating method, it is preferable to use barrel plating.

[0110] (8') If necessary, a plating treatment may be further carried out on the surface of the plating layer.

[0111] The present specification discloses the following:

[0112] <1> a laminate including a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction, and having a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of external electrodes arranged to cover the first end surface and the second end surface of the laminate, respectively, and connected to the internal electrode layer; The plurality of internal electrode layers are divided into M sets (M is a natural number of 2 or more), Each of the M sets independently includes N (N is a natural number of 2 or more) of the internal electrode layers continuously arranged in the stacking direction, The total number of the internal electrode layers included in the first to Mth sets is 1000 or more, The thickness of the dielectric layer is 0.8 μm or more, When a cross section including the width direction and the stacking direction in the center part in the longitudinal direction of the laminate is viewed, In at least one pair of the m-th set (m is a natural number of 1 to M-1) and the m+1-th set, the widthwise deviation between the n-th (n is a natural number of 1 to N-1) internal electrode layer and the n+1-th internal electrode layer is within α1, and When a shift amount in the width direction of the internal electrode layers adjacent to each other in the stacking direction between the m-th set and the (m+1)-th set is β1, α1<β1 is satisfied; When a cross section including the length direction and the stacking direction in the center part in the width direction of the laminate is viewed, In the m-th set and the m+1-th set, the amount of deviation in the length direction between the ends of the internal electrode layers connected to the same external electrode that are not connected to the external electrode is within α2, and When a shift amount in the length direction of ends of the internal electrode layers that are not connected to the external electrode and that are closest to each other and connected to the same external electrode between the mth set and the m+1th set is β2, α2<β2 is satisfied. Multilayer ceramic capacitor.

[0113] <2> In the m-th set, at least one of the width direction end portion and the length direction end portion of the internal electrode layer is curved in the same direction of the lamination direction. <1> The multilayer ceramic capacitor according to claim 1 .

[0114] <3> Furthermore, in the (m + 1)-th set, at least one of the end portions in the width direction and the end portions in the length direction of the internal electrode layer is curved in the same direction in the stacking direction. Between the m-th set and the (m + 1)-th set, the directions in which the end portions of the internal electrode layer are curved are the same. The multilayer ceramic capacitor according to <2>.

[0115] <4> Furthermore, in the (m + 1)-th set, at least one of the end portions in the width direction and the end portions in the length direction of the internal electrode layer is curved in the same direction in the stacking direction. Between the m-th set and the (m + 1)-th set, the directions in which the end portions of the internal electrode layer are curved are different. The multilayer ceramic capacitor according to <2>.

[0116] <5> When the distance between the internal electrode layers in the m-th set is t1 and the distance between the internal electrode layers between the m-th set and the (m + 1)-th set is t2, t1 < t2 is satisfied. The multilayer ceramic capacitor according to any one of <1> to <4>.

[0117] <6> When the number of the internal electrode layers included in the m-th set is N1 and the number of the internal electrode layers included in the (m + 1)-th set is N2, N1 and N2 are different. The multilayer ceramic capacitor according to any one of <1> to <5>.

[0118] <7> When looking at a cross section including the length direction and the stacking direction at the central portion in the width direction of the laminate, the closest internal electrode layers between the m-th set and the (m + 1)-th set are connected to the same external electrode. The multilayer ceramic capacitor according to any one of <1> to <6>. [Explanation of symbols]

[0119] 1. Multilayer ceramic capacitors 10 Laminate 10a First main surface 10b Second main surface 10c First aspect 10d. Second Aspect 10e First end face 10f Second end face 11, 12 External electrode 20 Dielectric layer 25 Outer layer 30 Internal electrode layer 31 First internal electrode layer 31a first counter electrode portion 31b First extraction electrode portion 32 Second internal electrode layer 32a Second opposing electrode portion 32b Second extraction electrode portion α1 Misalignment amount in the width direction between the nth internal electrode layer and the n+1th internal electrode layer α2 Displacement in the length direction between the nth internal electrode layer and the n+1th internal electrode layer β1 The amount of misalignment in the width direction between the mth set and the (m+1)th set of adjacent internal electrode layers in the stacking direction β2 The amount of misalignment in the length direction between the mth set and the (m+1)th set of adjacent internal electrode layers in the stacking direction t1 Distance between internal electrode layers in the mth set t2 Distance between the internal electrode layers between the mth set and the m+1th set G set L Length direction T Stacking direction W Width direction

Claims

1. a laminate including a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction, and having a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of external electrodes arranged to cover the first end surface and the second end surface of the laminate, respectively, and connected to the internal electrode layer; The plurality of internal electrode layers are divided into M sets (M is a natural number of 2 or more), Each of the M sets independently includes N (N is a natural number of 2 or more) internal electrode layers continuously arranged in the stacking direction, the total number of the internal electrode layers included in the first to Mth sets is 1000 or more; The thickness of the dielectric layer is 0.8 μm or more, When a cross section including the width direction and the stacking direction in the center portion of the longitudinal direction of the laminate is viewed, In at least one pair of the m-th set (m is a natural number of 1 to M-1) and the m+1-th set, the misalignment amount in the width direction between the n-th (n is a natural number of 1 to N-1) internal electrode layer and the n+1-th internal electrode layer is within α1, When a shift amount in the width direction of the internal electrode layers adjacent to each other in the stacking direction between the m-th set and the m+1-th set is β1, α1<β1 is satisfied, When a cross section including the length direction and the stacking direction in the center part in the width direction of the laminate is viewed, In the m-th set and the m+1-th set, the amount of deviation in the length direction of the ends of the internal electrode layers connected to the same external electrode that are not connected to the external electrode is within α2, and When a shift amount in the length direction of the end portions not connected to the external electrode between the internal electrode layers that are closest to each other and connected to the same external electrode between the m-th set and the m+1-th set is β2, α2<β2 is satisfied. Multilayer ceramic capacitor.

2. In the m-th set, at least one of the width direction end portion and the length direction end portion of the internal electrode layer is curved in the same direction of the lamination direction. The multilayer ceramic capacitor according to claim 1 .

3. Furthermore, in the m+1-th set, at least one of the width direction end portion and the length direction end portion of the internal electrode layer is curved in the same direction of the lamination direction, The direction in which the ends of the internal electrode layers are curved is the same between the mth set and the (m+1)th set. The multilayer ceramic capacitor according to claim 2 .

4. Furthermore, in the m+1-th set, at least one of the width direction end portion and the length direction end portion of the internal electrode layer is curved in the same direction of the lamination direction, The direction in which the end portions of the internal electrode layers are curved is different between the m-th set and the (m+1)-th set. The multilayer ceramic capacitor according to claim 2 .

5. When a distance between the internal electrode layers in the m-th set is t1 and a distance between the internal electrode layers between the m-th set and the (m+1)-th set is t2, t1<t2 is satisfied. The multilayer ceramic capacitor according to any one of claims 1 to 4.

6. When the number of the internal electrode layers included in the m-th set is N1 and the number of the internal electrode layers included in the m+1-th set is N2, N1 and N2 are different. The multilayer ceramic capacitor according to any one of claims 1 to 4.

7. When a cross section including the length direction and the stacking direction at a center part in the width direction of the laminate is viewed, the internal electrode layer that is closest to the m-th group and the (m+1)-th group is connected to the same external electrode. The multilayer ceramic capacitor according to any one of claims 1 to 4.

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