Information processing device, processing method, and program

Abstract

To provide an information processing device capable of performing information processing using a plurality of FPGAs and reducing a mounting area of a substrate.SOLUTION: An information processing device comprises: a first FPGA; a second FPGA; a configuration memory which is sealed in one package and stores information on the circuit configuration set in the first FPGA and the second FPGA; a first logic device which controls first processing in the first FPGA and when first processing is not controlled, puts the own terminal connected to the first FPGA or the configuration memory into a cut-off state; a second logic device which controls second processing in the second FPGA and when second processing is not controlled, puts the own terminal connected to the second FPGA or the configuration memory into the cut-off state; a signal line which directly connects the first FPGA and the configuration memory; and a signal line which directly connects the second FPGA and the configuration memory.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to an information processing device, a processing method, and a program. [Background technology]

[0002] Field programmable gate arrays (FPGAs) are used in various information processing. When the FPGA is started, it acquires information about the circuit configuration stored in a configuration memory, and the circuit is configured by making settings in the FPGA according to the acquired information. Patent Document 1 discloses a related technology, which is a technology about a configuration device that supplies configuration data to multiple FPGAs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2008 / 152697 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in an information processing device that executes information processing using multiple FPGAs, the mounting area on the board increases due to an increase in FPGAs, configuration memory, etc. Therefore, there is a demand for a technology that can reduce the mounting area on the board of an information processing device that executes information processing using multiple FPGAs.

[0005] An object of each aspect of the present disclosure is to provide an information processing device, a processing method, and a program that can solve the above-mentioned problems. [Means for solving the problem]

[0006] In order to achieve the above object, according to one aspect of the present disclosure, an information processing device includes a first FPGA (Field Programmable Gate Array), a second FPGA, a configuration memory sealed in a single package and storing information regarding circuit configurations set in the first FPGA and the second FPGA, a first logic device that controls processing of a first configuration in the first FPGA and, when the processing of the first configuration is not controlled, turns off its own terminals connected to the first FPGA or the configuration memory, a second logic device that controls processing of a second configuration in the second FPGA and, when the processing of the second configuration is not controlled, turns off its own terminals connected to the second FPGA or the configuration memory, a signal line that directly connects the first FPGA and the configuration memory, and a signal line that directly connects the second FPGA and the configuration memory.

[0007] In order to achieve the above-mentioned object, according to another aspect of the present disclosure, a processing method is executed by an information processing device including a first FPGA (Field Programmable Gate Array), a second FPGA, a configuration memory sealed in a single package and storing information regarding circuit configurations set in the first FPGA and the second FPGA, a signal line directly connecting the first FPGA and the configuration memory, and a signal line directly connecting the second FPGA and the configuration memory, the processing method including: controlling a processing of a first configuration in the first FPGA, and when the processing of the first configuration is not controlled, bringing its own terminals connected to the first FPGA or the configuration memory into a cut-off state; and controlling a processing of a second configuration in the second FPGA, and when the processing of the second configuration is not controlled, bringing its own terminals connected to the second FPGA or the configuration memory into a cut-off state.

[0008] In order to achieve the above object, according to another aspect of the present disclosure, a program causes a computer of an information processing device including a first FPGA (Field Programmable Gate Array), a second FPGA, a configuration memory sealed in a single package and storing information regarding the configuration of circuits set in the first FPGA and the second FPGA, a signal line directly connecting the first FPGA and the configuration memory, and a signal line directly connecting the second FPGA and the configuration memory to control processing of a first configuration in the first FPGA, and when control of the processing of the first configuration is not performed, to turn off its own terminals connected to the first FPGA or the configuration memory, and to control processing of a second configuration in the second FPGA, and when control of the processing of the second configuration is not performed, to turn off its own terminals connected to the second FPGA or the configuration memory. Effect of the Invention

[0009] According to each aspect of the present disclosure, it is possible to reduce the mounting area on a board of an information processing device that executes information processing using multiple FPGAs. [Brief description of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating an example of a configuration of an information processing device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram illustrating an example of a configuration of an information processing unit according to the first embodiment of the present disclosure. [Diagram 3] FIG. 2 is a diagram illustrating an example of a processing flow of the information processing device according to the first embodiment of the present disclosure. [Figure 4] FIG. 11 is a diagram illustrating an example of a configuration of an information processing device according to a second embodiment of the present disclosure. [Diagram 5] FIG. 11 is a diagram illustrating an example of a configuration of an information processing unit according to a second embodiment of the present disclosure. [Figure 6]FIG. 13 is a diagram illustrating an example of a configuration of an information processing device according to a third embodiment of the present disclosure. [Figure 7] FIG. 11 is a diagram illustrating an example of a processing flow of an information processing device according to a third embodiment of the present disclosure. [Figure 8] FIG. 1 is a diagram illustrating a minimum configuration of an information processing device according to an embodiment of the present disclosure. [Figure 9] FIG. 11 is a diagram illustrating an example of a processing flow of an information processing device with a minimum configuration according to an embodiment of the present disclosure. [Figure 10] FIG. 1 is a schematic block diagram illustrating a configuration of a computer according to at least one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described in detail with reference to the drawings. First Embodiment (Configuration of information processing device) An information processing device 1 according to a first embodiment of the present disclosure will be described with reference to the drawings. The information processing device 1 is a device that can configure circuits in multiple FPGAs (Field Programmable Gate Arrays) using a configuration memory sealed in one package at startup.

[0012] 1 is a diagram showing an example of a configuration of an information processing device 1 according to a first embodiment of the present disclosure. As shown in FIG 1, the information processing device 1 includes boards 10 and 20, and an inter-board interface (hereinafter referred to as "inter-board I / F") 30.

[0013] The board 10 is connected to the board 20 via the inter-board I / F 30. The board 10 executes information processing under instructions from the board 20. The board 10 includes a connector 101, a configuration memory 102, and an information processing unit 103, as shown in FIG.

[0014] 1, the connector 101 is connected to the board 20 via the inter-board I / F 30. The connector 101 receives a control signal from the board 20.

[0015] The configuration memory 102 is a memory contained in one package for configuring the FPGA 1031 described later. For example, the configuration memory 102 stores data for setting the configuration of a circuit in the FPGA 1031 described later that is included in the information processing unit 103 (i.e., data for configuring the FPGA 1031).

[0016] 2 is a diagram illustrating an example of a configuration of the information processing unit 103 according to the first embodiment of the present disclosure. As illustrated in FIG. 2, the information processing unit 103 includes FPGAs 1031a and 1031b, Complex Programmable Logic Devices (CPLDs) 1032a and 1032b, CONFIG interfaces (hereinafter, referred to as "CONFIG I / F") 1033a, 1033b, and 1034, and communication lines 1035a, 1035b, and 1036.

[0017] The FPGAs 1031a and 1031b may be collectively referred to as FPGA 1031. The CPLDs 1032a and 1032b may be collectively referred to as CPLD 1032. The CONFIG I / Fs 1033a and 1033b may be collectively referred to as CONFIG I / F 1033. The communication lines 1035a and 1035b may be collectively referred to as communication line 1035.

[0018] Each of the FPGAs 1031 communicates with the configuration memory 102 when the information processing device 1 is started up. An example of this communication is serial communication. Examples of serial communication include SPI (Serial Peripheral Interface) and QSPI (Quad Serial Peripheral Interface). In the first embodiment of the present disclosure, the configuration is performed in master mode (i.e., the FPGA 1031 serves as the master and the configuration memory 102 serves as the slave, and the configuration is performed).

[0019] Each of the FPGAs 1031 executes information processing to realize functions required of the information processing device 1. Each of the FPGAs 1031 receives instructions for information processing to be executed by a later-described CPU (Central Processing Unit) 202 provided on the board 20 via the inter-board I / F 30. Each of the FPGAs 1031 is an FPGA having the same function.

[0020] Each of the CPLDs 1032 is a peripheral circuit of the FPGA 1031. The CPLD 1032a manages the power supply of the FPGA 1031a. The CPLD 1032a also controls the configuration of the FPGA 1031a using the data stored in the configuration memory 102. The CPLD 1032b also manages the power supply of the FPGA 1031b. The CPLD 1032b also controls the configuration of the FPGA 1031b using the data stored in the configuration memory 102.

[0021] Each of the CPLDs 1032 shares, as control information, the startup status of the FPGA that it controls the configuration of, via the communication line 1036. This sharing of control information prevents each of the FPGAs 1031 from starting up at the same time. Also, the CPLD 1032 connected to the FPGA 1031 that is not started up fixes the connection terminals with the configuration memory 102, the CONFIG I / F 1033, and the CONFIG I / F 1034 in a cutoff state. As a result, the FPGA 1031 that is not started up and the CPLD 1032 that controls the startup of that FPGA 1031 are electrically disconnected from the other FPGA 1031 that is started up and the CPLD 1032 that controls the startup of that FPGA 1031.

[0022] As shown in FIG. 2, the CONFIG I / F 1033a connects the FPGA 1031a and the CPLD 1032a. The CONFIG I / F 1033a propagates a configuration clock signal (hereinafter, referred to as a "CCLK signal"), a chip select signal (hereinafter, referred to as a "CS signal"), and a serial input / serial output signal (hereinafter, referred to as an "SI / SO signal") between the FPGA 1031a and the CPLD 1032a. The CCLK signal is a reference signal for synchronization during configuration of the FPGA 1031. The CS signal is a memory selection signal for selecting a memory (the configuration memory 102 in each embodiment of the present disclosure) to be used during configuration of the FPGA 1031. The SI / SO signal is a data signal (a signal including data for setting the circuit configuration of the FPGA 1031 in each embodiment of the present disclosure).

[0023] The CONGIG I / F 1033b connects the FPGA 1031b and the CPLD 1032b as shown in Fig. 2. The CONGIG I / F 1033b propagates a CCLK signal, a CS signal, and an SI / SO signal between the FPGA 1031b and the CPLD 1032b.

[0024] 2, the CONFIG I / F 1034 connects the configuration memory 102 and the CPLD 1032. The CONFIG I / F 1034 propagates a CCLK signal, a CS signal, and an SI / SO signal between the configuration memory 102 and the CPLD 1032.

[0025] 2, the communication line 1035a connects the FPGA 1031a and the CPLD 1032a. When the CPLD 1032a starts configuration of the FPGA 1031a, the communication line 1035a propagates a start signal that notifies the FPGA 1031a of the start from the CPLD 1032a.

[0026] 2, the communication line 1035b connects the FPGA 1031b and the CPLD 1032b. When the CPLD 1032b starts configuration of the FPGA 1031b, the communication line 1035b propagates a start signal that notifies the FPGA 1031b from the CPLD 1032b of the start of the configuration.

[0027] 2, the communication line 1036 connects the CPLD 1032a and the CPLD 1032b. The communication line 1036 propagates control information shared between the CPLD 1032a and the CPLD 1032b. This control information includes information on the startup status of the FPGA 1031 in the configuration controlled by each of the CPLDs 1032.

[0028] By the above-mentioned connection via the CONFIG I / Fs 1033 and 1034, the FPGA 1031 and the configuration memory 102 are connected in a 2:1 ratio as shown in FIG.

[0029] Note that the processes performed by the information processing device 1 in each embodiment of the present disclosure are not limited to the processes described above. For example, the information processing device 1 may perform the processes described below.

[0030] Next, the process performed by the information processing device 1 will be described with reference to Fig. 3. Fig. 3 is a diagram showing an example of a process flow of the information processing device 1 according to the first embodiment of the present disclosure. Here, the configuration process performed by the information processing device 1 at startup to set the circuit configuration of FPGA 1031a and then set the circuit configuration of FPGA 1031b will be described with reference to Fig. 3. It is assumed that the control information shared between CPLD 1032a and CPLD 1032b includes information indicating that the circuit configuration of FPGA 1031a is set and then the circuit configuration of FPGA 1031b is set.

[0031] Based on control information shared between the CPLD 1032a and CPLD 1032b, each of the CPLDs 1032 determines to set the circuit configuration of the FPGA 1031a. Then, the CPLD 1032b connected to the FPGA 1031b in an inactive state fixes the connection terminals with the configuration memory 102, the CONFIG I / F 1033, and the CONFIG I / F 1034 to a disconnected state.

[0032] The CPLD 1032a enters a state in which it can propagate the CCLK signal, the CS signal, and the SI / SO signal between the CONFIG I / F 1033a and the CONFIG I / F 1034 (step S1). This causes the FPGA 1031a to function as the master and the configuration memory 102 to function as the slave, enabling communication between the FPGA 1031a and the configuration memory 102. The CPLD 1032a then notifies the FPGA 1031a of the start of configuration via the communication line 1035a (step S2).

[0033] The FPGA 1031a outputs a CCLK signal and a CS signal to the configuration memory 102. The configuration memory 102 is selected by this CS signal. Then, in synchronization with the CCLK signal, the configuration memory 102 transfers data for setting the configuration of the circuit in the FPGA 1031a to the FPGA 1031a as SI / SO signals (step S3).

[0034] The FPGA 1031a receives the SI / SO signal. In response to the received SI / SO signal, the FPGA 1031a configures the circuit according to the SI / SO signal (step S4). When the circuit configuration is set (i.e., when the configuration process of the FPGA 1031a is completed), the FPGA 1031a notifies the CPLD 1032a that the configuration process of the FPGA 1031a is completed. Upon receiving the notification, the CPLD 1032a outputs control information including the completion of the configuration process of the FPGA 1031a to the CPLD 1032b (step S5). As a result, the CPLD 1032b determines that the configuration process of the FPGA 1031a is completed. Then, each of the FPGAs 1031 determines to set the circuit configuration of the FPGA 1031b in response to this notification.

[0035] The CPLD 1032a connected to the FPGA 1031a in a non-activated state fixes the connection terminals with the configuration memory 102, the CONFIG I / F 1033, and the CONFIG I / F 1034 in a disconnected state.

[0036] The CPLD 1032b enters a state in which it can propagate the CCLK signal, the CS signal, and the SI / SO signal between the CONFIG I / F 1033b and the CONFIG I / F 1034 (step S6). This causes the FPGA 1031b to function as the master and the configuration memory 102 to function as the slave, enabling communication between the FPGA 1031b and the configuration memory 102. The CPLD 1032b then notifies the FPGA 1031b of the start of configuration via the communication line 1035b (step S7).

[0037] The FPGA 1031b outputs the CCLK signal and the CS signal to the configuration memory 102. The configuration memory 102 is selected by this CS signal. Then, in synchronization with the CCLK signal, the configuration memory 102 transfers data for setting the circuit configuration in the FPGA 1031b (i.e., the same data as the data for setting the circuit configuration in the FPGA 1031a) to the FPGA 1031b as an SI / SO signal (step S8).

[0038] The FPGA 1031b receives the SI / SO signal. In response to the received SI / SO signal, the FPGA 1031b configures the circuit according to the SI / SO signal (step S9). When the circuit configuration is set (i.e., when the configuration process of the FPGA 1031a is completed), the FPGA 1031b notifies the CPLD 1032b that the configuration process of the FPGA 1031b is completed. Upon receiving the notification, the CPLD 1032b outputs control information including the completion of the configuration process of the FPGA 1031b to the CPLD 1032a (step S10). As a result, each of the CPLDs 1032 determines that the configuration process of each of the FPGAs 1031 is completed. Then, each of the CPLDs 1032 ends the configuration process (step S11).

[0039] The information processing device 1 according to the first embodiment of the present disclosure has been described above. In the information processing device 1 including an FPGA (Field Programmable Gate Array) 1031a (an example of a first FPGA) and an FPGA 1031b (an example of a second FPGA), a configuration memory 102 is sealed in one package and stores information on the configuration of circuits set in the FPGA 1031a and the FPGA 1031b. A CPLD 1032a (an example of a first logic device) controls the processing of a first configuration in the FPGA 1031a, and when not controlling the processing of the first configuration, shuts off its own terminals connected to the FPGA 1031a or the configuration memory 102. CPLD 1032b (an example of a second logic device) controls the processing of the second configuration in FPGA 1031b, and when not controlling the processing of the second configuration, blocks its own terminals connected to FPGA 1031b or the configuration memory 102.

[0040] This information processing device 1 allows a configuration memory sealed in one package to be shared by multiple FPGAs. As a result, this information processing device 1 can reduce the mounting area on the board of an information processing device that executes information processing using multiple FPGAs.

[0041] <Second embodiment> (Configuration of information processing device) In the first embodiment of the present disclosure, the information processing device 1 has been described as being configured in master mode (i.e., the FPGA 1031 serves as the master and the configuration memory 102 serves as the slave to perform the configuration). However, in another embodiment of the present disclosure, the configuration may be configured in slave mode (i.e., the configuration memory 102 may exist outside the information processing device 1, the external CPU serves as the master, and the FPGA 1031 serves as the slave to perform the configuration).

[0042] FIG. 4 is a diagram showing an example of the configuration of the information processing device 1 according to the second embodiment of the present disclosure. FIG. 5 is a diagram showing an example of the configuration of the information processing unit 103 according to the second embodiment of the present disclosure. In addition to the information processing unit 103, FIG. 5 also shows connectors 101, 201, and a configuration memory 102. As shown in FIG. 4, the information processing device 1 includes boards 10, 20, and an inter-board I / F 30. As shown in FIG. 5, the information processing unit 103 is connected to the connector 101 via a CONFIG I / F 1034. As shown in FIG. 5, the connector 101 is connected to a connector 201 of the board 20 via the inter-board I / F 30. As shown in FIG. 5, the connector 201 is connected to the configuration memory 102.

[0043] The configuration process of each FPGA 1031 is executed as follows. That is, the CPU 202 of the board 20 outputs a CCLK signal and a CS signal to the FPGA 1031 and the configuration memory 102, whereby the configuration memory 102 is selected and synchronized by the CCLK signal. Each CPLD 1032 operates in the same manner as the information processing device 1 according to the first embodiment of the present disclosure. Then, the configuration memory 102 outputs an SI / SO signal to the FPGA 1031, which is the target of the configuration process, via the connector 201, the inter-board I / F 30, the connector 101, and the CONFIG I / F 1034, in the same manner as the first embodiment of the present disclosure.

[0044] The information processing device 1 according to the second embodiment of the present disclosure has been described above. The configuration memory 102 is provided outside the substrate 10. For example, the substrate 20 includes the configuration memory 102. With such an information processing device 1, even in the slave mode, the configuration memory 102 sealed in one package can execute the configuration process for each of the FPGAs 1031 (i.e., multiple FPGAs).

[0045] <Third embodiment> (Configuration of information processing device) Each of the FPGAs 1031 according to the first embodiment of the present disclosure receives an SI / SO signal from the configuration memory 102 via the CONFIG I / Fs 1033 and 1034. In contrast, each of the FPGAs 1031 according to the third embodiment of the present disclosure receives an SI / SO signal from the configuration memory 102 via a CONFIG I / F 1038, which will be described later. FIG. 6 is a diagram showing an example of a configuration of an information processing device 1 according to the third embodiment of the present disclosure. As shown in FIG. 6, the information processing device 1 includes FPGAs 1031a and 1031b, CPLDs 1032a and 1032b, CONFIG I / Fs 1037a, 1037b, 1038, and 1039, and communication lines 1035a, 1035b, and 1036. The CONFIG I / Fs 1037a and 1037b may be collectively referred to as the CONFIG I / F 1037.

[0046] Each FPGA 1031 communicates with the configuration memory 102 when the information processing device 1 is started up. An example of this communication is serial communication. Examples of serial communication include SPI and QSPI. In the third embodiment of the present disclosure, the configuration is performed in master mode (i.e., the FPGA 1031 serves as the master and the configuration memory 102 serves as the slave, and the configuration is performed).

[0047] Furthermore, each of the FPGAs 1031 executes information processing for implementing functions required of the information processing device 1. Each of the FPGAs 1031 receives instructions for information processing to be executed by the CPU 202 provided on the board 20 via the inter-board I / F 30. Each of the FPGAs 1031 is an FPGA having the same function.

[0048] Each of the CPLDs 1032 is a peripheral circuit of the FPGA 1031. The CPLD 1032a manages the power supply of the FPGA 1031a. The CPLD 1032a also controls the configuration of the FPGA 1031a using the data stored in the configuration memory 102. The CPLD 1032b also manages the power supply of the FPGA 1031b. The CPLD 1032b also controls the configuration of the FPGA 1031b using the data stored in the configuration memory 102.

[0049] Each of the CPLDs 1032 shares, as control information, the startup status of the FPGA that it controls the configuration of, via the communication line 1036. This sharing of control information prevents each of the FPGAs 1031 from starting up at the same time. Also, the CPLD 1032 connected to the FPGA 1031 that is not started up fixes the connection terminals with the configuration memory 102, the CONFIG I / F 1037, and the CONFIG I / F 1038 in a cutoff state. As a result, the FPGA 1031 that is not started up and the CPLD 1032 that controls the startup of that FPGA 1031 are electrically disconnected from the other FPGA 1031 that is started up and the CPLD 1032 that controls the startup of that FPGA 1031.

[0050] 6, the CONFIG I / F 1037a connects the FPGA 1031a and the CPLD 1032a. The CONFIG I / F 1037a propagates a CCLK signal and a CS signal between the FPGA 1031a and the CPLD 1032a. The CCLK signal is a reference signal for synchronization when the FPGA 1031 is configured. The CS signal is a memory selection signal that selects a memory (the configuration memory 102 in each embodiment of the present disclosure) to be used when the FPGA 1031 is configured.

[0051] The CONGIG I / F 1037b connects the FPGA 1031b and the CPLD 1032b as shown in Fig. 6. The CONGIG I / F 1037b propagates a CCLK signal and a CS signal between the FPGA 1031b and the CPLD 1032b.

[0052] 6, the CONFIG I / F 1038 connects the configuration memory 102 and the CPLD 1032. The CONFIG I / F 1038 propagates a CCLK signal and a CS signal between the configuration memory 102 and the CPLD 1032.

[0053] 6, the CONFIG I / F 1039 connects the configuration memory 102 and each of the FPGAs 1031. The CONFIG I / F 1039 propagates SI / SO signals between the configuration memory 102 and each of the FPGAs 1031. The SI / SO signals are data signals (signals including data for setting the circuit configuration of the FPGA 1031 in each embodiment of the present disclosure).

[0054] 6, the communication line 1035a connects the FPGA 1031a and the CPLD 1032a. When the CPLD 1032a starts configuration of the FPGA 1031a, the communication line 1035a propagates a start signal that notifies the FPGA 1031a from the CPLD 1032a of the start of the configuration.

[0055] 6, the communication line 1035b connects the FPGA 1031b and the CPLD 1032b. When the CPLD 1032b starts configuration of the FPGA 1031b, the communication line 1035b propagates a start signal that notifies the FPGA 1031b from the CPLD 1032b of the start of the configuration.

[0056] 6, the communication line 1036 connects the CPLD 1032a and the CPLD 1032b. The communication line 1036 propagates control information shared between the CPLD 1032a and the CPLD 1032b. This control information includes information on the startup status of the FPGA 1031 in the configuration controlled by each of the CPLDs 1032.

[0057] By the above-mentioned connection via the CONFIG I / Fs 1033 and 1034, the FPGA 1031 and the configuration memory 102 are connected in a 2-to-1 ratio as shown in FIG.

[0058] Note that the processing performed by the information processing device 1 in the third embodiment of the present disclosure is not limited to the above-mentioned processing. For example, the information processing device 1 may perform the processing described below.

[0059] Next, the process performed by the information processing device 1 will be described with reference to FIG. 7. FIG. 7 is a diagram showing an example of a process flow of the information processing device 1 according to the third embodiment of the present disclosure. Here, the configuration process performed by the information processing device 1 at the time of startup, which sets the circuit configuration of the FPGA 1031a and then sets the circuit configuration of the FPGA 1031b, will be described with reference to FIG. 7. It is assumed that the control information shared between the CPLD 1032a and the CPLD 1032b includes information indicating that the circuit configuration of the FPGA 1031a is set and then the circuit configuration of the FPGA 1031b is set. It is also assumed that each of the FPGAs 1031 has a connection terminal with the CONFIG I / F 1039 fixed to a cutoff state.

[0060] Based on control information shared between the CPLD 1032a and CPLD 1032b, each of the CPLDs 1032 determines to set the circuit configuration of the FPGA 1031a. Then, the CPLD 1032b connected to the FPGA 1031b in an inactive state fixes the connection terminals with the configuration memory 102, the CONFIG I / F 1033, and the CONFIG I / F 1034 to a disconnected state.

[0061] The CPLD 1032a is in a state in which it can propagate the CCLK signal and the CS signal between the CONFIG I / F 1033a and the CONFIG I / F 1034 (step S21). This causes the FPGA 1031a to become the master and the configuration memory 102 to become the slave, enabling communication between the FPGA 1031a and the configuration memory 102. The FPGA 1031a that has become the master changes the connection terminal with the CONFIG I / F 1039 from a cutoff state to an impedance that allows communication. The CPLD 1032a then notifies the FPGA 1031a of the start of configuration via the communication line 1035a (step S22).

[0062] The FPGA 1031a outputs a CCLK signal and a CS signal to the configuration memory 102. The configuration memory 102 is selected by this CS signal. Then, in synchronization with the CCLK signal, the configuration memory 102 transfers data for setting the configuration of the circuit in the FPGA 1031a as SI / SO signals to the FPGA 1031a via the CONFIG I / F 1039 (step S23).

[0063] The FPGA 1031a receives the SI / SO signal. In response to the received SI / SO signal, the FPGA 1031a configures the circuit according to the SI / SO signal (step S24). When the circuit configuration is set (i.e., when the configuration process of the FPGA 1031a is completed), the FPGA 1031a notifies the CPLD 1032a that the configuration process of the FPGA 1031a is completed. In addition, the FPGA 1031a fixes the connection terminal with the CONFIG I / F 1039 to a disconnected state. Upon receiving the notification, the CPLD 1032a outputs control information including the completion of the configuration process of the FPGA 1031a to the CPLD 1032b (step S25). As a result, the CPLD 1032b determines that the configuration process of the FPGA 1031a is completed. Then, each of the FPGAs 1031 determines based on this notification that the circuit configuration of the FPGA 1031b should be set.

[0064] The CPLD 1032a connected to the FPGA 1031a in a non-activated state fixes the connection terminals with the configuration memory 102, the CONFIG I / F 1037, and the CONFIG I / F 1038 in a disconnected state.

[0065] The CPLD 1032b is in a state in which it can propagate the CCLK signal and the CS signal between the CONFIG I / F 1037b and the CONFIG I / F 1038 (step S26). This causes the FPGA 1031b to become the master and the configuration memory 102 to become the slave, enabling communication between the FPGA 1031b and the configuration memory 102. The FPGA 1031b that has become the master changes the connection terminal with the CONFIG I / F 1039 from a cutoff state to an impedance that allows communication. The CPLD 1032b then notifies the FPGA 1031b of the start of configuration via the communication line 10385b (step S27).

[0066] The FPGA 1031b outputs a CCLK signal and a CS signal to the configuration memory 102. The configuration memory 102 is selected by this CS signal. Then, in synchronization with the CCLK signal, the configuration memory 102 transfers data for setting the circuit configuration in the FPGA 1031b (i.e., the same data as the data for setting the circuit configuration in the FPGA 1031a) as an SI / SO signal to the FPGA 1031b via the CONFIG I / F 1039 (step S28).

[0067] The FPGA 1031b receives the SI / SO signal. In response to the received SI / SO signal, the FPGA 1031b configures the circuit according to the SI / SO signal (step S29). When the circuit configuration is set (i.e., when the configuration process of the FPGA 1031a is completed), the FPGA 1031b notifies the CPLD 1032b that the configuration process of the FPGA 1031b is completed. When the CPLD 1032b receives the notification, it outputs control information including the completion of the configuration process of the FPGA 1031b to the CPLD 1032a (step S30). As a result, each of the CPLDs 1032 determines that the configuration process of each of the FPGAs 1031 is completed. Then, each of the CPLDs 1032 ends the configuration process (step S31).

[0068] The information processing device 1 according to the third embodiment of the present disclosure has been described above. In the information processing device 1 including an FPGA (Field Programmable Gate Array) 1031a (an example of a first FPGA) and an FPGA 1031b (an example of a second FPGA), a configuration memory 102 is sealed in one package and stores information on the configuration of circuits set in the FPGA 1031a and the FPGA 1031b. A CPLD 1032a (an example of a first logic device) controls the processing of a first configuration in the FPGA 1031a, and when not controlling the processing of the first configuration, shuts off its own terminals connected to the FPGA 1031a or the configuration memory 102. CPLD 1032b (an example of a second logic device) controls the processing of the second configuration in FPGA 1031b, and when not controlling the processing of the second configuration, blocks its own terminals connected to FPGA 1031b or the configuration memory 102.

[0069] This information processing device 1 allows a configuration memory sealed in one package to be shared by multiple FPGAs. As a result, this information processing device 1 can reduce the mounting area on the board of an information processing device that executes information processing using multiple FPGAs.

[0070] Note that the information processing device 1 according to the third embodiment of the present disclosure can have the following number of CONFIG I / Fs, and the circuit scale of the information processing device 1 can be reduced.

[0071] If the serial communication between the FPGA 1031 and the configuration memory 102 at the start of the information processing device 1 is SPI, a total of four signal lines are required for the configuration. If the serial communication between the FPGA 1031 and the configuration memory 102 at the start of the information processing device 1 is QSPI, a total of six signal lines are required for the configuration.

[0072] In addition, when using the same bus for directly propagating data signals between the FPGA 1031 and the configuration memory 10 in a direction in which the data signals propagate through each of the CONFIG I / Fs 1037, 1038, and 1039 are in one direction and in the opposite direction, the number of signal lines required for configuration can be reduced by 2 lines x the number of FPGAs 1031 implemented in the case of SPI, and 3 lines x the number of FPGAs 1031 implemented in the case of QSPI. Also, the implementation for propagating the data signals inside the CPLD 1032 becomes unnecessary. This is more noticeable in the case of QSPI than in the case of SPI. In the case of QSPI, the FPGA 1031, which is the master, and the configuration memory 102, which is the slave, switch between the input and output of each terminal by a common SPI command (a control signal in a data signal). Therefore, in the case of QSPI, it is not necessary to implement a function for controlling bidirectional data signals. As a result, it is also possible to reduce the circuit resources (and the number of pins) and design costs of the CPLD 1032.

[0073] Fig. 8 is a diagram showing a minimum configuration of an information processing device 1 according to an embodiment of the present disclosure. As shown in Fig. 8, the information processing device 1 includes a first FPGA (Field Programmable Gate Array) 301, a second FPGA 302, a configuration memory 303, a first logic device 304, a second logic device 305, a signal line that directly connects the first FPGA 301 and the configuration memory 303, and a signal line that directly connects the second FPGA 302 and the configuration memory 303.

[0074] The configuration memory 303 is sealed in one package and stores information about the configuration of circuits set in the first FPGA 301 and the second FPGA 302. The first logic device 304 controls the processing of the first configuration in the first FPGA 301, and when not controlling the processing of the first configuration, sets its own terminals connected to the first FPGA 301 or the configuration memory 303 to a cutoff state. The second logic device 305 controls the processing of the second configuration in the second FPGA 302, and when not controlling the processing of the second configuration, sets its own terminals connected to the second FPGA 302 or the configuration memory 303 to a cutoff state.

[0075] The first FPGA 301 can be realized, for example, by using the function of the FPGA 1031a illustrated in FIG. 2. The second FPGA 302 can be realized, for example, by using the function of the FPGA 1031b illustrated in FIG. 2. The configuration memory 303 can be realized, for example, by using the function of the configuration memory 102 illustrated in FIG. 1. The first logic device 304 can be realized, for example, by using the function of the CPLD 1032a illustrated in FIG. 2. The second logic device 305 can be realized, for example, by using the function of the CPLD 1032b illustrated in FIG. 2. The signal line directly connecting the first FPGA 301 and the configuration memory 303 and the signal line directly connecting the second FPGA 302 and the configuration memory 303 can be realized, for example, by using the function of the CONFIG I / F 1039 illustrated in FIG. 6.

[0076] 9 is a diagram showing an example of a processing flow of the information processing device 1 with a minimum configuration according to the embodiment of the present disclosure. Next, the processing of the information processing device 1 with a minimum configuration according to the embodiment of the present disclosure will be described with reference to FIG.

[0077] In an information processing device 1 including a first FPGA 301, a second FPGA 302, a configuration memory 303 sealed in a single package and storing information regarding the configuration of circuits set in the first FPGA 301 and the second FPGA 302, a signal line directly connecting the first FPGA 301 and the configuration memory 303, and a signal line directly connecting the second FPGA 302 and the configuration memory 303, a first logic device 304 controls processing of a first configuration in the first FPGA 301, and when not controlling the processing of the first configuration, sets its own terminals connected to the first FPGA 301 or the configuration memory 303 to a cut-off state (step S101). The second logic device 305 controls the processing of the second configuration in the second FPGA 302, and when not controlling the processing of the second configuration, sets its own terminals connected to the second FPGA 302 or the configuration memory 303 to a cut-off state (step S102).

[0078] The information processing device 1 with the minimum configuration according to the embodiment of the present disclosure has been described above. This information processing device 1 makes it possible to use a configuration memory sealed in one package in common for multiple FPGAs. As a result, this information processing device 1 can reduce the mounting area on the board of an information processing device that executes information processing using multiple FPGAs.

[0079] It should be noted that the order of the processes in the embodiments of the present disclosure may be changed as long as appropriate processes are performed.

[0080] Although the embodiment of the present disclosure has been described, the above-mentioned information processing device 1, the boards 10, 20, the CPLD 1032, and other control devices may have a computer system inside. The above-mentioned process steps are stored in a computer-readable recording medium in the form of a program, and the above-mentioned process is performed by the computer reading and executing the program. Specific examples of computers are shown below.

[0081] 10 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in FIG. 10, the computer 5 includes a CPU (Central Processing Unit) 6, a main memory 7, a storage 8, and an interface 9.

[0082] For example, the above-mentioned information processing device 1, boards 10, 20, CPLD 1032, and other control devices are each implemented in a computer 5. The operations of the above-mentioned processing units are stored in the storage 8 in the form of a program. The CPU 6 reads the program from the storage 8, loads it in the main memory 7, and executes the above-mentioned processes according to the program. The CPU 6 also secures storage areas in the main memory 7 corresponding to the above-mentioned storage units according to the program.

[0083] Examples of the storage 8 include a hard disk drive (HDD), a solid state drive (SSD), a magnetic disk, a magneto-optical disk, a compact disc read only memory (CD-ROM), a digital versatile disc read only memory (DVD-ROM), and a semiconductor memory. The storage 8 may be an internal medium directly connected to the bus of the computer 5, or an external medium connected to the computer 5 via an interface 9 or a communication line. In addition, when the program is distributed to the computer 5 via a communication line, the computer 5 that receives the program may load the program into the main memory 7 and execute the above-mentioned process. In at least one embodiment, the storage 8 is a non-transitory tangible storage medium.

[0084] The program may also realize some of the functions described above. Furthermore, the program may be a file that can realize the functions described above in combination with a program already recorded in the computer system, that is, a so-called differential file (differential program).

[0085] Although some embodiments of the present disclosure have been described, these embodiments are merely examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and modifications may be made to these embodiments without departing from the spirit of the disclosure.

[0086] Note that some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0087] (Appendix 1) A first FPGA (Field Programmable Gate Array); A second FPGA; and a configuration memory sealed in one package and configured to store information regarding the configuration of circuits set in the first FPGA and the second FPGA; a first logic device that controls a process of a first configuration in the first FPGA and, when not controlling the process of the first configuration, shuts off a terminal of the first logic device that is connected to the first FPGA or the configuration memory; a second logic device that controls a process of a second configuration in the second FPGA and, when not controlling the process of the second configuration, shuts off a terminal of the second logic device that is connected to the second FPGA or the configuration memory; a signal line that directly connects the first FPGA and the configuration memory; a signal line that directly connects the second FPGA and the configuration memory; An information processing device comprising:

[0088] (Appendix 2) The first logical device and the second logical device are The order of processing the first configuration and the second configuration is shared; 2. An information processing device according to claim 1.

[0089] (Appendix 3) The first logical device is notifying the second logical device of the completion of the processing of the first configuration; The second logical device is in response to a notification from the first logic device, changing a terminal of the first logic device connected to the first FPGA or the configuration memory from a cut-off state to a state in which communication with the second FPGA and the configuration memory is possible; 3. An information processing device according to claim 1 or 2.

[0090] (Appendix 4) The second logical device is notifying the first logical device of the completion of the processing of the second configuration and terminating the processing of the second configuration; The first logical device is terminating the processing of the first configuration in response to a notification from the second logical device. An information processing device according to any one of Supplementary Note 1 to Supplementary Note 3.

[0091] (Appendix 5) A processing method executed by an information processing device including a first FPGA (Field Programmable Gate Array), a second FPGA, a configuration memory sealed in a single package and storing information relating to a configuration of a circuit set in the first FPGA and the second FPGA, a signal line directly connecting the first FPGA and the configuration memory, and a signal line directly connecting the second FPGA and the configuration memory, the method comprising: controlling a process of a first configuration in the first FPGA, and, when not controlling the process of the first configuration, bringing its own terminal connected to the first FPGA or the configuration memory into a cutoff state; controlling a process of a second configuration in the second FPGA, and, when not controlling the process of the second configuration, bringing its own terminal connected to the second FPGA or the configuration memory into a cutoff state; A processing method comprising:

[0092] (Appendix 6) A computer of an information processing device including a first FPGA (Field Programmable Gate Array), a second FPGA, a configuration memory sealed in a single package and storing information about a configuration of a circuit set in the first FPGA and the second FPGA, a signal line directly connecting the first FPGA and the configuration memory, and a signal line directly connecting the second FPGA and the configuration memory, controlling a process of a first configuration in the first FPGA, and, when not controlling the process of the first configuration, bringing its own terminal connected to the first FPGA or the configuration memory into a cutoff state; controlling a process of a second configuration in the second FPGA, and, when not controlling the process of the second configuration, bringing its own terminal connected to the second FPGA or the configuration memory into a cutoff state; A program that executes the following. [Explanation of symbols]

[0093] 1. Information processing device 5. Computers 6, 202...CPU 7. Main memory 8. Storage 9. Interface 10, 20... Board 30... Board-to-board interface 101, 201... Connector 102, 303... Configuration memory 103 Information Processing Unit 301: First FPGA 302: Second FPGA 304: First logical device 305 Second logical device 1031, 1031a, 1031b...FPGA 1032, 1032a, 1032b...CPLD 1033, 1033a, 1033b, 1034, 1037, 1037a, 1037b, 1038, 1039...CONFIG I / F 1035, 1035a, 1035b, 1036... communication lines

Claims

1. a first FPGA (Field Programmable Gate Array); A second FPGA; and a configuration memory sealed in one package and configured to store information regarding the configuration of circuits set in the first FPGA and the second FPGA; a first logic device that controls a process of a first configuration in the first FPGA and, when not controlling the process of the first configuration, shuts off a terminal of the first logic device that is connected to the first FPGA or the configuration memory; a second logic device that controls a process of a second configuration in the second FPGA and, when not controlling the process of the second configuration, shuts off a terminal of the second logic device that is connected to the second FPGA or the configuration memory; a signal line directly connecting the first FPGA and the configuration memory; a signal line directly connecting the second FPGA and the configuration memory; An information processing device comprising:

2. The first logical device and the second logical device are The order of processing the first configuration and the order of processing the second configuration are shared. The information processing device according to claim 1 .

3. The first logical device is notifying the second logical device of the completion of the processing of the first configuration; The second logical device is in response to a notification from the first logic device, changing a terminal of the device connected to the first FPGA or the configuration memory from a cut-off state to a state in which communication with the second FPGA and the configuration memory is possible; The information processing device according to claim 1 .

4. The second logical device is notifying the first logical device of the completion of the processing of the second configuration and terminating the processing of the second configuration; The first logical device is end the processing of the first configuration in response to a notification from the second logical device; The information processing device according to claim 1 .

5. A processing method executed by an information processing device including a first FPGA (Field Programmable Gate Array), a second FPGA, a configuration memory sealed in a single package and storing information relating to a configuration of a circuit set in the first FPGA and the second FPGA, a signal line directly connecting the first FPGA and the configuration memory, and a signal line directly connecting the second FPGA and the configuration memory, the method comprising: controlling a process of a first configuration in the first FPGA, and, when not controlling the process of the first configuration, shutting off a terminal of the first FPGA or the configuration memory; controlling a process of a second configuration in the second FPGA, and, when not controlling the process of the second configuration, shutting off a terminal of the device itself connected to the second FPGA or the configuration memory; A processing method comprising:

6. A computer of an information processing device including a first FPGA (Field Programmable Gate Array), a second FPGA, a configuration memory sealed in one package and storing information on a configuration of a circuit set in the first FPGA and the second FPGA, a signal line directly connecting the first FPGA and the configuration memory, and a signal line directly connecting the second FPGA and the configuration memory, controlling a process of a first configuration in the first FPGA, and, when not controlling the process of the first configuration, shutting off a terminal of the first FPGA or the configuration memory; controlling a process of a second configuration in the second FPGA, and, when not controlling the process of the second configuration, shutting off a terminal of the device itself connected to the second FPGA or the configuration memory; A program that executes the following.

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