Mesh decoding device, mesh encoding device, mesh decoding method, and program

Abstract

To improve encoding efficiency.SOLUTION: A basic mesh decoding unit 202 of a mesh decoding device 200 according to the present invention includes: a multiple separation block that separates a basic mesh bit stream into an intraframe bit stream and a partial interframe bit stream; an intra basic mesh decoding block 202A that decodes the intraframe bit stream in an intra mode; and a partial inter basic mesh decoding block 103 that decodes the partial interframe bit stream in a partial inter mode.SELECTED DRAWING: Figure 17

Description

[Technical field]

[0001] The present invention relates to a mesh decoding device, a mesh encoding device, a mesh decoding method, and a program. [Background technology]

[0002] In the current video-based dynamic mesh coding (V-DMC) model, there are two coding modes: (1) intra-frame coding mode and (2) inter-frame coding mode (see, for example, Non-Patent Document 1).

[0003] The choice of different modes is determined by whether the input dynamic mesh is tracked or not.

[0004] A tracked mesh has both one-to-one vertex and edge correspondences between frames, as shown in Figure 1(a), while a non-tracked mesh does not, as shown in Figure 1(b).

[0005] For tracking meshes, V-DMC skips coding of the current base mesh and codes the difference between the current base mesh and the previous base mesh, allowing for better temporal prediction.

[0006] On the other hand, in V-DMC, non-tracked meshes are coded separately, resulting in poor coding efficiency. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] Khaled Mammou, Jungsun Kim, Alexis M Tourapis, Dimitri Podborski, and Krasimir Kolarov, “[V-CG] Apple's Dynamic Mesh Coding CfP Response,” April 2022, ISO / IEC JTC 1 / SC 29 / WG 7. Summary of the Invention [Problem to be solved by the invention]

[0008] In the above-mentioned prior art, there are only two coding modes: intra-frame coding mode and inter-frame coding mode, depending on whether the input dynamic mesh is tracked or not.

[0009] However, in the non-tracked mesh shown in FIG. 2(a), as shown in FIG. 2(b), some parts may be tracked (tracked part in FIG. 2(b)) and some parts may not be tracked (non-tracked part in FIG. 2(b)).

[0010] In such a case, the conventional technology can only apply intra-frame coding, resulting in low coding efficiency.

[0011] Therefore, the present invention has been made in consideration of the above-mentioned problems, and aims to provide a mesh encoding device, a mesh decoding device, a mesh encoding method, and a program that can improve encoding efficiency. [Means for solving the problem]

[0012] The first feature of the present invention is a mesh decoding device comprising a basic mesh decoding unit configured to decode one of the bit streams of a basic mesh in intra mode and decode the other bit stream of the basic mesh in partial inter mode, the basic mesh decoding unit comprising a multiplexing separation block configured to separate the bit stream of the basic mesh into a bit stream of an intra frame and a bit stream of a partial inter frame, an intra basic mesh decoding block configured to decode the bit stream of the intra frame in intra mode, and a partial inter basic mesh decoding block configured to decode the bit stream of the partial inter frame in partial inter mode.

[0013] A second feature of the present invention is summarized as a mesh encoding device comprising: a pre-processing block configured to generate two base meshes, a non-tracking base mesh and a tracking base mesh; an intra-coding block configured to encode the non-tracking base mesh in an intra-coding mode; and a partial inter-coding block configured to encode the tracking base mesh in a partial inter-coding mode.

[0014] A third feature of the present invention is a mesh decoding method comprising the steps of decoding one of the bit streams of a basic mesh in intra mode and decoding the other bit stream of the basic mesh in partial inter mode, and in a previous step, separating the bit stream of the basic mesh into an intra frame bit stream and a partial inter frame bit stream, decoding the intra frame bit stream in intra mode, and decoding the partial inter frame bit stream in partial inter mode.

[0015] A fourth feature of the present invention is summarized as a program for causing a computer to function as a mesh decoding device, the mesh decoding device comprising a basic mesh decoding unit configured to decode one of the bit streams of a basic mesh in intra mode and to decode the other bit stream of the basic mesh in partial inter mode, the basic mesh decoding unit comprising a multiplexing separation block configured to separate the bit stream of the basic mesh into a bit stream of an intra frame and a bit stream of a partial inter frame, an intra basic mesh decoding block configured to decode the bit stream of the intra frame in intra mode, and a partial inter basic mesh decoding block configured to decode the bit stream of the partial inter frame in partial inter mode. Effect of the Invention

[0016] According to the present invention, it is possible to provide a mesh decoding device, a mesh encoding device, a mesh decoding method, and a program capable of improving encoding efficiency. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a diagram for explaining the prior art. [Diagram 2] FIG. 2 is a diagram for explaining the prior art. [Diagram 3] FIG. 3 is a diagram showing an example of the configuration of a mesh processing system 1 according to an embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of functional blocks of the mesh encoding device 100 according to an embodiment. [Diagram 5] FIG. 5 is a diagram showing an example of functional blocks of the pre-processing unit 101 of the mesh encoding device 100 according to an embodiment. [Figure 6] FIG. 6 is a diagram for explaining an example of the pre-processing sub-block 101A of the pre-processing unit 101 of the mesh encoding device 100 according to an embodiment. [Figure 7] FIG. 7 is a flowchart showing an example of the operation of the mesh separation sub-block 101B of the pre-processing unit 101 of the mesh encoding device 100 according to an embodiment. [Figure 8] FIG. 8 is a diagram showing an example of functional blocks of the intra-coding block 102 of the mesh coding device 100 according to an embodiment. [Figure 9] FIG. 9 is a diagram for explaining an example of the operation of the mesh merging block 102C of the intra-coding block 102 of the mesh coding device 100 according to an embodiment. [Figure 10] FIG. 10 is a diagram for explaining an example of the operation of the mesh counting block 102A of the intra-coding block 102 of the mesh coding device 100 according to an embodiment. [Figure 11] FIG. 11 is a diagram showing a rough image of how a compressed bit stream b(j) is generated from a non-tracking basic mesh p(j) and a tracking basic mesh q(j). [Figure 12] FIG. 12 is a flowchart showing an example of the operation of the mesh counting block 102A of the intra-coding block 102 of the mesh encoding device 100 according to an embodiment. [Figure 13] FIG. 13 is a diagram showing an example of functional blocks of the mesh order change block 102G of the intra-coding block 102 of the mesh coding device 100 according to an embodiment. [Figure 14] FIG. 14 is a flowchart showing an example of the operation of the face selection block 102G02 of the mesh order change block 102G of the intra-coding block 102 of the mesh coding device 100 according to an embodiment. [Figure 15] FIG. 15 is a diagram showing an example of functional blocks of the partial inter-coding block 103 of the mesh coding device 100 according to an embodiment. [Figure 16] FIG. 16 is a diagram showing an example of functional blocks of the mesh decoding device 200 according to this embodiment. [Figure 17]FIG. 17 is a diagram showing an example of functional blocks of the basic mesh decoding unit 202 of the mesh decoding device 200 according to this embodiment. [Figure 18] FIG. 18 is a diagram showing an example of functional blocks of the intra base mesh decoding block 202A of the base mesh decoding unit 202 of the mesh decoding device 200 according to this embodiment. [Figure 19] FIG. 19 is a diagram showing an example of functional blocks of the mesh separation block 202A05 of the intra basic mesh decoding block 202A of the basic mesh decoding unit 202 of the mesh decoding device 200 according to this embodiment. [Figure 20] FIG. 20 is a flowchart showing an example of the operation of the vertex division sub-block 202A05A of the mesh separation block 202A05 of the intra basic mesh decoding block 202A of the basic mesh decoding unit 202 of the mesh decoding device 200 according to this embodiment. [Figure 21] FIG. 21 is a diagram showing an example of functional blocks of the partial inter basic mesh decoding block 202B of the basic mesh decoding unit 202 of the mesh decoding device 200 according to this embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, the embodiments of the present invention will be described with reference to the drawings. Note that the components in the following embodiments can be appropriately replaced with existing components, and various variations including combinations with other existing components are possible. Therefore, the description of the following embodiments does not limit the content of the invention described in the claims.

[0019] First Embodiment The mesh processing system 1 according to this embodiment will be described below with reference to FIGS.

[0020] 3 is a diagram showing an example of the configuration of a mesh processing system 1 according to this embodiment. As shown in FIG.

[0021] Hereinafter, in this embodiment, the frame is synonymous with the mesh.

[0022] <Mesh encoding device 100> FIG. 4 is a diagram showing an example of functional blocks of the mesh coding device 100 according to this embodiment.

[0023] As shown in FIG. 4, the mesh coding device 100 includes a pre-processing block 101, an intra-coding block 102, and a partial inter-coding block 103.

[0024] The pre-processing block 101 is configured to generate two base meshes: a non-tracked base mesh and a tracked base mesh.

[0025] Here, as shown in FIG. 4, the tracking base mesh q(j) generated from the reference mesh M(j) is transmitted to a partial inter-coding block 103 for inter-frame coding.

[0026] (Pre-processing block 101) An example of the pre-processing block 101 will now be described with reference to FIGS.

[0027] As shown in FIG. 5, the pre-processing block 101 includes a pre-processing sub-block 101A and a mesh separation sub-block 101B.

[0028] The pre-processing sub-block 101A is the same as that disclosed in Non-Patent Document 1, and is configured to generate basic meshes m(i) / m(j) and displacements d(i) / d(j) from input meshes M(i) / M(j), as shown in Figs. 5 and 6.

[0029] As shown in FIG. 5, the mesh separation sub-block 101B is configured to receive a base mesh m(i) / m(j) as input and separate the base mesh m(i) / m(j) into two base meshes: a non-tracking base mesh p(i) / p(j) and a tracking base mesh q(i) / q(j).

[0030] An example of the mesh separation sub-block 101B will be described below with reference to FIG.

[0031] As shown in FIG. 7, in step S101B-1, the mesh separation block 101B determines whether or not all the faces of the basic mesh m(i) / m(j) have been processed.

[0032] If the answer is Yes, the mesh separation block 101B ends this process. If the answer is No, the mesh separation block 101B proceeds to step S101B-2.

[0033] In step S101B-2, the mesh separation block 101B calculates the average height h of the three vertices of the current face. c Calculate.

[0034] For example, if the coordinates of the three vertices of the current face are (x1, y1, z1), (x2, y2, z2) and (x3, y3, z3), the average height of these three vertices h c is (z1+z2+z3) / 3.

[0035] In step S101B-3, the mesh separation block 101B is divided into 100 pieces of the mesh separation block 101B having the above-mentioned average height h c is the threshold h t It is determined whether the value is greater than .

[0036] If Yes, the mesh separation block 101B adds the current face to the tracking base mesh q(i) / q(j) in step S101B-4.

[0037] On the other hand, if the answer is No, then mesh separation block 101B adds the current face to the non-tracked base mesh p(i) / p(j) in step S101B-5.

[0038] Mesh separation block 101B then proceeds to process the next face in step S101B-6.

[0039] (Intra coding block 102) FIG. 8 shows an example of functional blocks of the intra-coding block 102.

[0040] As shown in FIG. 8, the intra-coding block 102 includes a mesh counting block 102A, a separation index coding block 102B, a mesh merging block 102C, a quantization block 102D, a static mesh coding block 102E, a static mesh decoding block 102F, a mesh order change block 102G, a displacement amount update block 102H, a displacement amount coding block 102I, a texture coding block 102J, and a MUX 102K.

[0041] As shown in FIG. 9, the non-tracked basic mesh p(j) and the tracked basic mesh q(j) are merged into a merged basic mesh m'(j) by the mesh merging block 102C.

[0042] The merged base mesh m'(j) is compressed into a compressed base mesh bitstream by the quantization block 102D and the static mesh coding block 102E.

[0043] Furthermore, as shown in FIG. 10, a mesh counting block 102A is configured to count the number of cut components in the input mesh.

[0044] In the example of FIG. 10(a), the mesh counting block 102A counts the number of cut components 1 to 5 in the input mesh and outputs "5."

[0045] On the other hand, in the example of FIG. 10(b), the mesh counting block 102A counts the number of cut components 1 to 3 in the input mesh and outputs "3."

[0046] In this embodiment, the mesh counting block 102A counts the number of disconnected components in the non-tracked base mesh and sends the counting result as a separated index h(j) to the separated index encoding block 102B, which encodes the separated index h(j) and transmits it to the MUX 102K as a compressed separated index bitstream.

[0047] Furthermore, the mesh order change block 102G changes the order of the vertices and faces of the reconstructed base mesh m''(j) and sends it to the displacement amount update block 102H as a reordered base mesh m''(j), and the displacement amount update block 102H updates the order of the displacement amounts according to the reordered base mesh m'''(j).

[0048] In addition, the quantization block 102D, static mesh encoding block 102E, static mesh decoding block 102F, displacement amount update block 102H, displacement amount encoding block 102I, texture encoding block 102J and MUX 102K are the same as those described in non-patent document 1.

[0049] FIG. 11 shows a rough image of how a compressed bit stream b(j) is generated from a non-tracking basic mesh p(j) and a tracking basic mesh q(j).

[0050] An example of the operation of the mesh counting block 102A will be described with reference to FIG.

[0051] 12, in step S102A-1, mesh counting block 102A sets Q and V' to empty sets and sets Count to 0. Here, V' is a set of vertices, and Count is the number of cut components in the input mesh.

[0052] In step S102A-2, mesh counting block 102A determines whether all vertices have been visited.

[0053] If the answer is Yes, the mesh counting block 102A ends this operation, whereas if the answer is No, the mesh counting block 102A proceeds to step S102A-3.

[0054] In step S102A-3, mesh counting block 102A determines whether the current vertex has already been visited.

[0055] If the answer is Yes, the mesh counting block 102A returns to step S102A-2, whereas if the answer is No, the mesh counting block 102A proceeds to step S102A-4.

[0056] At step S102A-4, mesh counting block 102A adds the current vertex to the end of Q.

[0057] At step S102A-5, mesh counting block 102A determines whether Q is empty.

[0058] If the answer is Yes, the mesh counting block 102A proceeds to step S102A-6, whereas if the answer is No, the mesh counting block 102A proceeds to step S102A-7.

[0059] At step 102A-6, mesh counting block 102A adds 1 to Count.

[0060] At step 102A-7, mesh counting block 102A searches all vertices connected to the first element of Q.

[0061] At step 102A-8, mesh counting block 102A determines whether all vertices connected to the first element of Q have been visited.

[0062] If the answer is Yes, the mesh counting block 102A proceeds to step S102A-9, whereas if the answer is No, the mesh counting block 102A proceeds to step S102A-10.

[0063] At step 102A-9, mesh counting block 102A removes the first element from Q and adds it to V'.

[0064] At step 102A-10, mesh counting block 102A determines whether a vertex adjacent to the current vertex has been visited.

[0065] If the answer is Yes, the mesh counting block 102A returns to step S102A-8, whereas if the answer is No, the mesh counting block 102A proceeds to step S102A-11.

[0066] At step 102A-10, mesh counting block 102A adds the vertices adjacent to the current vertex to the end of Q.

[0067] The mesh counting block 102A outputs the value of Count.

[0068] The separate index coding block 102B is configured to compress the separate indexes h(j) into a compressed separate index bitstream.

[0069] The mesh merging block 102C merges the separated meshes (the non-tracked basic mesh p(j) and the tracked basic mesh q(j)) into a single mesh (the merged basic mesh m'(j)).

[0070] Here, if the meshes input to the mesh merge block 102C are {V1, F1} and {V2, F2}, where V1 and V2 are sets of vertices and F1 and F2 are sets of faces, then the merged base mesh m'(j) generated by the mesh merge block 102C is {V1 ∪ V2, F1 ∪ (F2 + |V1|)}, where |V1| is the total number of vertices in V1.

[0071] The mesh reordering block 102G is configured to reorder vertices and faces.

[0072] FIG. 13 is a diagram showing an example of a functional block of the mesh order change block 102G.

[0073] As shown in FIG. 13, the mesh order change block 102G includes a mesh counting block 102G01 and a face selection block 102G02.

[0074] Here, mesh counting block 102G01 performs the same operation as mesh counting block 102A shown in FIG. 12, except that the output is V' shown in step 102A-1.

[0075] An example of the operation of the face selection block 102G02 will be described with reference to FIG.

[0076] As shown in FIG. 14, in step S102G02-1, the face selection block 102G02 initializes a new face set F' as an empty set.

[0077] In step S102G02-2, the face selection block 102G02 determines whether or not all vertices have already been visited.

[0078] If the answer is Yes, the face selection block 102G02 ends this operation, whereas if the answer is No, the face selection block 102G02 proceeds to step S102G02-3.

[0079] In step S102G02-3, the Face Selection Block 102G02 searches all faces connected to the current vertex.

[0080] In step S102G02-4, the Face Selection Block 102G02 determines whether or not all faces have already been visited.

[0081] If the answer is Yes, the face selection block 102G02 returns to step S102G02-2, whereas if the answer is No, the face selection block 102G02 proceeds to step S102G02-5.

[0082] In step S102G02-4, the face selection block 102G02 determines whether the current face has already been visited.

[0083] If the answer is Yes, the face selection block 102G02 proceeds to step S102G02-7, whereas if the answer is No, the face selection block 102G02 proceeds to step S102G02-6.

[0084] In step S102G02-6, the face selection block 102G02 adds the current face to F'.

[0085] In step S102G02-7, the face selection block 102G02 proceeds to the next face.

[0086] (Partial inter-coding block 103) FIG. 15 is a diagram showing an example of functional blocks of the partial inter-coding block 103.

[0087] As shown in Figure 15, the partial inter-coding block 103 includes a quantization block 103A, a static mesh coding block 103B, a motion coding block 103C, a static mesh decoding block 103D, a mesh merging block 103E, a mesh order change block 103F, a displacement amount update block 103G, a displacement amount coding block 103H, a texture coding block 103I, and a MUX 103J.

[0088] The motion coding block 103C is the same as that described in Non-Patent Document 1. Also, the blocks in Figure 15 basically have the same functions as the blocks with the same names in Figure 8.

[0089] A feature of the partial inter coding block 103 is that the current non-tracked base mesh p(i) is compressed by the static mesh coding block 103B, while the tracking bases q(i) are used to be compressed by the motion coding block 103C.

[0090] <Mesh Decoding Device 200> FIG. 16 is a diagram showing an example of functional blocks of the mesh decoding device 200 according to this embodiment.

[0091] As shown in FIG. 16, the mesh decoding device 200 includes a demultiplexing unit 201, a basic mesh decoding unit 202, a displacement amount decoding unit 203, a video decoding unit 204, a subdivision unit 205, and a mesh decoding unit 206.

[0092] The demultiplexing unit 201 is configured to separate the bit stream into three: a base mesh bit stream, a displacement amount bit stream, and a texture bit stream.

[0093] (Basic mesh decoding unit 202) FIG. 17 is a diagram showing an example of functional blocks of the basic mesh decoding unit 202. As shown in FIG.

[0094] As shown in FIG. 17, the base mesh decoding unit 202 includes an intra base mesh decoding block 202A and a partial inter base mesh decoding block 202B.

[0095] The intra base mesh decoding block 202A is configured to decode the bitstream of base meshes of an intra frame and output a reconstructed base mesh of an intra frame.

[0096] The partial inter base mesh decoding block 202B is configured to decode the bitstream of the base mesh of the current frame, and output the bitstream of the reconstructed base mesh of the current frame.

[0097] FIG. 18 is a diagram showing an example of functional blocks of the intra base mesh decoding block 202A.

[0098] As shown in FIG. 18, the intra basic mesh decoding block 202A includes a demultiplexing block 202A01, a separated index decoding block 202A02, a static mesh decoding block 202A03, a mesh order changing block 202A04, and a mesh separation block 202A05.

[0099] The demultiplexing block 202A01 is configured to separate the intra-frame bitstream into two: a separate index bitstream and a base mesh bitstream.

[0100] The separate index decoding block 202A02 is configured to decode the separate index bitstream to obtain a separate index j(j).

[0101] The static mesh decoding block 202A03 is configured to decode the base mesh bitstream and obtain the merged base mesh m'(j).

[0102] The mesh reordering block 202A04 is configured to reorder the vertices and faces of the merged base mesh m'(j), similar to the mesh reordering block 102G shown in FIG.

[0103] FIG. 19 is a diagram showing an example of a functional block of the mesh separation block 202A05.

[0104] As shown in FIG. 19, the mesh separation block 202A05 includes a vertex division sub-block 202A05A and a face selection block 202A05B.

[0105] An example of the operation of the vertex split sub-block 202A05A will be described with reference to FIG.

[0106] As shown in FIG. 20, in step S202A05-1, the vertex split sub-block 202A05A initializes V', V'', Q and Count. Here, V' is an initial inter-vertex set, and V'' is an initial intra-vertex set.

[0107] The operations of steps S202A05-2 to S202A05-8 and steps S202A05-9 to S202A05-10 are the same as the operations of steps S102A05-2 to S102A05-8 and steps S102A05-10 to S102A05-11 shown in FIG. 12, respectively.

[0108] In step S202A05-11, the vertex split sub-block 202A05A determines whether or not Count is greater than the separation index h(j).

[0109] If the answer is Yes, the vertex split sub-block 202A05A proceeds to step S202A05-13, whereas if the answer is No, the vertex split sub-block 202A05A proceeds to step S202A05-12.

[0110] In step S202A05-12, the vertex split sub-block 202A05A removes the first element from Q and adds it to V'.

[0111] In step S202A05-13, the vertex split sub-block 202A05A removes the first element from Q and adds it to V''.

[0112] The operation of the face selection block 202A05B is the same as the operation of the face selection block 102G02 shown in Fig. 14. The face selection block 202A05B selects all faces connected to the input vertex from the reconstructed basic mesh.

[0113] FIG. 21 is a diagram showing an example of functional blocks of the partial inter basic mesh decoding block 202B.

[0114] As shown in FIG. 21, the partial inter basic mesh decoding block 202B includes a demultiplexing block 202B01, a motion decoding block 202B02, a static mesh decoding block 202B03, a mesh merging block 202B04, and a mesh order changing block 202B05.

[0115] The demultiplexing block 202B01 is configured to separate the partial inter-frame bitstream into two: a motion bitstream and a base mesh bitstream.

[0116] The motion decoding block 202B02 is configured to decode the motion bitstream into motion vectors and add the motion vectors to the tracking basis mesh q''(j) of the intra-frame to obtain the tracking basis mesh q''(i) of the current frame.

[0117] The motion decoding block 202B02 is the same as that described in Non-Patent Document 1.

[0118] The static mesh decoding block 202B03 decodes the base mesh bitstream to obtain the non-tracked base mesh p''(i) of the current frame.

[0119] The mesh merging block 202B04 merges the tracked base mesh q''(i) of the current frame (the reconstructed tracked base mesh) and the non-tracked base mesh p''(i) of the current frame (the reconstructed non-tracked base mesh) into a single mesh m'(i).

[0120] The mesh reordering block 202B05 reorders the vertices and faces to obtain a reconstructed base mesh m''(i) of the current frame.

[0121] The above-mentioned mesh encoding device 100 and mesh decoding device 200 may be realized as a program that causes a computer to execute each function (each step). [Industrial Applicability]

[0122] According to this embodiment, for example, it is possible to improve the overall service quality in video communication, which makes it possible to contribute to Goal 9 of the Sustainable Development Goals (SDGs) led by the United Nations, which is to "build resilient infrastructure, promote sustainable industrialization and foster innovation." [Explanation of symbols]

[0123] 1…Mesh processing system 100...Mesh coding device 101…Pre-processing block 101A…Pre-treatment sub-block 101B…Mesh separation sub-block 102...Intra coding block 102A…Mesh counting block 102B…Separate index coding block 102C, 103E, 202B04…Mesh merge block 102D, 103A...Quantization block 102E, 103B...Static mesh coding block 102F, 103D...Static mesh decoding block 102G, 103F, 202B05...Mesh order change block 102G01…Mesh counting block 102G02...Face selection block 102H, 103G...Displacement update block 102I, 103H...Displacement encoding block 102J, 103I...Texture coding block 102K, 103J…MUX 103...Partial inter-coding block 103C...Motion coding block 200…Mesh decoding device 201…Demultiplexer 202...Basic mesh decoding unit 202A... Intra basic mesh decoding block 202A01, 202B01...Demultiplexing block 202A02…Separate index decoding block 202A03, 202B03...Static mesh decoding block 202A04…Mesh order change block 202A05…Mesh separation block 202A05A…Vertex division subblock 202A05B…Face selection block 202B...Partial inter-basic mesh decoding block 202B02...Motion decoding block 203...Displacement amount decoding unit 204...Video decoding section 205…Subdivision part 206…Mesh decoding unit

Claims

1. A mesh decoding device, comprising: A base mesh decoding unit configured to decode one of the bit streams of base meshes in intra mode and to decode the other of the bit streams of said base meshes in partial inter mode, The basic mesh decoding unit a demultiplexing block configured to separate said base mesh bitstream into an intraframe bitstream and a partial interframe bitstream; an intra basic mesh decoding block configured to decode the bitstream of said intra frames in intra mode; a partial inter elementary mesh decoding block adapted to decode the bitstream of the partial inter frame in a partial inter mode.

2. The intra-element mesh decoding block is a demultiplexing block configured to separate the intra-frame bitstream into a separate index bitstream and a base mesh bitstream; a separate index decoding block configured to decode the separate index bitstream to generate a separate index; a static mesh decoding block configured to decode the base mesh bitstream to generate a merged base mesh; a mesh reordering block configured to reorder the vertices and faces of the merged base meshes and output an intra-frame base mesh; 2. The mesh decoding device according to claim 1, further comprising a mesh separation block configured to separate the base meshes of the intra-frame into tracking base meshes and non-tracking base meshes using the separation index.

3. The mesh separation block is a vertex splitting block configured to split vertices of the intra-frame base mesh into disconnected components, assigning a number of the components corresponding to the split index to non-tracked vertices, and assigning the remaining components of the components to tracked vertices; 3. The mesh decoding device according to claim 2, further comprising: a face selection block adapted to separate faces of said intra-frame base meshes according to selected vertices.

4. The partial inter-basic mesh decoding block includes: a demultiplexing block configured to separate the partial inter frame bitstream into a motion bitstream and a base mesh bitstream; a motion decoding block configured to decode the motion bitstream and update vertex positions of the tracking base mesh; a static mesh decoding block configured to decode the base mesh bitstream to generate a non-tracked base mesh; a mesh merging block configured to merge the tracked base mesh and the non-tracked base mesh into a single base mesh; and a mesh reordering block configured to reorder the vertices and faces of the merged base meshes and output an intra-frame base mesh.

5. A mesh encoding device, comprising: a pre-processing block configured to generate two base meshes, a non-tracked base mesh and a tracked base mesh; an intra-coding block configured to code the non-tracked base mesh in an intra-coding mode; a partial inter-coding block adapted to code said tracking base mesh in a partial inter-coding mode.

6. 6. The mesh encoding device according to claim 5, wherein said pre-processing block comprises a mesh separation sub-block capable of separating a base mesh into said non-tracked base mesh and said tracked base mesh.

7. The intra-coded block is a mesh counting block configured to generate a separation index; a mesh merging block configured to generate a base mesh in which the non-tracked mesh and the tracked mesh are merged; a mesh reordering block configured to reorder the vertices and faces of the merged base mesh; A displacement update block configured to update a displacement using the reordered base meshes.

8. The partial inter-coded block is a static mesh coding block configured to code the non-tracked base mesh; a motion coding block configured to code said tracking basis mesh; a mesh merging block configured to merge the reconstructed non-tracked base mesh and the tracked base mesh into a single mesh; a mesh reordering block configured to reorder the vertices and faces of the merged base mesh; and a displacement update block configured to update the displacements using the reordered base meshes.

9. 1. A mesh decoding method, comprising: Decoding one of the bitstreams of the base meshes in intra mode and decoding the other of the bitstreams of the base meshes in partial inter mode, In the front-end process, Separating the basic mesh bitstream into an intraframe bitstream and a partial interframe bitstream; Decoding the intra frame bitstream in intra mode; A mesh decoding method, comprising decoding the partial inter frame bit stream in a partial inter mode.

10. A program for causing a computer to function as a mesh decoding device, comprising: The mesh decoding device comprises: A base mesh decoding unit configured to decode one of the bit streams of base meshes in intra mode and to decode the other of the bit streams of said base meshes in partial inter mode, The basic mesh decoding unit a demultiplexing block configured to separate said base mesh bitstream into an intraframe bitstream and a partial interframe bitstream; an intra basic mesh decoding block configured to decode the bitstream of said intra frames in intra mode; a partial inter basic mesh decoding block configured to decode the partial inter frame bitstream in a partial inter mode.

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